Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
10 | * | |
11 | * Authors: | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * | |
15 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
16 | * the COPYING file in the top-level directory. | |
17 | * | |
18 | */ | |
19 | ||
20 | /* | |
21 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
22 | * so the code in this file is compiled twice, once per pte size. | |
23 | */ | |
24 | ||
25 | #if PTTYPE == 64 | |
26 | #define pt_element_t u64 | |
27 | #define guest_walker guest_walker64 | |
28 | #define FNAME(name) paging##64_##name | |
29 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
30 | #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK | |
31 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
32 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
33 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) | |
34 | #define PT_PTE_COPY_MASK PT64_PTE_COPY_MASK | |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
37 | #else | |
38 | #define PT_MAX_FULL_LEVELS 2 | |
39 | #endif | |
6aa8b732 AK |
40 | #elif PTTYPE == 32 |
41 | #define pt_element_t u32 | |
42 | #define guest_walker guest_walker32 | |
43 | #define FNAME(name) paging##32_##name | |
44 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
45 | #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK | |
46 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) | |
47 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
48 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) | |
49 | #define PT_PTE_COPY_MASK PT32_PTE_COPY_MASK | |
cea0f0e7 | 50 | #define PT_MAX_FULL_LEVELS 2 |
6aa8b732 AK |
51 | #else |
52 | #error Invalid PTTYPE value | |
53 | #endif | |
54 | ||
55 | /* | |
56 | * The guest_walker structure emulates the behavior of the hardware page | |
57 | * table walker. | |
58 | */ | |
59 | struct guest_walker { | |
60 | int level; | |
cea0f0e7 | 61 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
6aa8b732 | 62 | pt_element_t *table; |
ac79c978 | 63 | pt_element_t *ptep; |
6aa8b732 | 64 | pt_element_t inherited_ar; |
815af8d4 | 65 | gfn_t gfn; |
7993ba43 | 66 | u32 error_code; |
6aa8b732 AK |
67 | }; |
68 | ||
ac79c978 AK |
69 | /* |
70 | * Fetch a guest pte for a guest virtual address | |
71 | */ | |
7993ba43 AK |
72 | static int FNAME(walk_addr)(struct guest_walker *walker, |
73 | struct kvm_vcpu *vcpu, gva_t addr, | |
73b1087e | 74 | int write_fault, int user_fault, int fetch_fault) |
6aa8b732 AK |
75 | { |
76 | hpa_t hpa; | |
77 | struct kvm_memory_slot *slot; | |
ac79c978 | 78 | pt_element_t *ptep; |
1b0973bd | 79 | pt_element_t root; |
cea0f0e7 | 80 | gfn_t table_gfn; |
6aa8b732 | 81 | |
cea0f0e7 | 82 | pgprintk("%s: addr %lx\n", __FUNCTION__, addr); |
6aa8b732 | 83 | walker->level = vcpu->mmu.root_level; |
1b0973bd AK |
84 | walker->table = NULL; |
85 | root = vcpu->cr3; | |
86 | #if PTTYPE == 64 | |
87 | if (!is_long_mode(vcpu)) { | |
88 | walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3]; | |
89 | root = *walker->ptep; | |
90 | if (!(root & PT_PRESENT_MASK)) | |
7993ba43 | 91 | goto not_present; |
1b0973bd AK |
92 | --walker->level; |
93 | } | |
94 | #endif | |
cea0f0e7 AK |
95 | table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
96 | walker->table_gfn[walker->level - 1] = table_gfn; | |
97 | pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__, | |
98 | walker->level - 1, table_gfn); | |
99 | slot = gfn_to_memslot(vcpu->kvm, table_gfn); | |
1b0973bd | 100 | hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK); |
6aa8b732 AK |
101 | walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0); |
102 | ||
a9058ecd | 103 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
6aa8b732 AK |
104 | (vcpu->cr3 & ~(PAGE_MASK | CR3_FLAGS_MASK)) == 0); |
105 | ||
6aa8b732 | 106 | walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK; |
ac79c978 AK |
107 | |
108 | for (;;) { | |
109 | int index = PT_INDEX(addr, walker->level); | |
110 | hpa_t paddr; | |
111 | ||
112 | ptep = &walker->table[index]; | |
113 | ASSERT(((unsigned long)walker->table & PAGE_MASK) == | |
114 | ((unsigned long)ptep & PAGE_MASK)); | |
115 | ||
815af8d4 | 116 | if (!is_present_pte(*ptep)) |
7993ba43 AK |
117 | goto not_present; |
118 | ||
119 | if (write_fault && !is_writeble_pte(*ptep)) | |
120 | if (user_fault || is_write_protection(vcpu)) | |
121 | goto access_error; | |
122 | ||
123 | if (user_fault && !(*ptep & PT_USER_MASK)) | |
124 | goto access_error; | |
125 | ||
73b1087e AK |
126 | #if PTTYPE == 64 |
127 | if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK)) | |
128 | goto access_error; | |
129 | #endif | |
130 | ||
7993ba43 AK |
131 | if (!(*ptep & PT_ACCESSED_MASK)) |
132 | *ptep |= PT_ACCESSED_MASK; /* avoid rmw */ | |
815af8d4 AK |
133 | |
134 | if (walker->level == PT_PAGE_TABLE_LEVEL) { | |
135 | walker->gfn = (*ptep & PT_BASE_ADDR_MASK) | |
136 | >> PAGE_SHIFT; | |
137 | break; | |
138 | } | |
139 | ||
140 | if (walker->level == PT_DIRECTORY_LEVEL | |
141 | && (*ptep & PT_PAGE_SIZE_MASK) | |
142 | && (PTTYPE == 64 || is_pse(vcpu))) { | |
143 | walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK) | |
144 | >> PAGE_SHIFT; | |
145 | walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL); | |
ac79c978 | 146 | break; |
815af8d4 | 147 | } |
ac79c978 AK |
148 | |
149 | if (walker->level != 3 || is_long_mode(vcpu)) | |
150 | walker->inherited_ar &= walker->table[index]; | |
cea0f0e7 | 151 | table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT; |
ac79c978 AK |
152 | paddr = safe_gpa_to_hpa(vcpu, *ptep & PT_BASE_ADDR_MASK); |
153 | kunmap_atomic(walker->table, KM_USER0); | |
154 | walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT), | |
155 | KM_USER0); | |
156 | --walker->level; | |
cea0f0e7 AK |
157 | walker->table_gfn[walker->level - 1 ] = table_gfn; |
158 | pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__, | |
159 | walker->level - 1, table_gfn); | |
ac79c978 AK |
160 | } |
161 | walker->ptep = ptep; | |
374cbac0 | 162 | pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep); |
7993ba43 AK |
163 | return 1; |
164 | ||
165 | not_present: | |
166 | walker->error_code = 0; | |
167 | goto err; | |
168 | ||
169 | access_error: | |
170 | walker->error_code = PFERR_PRESENT_MASK; | |
171 | ||
172 | err: | |
173 | if (write_fault) | |
174 | walker->error_code |= PFERR_WRITE_MASK; | |
175 | if (user_fault) | |
176 | walker->error_code |= PFERR_USER_MASK; | |
73b1087e AK |
177 | if (fetch_fault) |
178 | walker->error_code |= PFERR_FETCH_MASK; | |
7993ba43 | 179 | return 0; |
6aa8b732 AK |
180 | } |
181 | ||
182 | static void FNAME(release_walker)(struct guest_walker *walker) | |
183 | { | |
1b0973bd AK |
184 | if (walker->table) |
185 | kunmap_atomic(walker->table, KM_USER0); | |
6aa8b732 AK |
186 | } |
187 | ||
188 | static void FNAME(set_pte)(struct kvm_vcpu *vcpu, u64 guest_pte, | |
815af8d4 | 189 | u64 *shadow_pte, u64 access_bits, gfn_t gfn) |
6aa8b732 AK |
190 | { |
191 | ASSERT(*shadow_pte == 0); | |
192 | access_bits &= guest_pte; | |
193 | *shadow_pte = (guest_pte & PT_PTE_COPY_MASK); | |
194 | set_pte_common(vcpu, shadow_pte, guest_pte & PT_BASE_ADDR_MASK, | |
815af8d4 | 195 | guest_pte & PT_DIRTY_MASK, access_bits, gfn); |
6aa8b732 AK |
196 | } |
197 | ||
198 | static void FNAME(set_pde)(struct kvm_vcpu *vcpu, u64 guest_pde, | |
815af8d4 | 199 | u64 *shadow_pte, u64 access_bits, gfn_t gfn) |
6aa8b732 AK |
200 | { |
201 | gpa_t gaddr; | |
202 | ||
203 | ASSERT(*shadow_pte == 0); | |
204 | access_bits &= guest_pde; | |
815af8d4 | 205 | gaddr = (gpa_t)gfn << PAGE_SHIFT; |
6aa8b732 AK |
206 | if (PTTYPE == 32 && is_cpuid_PSE36()) |
207 | gaddr |= (guest_pde & PT32_DIR_PSE36_MASK) << | |
208 | (32 - PT32_DIR_PSE36_SHIFT); | |
8c7bb723 | 209 | *shadow_pte = guest_pde & PT_PTE_COPY_MASK; |
6aa8b732 | 210 | set_pte_common(vcpu, shadow_pte, gaddr, |
815af8d4 | 211 | guest_pde & PT_DIRTY_MASK, access_bits, gfn); |
6aa8b732 AK |
212 | } |
213 | ||
6aa8b732 AK |
214 | /* |
215 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
216 | */ | |
217 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, | |
218 | struct guest_walker *walker) | |
219 | { | |
220 | hpa_t shadow_addr; | |
221 | int level; | |
222 | u64 *prev_shadow_ent = NULL; | |
ac79c978 AK |
223 | pt_element_t *guest_ent = walker->ptep; |
224 | ||
225 | if (!is_present_pte(*guest_ent)) | |
226 | return NULL; | |
6aa8b732 AK |
227 | |
228 | shadow_addr = vcpu->mmu.root_hpa; | |
229 | level = vcpu->mmu.shadow_root_level; | |
aef3d3fe AK |
230 | if (level == PT32E_ROOT_LEVEL) { |
231 | shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3]; | |
232 | shadow_addr &= PT64_BASE_ADDR_MASK; | |
233 | --level; | |
234 | } | |
6aa8b732 AK |
235 | |
236 | for (; ; level--) { | |
237 | u32 index = SHADOW_PT_INDEX(addr, level); | |
238 | u64 *shadow_ent = ((u64 *)__va(shadow_addr)) + index; | |
25c0de2c | 239 | struct kvm_mmu_page *shadow_page; |
8c7bb723 | 240 | u64 shadow_pte; |
cea0f0e7 AK |
241 | int metaphysical; |
242 | gfn_t table_gfn; | |
6aa8b732 AK |
243 | |
244 | if (is_present_pte(*shadow_ent) || is_io_pte(*shadow_ent)) { | |
245 | if (level == PT_PAGE_TABLE_LEVEL) | |
246 | return shadow_ent; | |
247 | shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK; | |
248 | prev_shadow_ent = shadow_ent; | |
249 | continue; | |
250 | } | |
251 | ||
6aa8b732 AK |
252 | if (level == PT_PAGE_TABLE_LEVEL) { |
253 | ||
254 | if (walker->level == PT_DIRECTORY_LEVEL) { | |
255 | if (prev_shadow_ent) | |
256 | *prev_shadow_ent |= PT_SHADOW_PS_MARK; | |
257 | FNAME(set_pde)(vcpu, *guest_ent, shadow_ent, | |
258 | walker->inherited_ar, | |
815af8d4 | 259 | walker->gfn); |
6aa8b732 AK |
260 | } else { |
261 | ASSERT(walker->level == PT_PAGE_TABLE_LEVEL); | |
815af8d4 AK |
262 | FNAME(set_pte)(vcpu, *guest_ent, shadow_ent, |
263 | walker->inherited_ar, | |
264 | walker->gfn); | |
6aa8b732 AK |
265 | } |
266 | return shadow_ent; | |
267 | } | |
268 | ||
cea0f0e7 AK |
269 | if (level - 1 == PT_PAGE_TABLE_LEVEL |
270 | && walker->level == PT_DIRECTORY_LEVEL) { | |
271 | metaphysical = 1; | |
272 | table_gfn = (*guest_ent & PT_BASE_ADDR_MASK) | |
273 | >> PAGE_SHIFT; | |
274 | } else { | |
275 | metaphysical = 0; | |
276 | table_gfn = walker->table_gfn[level - 2]; | |
277 | } | |
278 | shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1, | |
279 | metaphysical, shadow_ent); | |
25c0de2c | 280 | shadow_addr = shadow_page->page_hpa; |
aef3d3fe AK |
281 | shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK |
282 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
8c7bb723 | 283 | *shadow_ent = shadow_pte; |
6aa8b732 AK |
284 | prev_shadow_ent = shadow_ent; |
285 | } | |
286 | } | |
287 | ||
288 | /* | |
289 | * The guest faulted for write. We need to | |
290 | * | |
291 | * - check write permissions | |
292 | * - update the guest pte dirty bit | |
293 | * - update our own dirty page tracking structures | |
294 | */ | |
295 | static int FNAME(fix_write_pf)(struct kvm_vcpu *vcpu, | |
296 | u64 *shadow_ent, | |
297 | struct guest_walker *walker, | |
298 | gva_t addr, | |
cea0f0e7 AK |
299 | int user, |
300 | int *write_pt) | |
6aa8b732 AK |
301 | { |
302 | pt_element_t *guest_ent; | |
303 | int writable_shadow; | |
304 | gfn_t gfn; | |
14364656 | 305 | struct kvm_mmu_page *page; |
6aa8b732 AK |
306 | |
307 | if (is_writeble_pte(*shadow_ent)) | |
fc3dffe1 | 308 | return !user || (*shadow_ent & PT_USER_MASK); |
6aa8b732 AK |
309 | |
310 | writable_shadow = *shadow_ent & PT_SHADOW_WRITABLE_MASK; | |
311 | if (user) { | |
312 | /* | |
313 | * User mode access. Fail if it's a kernel page or a read-only | |
314 | * page. | |
315 | */ | |
316 | if (!(*shadow_ent & PT_SHADOW_USER_MASK) || !writable_shadow) | |
317 | return 0; | |
318 | ASSERT(*shadow_ent & PT_USER_MASK); | |
319 | } else | |
320 | /* | |
321 | * Kernel mode access. Fail if it's a read-only page and | |
322 | * supervisor write protection is enabled. | |
323 | */ | |
324 | if (!writable_shadow) { | |
325 | if (is_write_protection(vcpu)) | |
326 | return 0; | |
327 | *shadow_ent &= ~PT_USER_MASK; | |
328 | } | |
329 | ||
ac79c978 | 330 | guest_ent = walker->ptep; |
6aa8b732 AK |
331 | |
332 | if (!is_present_pte(*guest_ent)) { | |
333 | *shadow_ent = 0; | |
334 | return 0; | |
335 | } | |
336 | ||
815af8d4 | 337 | gfn = walker->gfn; |
14364656 AK |
338 | |
339 | if (user) { | |
340 | /* | |
341 | * Usermode page faults won't be for page table updates. | |
342 | */ | |
343 | while ((page = kvm_mmu_lookup_page(vcpu, gfn)) != NULL) { | |
344 | pgprintk("%s: zap %lx %x\n", | |
345 | __FUNCTION__, gfn, page->role.word); | |
346 | kvm_mmu_zap_page(vcpu, page); | |
347 | } | |
348 | } else if (kvm_mmu_lookup_page(vcpu, gfn)) { | |
cea0f0e7 AK |
349 | pgprintk("%s: found shadow page for %lx, marking ro\n", |
350 | __FUNCTION__, gfn); | |
760db773 | 351 | *guest_ent |= PT_DIRTY_MASK; |
cea0f0e7 AK |
352 | *write_pt = 1; |
353 | return 0; | |
354 | } | |
6aa8b732 AK |
355 | mark_page_dirty(vcpu->kvm, gfn); |
356 | *shadow_ent |= PT_WRITABLE_MASK; | |
357 | *guest_ent |= PT_DIRTY_MASK; | |
714b93da | 358 | rmap_add(vcpu, shadow_ent); |
6aa8b732 AK |
359 | |
360 | return 1; | |
361 | } | |
362 | ||
363 | /* | |
364 | * Page fault handler. There are several causes for a page fault: | |
365 | * - there is no shadow pte for the guest pte | |
366 | * - write access through a shadow pte marked read only so that we can set | |
367 | * the dirty bit | |
368 | * - write access to a shadow pte marked read only so we can update the page | |
369 | * dirty bitmap, when userspace requests it | |
370 | * - mmio access; in this case we will never install a present shadow pte | |
371 | * - normal guest page fault due to the guest pte marked not present, not | |
372 | * writable, or not executable | |
373 | * | |
e2dec939 AK |
374 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
375 | * a negative value on error. | |
6aa8b732 AK |
376 | */ |
377 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, | |
378 | u32 error_code) | |
379 | { | |
380 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 | 381 | int user_fault = error_code & PFERR_USER_MASK; |
73b1087e | 382 | int fetch_fault = error_code & PFERR_FETCH_MASK; |
6aa8b732 AK |
383 | struct guest_walker walker; |
384 | u64 *shadow_pte; | |
385 | int fixed; | |
cea0f0e7 | 386 | int write_pt = 0; |
e2dec939 | 387 | int r; |
6aa8b732 | 388 | |
cea0f0e7 | 389 | pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code); |
37a7d8b0 | 390 | kvm_mmu_audit(vcpu, "pre page fault"); |
714b93da | 391 | |
e2dec939 AK |
392 | r = mmu_topup_memory_caches(vcpu); |
393 | if (r) | |
394 | return r; | |
714b93da | 395 | |
6aa8b732 AK |
396 | /* |
397 | * Look up the shadow pte for the faulting address. | |
398 | */ | |
73b1087e AK |
399 | r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault, |
400 | fetch_fault); | |
6aa8b732 AK |
401 | |
402 | /* | |
403 | * The page is not mapped by the guest. Let the guest handle it. | |
404 | */ | |
7993ba43 AK |
405 | if (!r) { |
406 | pgprintk("%s: guest page fault\n", __FUNCTION__); | |
407 | inject_page_fault(vcpu, addr, walker.error_code); | |
6aa8b732 AK |
408 | FNAME(release_walker)(&walker); |
409 | return 0; | |
410 | } | |
411 | ||
7993ba43 | 412 | shadow_pte = FNAME(fetch)(vcpu, addr, &walker); |
cea0f0e7 AK |
413 | pgprintk("%s: shadow pte %p %llx\n", __FUNCTION__, |
414 | shadow_pte, *shadow_pte); | |
415 | ||
6aa8b732 AK |
416 | /* |
417 | * Update the shadow pte. | |
418 | */ | |
419 | if (write_fault) | |
420 | fixed = FNAME(fix_write_pf)(vcpu, shadow_pte, &walker, addr, | |
cea0f0e7 | 421 | user_fault, &write_pt); |
6aa8b732 AK |
422 | else |
423 | fixed = fix_read_pf(shadow_pte); | |
424 | ||
cea0f0e7 AK |
425 | pgprintk("%s: updated shadow pte %p %llx\n", __FUNCTION__, |
426 | shadow_pte, *shadow_pte); | |
427 | ||
6aa8b732 AK |
428 | FNAME(release_walker)(&walker); |
429 | ||
430 | /* | |
431 | * mmio: emulate if accessible, otherwise its a guest fault. | |
432 | */ | |
433 | if (is_io_pte(*shadow_pte)) { | |
7993ba43 | 434 | return 1; |
6aa8b732 AK |
435 | } |
436 | ||
437 | ++kvm_stat.pf_fixed; | |
37a7d8b0 | 438 | kvm_mmu_audit(vcpu, "post page fault (fixed)"); |
6aa8b732 | 439 | |
cea0f0e7 | 440 | return write_pt; |
6aa8b732 AK |
441 | } |
442 | ||
443 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr) | |
444 | { | |
445 | struct guest_walker walker; | |
446 | pt_element_t guest_pte; | |
447 | gpa_t gpa; | |
448 | ||
73b1087e | 449 | FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0); |
ac79c978 | 450 | guest_pte = *walker.ptep; |
6aa8b732 AK |
451 | FNAME(release_walker)(&walker); |
452 | ||
453 | if (!is_present_pte(guest_pte)) | |
454 | return UNMAPPED_GVA; | |
455 | ||
456 | if (walker.level == PT_DIRECTORY_LEVEL) { | |
457 | ASSERT((guest_pte & PT_PAGE_SIZE_MASK)); | |
458 | ASSERT(PTTYPE == 64 || is_pse(vcpu)); | |
459 | ||
460 | gpa = (guest_pte & PT_DIR_BASE_ADDR_MASK) | (vaddr & | |
461 | (PT_LEVEL_MASK(PT_PAGE_TABLE_LEVEL) | ~PAGE_MASK)); | |
462 | ||
463 | if (PTTYPE == 32 && is_cpuid_PSE36()) | |
464 | gpa |= (guest_pte & PT32_DIR_PSE36_MASK) << | |
465 | (32 - PT32_DIR_PSE36_SHIFT); | |
466 | } else { | |
467 | gpa = (guest_pte & PT_BASE_ADDR_MASK); | |
468 | gpa |= (vaddr & ~PAGE_MASK); | |
469 | } | |
470 | ||
471 | return gpa; | |
472 | } | |
473 | ||
474 | #undef pt_element_t | |
475 | #undef guest_walker | |
476 | #undef FNAME | |
477 | #undef PT_BASE_ADDR_MASK | |
478 | #undef PT_INDEX | |
479 | #undef SHADOW_PT_INDEX | |
480 | #undef PT_LEVEL_MASK | |
481 | #undef PT_PTE_COPY_MASK | |
482 | #undef PT_NON_PTE_COPY_MASK | |
483 | #undef PT_DIR_BASE_ADDR_MASK | |
cea0f0e7 | 484 | #undef PT_MAX_FULL_LEVELS |