Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
34c16eec | 16 | #include "x86.h" |
e495606d AK |
17 | #include "kvm_svm.h" |
18 | #include "x86_emulate.h" | |
85f455f7 | 19 | #include "irq.h" |
e495606d | 20 | |
6aa8b732 | 21 | #include <linux/module.h> |
9d8f549d | 22 | #include <linux/kernel.h> |
6aa8b732 AK |
23 | #include <linux/vmalloc.h> |
24 | #include <linux/highmem.h> | |
e8edc6e0 | 25 | #include <linux/sched.h> |
6aa8b732 | 26 | |
e495606d | 27 | #include <asm/desc.h> |
6aa8b732 AK |
28 | |
29 | MODULE_AUTHOR("Qumranet"); | |
30 | MODULE_LICENSE("GPL"); | |
31 | ||
32 | #define IOPM_ALLOC_ORDER 2 | |
33 | #define MSRPM_ALLOC_ORDER 1 | |
34 | ||
35 | #define DB_VECTOR 1 | |
36 | #define UD_VECTOR 6 | |
37 | #define GP_VECTOR 13 | |
38 | ||
39 | #define DR7_GD_MASK (1 << 13) | |
40 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
41 | |
42 | #define SEG_TYPE_LDT 2 | |
43 | #define SEG_TYPE_BUSY_TSS16 3 | |
44 | ||
80b7706e JR |
45 | #define SVM_FEATURE_NPT (1 << 0) |
46 | #define SVM_FEATURE_LBRV (1 << 1) | |
47 | #define SVM_DEATURE_SVML (1 << 2) | |
48 | ||
04d2cc77 AK |
49 | static void kvm_reput_irq(struct vcpu_svm *svm); |
50 | ||
a2fa3e9f GH |
51 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
52 | { | |
fb3f0f51 | 53 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
54 | } |
55 | ||
6aa8b732 AK |
56 | unsigned long iopm_base; |
57 | unsigned long msrpm_base; | |
58 | ||
59 | struct kvm_ldttss_desc { | |
60 | u16 limit0; | |
61 | u16 base0; | |
62 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
63 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
64 | u32 base3; | |
65 | u32 zero1; | |
66 | } __attribute__((packed)); | |
67 | ||
68 | struct svm_cpu_data { | |
69 | int cpu; | |
70 | ||
5008fdf5 AK |
71 | u64 asid_generation; |
72 | u32 max_asid; | |
73 | u32 next_asid; | |
6aa8b732 AK |
74 | struct kvm_ldttss_desc *tss_desc; |
75 | ||
76 | struct page *save_area; | |
77 | }; | |
78 | ||
79 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 80 | static uint32_t svm_features; |
6aa8b732 AK |
81 | |
82 | struct svm_init_data { | |
83 | int cpu; | |
84 | int r; | |
85 | }; | |
86 | ||
87 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
88 | ||
9d8f549d | 89 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
90 | #define MSRS_RANGE_SIZE 2048 |
91 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
92 | ||
93 | #define MAX_INST_SIZE 15 | |
94 | ||
80b7706e JR |
95 | static inline u32 svm_has(u32 feat) |
96 | { | |
97 | return svm_features & feat; | |
98 | } | |
99 | ||
6aa8b732 AK |
100 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
101 | { | |
102 | int word_index = __ffs(vcpu->irq_summary); | |
103 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
104 | int irq = word_index * BITS_PER_LONG + bit_index; | |
105 | ||
106 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
107 | if (!vcpu->irq_pending[word_index]) | |
108 | clear_bit(word_index, &vcpu->irq_summary); | |
109 | return irq; | |
110 | } | |
111 | ||
112 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
113 | { | |
114 | set_bit(irq, vcpu->irq_pending); | |
115 | set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary); | |
116 | } | |
117 | ||
118 | static inline void clgi(void) | |
119 | { | |
120 | asm volatile (SVM_CLGI); | |
121 | } | |
122 | ||
123 | static inline void stgi(void) | |
124 | { | |
125 | asm volatile (SVM_STGI); | |
126 | } | |
127 | ||
128 | static inline void invlpga(unsigned long addr, u32 asid) | |
129 | { | |
130 | asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid)); | |
131 | } | |
132 | ||
133 | static inline unsigned long kvm_read_cr2(void) | |
134 | { | |
135 | unsigned long cr2; | |
136 | ||
137 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
138 | return cr2; | |
139 | } | |
140 | ||
141 | static inline void kvm_write_cr2(unsigned long val) | |
142 | { | |
143 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
144 | } | |
145 | ||
146 | static inline unsigned long read_dr6(void) | |
147 | { | |
148 | unsigned long dr6; | |
149 | ||
150 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
151 | return dr6; | |
152 | } | |
153 | ||
154 | static inline void write_dr6(unsigned long val) | |
155 | { | |
156 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
157 | } | |
158 | ||
159 | static inline unsigned long read_dr7(void) | |
160 | { | |
161 | unsigned long dr7; | |
162 | ||
163 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
164 | return dr7; | |
165 | } | |
166 | ||
167 | static inline void write_dr7(unsigned long val) | |
168 | { | |
169 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
170 | } | |
171 | ||
6aa8b732 AK |
172 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
173 | { | |
a2fa3e9f | 174 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
175 | } |
176 | ||
177 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
178 | { | |
179 | force_new_asid(vcpu); | |
180 | } | |
181 | ||
182 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
183 | { | |
2b5203ee CMAB |
184 | if (!(efer & EFER_LMA)) |
185 | efer &= ~EFER_LME; | |
6aa8b732 | 186 | |
a2fa3e9f | 187 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
6aa8b732 AK |
188 | vcpu->shadow_efer = efer; |
189 | } | |
190 | ||
298101da AK |
191 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
192 | bool has_error_code, u32 error_code) | |
193 | { | |
194 | struct vcpu_svm *svm = to_svm(vcpu); | |
195 | ||
196 | svm->vmcb->control.event_inj = nr | |
197 | | SVM_EVTINJ_VALID | |
198 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
199 | | SVM_EVTINJ_TYPE_EXEPT; | |
200 | svm->vmcb->control.event_inj_err = error_code; | |
201 | } | |
202 | ||
203 | static bool svm_exception_injected(struct kvm_vcpu *vcpu) | |
204 | { | |
205 | struct vcpu_svm *svm = to_svm(vcpu); | |
206 | ||
207 | return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID); | |
208 | } | |
209 | ||
6aa8b732 AK |
210 | static int is_external_interrupt(u32 info) |
211 | { | |
212 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
213 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
214 | } | |
215 | ||
216 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
217 | { | |
a2fa3e9f GH |
218 | struct vcpu_svm *svm = to_svm(vcpu); |
219 | ||
220 | if (!svm->next_rip) { | |
6aa8b732 AK |
221 | printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__); |
222 | return; | |
223 | } | |
d77c26fc | 224 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) |
6aa8b732 AK |
225 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
226 | __FUNCTION__, | |
a2fa3e9f GH |
227 | svm->vmcb->save.rip, |
228 | svm->next_rip); | |
6aa8b732 | 229 | |
a2fa3e9f GH |
230 | vcpu->rip = svm->vmcb->save.rip = svm->next_rip; |
231 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
c1150d8c DL |
232 | |
233 | vcpu->interrupt_window_open = 1; | |
6aa8b732 AK |
234 | } |
235 | ||
236 | static int has_svm(void) | |
237 | { | |
238 | uint32_t eax, ebx, ecx, edx; | |
239 | ||
1e885461 | 240 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
241 | printk(KERN_INFO "has_svm: not amd\n"); |
242 | return 0; | |
243 | } | |
244 | ||
245 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
246 | if (eax < SVM_CPUID_FUNC) { | |
247 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
248 | return 0; | |
249 | } | |
250 | ||
251 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
252 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
253 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
254 | return 0; | |
255 | } | |
256 | return 1; | |
257 | } | |
258 | ||
259 | static void svm_hardware_disable(void *garbage) | |
260 | { | |
261 | struct svm_cpu_data *svm_data | |
262 | = per_cpu(svm_data, raw_smp_processor_id()); | |
263 | ||
264 | if (svm_data) { | |
265 | uint64_t efer; | |
266 | ||
267 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
268 | rdmsrl(MSR_EFER, efer); | |
269 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 270 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
271 | __free_page(svm_data->save_area); |
272 | kfree(svm_data); | |
273 | } | |
274 | } | |
275 | ||
276 | static void svm_hardware_enable(void *garbage) | |
277 | { | |
278 | ||
279 | struct svm_cpu_data *svm_data; | |
280 | uint64_t efer; | |
05b3e0c2 | 281 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
282 | struct desc_ptr gdt_descr; |
283 | #else | |
6b68f01b | 284 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
285 | #endif |
286 | struct desc_struct *gdt; | |
287 | int me = raw_smp_processor_id(); | |
288 | ||
289 | if (!has_svm()) { | |
290 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
291 | return; | |
292 | } | |
293 | svm_data = per_cpu(svm_data, me); | |
294 | ||
295 | if (!svm_data) { | |
296 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
297 | me); | |
298 | return; | |
299 | } | |
300 | ||
301 | svm_data->asid_generation = 1; | |
302 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
303 | svm_data->next_asid = svm_data->max_asid + 1; | |
80b7706e | 304 | svm_features = cpuid_edx(SVM_CPUID_FUNC); |
6aa8b732 | 305 | |
d77c26fc | 306 | asm volatile ("sgdt %0" : "=m"(gdt_descr)); |
6aa8b732 AK |
307 | gdt = (struct desc_struct *)gdt_descr.address; |
308 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
309 | ||
310 | rdmsrl(MSR_EFER, efer); | |
311 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
312 | ||
313 | wrmsrl(MSR_VM_HSAVE_PA, | |
314 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
315 | } | |
316 | ||
317 | static int svm_cpu_init(int cpu) | |
318 | { | |
319 | struct svm_cpu_data *svm_data; | |
320 | int r; | |
321 | ||
322 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
323 | if (!svm_data) | |
324 | return -ENOMEM; | |
325 | svm_data->cpu = cpu; | |
326 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
327 | r = -ENOMEM; | |
328 | if (!svm_data->save_area) | |
329 | goto err_1; | |
330 | ||
331 | per_cpu(svm_data, cpu) = svm_data; | |
332 | ||
333 | return 0; | |
334 | ||
335 | err_1: | |
336 | kfree(svm_data); | |
337 | return r; | |
338 | ||
339 | } | |
340 | ||
bfc733a7 RR |
341 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
342 | int read, int write) | |
6aa8b732 AK |
343 | { |
344 | int i; | |
345 | ||
346 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
347 | if (msr >= msrpm_ranges[i] && | |
348 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
349 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
350 | msrpm_ranges[i]) * 2; | |
351 | ||
352 | u32 *base = msrpm + (msr_offset / 32); | |
353 | u32 msr_shift = msr_offset % 32; | |
354 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
355 | *base = (*base & ~(0x3 << msr_shift)) | | |
356 | (mask << msr_shift); | |
bfc733a7 | 357 | return; |
6aa8b732 AK |
358 | } |
359 | } | |
bfc733a7 | 360 | BUG(); |
6aa8b732 AK |
361 | } |
362 | ||
363 | static __init int svm_hardware_setup(void) | |
364 | { | |
365 | int cpu; | |
366 | struct page *iopm_pages; | |
367 | struct page *msrpm_pages; | |
c8681339 | 368 | void *iopm_va, *msrpm_va; |
6aa8b732 AK |
369 | int r; |
370 | ||
6aa8b732 AK |
371 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
372 | ||
373 | if (!iopm_pages) | |
374 | return -ENOMEM; | |
c8681339 AL |
375 | |
376 | iopm_va = page_address(iopm_pages); | |
377 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
378 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
379 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
380 | ||
381 | ||
382 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
383 | ||
384 | r = -ENOMEM; | |
385 | if (!msrpm_pages) | |
386 | goto err_1; | |
387 | ||
388 | msrpm_va = page_address(msrpm_pages); | |
389 | memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
390 | msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT; | |
391 | ||
05b3e0c2 | 392 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
393 | set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1); |
394 | set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1); | |
395 | set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1); | |
6aa8b732 AK |
396 | set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1); |
397 | set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1); | |
398 | set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1); | |
399 | #endif | |
0e859cac | 400 | set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1); |
6aa8b732 AK |
401 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1); |
402 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1); | |
403 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1); | |
404 | ||
405 | for_each_online_cpu(cpu) { | |
406 | r = svm_cpu_init(cpu); | |
407 | if (r) | |
408 | goto err_2; | |
409 | } | |
410 | return 0; | |
411 | ||
412 | err_2: | |
413 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
414 | msrpm_base = 0; | |
415 | err_1: | |
416 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); | |
417 | iopm_base = 0; | |
418 | return r; | |
419 | } | |
420 | ||
421 | static __exit void svm_hardware_unsetup(void) | |
422 | { | |
423 | __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER); | |
424 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); | |
425 | iopm_base = msrpm_base = 0; | |
426 | } | |
427 | ||
428 | static void init_seg(struct vmcb_seg *seg) | |
429 | { | |
430 | seg->selector = 0; | |
431 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
432 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
433 | seg->limit = 0xffff; | |
434 | seg->base = 0; | |
435 | } | |
436 | ||
437 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
438 | { | |
439 | seg->selector = 0; | |
440 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
441 | seg->limit = 0xffff; | |
442 | seg->base = 0; | |
443 | } | |
444 | ||
6aa8b732 AK |
445 | static void init_vmcb(struct vmcb *vmcb) |
446 | { | |
447 | struct vmcb_control_area *control = &vmcb->control; | |
448 | struct vmcb_save_area *save = &vmcb->save; | |
6aa8b732 AK |
449 | |
450 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
451 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
452 | INTERCEPT_CR4_MASK | |
453 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
454 | |
455 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
456 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
457 | INTERCEPT_CR4_MASK | |
458 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
459 | |
460 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
461 | INTERCEPT_DR1_MASK | | |
462 | INTERCEPT_DR2_MASK | | |
463 | INTERCEPT_DR3_MASK; | |
464 | ||
465 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
466 | INTERCEPT_DR1_MASK | | |
467 | INTERCEPT_DR2_MASK | | |
468 | INTERCEPT_DR3_MASK | | |
469 | INTERCEPT_DR5_MASK | | |
470 | INTERCEPT_DR7_MASK; | |
471 | ||
7aa81cc0 AL |
472 | control->intercept_exceptions = (1 << PF_VECTOR) | |
473 | (1 << UD_VECTOR); | |
6aa8b732 AK |
474 | |
475 | ||
476 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
477 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 478 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 AK |
479 | /* |
480 | * selective cr0 intercept bug? | |
481 | * 0: 0f 22 d8 mov %eax,%cr3 | |
482 | * 3: 0f 20 c0 mov %cr0,%eax | |
483 | * 6: 0d 00 00 00 80 or $0x80000000,%eax | |
484 | * b: 0f 22 c0 mov %eax,%cr0 | |
485 | * set cr3 ->interception | |
486 | * get cr0 ->interception | |
487 | * set cr0 -> no interception | |
488 | */ | |
489 | /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */ | |
490 | (1ULL << INTERCEPT_CPUID) | | |
cf5a94d1 | 491 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 492 | (1ULL << INTERCEPT_HLT) | |
6aa8b732 AK |
493 | (1ULL << INTERCEPT_INVLPGA) | |
494 | (1ULL << INTERCEPT_IOIO_PROT) | | |
495 | (1ULL << INTERCEPT_MSR_PROT) | | |
496 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 497 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
498 | (1ULL << INTERCEPT_VMRUN) | |
499 | (1ULL << INTERCEPT_VMMCALL) | | |
500 | (1ULL << INTERCEPT_VMLOAD) | | |
501 | (1ULL << INTERCEPT_VMSAVE) | | |
502 | (1ULL << INTERCEPT_STGI) | | |
503 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 504 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 505 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
506 | (1ULL << INTERCEPT_MONITOR) | |
507 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
508 | |
509 | control->iopm_base_pa = iopm_base; | |
510 | control->msrpm_base_pa = msrpm_base; | |
0cc5064d | 511 | control->tsc_offset = 0; |
6aa8b732 AK |
512 | control->int_ctl = V_INTR_MASKING_MASK; |
513 | ||
514 | init_seg(&save->es); | |
515 | init_seg(&save->ss); | |
516 | init_seg(&save->ds); | |
517 | init_seg(&save->fs); | |
518 | init_seg(&save->gs); | |
519 | ||
520 | save->cs.selector = 0xf000; | |
521 | /* Executable/Readable Code Segment */ | |
522 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
523 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
524 | save->cs.limit = 0xffff; | |
d92899a0 AK |
525 | /* |
526 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
527 | * be consistent with it. | |
528 | * | |
529 | * Replace when we have real mode working for vmx. | |
530 | */ | |
531 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
532 | |
533 | save->gdtr.limit = 0xffff; | |
534 | save->idtr.limit = 0xffff; | |
535 | ||
536 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
537 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
538 | ||
539 | save->efer = MSR_EFER_SVME_MASK; | |
d77c26fc | 540 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
541 | save->dr7 = 0x400; |
542 | save->rflags = 2; | |
543 | save->rip = 0x0000fff0; | |
544 | ||
545 | /* | |
546 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
547 | * cache by default. the orderly way is to enable cache in bios. | |
548 | */ | |
707d92fa | 549 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 550 | save->cr4 = X86_CR4_PAE; |
6aa8b732 AK |
551 | /* rdx = ?? */ |
552 | } | |
553 | ||
e00c8cf2 | 554 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
555 | { |
556 | struct vcpu_svm *svm = to_svm(vcpu); | |
557 | ||
558 | init_vmcb(svm->vmcb); | |
70433389 AK |
559 | |
560 | if (vcpu->vcpu_id != 0) { | |
561 | svm->vmcb->save.rip = 0; | |
562 | svm->vmcb->save.cs.base = svm->vcpu.sipi_vector << 12; | |
563 | svm->vmcb->save.cs.selector = svm->vcpu.sipi_vector << 8; | |
564 | } | |
e00c8cf2 AK |
565 | |
566 | return 0; | |
04d2cc77 AK |
567 | } |
568 | ||
fb3f0f51 | 569 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 570 | { |
a2fa3e9f | 571 | struct vcpu_svm *svm; |
6aa8b732 | 572 | struct page *page; |
fb3f0f51 | 573 | int err; |
6aa8b732 | 574 | |
c16f862d | 575 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
576 | if (!svm) { |
577 | err = -ENOMEM; | |
578 | goto out; | |
579 | } | |
580 | ||
581 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
582 | if (err) | |
583 | goto free_svm; | |
584 | ||
6aa8b732 | 585 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
586 | if (!page) { |
587 | err = -ENOMEM; | |
588 | goto uninit; | |
589 | } | |
6aa8b732 | 590 | |
a2fa3e9f GH |
591 | svm->vmcb = page_address(page); |
592 | clear_page(svm->vmcb); | |
593 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
594 | svm->asid_generation = 0; | |
595 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
596 | init_vmcb(svm->vmcb); | |
597 | ||
fb3f0f51 RR |
598 | fx_init(&svm->vcpu); |
599 | svm->vcpu.fpu_active = 1; | |
600 | svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; | |
601 | if (svm->vcpu.vcpu_id == 0) | |
602 | svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP; | |
6aa8b732 | 603 | |
fb3f0f51 | 604 | return &svm->vcpu; |
36241b8c | 605 | |
fb3f0f51 RR |
606 | uninit: |
607 | kvm_vcpu_uninit(&svm->vcpu); | |
608 | free_svm: | |
a4770347 | 609 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
610 | out: |
611 | return ERR_PTR(err); | |
6aa8b732 AK |
612 | } |
613 | ||
614 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
615 | { | |
a2fa3e9f GH |
616 | struct vcpu_svm *svm = to_svm(vcpu); |
617 | ||
fb3f0f51 RR |
618 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
619 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 620 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
621 | } |
622 | ||
15ad7146 | 623 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 624 | { |
a2fa3e9f | 625 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 626 | int i; |
0cc5064d | 627 | |
0cc5064d AK |
628 | if (unlikely(cpu != vcpu->cpu)) { |
629 | u64 tsc_this, delta; | |
630 | ||
631 | /* | |
632 | * Make sure that the guest sees a monotonically | |
633 | * increasing TSC. | |
634 | */ | |
635 | rdtscll(tsc_this); | |
636 | delta = vcpu->host_tsc - tsc_this; | |
a2fa3e9f | 637 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 638 | vcpu->cpu = cpu; |
a3d7f85f | 639 | kvm_migrate_apic_timer(vcpu); |
0cc5064d | 640 | } |
94dfbdb3 AL |
641 | |
642 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 643 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
644 | } |
645 | ||
646 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
647 | { | |
a2fa3e9f | 648 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
649 | int i; |
650 | ||
e1beb1d3 | 651 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 652 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 653 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 654 | |
0cc5064d | 655 | rdtscll(vcpu->host_tsc); |
6aa8b732 AK |
656 | } |
657 | ||
774c47f1 AK |
658 | static void svm_vcpu_decache(struct kvm_vcpu *vcpu) |
659 | { | |
660 | } | |
661 | ||
6aa8b732 AK |
662 | static void svm_cache_regs(struct kvm_vcpu *vcpu) |
663 | { | |
a2fa3e9f GH |
664 | struct vcpu_svm *svm = to_svm(vcpu); |
665 | ||
666 | vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
667 | vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
668 | vcpu->rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
669 | } |
670 | ||
671 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
672 | { | |
a2fa3e9f GH |
673 | struct vcpu_svm *svm = to_svm(vcpu); |
674 | svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX]; | |
675 | svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP]; | |
676 | svm->vmcb->save.rip = vcpu->rip; | |
6aa8b732 AK |
677 | } |
678 | ||
679 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
680 | { | |
a2fa3e9f | 681 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
682 | } |
683 | ||
684 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
685 | { | |
a2fa3e9f | 686 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
687 | } |
688 | ||
689 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
690 | { | |
a2fa3e9f | 691 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
692 | |
693 | switch (seg) { | |
694 | case VCPU_SREG_CS: return &save->cs; | |
695 | case VCPU_SREG_DS: return &save->ds; | |
696 | case VCPU_SREG_ES: return &save->es; | |
697 | case VCPU_SREG_FS: return &save->fs; | |
698 | case VCPU_SREG_GS: return &save->gs; | |
699 | case VCPU_SREG_SS: return &save->ss; | |
700 | case VCPU_SREG_TR: return &save->tr; | |
701 | case VCPU_SREG_LDTR: return &save->ldtr; | |
702 | } | |
703 | BUG(); | |
8b6d44c7 | 704 | return NULL; |
6aa8b732 AK |
705 | } |
706 | ||
707 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
708 | { | |
709 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
710 | ||
711 | return s->base; | |
712 | } | |
713 | ||
714 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
715 | struct kvm_segment *var, int seg) | |
716 | { | |
717 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
718 | ||
719 | var->base = s->base; | |
720 | var->limit = s->limit; | |
721 | var->selector = s->selector; | |
722 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
723 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
724 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
725 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
726 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
727 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
728 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
729 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
730 | var->unusable = !var->present; | |
731 | } | |
732 | ||
6aa8b732 AK |
733 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
734 | { | |
a2fa3e9f GH |
735 | struct vcpu_svm *svm = to_svm(vcpu); |
736 | ||
737 | dt->limit = svm->vmcb->save.idtr.limit; | |
738 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
739 | } |
740 | ||
741 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
742 | { | |
a2fa3e9f GH |
743 | struct vcpu_svm *svm = to_svm(vcpu); |
744 | ||
745 | svm->vmcb->save.idtr.limit = dt->limit; | |
746 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
747 | } |
748 | ||
749 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
750 | { | |
a2fa3e9f GH |
751 | struct vcpu_svm *svm = to_svm(vcpu); |
752 | ||
753 | dt->limit = svm->vmcb->save.gdtr.limit; | |
754 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
755 | } |
756 | ||
757 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
758 | { | |
a2fa3e9f GH |
759 | struct vcpu_svm *svm = to_svm(vcpu); |
760 | ||
761 | svm->vmcb->save.gdtr.limit = dt->limit; | |
762 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
763 | } |
764 | ||
25c4c276 | 765 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
766 | { |
767 | } | |
768 | ||
6aa8b732 AK |
769 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
770 | { | |
a2fa3e9f GH |
771 | struct vcpu_svm *svm = to_svm(vcpu); |
772 | ||
05b3e0c2 | 773 | #ifdef CONFIG_X86_64 |
2b5203ee | 774 | if (vcpu->shadow_efer & EFER_LME) { |
707d92fa | 775 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
2b5203ee CMAB |
776 | vcpu->shadow_efer |= EFER_LMA; |
777 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; | |
6aa8b732 AK |
778 | } |
779 | ||
d77c26fc | 780 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
2b5203ee CMAB |
781 | vcpu->shadow_efer &= ~EFER_LMA; |
782 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); | |
6aa8b732 AK |
783 | } |
784 | } | |
785 | #endif | |
707d92fa | 786 | if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 787 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
788 | vcpu->fpu_active = 1; |
789 | } | |
790 | ||
6aa8b732 | 791 | vcpu->cr0 = cr0; |
707d92fa RR |
792 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
793 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 794 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
795 | } |
796 | ||
797 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
798 | { | |
799 | vcpu->cr4 = cr4; | |
a2fa3e9f | 800 | to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE; |
6aa8b732 AK |
801 | } |
802 | ||
803 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
804 | struct kvm_segment *var, int seg) | |
805 | { | |
a2fa3e9f | 806 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
807 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
808 | ||
809 | s->base = var->base; | |
810 | s->limit = var->limit; | |
811 | s->selector = var->selector; | |
812 | if (var->unusable) | |
813 | s->attrib = 0; | |
814 | else { | |
815 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
816 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
817 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
818 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
819 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
820 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
821 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
822 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
823 | } | |
824 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
825 | svm->vmcb->save.cpl |
826 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
827 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
828 | ||
829 | } | |
830 | ||
831 | /* FIXME: | |
832 | ||
a2fa3e9f GH |
833 | svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK; |
834 | svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK); | |
6aa8b732 AK |
835 | |
836 | */ | |
837 | ||
838 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
839 | { | |
840 | return -EOPNOTSUPP; | |
841 | } | |
842 | ||
2a8067f1 ED |
843 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
844 | { | |
845 | struct vcpu_svm *svm = to_svm(vcpu); | |
846 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
847 | ||
848 | if (is_external_interrupt(exit_int_info)) | |
849 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
850 | return -1; | |
851 | } | |
852 | ||
6aa8b732 AK |
853 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
854 | { | |
94dfbdb3 | 855 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 856 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 857 | #endif |
6aa8b732 AK |
858 | } |
859 | ||
860 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
861 | { | |
94dfbdb3 | 862 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 863 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 864 | #endif |
6aa8b732 AK |
865 | } |
866 | ||
e756fc62 | 867 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
868 | { |
869 | if (svm_data->next_asid > svm_data->max_asid) { | |
870 | ++svm_data->asid_generation; | |
871 | svm_data->next_asid = 1; | |
a2fa3e9f | 872 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
873 | } |
874 | ||
e756fc62 | 875 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
876 | svm->asid_generation = svm_data->asid_generation; |
877 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
878 | } |
879 | ||
6aa8b732 AK |
880 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
881 | { | |
a2fa3e9f | 882 | return to_svm(vcpu)->db_regs[dr]; |
6aa8b732 AK |
883 | } |
884 | ||
885 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
886 | int *exception) | |
887 | { | |
a2fa3e9f GH |
888 | struct vcpu_svm *svm = to_svm(vcpu); |
889 | ||
6aa8b732 AK |
890 | *exception = 0; |
891 | ||
a2fa3e9f GH |
892 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
893 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
894 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
895 | *exception = DB_VECTOR; |
896 | return; | |
897 | } | |
898 | ||
899 | switch (dr) { | |
900 | case 0 ... 3: | |
a2fa3e9f | 901 | svm->db_regs[dr] = value; |
6aa8b732 AK |
902 | return; |
903 | case 4 ... 5: | |
66aee91a | 904 | if (vcpu->cr4 & X86_CR4_DE) { |
6aa8b732 AK |
905 | *exception = UD_VECTOR; |
906 | return; | |
907 | } | |
908 | case 7: { | |
909 | if (value & ~((1ULL << 32) - 1)) { | |
910 | *exception = GP_VECTOR; | |
911 | return; | |
912 | } | |
a2fa3e9f | 913 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
914 | return; |
915 | } | |
916 | default: | |
917 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
918 | __FUNCTION__, dr); | |
919 | *exception = UD_VECTOR; | |
920 | return; | |
921 | } | |
922 | } | |
923 | ||
e756fc62 | 924 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 925 | { |
a2fa3e9f | 926 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 927 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
928 | u64 fault_address; |
929 | u32 error_code; | |
6aa8b732 | 930 | |
85f455f7 ED |
931 | if (!irqchip_in_kernel(kvm) && |
932 | is_external_interrupt(exit_int_info)) | |
e756fc62 | 933 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
6aa8b732 | 934 | |
a2fa3e9f GH |
935 | fault_address = svm->vmcb->control.exit_info_2; |
936 | error_code = svm->vmcb->control.exit_info_1; | |
3067714c | 937 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
938 | } |
939 | ||
7aa81cc0 AL |
940 | static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
941 | { | |
942 | int er; | |
943 | ||
3427318f | 944 | er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0); |
7aa81cc0 | 945 | if (er != EMULATE_DONE) |
7ee5d940 | 946 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
947 | return 1; |
948 | } | |
949 | ||
e756fc62 | 950 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 951 | { |
a2fa3e9f | 952 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
e756fc62 | 953 | if (!(svm->vcpu.cr0 & X86_CR0_TS)) |
a2fa3e9f | 954 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 955 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
956 | |
957 | return 1; | |
7807fa6c AL |
958 | } |
959 | ||
e756fc62 | 960 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
961 | { |
962 | /* | |
963 | * VMCB is undefined after a SHUTDOWN intercept | |
964 | * so reinitialize it. | |
965 | */ | |
a2fa3e9f GH |
966 | clear_page(svm->vmcb); |
967 | init_vmcb(svm->vmcb); | |
46fe4ddd JR |
968 | |
969 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
970 | return 0; | |
971 | } | |
972 | ||
e756fc62 | 973 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 974 | { |
d77c26fc | 975 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
039576c0 AK |
976 | int size, down, in, string, rep; |
977 | unsigned port; | |
6aa8b732 | 978 | |
e756fc62 | 979 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 980 | |
a2fa3e9f | 981 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 982 | |
e70669ab LV |
983 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
984 | ||
985 | if (string) { | |
3427318f LV |
986 | if (emulate_instruction(&svm->vcpu, |
987 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
988 | return 0; |
989 | return 1; | |
990 | } | |
991 | ||
039576c0 AK |
992 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
993 | port = io_info >> 16; | |
994 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 995 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 996 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 997 | |
3090dd73 | 998 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
999 | } |
1000 | ||
e756fc62 | 1001 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1002 | { |
1003 | return 1; | |
1004 | } | |
1005 | ||
e756fc62 | 1006 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1007 | { |
a2fa3e9f | 1008 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1009 | skip_emulated_instruction(&svm->vcpu); |
1010 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1011 | } |
1012 | ||
e756fc62 | 1013 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1014 | { |
a2fa3e9f | 1015 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 | 1016 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1017 | kvm_emulate_hypercall(&svm->vcpu); |
1018 | return 1; | |
02e235bc AK |
1019 | } |
1020 | ||
e756fc62 RR |
1021 | static int invalid_op_interception(struct vcpu_svm *svm, |
1022 | struct kvm_run *kvm_run) | |
6aa8b732 | 1023 | { |
7ee5d940 | 1024 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
1025 | return 1; |
1026 | } | |
1027 | ||
e756fc62 RR |
1028 | static int task_switch_interception(struct vcpu_svm *svm, |
1029 | struct kvm_run *kvm_run) | |
6aa8b732 | 1030 | { |
f0242478 | 1031 | pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__); |
6aa8b732 AK |
1032 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
1033 | return 0; | |
1034 | } | |
1035 | ||
e756fc62 | 1036 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1037 | { |
a2fa3e9f | 1038 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1039 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1040 | return 1; |
6aa8b732 AK |
1041 | } |
1042 | ||
e756fc62 RR |
1043 | static int emulate_on_interception(struct vcpu_svm *svm, |
1044 | struct kvm_run *kvm_run) | |
6aa8b732 | 1045 | { |
3427318f | 1046 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE) |
f0242478 | 1047 | pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__); |
6aa8b732 AK |
1048 | return 1; |
1049 | } | |
1050 | ||
1051 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) | |
1052 | { | |
a2fa3e9f GH |
1053 | struct vcpu_svm *svm = to_svm(vcpu); |
1054 | ||
6aa8b732 | 1055 | switch (ecx) { |
6aa8b732 AK |
1056 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1057 | u64 tsc; | |
1058 | ||
1059 | rdtscll(tsc); | |
a2fa3e9f | 1060 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1061 | break; |
1062 | } | |
0e859cac | 1063 | case MSR_K6_STAR: |
a2fa3e9f | 1064 | *data = svm->vmcb->save.star; |
6aa8b732 | 1065 | break; |
0e859cac | 1066 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1067 | case MSR_LSTAR: |
a2fa3e9f | 1068 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1069 | break; |
1070 | case MSR_CSTAR: | |
a2fa3e9f | 1071 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1072 | break; |
1073 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1074 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1075 | break; |
1076 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1077 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1078 | break; |
1079 | #endif | |
1080 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1081 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1082 | break; |
1083 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1084 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1085 | break; |
1086 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1087 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 AK |
1088 | break; |
1089 | default: | |
3bab1f5d | 1090 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1091 | } |
1092 | return 0; | |
1093 | } | |
1094 | ||
e756fc62 | 1095 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1096 | { |
e756fc62 | 1097 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1098 | u64 data; |
1099 | ||
e756fc62 | 1100 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 1101 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1102 | else { |
a2fa3e9f | 1103 | svm->vmcb->save.rax = data & 0xffffffff; |
e756fc62 | 1104 | svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1105 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1106 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1107 | } |
1108 | return 1; | |
1109 | } | |
1110 | ||
1111 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1112 | { | |
a2fa3e9f GH |
1113 | struct vcpu_svm *svm = to_svm(vcpu); |
1114 | ||
6aa8b732 | 1115 | switch (ecx) { |
6aa8b732 AK |
1116 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1117 | u64 tsc; | |
1118 | ||
1119 | rdtscll(tsc); | |
a2fa3e9f | 1120 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1121 | break; |
1122 | } | |
0e859cac | 1123 | case MSR_K6_STAR: |
a2fa3e9f | 1124 | svm->vmcb->save.star = data; |
6aa8b732 | 1125 | break; |
49b14f24 | 1126 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1127 | case MSR_LSTAR: |
a2fa3e9f | 1128 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1129 | break; |
1130 | case MSR_CSTAR: | |
a2fa3e9f | 1131 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1132 | break; |
1133 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1134 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1135 | break; |
1136 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1137 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1138 | break; |
1139 | #endif | |
1140 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1141 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1142 | break; |
1143 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1144 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1145 | break; |
1146 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1147 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 AK |
1148 | break; |
1149 | default: | |
3bab1f5d | 1150 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1151 | } |
1152 | return 0; | |
1153 | } | |
1154 | ||
e756fc62 | 1155 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1156 | { |
e756fc62 | 1157 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1158 | u64 data = (svm->vmcb->save.rax & -1u) |
e756fc62 | 1159 | | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32); |
a2fa3e9f | 1160 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1161 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 1162 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1163 | else |
e756fc62 | 1164 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1165 | return 1; |
1166 | } | |
1167 | ||
e756fc62 | 1168 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1169 | { |
e756fc62 RR |
1170 | if (svm->vmcb->control.exit_info_1) |
1171 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1172 | else |
e756fc62 | 1173 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1174 | } |
1175 | ||
e756fc62 | 1176 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1177 | struct kvm_run *kvm_run) |
1178 | { | |
85f455f7 ED |
1179 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); |
1180 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
c1150d8c DL |
1181 | /* |
1182 | * If the user space waits to inject interrupts, exit as soon as | |
1183 | * possible | |
1184 | */ | |
1185 | if (kvm_run->request_interrupt_window && | |
e756fc62 RR |
1186 | !svm->vcpu.irq_summary) { |
1187 | ++svm->vcpu.stat.irq_window_exits; | |
c1150d8c DL |
1188 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1189 | return 0; | |
1190 | } | |
1191 | ||
1192 | return 1; | |
1193 | } | |
1194 | ||
e756fc62 | 1195 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1196 | struct kvm_run *kvm_run) = { |
1197 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1198 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1199 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 1200 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
6aa8b732 AK |
1201 | /* for now: */ |
1202 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1203 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1204 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
80a8119c | 1205 | [SVM_EXIT_WRITE_CR8] = emulate_on_interception, |
6aa8b732 AK |
1206 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
1207 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1208 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1209 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1210 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1211 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1212 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1213 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1214 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1215 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
7aa81cc0 | 1216 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 1217 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 1218 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
6aa8b732 AK |
1219 | [SVM_EXIT_INTR] = nop_on_interception, |
1220 | [SVM_EXIT_NMI] = nop_on_interception, | |
1221 | [SVM_EXIT_SMI] = nop_on_interception, | |
1222 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1223 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1224 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1225 | [SVM_EXIT_CPUID] = cpuid_interception, | |
cf5a94d1 | 1226 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 AK |
1227 | [SVM_EXIT_HLT] = halt_interception, |
1228 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1229 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1230 | [SVM_EXIT_IOIO] = io_interception, | |
1231 | [SVM_EXIT_MSR] = msr_interception, | |
1232 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1233 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1234 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1235 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1236 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1237 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1238 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1239 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1240 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
cf5a94d1 | 1241 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
1242 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1243 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
6aa8b732 AK |
1244 | }; |
1245 | ||
1246 | ||
04d2cc77 | 1247 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 1248 | { |
04d2cc77 | 1249 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1250 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1251 | |
04d2cc77 AK |
1252 | kvm_reput_irq(svm); |
1253 | ||
1254 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
1255 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
1256 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1257 | = svm->vmcb->control.exit_code; | |
1258 | return 0; | |
1259 | } | |
1260 | ||
a2fa3e9f | 1261 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
6aa8b732 AK |
1262 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR) |
1263 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " | |
1264 | "exit_code 0x%x\n", | |
a2fa3e9f | 1265 | __FUNCTION__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1266 | exit_code); |
1267 | ||
9d8f549d | 1268 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 1269 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 1270 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 1271 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1272 | return 0; |
1273 | } | |
1274 | ||
e756fc62 | 1275 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1276 | } |
1277 | ||
1278 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1279 | { | |
1280 | int cpu = raw_smp_processor_id(); | |
1281 | ||
1282 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 1283 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
1284 | load_TR_desc(); |
1285 | } | |
1286 | ||
e756fc62 | 1287 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1288 | { |
1289 | int cpu = raw_smp_processor_id(); | |
1290 | ||
1291 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1292 | ||
a2fa3e9f | 1293 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1294 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1295 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1296 | new_asid(svm, svm_data); |
6aa8b732 AK |
1297 | } |
1298 | ||
1299 | ||
85f455f7 | 1300 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
1301 | { |
1302 | struct vmcb_control_area *control; | |
1303 | ||
e756fc62 | 1304 | control = &svm->vmcb->control; |
85f455f7 | 1305 | control->int_vector = irq; |
6aa8b732 AK |
1306 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1307 | control->int_ctl |= V_IRQ_MASK | | |
1308 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1309 | } | |
1310 | ||
2a8067f1 ED |
1311 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
1312 | { | |
1313 | struct vcpu_svm *svm = to_svm(vcpu); | |
1314 | ||
1315 | svm_inject_irq(svm, irq); | |
1316 | } | |
1317 | ||
04d2cc77 | 1318 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 1319 | { |
04d2cc77 | 1320 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
1321 | struct vmcb *vmcb = svm->vmcb; |
1322 | int intr_vector = -1; | |
1323 | ||
1324 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && | |
1325 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
1326 | intr_vector = vmcb->control.exit_int_info & | |
1327 | SVM_EVTINJ_VEC_MASK; | |
1328 | vmcb->control.exit_int_info = 0; | |
1329 | svm_inject_irq(svm, intr_vector); | |
1330 | return; | |
1331 | } | |
1332 | ||
1333 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
1334 | return; | |
1335 | ||
1b9778da | 1336 | if (!kvm_cpu_has_interrupt(vcpu)) |
85f455f7 ED |
1337 | return; |
1338 | ||
1339 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || | |
1340 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
1341 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
1342 | /* unable to deliver irq, set pending irq */ | |
1343 | vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); | |
1344 | svm_inject_irq(svm, 0x0); | |
1345 | return; | |
1346 | } | |
1347 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 1348 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 1349 | svm_inject_irq(svm, intr_vector); |
1b9778da | 1350 | kvm_timer_intr_post(vcpu, intr_vector); |
85f455f7 ED |
1351 | } |
1352 | ||
1353 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
1354 | { | |
e756fc62 | 1355 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 1356 | |
7017fc3d ED |
1357 | if ((control->int_ctl & V_IRQ_MASK) |
1358 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 1359 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 1360 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1361 | } |
c1150d8c | 1362 | |
e756fc62 | 1363 | svm->vcpu.interrupt_window_open = |
c1150d8c DL |
1364 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1365 | } | |
1366 | ||
85f455f7 ED |
1367 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
1368 | { | |
1369 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
1370 | int word_index = __ffs(vcpu->irq_summary); | |
1371 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
1372 | int irq = word_index * BITS_PER_LONG + bit_index; | |
1373 | ||
1374 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
1375 | if (!vcpu->irq_pending[word_index]) | |
1376 | clear_bit(word_index, &vcpu->irq_summary); | |
1377 | svm_inject_irq(svm, irq); | |
1378 | } | |
1379 | ||
04d2cc77 | 1380 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
1381 | struct kvm_run *kvm_run) |
1382 | { | |
04d2cc77 | 1383 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1384 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1385 | |
e756fc62 | 1386 | svm->vcpu.interrupt_window_open = |
c1150d8c | 1387 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1388 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1389 | |
e756fc62 | 1390 | if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary) |
c1150d8c DL |
1391 | /* |
1392 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1393 | */ | |
85f455f7 | 1394 | svm_do_inject_vector(svm); |
c1150d8c DL |
1395 | |
1396 | /* | |
1397 | * Interrupts blocked. Wait for unblock. | |
1398 | */ | |
e756fc62 | 1399 | if (!svm->vcpu.interrupt_window_open && |
d77c26fc | 1400 | (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) |
c1150d8c | 1401 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
d77c26fc | 1402 | else |
c1150d8c DL |
1403 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); |
1404 | } | |
1405 | ||
cbc94022 IE |
1406 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1407 | { | |
1408 | return 0; | |
1409 | } | |
1410 | ||
6aa8b732 AK |
1411 | static void save_db_regs(unsigned long *db_regs) |
1412 | { | |
5aff458e AK |
1413 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1414 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1415 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1416 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1417 | } |
1418 | ||
1419 | static void load_db_regs(unsigned long *db_regs) | |
1420 | { | |
5aff458e AK |
1421 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1422 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1423 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1424 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1425 | } |
1426 | ||
d9e368d6 AK |
1427 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1428 | { | |
1429 | force_new_asid(vcpu); | |
1430 | } | |
1431 | ||
04d2cc77 AK |
1432 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
1433 | { | |
1434 | } | |
1435 | ||
1436 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
6aa8b732 | 1437 | { |
a2fa3e9f | 1438 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1439 | u16 fs_selector; |
1440 | u16 gs_selector; | |
1441 | u16 ldt_selector; | |
d9e368d6 | 1442 | |
e756fc62 | 1443 | pre_svm_run(svm); |
6aa8b732 AK |
1444 | |
1445 | save_host_msrs(vcpu); | |
1446 | fs_selector = read_fs(); | |
1447 | gs_selector = read_gs(); | |
1448 | ldt_selector = read_ldt(); | |
a2fa3e9f GH |
1449 | svm->host_cr2 = kvm_read_cr2(); |
1450 | svm->host_dr6 = read_dr6(); | |
1451 | svm->host_dr7 = read_dr7(); | |
1452 | svm->vmcb->save.cr2 = vcpu->cr2; | |
6aa8b732 | 1453 | |
a2fa3e9f | 1454 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1455 | write_dr7(0); |
a2fa3e9f GH |
1456 | save_db_regs(svm->host_db_regs); |
1457 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1458 | } |
36241b8c | 1459 | |
04d2cc77 AK |
1460 | clgi(); |
1461 | ||
1462 | local_irq_enable(); | |
36241b8c | 1463 | |
6aa8b732 | 1464 | asm volatile ( |
05b3e0c2 | 1465 | #ifdef CONFIG_X86_64 |
54a08c04 | 1466 | "push %%rbp; \n\t" |
6aa8b732 | 1467 | #else |
fe7935d4 | 1468 | "push %%ebp; \n\t" |
6aa8b732 AK |
1469 | #endif |
1470 | ||
05b3e0c2 | 1471 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1472 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1473 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1474 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1475 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1476 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1477 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1478 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1479 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1480 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1481 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1482 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1483 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1484 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1485 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1486 | #else |
fb3f0f51 RR |
1487 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1488 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1489 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1490 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1491 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1492 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1493 | #endif |
1494 | ||
05b3e0c2 | 1495 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1496 | /* Enter guest mode */ |
1497 | "push %%rax \n\t" | |
fb3f0f51 | 1498 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
6aa8b732 AK |
1499 | SVM_VMLOAD "\n\t" |
1500 | SVM_VMRUN "\n\t" | |
1501 | SVM_VMSAVE "\n\t" | |
1502 | "pop %%rax \n\t" | |
1503 | #else | |
1504 | /* Enter guest mode */ | |
1505 | "push %%eax \n\t" | |
fb3f0f51 | 1506 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
6aa8b732 AK |
1507 | SVM_VMLOAD "\n\t" |
1508 | SVM_VMRUN "\n\t" | |
1509 | SVM_VMSAVE "\n\t" | |
1510 | "pop %%eax \n\t" | |
1511 | #endif | |
1512 | ||
1513 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1514 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1515 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1516 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1517 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1518 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1519 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1520 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1521 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1522 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1523 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1524 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1525 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1526 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1527 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1528 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 1529 | |
54a08c04 | 1530 | "pop %%rbp; \n\t" |
6aa8b732 | 1531 | #else |
fb3f0f51 RR |
1532 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1533 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1534 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1535 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1536 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1537 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 | 1538 | |
fe7935d4 | 1539 | "pop %%ebp; \n\t" |
6aa8b732 AK |
1540 | #endif |
1541 | : | |
fb3f0f51 | 1542 | : [svm]"a"(svm), |
6aa8b732 | 1543 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
d77c26fc MD |
1544 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RBX])), |
1545 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RCX])), | |
1546 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RDX])), | |
1547 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RSI])), | |
1548 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RDI])), | |
1549 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1550 | #ifdef CONFIG_X86_64 |
d77c26fc MD |
1551 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R8])), |
1552 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R9])), | |
1553 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R10])), | |
1554 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R11])), | |
1555 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R12])), | |
1556 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R13])), | |
1557 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R14])), | |
1558 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R15])) | |
6aa8b732 | 1559 | #endif |
54a08c04 LV |
1560 | : "cc", "memory" |
1561 | #ifdef CONFIG_X86_64 | |
1562 | , "rbx", "rcx", "rdx", "rsi", "rdi" | |
1563 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" | |
fe7935d4 LV |
1564 | #else |
1565 | , "ebx", "ecx", "edx" , "esi", "edi" | |
54a08c04 LV |
1566 | #endif |
1567 | ); | |
6aa8b732 | 1568 | |
a2fa3e9f GH |
1569 | if ((svm->vmcb->save.dr7 & 0xff)) |
1570 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1571 | |
a2fa3e9f | 1572 | vcpu->cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1573 | |
a2fa3e9f GH |
1574 | write_dr6(svm->host_dr6); |
1575 | write_dr7(svm->host_dr7); | |
1576 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 AK |
1577 | |
1578 | load_fs(fs_selector); | |
1579 | load_gs(gs_selector); | |
1580 | load_ldt(ldt_selector); | |
1581 | load_host_msrs(vcpu); | |
1582 | ||
1583 | reload_tss(vcpu); | |
1584 | ||
56ba47dd AK |
1585 | local_irq_disable(); |
1586 | ||
1587 | stgi(); | |
1588 | ||
a2fa3e9f | 1589 | svm->next_rip = 0; |
6aa8b732 AK |
1590 | } |
1591 | ||
6aa8b732 AK |
1592 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1593 | { | |
a2fa3e9f GH |
1594 | struct vcpu_svm *svm = to_svm(vcpu); |
1595 | ||
1596 | svm->vmcb->save.cr3 = root; | |
6aa8b732 | 1597 | force_new_asid(vcpu); |
7807fa6c AL |
1598 | |
1599 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1600 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1601 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1602 | vcpu->fpu_active = 0; |
1603 | } | |
6aa8b732 AK |
1604 | } |
1605 | ||
6aa8b732 AK |
1606 | static int is_disabled(void) |
1607 | { | |
6031a61c JR |
1608 | u64 vm_cr; |
1609 | ||
1610 | rdmsrl(MSR_VM_CR, vm_cr); | |
1611 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1612 | return 1; | |
1613 | ||
6aa8b732 AK |
1614 | return 0; |
1615 | } | |
1616 | ||
102d8325 IM |
1617 | static void |
1618 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1619 | { | |
1620 | /* | |
1621 | * Patch in the VMMCALL instruction: | |
1622 | */ | |
1623 | hypercall[0] = 0x0f; | |
1624 | hypercall[1] = 0x01; | |
1625 | hypercall[2] = 0xd9; | |
102d8325 IM |
1626 | } |
1627 | ||
002c7f7c YS |
1628 | static void svm_check_processor_compat(void *rtn) |
1629 | { | |
1630 | *(int *)rtn = 0; | |
1631 | } | |
1632 | ||
cbdd1bea | 1633 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
1634 | .cpu_has_kvm_support = has_svm, |
1635 | .disabled_by_bios = is_disabled, | |
1636 | .hardware_setup = svm_hardware_setup, | |
1637 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1638 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1639 | .hardware_enable = svm_hardware_enable, |
1640 | .hardware_disable = svm_hardware_disable, | |
1641 | ||
1642 | .vcpu_create = svm_create_vcpu, | |
1643 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 1644 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 1645 | |
04d2cc77 | 1646 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
1647 | .vcpu_load = svm_vcpu_load, |
1648 | .vcpu_put = svm_vcpu_put, | |
774c47f1 | 1649 | .vcpu_decache = svm_vcpu_decache, |
6aa8b732 AK |
1650 | |
1651 | .set_guest_debug = svm_guest_debug, | |
1652 | .get_msr = svm_get_msr, | |
1653 | .set_msr = svm_set_msr, | |
1654 | .get_segment_base = svm_get_segment_base, | |
1655 | .get_segment = svm_get_segment, | |
1656 | .set_segment = svm_set_segment, | |
1747fb71 | 1657 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 1658 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1659 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1660 | .set_cr3 = svm_set_cr3, |
1661 | .set_cr4 = svm_set_cr4, | |
1662 | .set_efer = svm_set_efer, | |
1663 | .get_idt = svm_get_idt, | |
1664 | .set_idt = svm_set_idt, | |
1665 | .get_gdt = svm_get_gdt, | |
1666 | .set_gdt = svm_set_gdt, | |
1667 | .get_dr = svm_get_dr, | |
1668 | .set_dr = svm_set_dr, | |
1669 | .cache_regs = svm_cache_regs, | |
1670 | .decache_regs = svm_decache_regs, | |
1671 | .get_rflags = svm_get_rflags, | |
1672 | .set_rflags = svm_set_rflags, | |
1673 | ||
6aa8b732 | 1674 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 1675 | |
6aa8b732 | 1676 | .run = svm_vcpu_run, |
04d2cc77 | 1677 | .handle_exit = handle_exit, |
6aa8b732 | 1678 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 1679 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
1680 | .get_irq = svm_get_irq, |
1681 | .set_irq = svm_set_irq, | |
298101da AK |
1682 | .queue_exception = svm_queue_exception, |
1683 | .exception_injected = svm_exception_injected, | |
04d2cc77 AK |
1684 | .inject_pending_irq = svm_intr_assist, |
1685 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
1686 | |
1687 | .set_tss_addr = svm_set_tss_addr, | |
6aa8b732 AK |
1688 | }; |
1689 | ||
1690 | static int __init svm_init(void) | |
1691 | { | |
cb498ea2 | 1692 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 1693 | THIS_MODULE); |
6aa8b732 AK |
1694 | } |
1695 | ||
1696 | static void __exit svm_exit(void) | |
1697 | { | |
cb498ea2 | 1698 | kvm_exit(); |
6aa8b732 AK |
1699 | } |
1700 | ||
1701 | module_init(svm_init) | |
1702 | module_exit(svm_exit) |