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KVM: Portability: Move address types to their own header file
[deliverable/linux.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
34c16eec 19#include "x86.h"
e7d5d76c 20#include "x86_emulate.h"
85f455f7 21#include "irq.h"
6aa8b732 22#include "vmx.h"
e495606d
AK		 23#include "segment_descriptor.h"
24
6aa8b732 25#include <linux/module.h>
9d8f549d 26#include <linux/kernel.h>
6aa8b732
AK		 27#include <linux/mm.h>
28#include <linux/highmem.h>
e8edc6e0 29#include <linux/sched.h>
c7addb90 30#include <linux/moduleparam.h>
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
6aa8b732 34
6aa8b732
AK		 35MODULE_AUTHOR("Qumranet");
36MODULE_LICENSE("GPL");
37
c7addb90
AK		 38static int bypass_guest_pf = 1;
39module_param(bypass_guest_pf, bool, 0);
40
a2fa3e9f
GH		 41struct vmcs {
42 u32 revision_id;
43 u32 abort;
44 char data[0];
45};
46
47struct vcpu_vmx {
fb3f0f51 48 struct kvm_vcpu vcpu;
a2fa3e9f 49 int launched;
29bd8a78 50 u8 fail;
1155f76a 51 u32 idt_vectoring_info;
a2fa3e9f
GH		 52 struct kvm_msr_entry *guest_msrs;
53 struct kvm_msr_entry *host_msrs;
54 int nmsrs;
55 int save_nmsrs;
56 int msr_offset_efer;
57#ifdef CONFIG_X86_64
58 int msr_offset_kernel_gs_base;
59#endif
60 struct vmcs *vmcs;
61 struct {
62 int loaded;
63 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 64 int gs_ldt_reload_needed;
65 int fs_reload_needed;
51c6cf66 66 int guest_efer_loaded;
d77c26fc 67 } host_state;
9c8cba37
AK		 68 struct {
69 struct {
70 bool pending;
71 u8 vector;
72 unsigned rip;
73 } irq;
74 } rmode;
a2fa3e9f
GH		 75};
76
77static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
78{
fb3f0f51 79 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 80}
81
75880a01
AK		 82static int init_rmode_tss(struct kvm *kvm);
83
6aa8b732
AK		 84static DEFINE_PER_CPU(struct vmcs *, vmxarea);
85static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
86
fdef3ad1
HQ		 87static struct page *vmx_io_bitmap_a;
88static struct page *vmx_io_bitmap_b;
89
1c3d14fe 90static struct vmcs_config {
6aa8b732
AK		 91 int size;
92 int order;
93 u32 revision_id;
1c3d14fe
YS		 94 u32 pin_based_exec_ctrl;
95 u32 cpu_based_exec_ctrl;
f78e0e2e 96 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 97 u32 vmexit_ctrl;
98 u32 vmentry_ctrl;
99} vmcs_config;
6aa8b732
AK		 100
101#define VMX_SEGMENT_FIELD(seg) \
102 [VCPU_SREG_##seg] = { \
103 .selector = GUEST_##seg##_SELECTOR, \
104 .base = GUEST_##seg##_BASE, \
105 .limit = GUEST_##seg##_LIMIT, \
106 .ar_bytes = GUEST_##seg##_AR_BYTES, \
107 }
108
109static struct kvm_vmx_segment_field {
110 unsigned selector;
111 unsigned base;
112 unsigned limit;
113 unsigned ar_bytes;
114} kvm_vmx_segment_fields[] = {
115 VMX_SEGMENT_FIELD(CS),
116 VMX_SEGMENT_FIELD(DS),
117 VMX_SEGMENT_FIELD(ES),
118 VMX_SEGMENT_FIELD(FS),
119 VMX_SEGMENT_FIELD(GS),
120 VMX_SEGMENT_FIELD(SS),
121 VMX_SEGMENT_FIELD(TR),
122 VMX_SEGMENT_FIELD(LDTR),
123};
124
4d56c8a7
AK		 125/*
126 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
127 * away by decrementing the array size.
128 */
6aa8b732 129static const u32 vmx_msr_index[] = {
05b3e0c2 130#ifdef CONFIG_X86_64
6aa8b732
AK		 131 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
132#endif
133 MSR_EFER, MSR_K6_STAR,
134};
9d8f549d 135#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 136
a2fa3e9f
GH		 137static void load_msrs(struct kvm_msr_entry *e, int n)
138{
139 int i;
140
141 for (i = 0; i < n; ++i)
142 wrmsrl(e[i].index, e[i].data);
143}
144
145static void save_msrs(struct kvm_msr_entry *e, int n)
146{
147 int i;
148
149 for (i = 0; i < n; ++i)
150 rdmsrl(e[i].index, e[i].data);
151}
152
6aa8b732
AK		 153static inline int is_page_fault(u32 intr_info)
154{
155 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
156 INTR_INFO_VALID_MASK)) ==
157 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
158}
159
2ab455cc
AL		 160static inline int is_no_device(u32 intr_info)
161{
162 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
163 INTR_INFO_VALID_MASK)) ==
164 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
165}
166
7aa81cc0
AL		 167static inline int is_invalid_opcode(u32 intr_info)
168{
169 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
170 INTR_INFO_VALID_MASK)) ==
171 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
172}
173
6aa8b732
AK		 174static inline int is_external_interrupt(u32 intr_info)
175{
176 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
177 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
178}
179
6e5d865c
YS		 180static inline int cpu_has_vmx_tpr_shadow(void)
181{
182 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
183}
184
185static inline int vm_need_tpr_shadow(struct kvm *kvm)
186{
187 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
188}
189
f78e0e2e
SY		 190static inline int cpu_has_secondary_exec_ctrls(void)
191{
192 return (vmcs_config.cpu_based_exec_ctrl &
193 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
194}
195
f78e0e2e
SY		 196static inline int cpu_has_vmx_virtualize_apic_accesses(void)
197{
198 return (vmcs_config.cpu_based_2nd_exec_ctrl &
199 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
200}
201
202static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
203{
204 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
205 (irqchip_in_kernel(kvm)));
206}
207
8b9cf98c 208static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 209{
210 int i;
211
a2fa3e9f
GH		 212 for (i = 0; i < vmx->nmsrs; ++i)
213 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 214 return i;
215 return -1;
216}
217
8b9cf98c 218static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 219{
220 int i;
221
8b9cf98c 222 i = __find_msr_index(vmx, msr);
a75beee6 223 if (i >= 0)
a2fa3e9f 224 return &vmx->guest_msrs[i];
8b6d44c7 225 return NULL;
7725f0ba
AK		 226}
227
6aa8b732
AK		 228static void vmcs_clear(struct vmcs *vmcs)
229{
230 u64 phys_addr = __pa(vmcs);
231 u8 error;
232
233 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
234 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
235 : "cc", "memory");
236 if (error)
237 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
238 vmcs, phys_addr);
239}
240
241static void __vcpu_clear(void *arg)
242{
8b9cf98c 243 struct vcpu_vmx *vmx = arg;
d3b2c338 244 int cpu = raw_smp_processor_id();
6aa8b732 245
8b9cf98c 246 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 247 vmcs_clear(vmx->vmcs);
248 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 249 per_cpu(current_vmcs, cpu) = NULL;
8b9cf98c 250 rdtscll(vmx->vcpu.host_tsc);
6aa8b732
AK		 251}
252
8b9cf98c 253static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 254{
eae5ecb5
AK		 255 if (vmx->vcpu.cpu == -1)
256 return;
f566e09f 257 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
8b9cf98c 258 vmx->launched = 0;
8d0be2b3
AK		 259}
260
6aa8b732
AK		 261static unsigned long vmcs_readl(unsigned long field)
262{
263 unsigned long value;
264
265 asm volatile (ASM_VMX_VMREAD_RDX_RAX
266 : "=a"(value) : "d"(field) : "cc");
267 return value;
268}
269
270static u16 vmcs_read16(unsigned long field)
271{
272 return vmcs_readl(field);
273}
274
275static u32 vmcs_read32(unsigned long field)
276{
277 return vmcs_readl(field);
278}
279
280static u64 vmcs_read64(unsigned long field)
281{
05b3e0c2 282#ifdef CONFIG_X86_64
6aa8b732
AK		 283 return vmcs_readl(field);
284#else
285 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
286#endif
287}
288
e52de1b8
AK		 289static noinline void vmwrite_error(unsigned long field, unsigned long value)
290{
291 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
292 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
293 dump_stack();
294}
295
6aa8b732
AK		 296static void vmcs_writel(unsigned long field, unsigned long value)
297{
298 u8 error;
299
300 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
d77c26fc 301 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 302 if (unlikely(error))
303 vmwrite_error(field, value);
6aa8b732
AK		 304}
305
306static void vmcs_write16(unsigned long field, u16 value)
307{
308 vmcs_writel(field, value);
309}
310
311static void vmcs_write32(unsigned long field, u32 value)
312{
313 vmcs_writel(field, value);
314}
315
316static void vmcs_write64(unsigned long field, u64 value)
317{
05b3e0c2 318#ifdef CONFIG_X86_64
6aa8b732
AK		 319 vmcs_writel(field, value);
320#else
321 vmcs_writel(field, value);
322 asm volatile ("");
323 vmcs_writel(field+1, value >> 32);
324#endif
325}
326
2ab455cc
AL		 327static void vmcs_clear_bits(unsigned long field, u32 mask)
328{
329 vmcs_writel(field, vmcs_readl(field) & ~mask);
330}
331
332static void vmcs_set_bits(unsigned long field, u32 mask)
333{
334 vmcs_writel(field, vmcs_readl(field) | mask);
335}
336
abd3f2d6
AK		 337static void update_exception_bitmap(struct kvm_vcpu *vcpu)
338{
339 u32 eb;
340
7aa81cc0 341 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 342 if (!vcpu->fpu_active)
343 eb |= 1u << NM_VECTOR;
344 if (vcpu->guest_debug.enabled)
345 eb |= 1u << 1;
346 if (vcpu->rmode.active)
347 eb = ~0;
348 vmcs_write32(EXCEPTION_BITMAP, eb);
349}
350
33ed6329
AK		 351static void reload_tss(void)
352{
353#ifndef CONFIG_X86_64
354
355 /*
356 * VT restores TR but not its size. Useless.
357 */
358 struct descriptor_table gdt;
359 struct segment_descriptor *descs;
360
361 get_gdt(&gdt);
362 descs = (void *)gdt.base;
363 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
364 load_TR_desc();
365#endif
366}
367
8b9cf98c 368static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 369{
a2fa3e9f 370 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 371 u64 host_efer = vmx->host_msrs[efer_offset].data;
372 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
373 u64 ignore_bits;
374
375 if (efer_offset < 0)
376 return;
377 /*
378 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
379 * outside long mode
380 */
381 ignore_bits = EFER_NX | EFER_SCE;
382#ifdef CONFIG_X86_64
383 ignore_bits |= EFER_LMA | EFER_LME;
384 /* SCE is meaningful only in long mode on Intel */
385 if (guest_efer & EFER_LMA)
386 ignore_bits &= ~(u64)EFER_SCE;
387#endif
388 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
389 return;
2cc51560 390
51c6cf66
AK		 391 vmx->host_state.guest_efer_loaded = 1;
392 guest_efer &= ~ignore_bits;
393 guest_efer |= host_efer & ignore_bits;
394 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 395 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 396}
397
51c6cf66
AK		 398static void reload_host_efer(struct vcpu_vmx *vmx)
399{
400 if (vmx->host_state.guest_efer_loaded) {
401 vmx->host_state.guest_efer_loaded = 0;
402 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
403 }
404}
405
04d2cc77 406static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 407{
04d2cc77
AK		 408 struct vcpu_vmx *vmx = to_vmx(vcpu);
409
a2fa3e9f 410 if (vmx->host_state.loaded)
33ed6329
AK		 411 return;
412
a2fa3e9f 413 vmx->host_state.loaded = 1;
33ed6329
AK		 414 /*
415 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
416 * allow segment selectors with cpl > 0 or ti == 1.
417 */
a2fa3e9f 418 vmx->host_state.ldt_sel = read_ldt();
152d3f2f 419 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
a2fa3e9f 420 vmx->host_state.fs_sel = read_fs();
152d3f2f 421 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 422 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 423 vmx->host_state.fs_reload_needed = 0;
424 } else {
33ed6329 425 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 426 vmx->host_state.fs_reload_needed = 1;
33ed6329 427 }
a2fa3e9f
GH		 428 vmx->host_state.gs_sel = read_gs();
429 if (!(vmx->host_state.gs_sel & 7))
430 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 431 else {
432 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 433 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 434 }
435
436#ifdef CONFIG_X86_64
437 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
438 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
439#else
a2fa3e9f
GH		 440 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
441 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 442#endif
707c0874
AK		 443
444#ifdef CONFIG_X86_64
d77c26fc 445 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 446 save_msrs(vmx->host_msrs +
447 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 448
707c0874 449#endif
a2fa3e9f 450 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 451 load_transition_efer(vmx);
33ed6329
AK		 452}
453
8b9cf98c 454static void vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 455{
15ad7146 456 unsigned long flags;
33ed6329 457
a2fa3e9f 458 if (!vmx->host_state.loaded)
33ed6329
AK		 459 return;
460
e1beb1d3 461 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 462 vmx->host_state.loaded = 0;
152d3f2f 463 if (vmx->host_state.fs_reload_needed)
a2fa3e9f 464 load_fs(vmx->host_state.fs_sel);
152d3f2f
LV		 465 if (vmx->host_state.gs_ldt_reload_needed) {
466 load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 467 /*
468 * If we have to reload gs, we must take care to
469 * preserve our gs base.
470 */
15ad7146 471 local_irq_save(flags);
a2fa3e9f 472 load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 473#ifdef CONFIG_X86_64
474 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
475#endif
15ad7146 476 local_irq_restore(flags);
33ed6329 477 }
152d3f2f 478 reload_tss();
a2fa3e9f
GH		 479 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
480 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 481 reload_host_efer(vmx);
33ed6329
AK		 482}
483
6aa8b732
AK		 484/*
485 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
486 * vcpu mutex is already taken.
487 */
15ad7146 488static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 489{
a2fa3e9f
GH		 490 struct vcpu_vmx *vmx = to_vmx(vcpu);
491 u64 phys_addr = __pa(vmx->vmcs);
7700270e 492 u64 tsc_this, delta;
6aa8b732 493
a3d7f85f 494 if (vcpu->cpu != cpu) {
8b9cf98c 495 vcpu_clear(vmx);
a3d7f85f
ED		 496 kvm_migrate_apic_timer(vcpu);
497 }
6aa8b732 498
a2fa3e9f 499 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 500 u8 error;
501
a2fa3e9f 502 per_cpu(current_vmcs, cpu) = vmx->vmcs;
6aa8b732
AK		 503 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
504 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
505 : "cc");
506 if (error)
507 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 508 vmx->vmcs, phys_addr);
6aa8b732
AK		 509 }
510
511 if (vcpu->cpu != cpu) {
512 struct descriptor_table dt;
513 unsigned long sysenter_esp;
514
515 vcpu->cpu = cpu;
516 /*
517 * Linux uses per-cpu TSS and GDT, so set these when switching
518 * processors.
519 */
520 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
521 get_gdt(&dt);
522 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
523
524 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
525 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 526
527 /*
528 * Make sure the time stamp counter is monotonous.
529 */
530 rdtscll(tsc_this);
531 delta = vcpu->host_tsc - tsc_this;
532 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
6aa8b732 533 }
6aa8b732
AK		 534}
535
536static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
537{
8b9cf98c 538 vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 539}
540
5fd86fcf
AK		 541static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
542{
543 if (vcpu->fpu_active)
544 return;
545 vcpu->fpu_active = 1;
707d92fa
RR		 546 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
547 if (vcpu->cr0 & X86_CR0_TS)
548 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 549 update_exception_bitmap(vcpu);
550}
551
552static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
553{
554 if (!vcpu->fpu_active)
555 return;
556 vcpu->fpu_active = 0;
707d92fa 557 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 558 update_exception_bitmap(vcpu);
559}
560
774c47f1
AK		 561static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
562{
8b9cf98c 563 vcpu_clear(to_vmx(vcpu));
774c47f1
AK		 564}
565
6aa8b732
AK		 566static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
567{
568 return vmcs_readl(GUEST_RFLAGS);
569}
570
571static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
572{
78f78268 573 if (vcpu->rmode.active)
053de044 574 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 575 vmcs_writel(GUEST_RFLAGS, rflags);
576}
577
578static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
579{
580 unsigned long rip;
581 u32 interruptibility;
582
583 rip = vmcs_readl(GUEST_RIP);
584 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
585 vmcs_writel(GUEST_RIP, rip);
586
587 /*
588 * We emulated an instruction, so temporary interrupt blocking
589 * should be removed, if set.
590 */
591 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
592 if (interruptibility & 3)
593 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
594 interruptibility & ~3);
c1150d8c 595 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 596}
597
598static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
599{
600 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
601 vmcs_readl(GUEST_RIP));
602 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
603 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
604 GP_VECTOR |
605 INTR_TYPE_EXCEPTION |
606 INTR_INFO_DELIEVER_CODE_MASK |
607 INTR_INFO_VALID_MASK);
608}
609
7aa81cc0
AL		 610static void vmx_inject_ud(struct kvm_vcpu *vcpu)
611{
612 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
613 UD_VECTOR |
614 INTR_TYPE_EXCEPTION |
615 INTR_INFO_VALID_MASK);
616}
617
a75beee6
ED		 618/*
619 * Swap MSR entry in host/guest MSR entry array.
620 */
54e11fa1 621#ifdef CONFIG_X86_64
8b9cf98c 622static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 623{
a2fa3e9f
GH		 624 struct kvm_msr_entry tmp;
625
626 tmp = vmx->guest_msrs[to];
627 vmx->guest_msrs[to] = vmx->guest_msrs[from];
628 vmx->guest_msrs[from] = tmp;
629 tmp = vmx->host_msrs[to];
630 vmx->host_msrs[to] = vmx->host_msrs[from];
631 vmx->host_msrs[from] = tmp;
a75beee6 632}
54e11fa1 633#endif
a75beee6 634
e38aea3e
AK		 635/*
636 * Set up the vmcs to automatically save and restore system
637 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
638 * mode, as fiddling with msrs is very expensive.
639 */
8b9cf98c 640static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 641{
2cc51560 642 int save_nmsrs;
e38aea3e 643
a75beee6
ED		 644 save_nmsrs = 0;
645#ifdef CONFIG_X86_64
8b9cf98c 646 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 647 int index;
648
8b9cf98c 649 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 650 if (index >= 0)
8b9cf98c
RR		 651 move_msr_up(vmx, index, save_nmsrs++);
652 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 653 if (index >= 0)
8b9cf98c
RR		 654 move_msr_up(vmx, index, save_nmsrs++);
655 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 656 if (index >= 0)
8b9cf98c
RR		 657 move_msr_up(vmx, index, save_nmsrs++);
658 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 659 if (index >= 0)
8b9cf98c 660 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 661 /*
662 * MSR_K6_STAR is only needed on long mode guests, and only
663 * if efer.sce is enabled.
664 */
8b9cf98c
RR		 665 index = __find_msr_index(vmx, MSR_K6_STAR);
666 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
667 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 668 }
669#endif
a2fa3e9f 670 vmx->save_nmsrs = save_nmsrs;
e38aea3e 671
4d56c8a7 672#ifdef CONFIG_X86_64
a2fa3e9f 673 vmx->msr_offset_kernel_gs_base =
8b9cf98c 674 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 675#endif
8b9cf98c 676 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 677}
678
6aa8b732
AK		 679/*
680 * reads and returns guest's timestamp counter "register"
681 * guest_tsc = host_tsc + tsc_offset -- 21.3
682 */
683static u64 guest_read_tsc(void)
684{
685 u64 host_tsc, tsc_offset;
686
687 rdtscll(host_tsc);
688 tsc_offset = vmcs_read64(TSC_OFFSET);
689 return host_tsc + tsc_offset;
690}
691
692/*
693 * writes 'guest_tsc' into guest's timestamp counter "register"
694 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
695 */
696static void guest_write_tsc(u64 guest_tsc)
697{
698 u64 host_tsc;
699
700 rdtscll(host_tsc);
701 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
702}
703
6aa8b732
AK		 704/*
705 * Reads an msr value (of 'msr_index') into 'pdata'.
706 * Returns 0 on success, non-0 otherwise.
707 * Assumes vcpu_load() was already called.
708 */
709static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
710{
711 u64 data;
a2fa3e9f 712 struct kvm_msr_entry *msr;
6aa8b732
AK		 713
714 if (!pdata) {
715 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
716 return -EINVAL;
717 }
718
719 switch (msr_index) {
05b3e0c2 720#ifdef CONFIG_X86_64
6aa8b732
AK		 721 case MSR_FS_BASE:
722 data = vmcs_readl(GUEST_FS_BASE);
723 break;
724 case MSR_GS_BASE:
725 data = vmcs_readl(GUEST_GS_BASE);
726 break;
727 case MSR_EFER:
3bab1f5d 728 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 729#endif
730 case MSR_IA32_TIME_STAMP_COUNTER:
731 data = guest_read_tsc();
732 break;
733 case MSR_IA32_SYSENTER_CS:
734 data = vmcs_read32(GUEST_SYSENTER_CS);
735 break;
736 case MSR_IA32_SYSENTER_EIP:
f5b42c33 737 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 738 break;
739 case MSR_IA32_SYSENTER_ESP:
f5b42c33 740 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 741 break;
6aa8b732 742 default:
8b9cf98c 743 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 744 if (msr) {
745 data = msr->data;
746 break;
6aa8b732 747 }
3bab1f5d 748 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 749 }
750
751 *pdata = data;
752 return 0;
753}
754
755/*
756 * Writes msr value into into the appropriate "register".
757 * Returns 0 on success, non-0 otherwise.
758 * Assumes vcpu_load() was already called.
759 */
760static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
761{
a2fa3e9f
GH		 762 struct vcpu_vmx *vmx = to_vmx(vcpu);
763 struct kvm_msr_entry *msr;
2cc51560
ED		 764 int ret = 0;
765
6aa8b732 766 switch (msr_index) {
05b3e0c2 767#ifdef CONFIG_X86_64
3bab1f5d 768 case MSR_EFER:
2cc51560 769 ret = kvm_set_msr_common(vcpu, msr_index, data);
51c6cf66
AK		 770 if (vmx->host_state.loaded) {
771 reload_host_efer(vmx);
8b9cf98c 772 load_transition_efer(vmx);
51c6cf66 773 }
2cc51560 774 break;
6aa8b732
AK		 775 case MSR_FS_BASE:
776 vmcs_writel(GUEST_FS_BASE, data);
777 break;
778 case MSR_GS_BASE:
779 vmcs_writel(GUEST_GS_BASE, data);
780 break;
781#endif
782 case MSR_IA32_SYSENTER_CS:
783 vmcs_write32(GUEST_SYSENTER_CS, data);
784 break;
785 case MSR_IA32_SYSENTER_EIP:
f5b42c33 786 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 787 break;
788 case MSR_IA32_SYSENTER_ESP:
f5b42c33 789 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 790 break;
d27d4aca 791 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 792 guest_write_tsc(data);
793 break;
6aa8b732 794 default:
8b9cf98c 795 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 796 if (msr) {
797 msr->data = data;
a2fa3e9f
GH		 798 if (vmx->host_state.loaded)
799 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
3bab1f5d 800 break;
6aa8b732 801 }
2cc51560 802 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 803 }
804
2cc51560 805 return ret;
6aa8b732
AK		 806}
807
808/*
809 * Sync the rsp and rip registers into the vcpu structure. This allows
810 * registers to be accessed by indexing vcpu->regs.
811 */
812static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
813{
814 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
815 vcpu->rip = vmcs_readl(GUEST_RIP);
816}
817
818/*
819 * Syncs rsp and rip back into the vmcs. Should be called after possible
820 * modification.
821 */
822static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
823{
824 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
825 vmcs_writel(GUEST_RIP, vcpu->rip);
826}
827
828static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
829{
830 unsigned long dr7 = 0x400;
6aa8b732
AK		 831 int old_singlestep;
832
6aa8b732
AK		 833 old_singlestep = vcpu->guest_debug.singlestep;
834
835 vcpu->guest_debug.enabled = dbg->enabled;
836 if (vcpu->guest_debug.enabled) {
837 int i;
838
839 dr7 |= 0x200; /* exact */
840 for (i = 0; i < 4; ++i) {
841 if (!dbg->breakpoints[i].enabled)
842 continue;
843 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
844 dr7 |= 2 << (i*2); /* global enable */
845 dr7 |= 0 << (i*4+16); /* execution breakpoint */
846 }
847
6aa8b732 848 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 849 } else
6aa8b732 850 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 851
852 if (old_singlestep && !vcpu->guest_debug.singlestep) {
853 unsigned long flags;
854
855 flags = vmcs_readl(GUEST_RFLAGS);
856 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
857 vmcs_writel(GUEST_RFLAGS, flags);
858 }
859
abd3f2d6 860 update_exception_bitmap(vcpu);
6aa8b732
AK		 861 vmcs_writel(GUEST_DR7, dr7);
862
863 return 0;
864}
865
2a8067f1
ED		 866static int vmx_get_irq(struct kvm_vcpu *vcpu)
867{
1155f76a 868 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a8067f1
ED		 869 u32 idtv_info_field;
870
1155f76a 871 idtv_info_field = vmx->idt_vectoring_info;
2a8067f1
ED		 872 if (idtv_info_field & INTR_INFO_VALID_MASK) {
873 if (is_external_interrupt(idtv_info_field))
874 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
875 else
d77c26fc 876 printk(KERN_DEBUG "pending exception: not handled yet\n");
2a8067f1
ED		 877 }
878 return -1;
879}
880
6aa8b732
AK		 881static __init int cpu_has_kvm_support(void)
882{
883 unsigned long ecx = cpuid_ecx(1);
884 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
885}
886
887static __init int vmx_disabled_by_bios(void)
888{
889 u64 msr;
890
891 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
62b3ffb8
YS		 892 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
893 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
894 == MSR_IA32_FEATURE_CONTROL_LOCKED;
895 /* locked but not enabled */
6aa8b732
AK		 896}
897
774c47f1 898static void hardware_enable(void *garbage)
6aa8b732
AK		 899{
900 int cpu = raw_smp_processor_id();
901 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
902 u64 old;
903
904 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
62b3ffb8
YS		 905 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
906 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
907 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
908 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 909 /* enable and lock */
62b3ffb8
YS		 910 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
911 MSR_IA32_FEATURE_CONTROL_LOCKED |
912 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 913 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
6aa8b732
AK		 914 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
915 : "memory", "cc");
916}
917
918static void hardware_disable(void *garbage)
919{
920 asm volatile (ASM_VMX_VMXOFF : : : "cc");
921}
922
1c3d14fe 923static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 924 u32 msr, u32 *result)
1c3d14fe
YS		 925{
926 u32 vmx_msr_low, vmx_msr_high;
927 u32 ctl = ctl_min | ctl_opt;
928
929 rdmsr(msr, vmx_msr_low, vmx_msr_high);
930
931 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
932 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
933
934 /* Ensure minimum (required) set of control bits are supported. */
935 if (ctl_min & ~ctl)
002c7f7c 936 return -EIO;
1c3d14fe
YS		 937
938 *result = ctl;
939 return 0;
940}
941
002c7f7c 942static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 943{
944 u32 vmx_msr_low, vmx_msr_high;
1c3d14fe
YS		 945 u32 min, opt;
946 u32 _pin_based_exec_control = 0;
947 u32 _cpu_based_exec_control = 0;
f78e0e2e 948 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 949 u32 _vmexit_control = 0;
950 u32 _vmentry_control = 0;
951
952 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
953 opt = 0;
954 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
955 &_pin_based_exec_control) < 0)
002c7f7c 956 return -EIO;
1c3d14fe
YS		 957
958 min = CPU_BASED_HLT_EXITING |
959#ifdef CONFIG_X86_64
960 CPU_BASED_CR8_LOAD_EXITING |
961 CPU_BASED_CR8_STORE_EXITING |
962#endif
963 CPU_BASED_USE_IO_BITMAPS |
964 CPU_BASED_MOV_DR_EXITING |
965 CPU_BASED_USE_TSC_OFFSETING;
f78e0e2e
SY		 966 opt = CPU_BASED_TPR_SHADOW |
967 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 968 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
969 &_cpu_based_exec_control) < 0)
002c7f7c 970 return -EIO;
6e5d865c
YS		 971#ifdef CONFIG_X86_64
972 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
973 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
974 ~CPU_BASED_CR8_STORE_EXITING;
975#endif
f78e0e2e
SY		 976 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
977 min = 0;
e5edaa01
ED		 978 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
979 SECONDARY_EXEC_WBINVD_EXITING;
f78e0e2e
SY		 980 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
981 &_cpu_based_2nd_exec_control) < 0)
982 return -EIO;
983 }
984#ifndef CONFIG_X86_64
985 if (!(_cpu_based_2nd_exec_control &
986 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
987 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
988#endif
1c3d14fe
YS		 989
990 min = 0;
991#ifdef CONFIG_X86_64
992 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
993#endif
994 opt = 0;
995 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
996 &_vmexit_control) < 0)
002c7f7c 997 return -EIO;
1c3d14fe
YS		 998
999 min = opt = 0;
1000 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1001 &_vmentry_control) < 0)
002c7f7c 1002 return -EIO;
6aa8b732 1003
c68876fd 1004 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1005
1006 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1007 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1008 return -EIO;
1c3d14fe
YS		 1009
1010#ifdef CONFIG_X86_64
1011 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1012 if (vmx_msr_high & (1u<<16))
002c7f7c 1013 return -EIO;
1c3d14fe
YS		 1014#endif
1015
1016 /* Require Write-Back (WB) memory type for VMCS accesses. */
1017 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1018 return -EIO;
1c3d14fe 1019
002c7f7c
YS		 1020 vmcs_conf->size = vmx_msr_high & 0x1fff;
1021 vmcs_conf->order = get_order(vmcs_config.size);
1022 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1023
002c7f7c
YS		 1024 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1025 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1026 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1027 vmcs_conf->vmexit_ctrl = _vmexit_control;
1028 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1029
1030 return 0;
c68876fd 1031}
6aa8b732
AK		 1032
1033static struct vmcs *alloc_vmcs_cpu(int cpu)
1034{
1035 int node = cpu_to_node(cpu);
1036 struct page *pages;
1037 struct vmcs *vmcs;
1038
1c3d14fe 1039 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1040 if (!pages)
1041 return NULL;
1042 vmcs = page_address(pages);
1c3d14fe
YS		 1043 memset(vmcs, 0, vmcs_config.size);
1044 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1045 return vmcs;
1046}
1047
1048static struct vmcs *alloc_vmcs(void)
1049{
d3b2c338 1050 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1051}
1052
1053static void free_vmcs(struct vmcs *vmcs)
1054{
1c3d14fe 1055 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1056}
1057
39959588 1058static void free_kvm_area(void)
6aa8b732
AK		 1059{
1060 int cpu;
1061
1062 for_each_online_cpu(cpu)
1063 free_vmcs(per_cpu(vmxarea, cpu));
1064}
1065
6aa8b732
AK		 1066static __init int alloc_kvm_area(void)
1067{
1068 int cpu;
1069
1070 for_each_online_cpu(cpu) {
1071 struct vmcs *vmcs;
1072
1073 vmcs = alloc_vmcs_cpu(cpu);
1074 if (!vmcs) {
1075 free_kvm_area();
1076 return -ENOMEM;
1077 }
1078
1079 per_cpu(vmxarea, cpu) = vmcs;
1080 }
1081 return 0;
1082}
1083
1084static __init int hardware_setup(void)
1085{
002c7f7c
YS		 1086 if (setup_vmcs_config(&vmcs_config) < 0)
1087 return -EIO;
6aa8b732
AK		 1088 return alloc_kvm_area();
1089}
1090
1091static __exit void hardware_unsetup(void)
1092{
1093 free_kvm_area();
1094}
1095
6aa8b732
AK		 1096static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1097{
1098 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1099
6af11b9e 1100 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1101 vmcs_write16(sf->selector, save->selector);
1102 vmcs_writel(sf->base, save->base);
1103 vmcs_write32(sf->limit, save->limit);
1104 vmcs_write32(sf->ar_bytes, save->ar);
1105 } else {
1106 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1107 << AR_DPL_SHIFT;
1108 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1109 }
1110}
1111
1112static void enter_pmode(struct kvm_vcpu *vcpu)
1113{
1114 unsigned long flags;
1115
1116 vcpu->rmode.active = 0;
1117
1118 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1119 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1120 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1121
1122 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1123 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
6aa8b732
AK		 1124 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1125 vmcs_writel(GUEST_RFLAGS, flags);
1126
66aee91a
RR		 1127 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1128 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1129
1130 update_exception_bitmap(vcpu);
1131
1132 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1133 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1134 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1135 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1136
1137 vmcs_write16(GUEST_SS_SELECTOR, 0);
1138 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1139
1140 vmcs_write16(GUEST_CS_SELECTOR,
1141 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1142 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1143}
1144
d77c26fc 1145static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1146{
cbc94022
IE		 1147 if (!kvm->tss_addr) {
1148 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1149 kvm->memslots[0].npages - 3;
1150 return base_gfn << PAGE_SHIFT;
1151 }
1152 return kvm->tss_addr;
6aa8b732
AK		 1153}
1154
1155static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1156{
1157 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1158
1159 save->selector = vmcs_read16(sf->selector);
1160 save->base = vmcs_readl(sf->base);
1161 save->limit = vmcs_read32(sf->limit);
1162 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1163 vmcs_write16(sf->selector, save->base >> 4);
1164 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1165 vmcs_write32(sf->limit, 0xffff);
1166 vmcs_write32(sf->ar_bytes, 0xf3);
1167}
1168
1169static void enter_rmode(struct kvm_vcpu *vcpu)
1170{
1171 unsigned long flags;
1172
1173 vcpu->rmode.active = 1;
1174
1175 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1176 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1177
1178 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1179 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1180
1181 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1182 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1183
1184 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1185 vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1186
053de044 1187 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1188
1189 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1190 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1191 update_exception_bitmap(vcpu);
1192
1193 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1194 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1195 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1196
1197 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1198 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1199 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1200 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1201 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1202
1203 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1204 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1205 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1206 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
75880a01 1207
8668a3c4 1208 kvm_mmu_reset_context(vcpu);
75880a01 1209 init_rmode_tss(vcpu->kvm);
6aa8b732
AK		 1210}
1211
05b3e0c2 1212#ifdef CONFIG_X86_64
6aa8b732
AK		 1213
1214static void enter_lmode(struct kvm_vcpu *vcpu)
1215{
1216 u32 guest_tr_ar;
1217
1218 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1219 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1220 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1221 __FUNCTION__);
1222 vmcs_write32(GUEST_TR_AR_BYTES,
1223 (guest_tr_ar & ~AR_TYPE_MASK)
1224 | AR_TYPE_BUSY_64_TSS);
1225 }
1226
1227 vcpu->shadow_efer |= EFER_LMA;
1228
8b9cf98c 1229 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1230 vmcs_write32(VM_ENTRY_CONTROLS,
1231 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1232 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1233}
1234
1235static void exit_lmode(struct kvm_vcpu *vcpu)
1236{
1237 vcpu->shadow_efer &= ~EFER_LMA;
1238
1239 vmcs_write32(VM_ENTRY_CONTROLS,
1240 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1241 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1242}
1243
1244#endif
1245
25c4c276 1246static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1247{
399badf3
AK		 1248 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1249 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1250}
1251
6aa8b732
AK		 1252static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1253{
5fd86fcf
AK		 1254 vmx_fpu_deactivate(vcpu);
1255
707d92fa 1256 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1257 enter_pmode(vcpu);
1258
707d92fa 1259 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1260 enter_rmode(vcpu);
1261
05b3e0c2 1262#ifdef CONFIG_X86_64
6aa8b732 1263 if (vcpu->shadow_efer & EFER_LME) {
707d92fa 1264 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1265 enter_lmode(vcpu);
707d92fa 1266 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1267 exit_lmode(vcpu);
1268 }
1269#endif
1270
1271 vmcs_writel(CR0_READ_SHADOW, cr0);
1272 vmcs_writel(GUEST_CR0,
1273 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1274 vcpu->cr0 = cr0;
5fd86fcf 1275
707d92fa 1276 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1277 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1278}
1279
6aa8b732
AK		 1280static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1281{
1282 vmcs_writel(GUEST_CR3, cr3);
707d92fa 1283 if (vcpu->cr0 & X86_CR0_PE)
5fd86fcf 1284 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1285}
1286
1287static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1288{
1289 vmcs_writel(CR4_READ_SHADOW, cr4);
1290 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1291 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1292 vcpu->cr4 = cr4;
1293}
1294
05b3e0c2 1295#ifdef CONFIG_X86_64
6aa8b732
AK		 1296
1297static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1298{
8b9cf98c
RR		 1299 struct vcpu_vmx *vmx = to_vmx(vcpu);
1300 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732
AK		 1301
1302 vcpu->shadow_efer = efer;
1303 if (efer & EFER_LMA) {
1304 vmcs_write32(VM_ENTRY_CONTROLS,
1305 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1306 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1307 msr->data = efer;
1308
1309 } else {
1310 vmcs_write32(VM_ENTRY_CONTROLS,
1311 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1312 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1313
1314 msr->data = efer & ~EFER_LME;
1315 }
8b9cf98c 1316 setup_msrs(vmx);
6aa8b732
AK		 1317}
1318
1319#endif
1320
1321static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1322{
1323 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1324
1325 return vmcs_readl(sf->base);
1326}
1327
1328static void vmx_get_segment(struct kvm_vcpu *vcpu,
1329 struct kvm_segment *var, int seg)
1330{
1331 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1332 u32 ar;
1333
1334 var->base = vmcs_readl(sf->base);
1335 var->limit = vmcs_read32(sf->limit);
1336 var->selector = vmcs_read16(sf->selector);
1337 ar = vmcs_read32(sf->ar_bytes);
1338 if (ar & AR_UNUSABLE_MASK)
1339 ar = 0;
1340 var->type = ar & 15;
1341 var->s = (ar >> 4) & 1;
1342 var->dpl = (ar >> 5) & 3;
1343 var->present = (ar >> 7) & 1;
1344 var->avl = (ar >> 12) & 1;
1345 var->l = (ar >> 13) & 1;
1346 var->db = (ar >> 14) & 1;
1347 var->g = (ar >> 15) & 1;
1348 var->unusable = (ar >> 16) & 1;
1349}
1350
653e3108 1351static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1352{
6aa8b732
AK		 1353 u32 ar;
1354
653e3108 1355 if (var->unusable)
6aa8b732
AK		 1356 ar = 1 << 16;
1357 else {
1358 ar = var->type & 15;
1359 ar |= (var->s & 1) << 4;
1360 ar |= (var->dpl & 3) << 5;
1361 ar |= (var->present & 1) << 7;
1362 ar |= (var->avl & 1) << 12;
1363 ar |= (var->l & 1) << 13;
1364 ar |= (var->db & 1) << 14;
1365 ar |= (var->g & 1) << 15;
1366 }
f7fbf1fd
UL		 1367 if (ar == 0) /* a 0 value means unusable */
1368 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1369
1370 return ar;
1371}
1372
1373static void vmx_set_segment(struct kvm_vcpu *vcpu,
1374 struct kvm_segment *var, int seg)
1375{
1376 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1377 u32 ar;
1378
1379 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1380 vcpu->rmode.tr.selector = var->selector;
1381 vcpu->rmode.tr.base = var->base;
1382 vcpu->rmode.tr.limit = var->limit;
1383 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1384 return;
1385 }
1386 vmcs_writel(sf->base, var->base);
1387 vmcs_write32(sf->limit, var->limit);
1388 vmcs_write16(sf->selector, var->selector);
1389 if (vcpu->rmode.active && var->s) {
1390 /*
1391 * Hack real-mode segments into vm86 compatibility.
1392 */
1393 if (var->base == 0xffff0000 && var->selector == 0xf000)
1394 vmcs_writel(sf->base, 0xf0000);
1395 ar = 0xf3;
1396 } else
1397 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1398 vmcs_write32(sf->ar_bytes, ar);
1399}
1400
6aa8b732
AK		 1401static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1402{
1403 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1404
1405 *db = (ar >> 14) & 1;
1406 *l = (ar >> 13) & 1;
1407}
1408
1409static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1410{
1411 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1412 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1413}
1414
1415static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1416{
1417 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1418 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1419}
1420
1421static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1422{
1423 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1424 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1425}
1426
1427static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1428{
1429 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1430 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1431}
1432
d77c26fc 1433static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1434{
6aa8b732 1435 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 1436 u16 data = 0;
1437 int r;
6aa8b732 1438
195aefde
IE		 1439 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1440 if (r < 0)
1441 return 0;
1442 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1443 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1444 if (r < 0)
1445 return 0;
1446 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1447 if (r < 0)
1448 return 0;
1449 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1450 if (r < 0)
1451 return 0;
1452 data = ~0;
1453 r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1454 sizeof(u8));
1455 if (r < 0)
6aa8b732 1456 return 0;
6aa8b732
AK		 1457 return 1;
1458}
1459
6aa8b732
AK		 1460static void seg_setup(int seg)
1461{
1462 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1463
1464 vmcs_write16(sf->selector, 0);
1465 vmcs_writel(sf->base, 0);
1466 vmcs_write32(sf->limit, 0xffff);
1467 vmcs_write32(sf->ar_bytes, 0x93);
1468}
1469
f78e0e2e
SY		 1470static int alloc_apic_access_page(struct kvm *kvm)
1471{
1472 struct kvm_userspace_memory_region kvm_userspace_mem;
1473 int r = 0;
1474
1475 mutex_lock(&kvm->lock);
1476 if (kvm->apic_access_page)
1477 goto out;
1478 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1479 kvm_userspace_mem.flags = 0;
1480 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1481 kvm_userspace_mem.memory_size = PAGE_SIZE;
1482 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1483 if (r)
1484 goto out;
1485 kvm->apic_access_page = gfn_to_page(kvm, 0xfee00);
1486out:
1487 mutex_unlock(&kvm->lock);
1488 return r;
1489}
1490
6aa8b732
AK		 1491/*
1492 * Sets up the vmcs for emulated real mode.
1493 */
8b9cf98c 1494static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1495{
1496 u32 host_sysenter_cs;
1497 u32 junk;
1498 unsigned long a;
1499 struct descriptor_table dt;
1500 int i;
cd2276a7 1501 unsigned long kvm_vmx_return;
6e5d865c 1502 u32 exec_control;
6aa8b732 1503
6aa8b732 1504 /* I/O */
fdef3ad1
HQ		 1505 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1506 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732 1507
6aa8b732
AK		 1508 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1509
6aa8b732 1510 /* Control */
1c3d14fe
YS		 1511 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1512 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 1513
1514 exec_control = vmcs_config.cpu_based_exec_ctrl;
1515 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1516 exec_control &= ~CPU_BASED_TPR_SHADOW;
1517#ifdef CONFIG_X86_64
1518 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1519 CPU_BASED_CR8_LOAD_EXITING;
1520#endif
1521 }
1522 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 1523
83ff3b9d
SY		 1524 if (cpu_has_secondary_exec_ctrls()) {
1525 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1526 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1527 exec_control &=
1528 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1529 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1530 }
f78e0e2e 1531
c7addb90
AK		 1532 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1533 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 1534 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1535
1536 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1537 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1538 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1539
1540 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1541 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1542 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1543 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1544 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1545 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1546#ifdef CONFIG_X86_64
6aa8b732
AK		 1547 rdmsrl(MSR_FS_BASE, a);
1548 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1549 rdmsrl(MSR_GS_BASE, a);
1550 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1551#else
1552 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1553 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1554#endif
1555
1556 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1557
1558 get_idt(&dt);
1559 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1560
d77c26fc 1561 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 1562 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1563 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1564 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1565 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1566
1567 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1568 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1569 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1570 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1571 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1572 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1573
6aa8b732
AK		 1574 for (i = 0; i < NR_VMX_MSR; ++i) {
1575 u32 index = vmx_msr_index[i];
1576 u32 data_low, data_high;
1577 u64 data;
a2fa3e9f 1578 int j = vmx->nmsrs;
6aa8b732
AK		 1579
1580 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1581 continue;
432bd6cb
AK		 1582 if (wrmsr_safe(index, data_low, data_high) < 0)
1583 continue;
6aa8b732 1584 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1585 vmx->host_msrs[j].index = index;
1586 vmx->host_msrs[j].reserved = 0;
1587 vmx->host_msrs[j].data = data;
1588 vmx->guest_msrs[j] = vmx->host_msrs[j];
1589 ++vmx->nmsrs;
6aa8b732 1590 }
6aa8b732 1591
1c3d14fe 1592 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1593
1594 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1595 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1596
e00c8cf2
AK		 1597 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1598 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1599
f78e0e2e
SY		 1600 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1601 if (alloc_apic_access_page(vmx->vcpu.kvm) != 0)
1602 return -ENOMEM;
1603
e00c8cf2
AK		 1604 return 0;
1605}
1606
1607static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1608{
1609 struct vcpu_vmx *vmx = to_vmx(vcpu);
1610 u64 msr;
1611 int ret;
1612
1613 if (!init_rmode_tss(vmx->vcpu.kvm)) {
1614 ret = -ENOMEM;
1615 goto out;
1616 }
1617
1618 vmx->vcpu.rmode.active = 0;
1619
1620 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1621 set_cr8(&vmx->vcpu, 0);
1622 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1623 if (vmx->vcpu.vcpu_id == 0)
1624 msr |= MSR_IA32_APICBASE_BSP;
1625 kvm_set_apic_base(&vmx->vcpu, msr);
1626
1627 fx_init(&vmx->vcpu);
1628
1629 /*
1630 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1631 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1632 */
1633 if (vmx->vcpu.vcpu_id == 0) {
1634 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1635 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1636 } else {
1637 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1638 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1639 }
1640 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1641 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1642
1643 seg_setup(VCPU_SREG_DS);
1644 seg_setup(VCPU_SREG_ES);
1645 seg_setup(VCPU_SREG_FS);
1646 seg_setup(VCPU_SREG_GS);
1647 seg_setup(VCPU_SREG_SS);
1648
1649 vmcs_write16(GUEST_TR_SELECTOR, 0);
1650 vmcs_writel(GUEST_TR_BASE, 0);
1651 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1652 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1653
1654 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1655 vmcs_writel(GUEST_LDTR_BASE, 0);
1656 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1657 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1658
1659 vmcs_write32(GUEST_SYSENTER_CS, 0);
1660 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1661 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1662
1663 vmcs_writel(GUEST_RFLAGS, 0x02);
1664 if (vmx->vcpu.vcpu_id == 0)
1665 vmcs_writel(GUEST_RIP, 0xfff0);
1666 else
1667 vmcs_writel(GUEST_RIP, 0);
1668 vmcs_writel(GUEST_RSP, 0);
1669
1670 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1671 vmcs_writel(GUEST_DR7, 0x400);
1672
1673 vmcs_writel(GUEST_GDTR_BASE, 0);
1674 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1675
1676 vmcs_writel(GUEST_IDTR_BASE, 0);
1677 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1678
1679 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1680 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1681 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1682
1683 guest_write_tsc(0);
1684
1685 /* Special registers */
1686 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1687
1688 setup_msrs(vmx);
1689
6aa8b732
AK		 1690 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1691
f78e0e2e
SY		 1692 if (cpu_has_vmx_tpr_shadow()) {
1693 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1694 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1695 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1696 page_to_phys(vmx->vcpu.apic->regs_page));
1697 vmcs_write32(TPR_THRESHOLD, 0);
1698 }
1699
1700 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1701 vmcs_write64(APIC_ACCESS_ADDR,
1702 page_to_phys(vmx->vcpu.kvm->apic_access_page));
6aa8b732 1703
8b9cf98c 1704 vmx->vcpu.cr0 = 0x60000010;
d77c26fc 1705 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */
8b9cf98c 1706 vmx_set_cr4(&vmx->vcpu, 0);
05b3e0c2 1707#ifdef CONFIG_X86_64
8b9cf98c 1708 vmx_set_efer(&vmx->vcpu, 0);
6aa8b732 1709#endif
8b9cf98c
RR		 1710 vmx_fpu_activate(&vmx->vcpu);
1711 update_exception_bitmap(&vmx->vcpu);
6aa8b732
AK		 1712
1713 return 0;
1714
6aa8b732
AK		 1715out:
1716 return ret;
1717}
1718
85f455f7
ED		 1719static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1720{
9c8cba37
AK		 1721 struct vcpu_vmx *vmx = to_vmx(vcpu);
1722
85f455f7 1723 if (vcpu->rmode.active) {
9c8cba37
AK		 1724 vmx->rmode.irq.pending = true;
1725 vmx->rmode.irq.vector = irq;
1726 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
9c5623e3
AK		 1727 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1728 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1729 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
9c8cba37 1730 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
85f455f7
ED		 1731 return;
1732 }
1733 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1734 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1735}
1736
6aa8b732
AK		 1737static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1738{
1739 int word_index = __ffs(vcpu->irq_summary);
1740 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1741 int irq = word_index * BITS_PER_LONG + bit_index;
1742
1743 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1744 if (!vcpu->irq_pending[word_index])
1745 clear_bit(word_index, &vcpu->irq_summary);
85f455f7 1746 vmx_inject_irq(vcpu, irq);
6aa8b732
AK		 1747}
1748
c1150d8c
DL		 1749
1750static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1751 struct kvm_run *kvm_run)
6aa8b732 1752{
c1150d8c
DL		 1753 u32 cpu_based_vm_exec_control;
1754
1755 vcpu->interrupt_window_open =
1756 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1757 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1758
1759 if (vcpu->interrupt_window_open &&
1760 vcpu->irq_summary &&
1761 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1762 /*
c1150d8c 1763 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1764 */
1765 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1766
1767 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1768 if (!vcpu->interrupt_window_open &&
1769 (vcpu->irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1770 /*
1771 * Interrupts blocked. Wait for unblock.
1772 */
c1150d8c
DL		 1773 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1774 else
1775 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1776 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1777}
1778
cbc94022
IE		 1779static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1780{
1781 int ret;
1782 struct kvm_userspace_memory_region tss_mem = {
1783 .slot = 8,
1784 .guest_phys_addr = addr,
1785 .memory_size = PAGE_SIZE * 3,
1786 .flags = 0,
1787 };
1788
1789 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1790 if (ret)
1791 return ret;
1792 kvm->tss_addr = addr;
1793 return 0;
1794}
1795
6aa8b732
AK		 1796static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1797{
1798 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1799
1800 set_debugreg(dbg->bp[0], 0);
1801 set_debugreg(dbg->bp[1], 1);
1802 set_debugreg(dbg->bp[2], 2);
1803 set_debugreg(dbg->bp[3], 3);
1804
1805 if (dbg->singlestep) {
1806 unsigned long flags;
1807
1808 flags = vmcs_readl(GUEST_RFLAGS);
1809 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1810 vmcs_writel(GUEST_RFLAGS, flags);
1811 }
1812}
1813
1814static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1815 int vec, u32 err_code)
1816{
1817 if (!vcpu->rmode.active)
1818 return 0;
1819
b3f37707
NK		 1820 /*
1821 * Instruction with address size override prefix opcode 0x67
1822 * Cause the #SS fault with 0 error code in VM86 mode.
1823 */
1824 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 1825 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732
AK		 1826 return 1;
1827 return 0;
1828}
1829
1830static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1831{
1155f76a 1832 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 1833 u32 intr_info, error_code;
1834 unsigned long cr2, rip;
1835 u32 vect_info;
1836 enum emulation_result er;
1837
1155f76a 1838 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 1839 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1840
1841 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 1842 !is_page_fault(intr_info))
6aa8b732
AK		 1843 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1844 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
6aa8b732 1845
85f455f7 1846 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732
AK		 1847 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1848 set_bit(irq, vcpu->irq_pending);
1849 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1850 }
1851
1b6269db
AK		 1852 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1853 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 1854
1855 if (is_no_device(intr_info)) {
5fd86fcf 1856 vmx_fpu_activate(vcpu);
2ab455cc
AL		 1857 return 1;
1858 }
1859
7aa81cc0 1860 if (is_invalid_opcode(intr_info)) {
3427318f 1861 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
7aa81cc0
AL		 1862 if (er != EMULATE_DONE)
1863 vmx_inject_ud(vcpu);
1864
1865 return 1;
1866 }
1867
6aa8b732
AK		 1868 error_code = 0;
1869 rip = vmcs_readl(GUEST_RIP);
1870 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1871 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1872 if (is_page_fault(intr_info)) {
1873 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3067714c 1874 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 1875 }
1876
1877 if (vcpu->rmode.active &&
1878 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0
AK		 1879 error_code)) {
1880 if (vcpu->halt_request) {
1881 vcpu->halt_request = 0;
1882 return kvm_emulate_halt(vcpu);
1883 }
6aa8b732 1884 return 1;
72d6e5a0 1885 }
6aa8b732 1886
d77c26fc
MD		 1887 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1888 (INTR_TYPE_EXCEPTION | 1)) {
6aa8b732
AK		 1889 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1890 return 0;
1891 }
1892 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1893 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1894 kvm_run->ex.error_code = error_code;
1895 return 0;
1896}
1897
1898static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1899 struct kvm_run *kvm_run)
1900{
1165f5fe 1901 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1902 return 1;
1903}
1904
988ad74f
AK		 1905static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1906{
1907 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1908 return 0;
1909}
6aa8b732 1910
6aa8b732
AK		 1911static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1912{
bfdaab09 1913 unsigned long exit_qualification;
039576c0
AK		 1914 int size, down, in, string, rep;
1915 unsigned port;
6aa8b732 1916
1165f5fe 1917 ++vcpu->stat.io_exits;
bfdaab09 1918 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 1919 string = (exit_qualification & 16) != 0;
e70669ab
LV		 1920
1921 if (string) {
3427318f
LV		 1922 if (emulate_instruction(vcpu,
1923 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1924 return 0;
1925 return 1;
1926 }
1927
1928 size = (exit_qualification & 7) + 1;
1929 in = (exit_qualification & 8) != 0;
039576c0 1930 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 1931 rep = (exit_qualification & 32) != 0;
1932 port = exit_qualification >> 16;
e70669ab 1933
3090dd73 1934 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1935}
1936
102d8325
IM		 1937static void
1938vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1939{
1940 /*
1941 * Patch in the VMCALL instruction:
1942 */
1943 hypercall[0] = 0x0f;
1944 hypercall[1] = 0x01;
1945 hypercall[2] = 0xc1;
102d8325
IM		 1946}
1947
6aa8b732
AK		 1948static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1949{
bfdaab09 1950 unsigned long exit_qualification;
6aa8b732
AK		 1951 int cr;
1952 int reg;
1953
bfdaab09 1954 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 1955 cr = exit_qualification & 15;
1956 reg = (exit_qualification >> 8) & 15;
1957 switch ((exit_qualification >> 4) & 3) {
1958 case 0: /* mov to cr */
1959 switch (cr) {
1960 case 0:
1961 vcpu_load_rsp_rip(vcpu);
1962 set_cr0(vcpu, vcpu->regs[reg]);
1963 skip_emulated_instruction(vcpu);
1964 return 1;
1965 case 3:
1966 vcpu_load_rsp_rip(vcpu);
1967 set_cr3(vcpu, vcpu->regs[reg]);
1968 skip_emulated_instruction(vcpu);
1969 return 1;
1970 case 4:
1971 vcpu_load_rsp_rip(vcpu);
1972 set_cr4(vcpu, vcpu->regs[reg]);
1973 skip_emulated_instruction(vcpu);
1974 return 1;
1975 case 8:
1976 vcpu_load_rsp_rip(vcpu);
1977 set_cr8(vcpu, vcpu->regs[reg]);
1978 skip_emulated_instruction(vcpu);
253abdee
YS		 1979 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1980 return 0;
6aa8b732
AK		 1981 };
1982 break;
25c4c276
AL		 1983 case 2: /* clts */
1984 vcpu_load_rsp_rip(vcpu);
5fd86fcf 1985 vmx_fpu_deactivate(vcpu);
707d92fa 1986 vcpu->cr0 &= ~X86_CR0_TS;
2ab455cc 1987 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
5fd86fcf 1988 vmx_fpu_activate(vcpu);
25c4c276
AL		 1989 skip_emulated_instruction(vcpu);
1990 return 1;
6aa8b732
AK		 1991 case 1: /*mov from cr*/
1992 switch (cr) {
1993 case 3:
1994 vcpu_load_rsp_rip(vcpu);
1995 vcpu->regs[reg] = vcpu->cr3;
1996 vcpu_put_rsp_rip(vcpu);
1997 skip_emulated_instruction(vcpu);
1998 return 1;
1999 case 8:
6aa8b732 2000 vcpu_load_rsp_rip(vcpu);
7017fc3d 2001 vcpu->regs[reg] = get_cr8(vcpu);
6aa8b732
AK		 2002 vcpu_put_rsp_rip(vcpu);
2003 skip_emulated_instruction(vcpu);
2004 return 1;
2005 }
2006 break;
2007 case 3: /* lmsw */
2008 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2009
2010 skip_emulated_instruction(vcpu);
2011 return 1;
2012 default:
2013 break;
2014 }
2015 kvm_run->exit_reason = 0;
f0242478 2016 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2017 (int)(exit_qualification >> 4) & 3, cr);
2018 return 0;
2019}
2020
2021static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2022{
bfdaab09 2023 unsigned long exit_qualification;
6aa8b732
AK		 2024 unsigned long val;
2025 int dr, reg;
2026
2027 /*
2028 * FIXME: this code assumes the host is debugging the guest.
2029 * need to deal with guest debugging itself too.
2030 */
bfdaab09 2031 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2032 dr = exit_qualification & 7;
2033 reg = (exit_qualification >> 8) & 15;
2034 vcpu_load_rsp_rip(vcpu);
2035 if (exit_qualification & 16) {
2036 /* mov from dr */
2037 switch (dr) {
2038 case 6:
2039 val = 0xffff0ff0;
2040 break;
2041 case 7:
2042 val = 0x400;
2043 break;
2044 default:
2045 val = 0;
2046 }
2047 vcpu->regs[reg] = val;
2048 } else {
2049 /* mov to dr */
2050 }
2051 vcpu_put_rsp_rip(vcpu);
2052 skip_emulated_instruction(vcpu);
2053 return 1;
2054}
2055
2056static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2057{
06465c5a
AK		 2058 kvm_emulate_cpuid(vcpu);
2059 return 1;
6aa8b732
AK		 2060}
2061
2062static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2063{
2064 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2065 u64 data;
2066
2067 if (vmx_get_msr(vcpu, ecx, &data)) {
2068 vmx_inject_gp(vcpu, 0);
2069 return 1;
2070 }
2071
2072 /* FIXME: handling of bits 32:63 of rax, rdx */
2073 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2074 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2075 skip_emulated_instruction(vcpu);
2076 return 1;
2077}
2078
2079static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2080{
2081 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2082 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2083 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2084
2085 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2086 vmx_inject_gp(vcpu, 0);
2087 return 1;
2088 }
2089
2090 skip_emulated_instruction(vcpu);
2091 return 1;
2092}
2093
6e5d865c
YS		 2094static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2095 struct kvm_run *kvm_run)
2096{
2097 return 1;
2098}
2099
6aa8b732
AK		 2100static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2101 struct kvm_run *kvm_run)
2102{
85f455f7
ED		 2103 u32 cpu_based_vm_exec_control;
2104
2105 /* clear pending irq */
2106 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2107 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2108 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
c1150d8c
DL		 2109 /*
2110 * If the user space waits to inject interrupts, exit as soon as
2111 * possible
2112 */
2113 if (kvm_run->request_interrupt_window &&
022a9308 2114 !vcpu->irq_summary) {
c1150d8c 2115 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2116 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2117 return 0;
2118 }
6aa8b732
AK		 2119 return 1;
2120}
2121
2122static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2123{
2124 skip_emulated_instruction(vcpu);
d3bef15f 2125 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2126}
2127
c21415e8
IM		 2128static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2129{
510043da 2130 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2131 kvm_emulate_hypercall(vcpu);
2132 return 1;
c21415e8
IM		 2133}
2134
e5edaa01
ED		 2135static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2136{
2137 skip_emulated_instruction(vcpu);
2138 /* TODO: Add support for VT-d/pass-through device */
2139 return 1;
2140}
2141
f78e0e2e
SY		 2142static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2143{
2144 u64 exit_qualification;
2145 enum emulation_result er;
2146 unsigned long offset;
2147
2148 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2149 offset = exit_qualification & 0xffful;
2150
2151 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2152
2153 if (er != EMULATE_DONE) {
2154 printk(KERN_ERR
2155 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2156 offset);
2157 return -ENOTSUPP;
2158 }
2159 return 1;
2160}
2161
6aa8b732
AK		 2162/*
2163 * The exit handlers return 1 if the exit was handled fully and guest execution
2164 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2165 * to be done to userspace and return 0.
2166 */
2167static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2168 struct kvm_run *kvm_run) = {
2169 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2170 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2171 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 2172 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2173 [EXIT_REASON_CR_ACCESS] = handle_cr,
2174 [EXIT_REASON_DR_ACCESS] = handle_dr,
2175 [EXIT_REASON_CPUID] = handle_cpuid,
2176 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2177 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2178 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2179 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2180 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 2181 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2182 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 2183 [EXIT_REASON_WBINVD] = handle_wbinvd,
6aa8b732
AK		 2184};
2185
2186static const int kvm_vmx_max_exit_handlers =
50a3485c 2187 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2188
2189/*
2190 * The guest has exited. See if we can fix it or if we need userspace
2191 * assistance.
2192 */
2193static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2194{
6aa8b732 2195 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 2196 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 2197 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78
AK		 2198
2199 if (unlikely(vmx->fail)) {
2200 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2201 kvm_run->fail_entry.hardware_entry_failure_reason
2202 = vmcs_read32(VM_INSTRUCTION_ERROR);
2203 return 0;
2204 }
6aa8b732 2205
d77c26fc
MD		 2206 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2207 exit_reason != EXIT_REASON_EXCEPTION_NMI)
6aa8b732
AK		 2208 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2209 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
6aa8b732
AK		 2210 if (exit_reason < kvm_vmx_max_exit_handlers
2211 && kvm_vmx_exit_handlers[exit_reason])
2212 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2213 else {
2214 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2215 kvm_run->hw.hardware_exit_reason = exit_reason;
2216 }
2217 return 0;
2218}
2219
d9e368d6
AK		 2220static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2221{
d9e368d6
AK		 2222}
2223
6e5d865c
YS		 2224static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2225{
2226 int max_irr, tpr;
2227
2228 if (!vm_need_tpr_shadow(vcpu->kvm))
2229 return;
2230
2231 if (!kvm_lapic_enabled(vcpu) ||
2232 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2233 vmcs_write32(TPR_THRESHOLD, 0);
2234 return;
2235 }
2236
2237 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2238 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2239}
2240
85f455f7
ED		 2241static void enable_irq_window(struct kvm_vcpu *vcpu)
2242{
2243 u32 cpu_based_vm_exec_control;
2244
2245 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2246 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2247 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2248}
2249
2250static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2251{
1155f76a 2252 struct vcpu_vmx *vmx = to_vmx(vcpu);
85f455f7
ED		 2253 u32 idtv_info_field, intr_info_field;
2254 int has_ext_irq, interrupt_window_open;
1b9778da 2255 int vector;
85f455f7 2256
6e5d865c
YS		 2257 update_tpr_threshold(vcpu);
2258
85f455f7
ED		 2259 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2260 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
1155f76a 2261 idtv_info_field = vmx->idt_vectoring_info;
85f455f7
ED		 2262 if (intr_info_field & INTR_INFO_VALID_MASK) {
2263 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2264 /* TODO: fault when IDT_Vectoring */
2265 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2266 }
2267 if (has_ext_irq)
2268 enable_irq_window(vcpu);
2269 return;
2270 }
2271 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
9c8cba37
AK		 2272 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2273 == INTR_TYPE_EXT_INTR
2274 && vcpu->rmode.active) {
2275 u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2276
2277 vmx_inject_irq(vcpu, vect);
2278 if (unlikely(has_ext_irq))
2279 enable_irq_window(vcpu);
2280 return;
2281 }
2282
85f455f7
ED		 2283 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2284 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2285 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2286
2287 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2288 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2289 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2290 if (unlikely(has_ext_irq))
2291 enable_irq_window(vcpu);
2292 return;
2293 }
2294 if (!has_ext_irq)
2295 return;
2296 interrupt_window_open =
2297 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2298 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1b9778da
ED		 2299 if (interrupt_window_open) {
2300 vector = kvm_cpu_get_interrupt(vcpu);
2301 vmx_inject_irq(vcpu, vector);
2302 kvm_timer_intr_post(vcpu, vector);
2303 } else
85f455f7
ED		 2304 enable_irq_window(vcpu);
2305}
2306
9c8cba37
AK		 2307/*
2308 * Failure to inject an interrupt should give us the information
2309 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
2310 * when fetching the interrupt redirection bitmap in the real-mode
2311 * tss, this doesn't happen. So we do it ourselves.
2312 */
2313static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2314{
2315 vmx->rmode.irq.pending = 0;
2316 if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2317 return;
2318 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2319 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2320 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2321 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2322 return;
2323 }
2324 vmx->idt_vectoring_info =
2325 VECTORING_INFO_VALID_MASK
2326 | INTR_TYPE_EXT_INTR
2327 | vmx->rmode.irq.vector;
2328}
2329
04d2cc77 2330static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2331{
a2fa3e9f 2332 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 2333 u32 intr_info;
e6adf283
AK		 2334
2335 /*
2336 * Loading guest fpu may have cleared host cr0.ts
2337 */
2338 vmcs_writel(HOST_CR0, read_cr0());
2339
d77c26fc 2340 asm(
6aa8b732 2341 /* Store host registers */
05b3e0c2 2342#ifdef CONFIG_X86_64
c2036300 2343 "push %%rdx; push %%rbp;"
6aa8b732 2344 "push %%rcx \n\t"
6aa8b732 2345#else
ff593e5a
LV		 2346 "push %%edx; push %%ebp;"
2347 "push %%ecx \n\t"
6aa8b732 2348#endif
c2036300 2349 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
6aa8b732 2350 /* Check if vmlaunch of vmresume is needed */
e08aa78a 2351 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 2352 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2353#ifdef CONFIG_X86_64
e08aa78a 2354 "mov %c[cr2](%0), %%rax \n\t"
6aa8b732 2355 "mov %%rax, %%cr2 \n\t"
e08aa78a
AK		 2356 "mov %c[rax](%0), %%rax \n\t"
2357 "mov %c[rbx](%0), %%rbx \n\t"
2358 "mov %c[rdx](%0), %%rdx \n\t"
2359 "mov %c[rsi](%0), %%rsi \n\t"
2360 "mov %c[rdi](%0), %%rdi \n\t"
2361 "mov %c[rbp](%0), %%rbp \n\t"
2362 "mov %c[r8](%0), %%r8 \n\t"
2363 "mov %c[r9](%0), %%r9 \n\t"
2364 "mov %c[r10](%0), %%r10 \n\t"
2365 "mov %c[r11](%0), %%r11 \n\t"
2366 "mov %c[r12](%0), %%r12 \n\t"
2367 "mov %c[r13](%0), %%r13 \n\t"
2368 "mov %c[r14](%0), %%r14 \n\t"
2369 "mov %c[r15](%0), %%r15 \n\t"
2370 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
6aa8b732 2371#else
e08aa78a 2372 "mov %c[cr2](%0), %%eax \n\t"
6aa8b732 2373 "mov %%eax, %%cr2 \n\t"
e08aa78a
AK		 2374 "mov %c[rax](%0), %%eax \n\t"
2375 "mov %c[rbx](%0), %%ebx \n\t"
2376 "mov %c[rdx](%0), %%edx \n\t"
2377 "mov %c[rsi](%0), %%esi \n\t"
2378 "mov %c[rdi](%0), %%edi \n\t"
2379 "mov %c[rbp](%0), %%ebp \n\t"
2380 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
6aa8b732
AK		 2381#endif
2382 /* Enter guest mode */
cd2276a7 2383 "jne .Llaunched \n\t"
6aa8b732 2384 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2385 "jmp .Lkvm_vmx_return \n\t"
2386 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2387 ".Lkvm_vmx_return: "
6aa8b732 2388 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2389#ifdef CONFIG_X86_64
e08aa78a
AK		 2390 "xchg %0, (%%rsp) \n\t"
2391 "mov %%rax, %c[rax](%0) \n\t"
2392 "mov %%rbx, %c[rbx](%0) \n\t"
2393 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2394 "mov %%rdx, %c[rdx](%0) \n\t"
2395 "mov %%rsi, %c[rsi](%0) \n\t"
2396 "mov %%rdi, %c[rdi](%0) \n\t"
2397 "mov %%rbp, %c[rbp](%0) \n\t"
2398 "mov %%r8, %c[r8](%0) \n\t"
2399 "mov %%r9, %c[r9](%0) \n\t"
2400 "mov %%r10, %c[r10](%0) \n\t"
2401 "mov %%r11, %c[r11](%0) \n\t"
2402 "mov %%r12, %c[r12](%0) \n\t"
2403 "mov %%r13, %c[r13](%0) \n\t"
2404 "mov %%r14, %c[r14](%0) \n\t"
2405 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 2406 "mov %%cr2, %%rax \n\t"
e08aa78a 2407 "mov %%rax, %c[cr2](%0) \n\t"
6aa8b732 2408
e08aa78a 2409 "pop %%rbp; pop %%rbp; pop %%rdx \n\t"
6aa8b732 2410#else
e08aa78a
AK		 2411 "xchg %0, (%%esp) \n\t"
2412 "mov %%eax, %c[rax](%0) \n\t"
2413 "mov %%ebx, %c[rbx](%0) \n\t"
2414 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2415 "mov %%edx, %c[rdx](%0) \n\t"
2416 "mov %%esi, %c[rsi](%0) \n\t"
2417 "mov %%edi, %c[rdi](%0) \n\t"
2418 "mov %%ebp, %c[rbp](%0) \n\t"
6aa8b732 2419 "mov %%cr2, %%eax \n\t"
e08aa78a 2420 "mov %%eax, %c[cr2](%0) \n\t"
6aa8b732 2421
e08aa78a 2422 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
6aa8b732 2423#endif
e08aa78a
AK		 2424 "setbe %c[fail](%0) \n\t"
2425 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2426 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2427 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2428 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RAX])),
2429 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RBX])),
2430 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RCX])),
2431 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RDX])),
2432 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RSI])),
2433 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RDI])),
2434 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RBP])),
05b3e0c2 2435#ifdef CONFIG_X86_64
e08aa78a
AK		 2436 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R8])),
2437 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R9])),
2438 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R10])),
2439 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R11])),
2440 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R12])),
2441 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R13])),
2442 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R14])),
2443 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R15])),
6aa8b732 2444#endif
e08aa78a 2445 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.cr2))
c2036300
LV		 2446 : "cc", "memory"
2447#ifdef CONFIG_X86_64
2448 , "rbx", "rdi", "rsi"
2449 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
ff593e5a
LV		 2450#else
2451 , "ebx", "edi", "rsi"
c2036300
LV		 2452#endif
2453 );
6aa8b732 2454
1155f76a 2455 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 2456 if (vmx->rmode.irq.pending)
2457 fixup_rmode_irq(vmx);
1155f76a 2458
d77c26fc
MD		 2459 vcpu->interrupt_window_open =
2460 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2461
d77c26fc 2462 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 2463 vmx->launched = 1;
1b6269db
AK		 2464
2465 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2466
2467 /* We need to handle NMIs before interrupts are enabled */
2468 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2469 asm("int $2");
6aa8b732
AK		 2470}
2471
6aa8b732
AK		 2472static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2473 unsigned long addr,
2474 u32 err_code)
2475{
1155f76a
AK		 2476 struct vcpu_vmx *vmx = to_vmx(vcpu);
2477 u32 vect_info = vmx->idt_vectoring_info;
6aa8b732 2478
1165f5fe 2479 ++vcpu->stat.pf_guest;
6aa8b732
AK		 2480
2481 if (is_page_fault(vect_info)) {
2482 printk(KERN_DEBUG "inject_page_fault: "
2483 "double fault 0x%lx @ 0x%lx\n",
2484 addr, vmcs_readl(GUEST_RIP));
2485 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2486 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2487 DF_VECTOR |
2488 INTR_TYPE_EXCEPTION |
2489 INTR_INFO_DELIEVER_CODE_MASK |
2490 INTR_INFO_VALID_MASK);
2491 return;
2492 }
2493 vcpu->cr2 = addr;
2494 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2495 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2496 PF_VECTOR |
2497 INTR_TYPE_EXCEPTION |
2498 INTR_INFO_DELIEVER_CODE_MASK |
2499 INTR_INFO_VALID_MASK);
2500
2501}
2502
2503static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2504{
a2fa3e9f
GH		 2505 struct vcpu_vmx *vmx = to_vmx(vcpu);
2506
2507 if (vmx->vmcs) {
8b9cf98c 2508 on_each_cpu(__vcpu_clear, vmx, 0, 1);
a2fa3e9f
GH		 2509 free_vmcs(vmx->vmcs);
2510 vmx->vmcs = NULL;
6aa8b732
AK		 2511 }
2512}
2513
2514static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2515{
fb3f0f51
RR		 2516 struct vcpu_vmx *vmx = to_vmx(vcpu);
2517
6aa8b732 2518 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 2519 kfree(vmx->host_msrs);
2520 kfree(vmx->guest_msrs);
2521 kvm_vcpu_uninit(vcpu);
a4770347 2522 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 2523}
2524
fb3f0f51 2525static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 2526{
fb3f0f51 2527 int err;
c16f862d 2528 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 2529 int cpu;
6aa8b732 2530
a2fa3e9f 2531 if (!vmx)
fb3f0f51
RR		 2532 return ERR_PTR(-ENOMEM);
2533
2534 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2535 if (err)
2536 goto free_vcpu;
965b58a5 2537
a2fa3e9f 2538 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 2539 if (!vmx->guest_msrs) {
2540 err = -ENOMEM;
2541 goto uninit_vcpu;
2542 }
965b58a5 2543
a2fa3e9f
GH		 2544 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2545 if (!vmx->host_msrs)
fb3f0f51 2546 goto free_guest_msrs;
965b58a5 2547
a2fa3e9f
GH		 2548 vmx->vmcs = alloc_vmcs();
2549 if (!vmx->vmcs)
fb3f0f51 2550 goto free_msrs;
a2fa3e9f
GH		 2551
2552 vmcs_clear(vmx->vmcs);
2553
15ad7146
AK		 2554 cpu = get_cpu();
2555 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 2556 err = vmx_vcpu_setup(vmx);
fb3f0f51 2557 vmx_vcpu_put(&vmx->vcpu);
15ad7146 2558 put_cpu();
fb3f0f51
RR		 2559 if (err)
2560 goto free_vmcs;
2561
2562 return &vmx->vcpu;
2563
2564free_vmcs:
2565 free_vmcs(vmx->vmcs);
2566free_msrs:
2567 kfree(vmx->host_msrs);
2568free_guest_msrs:
2569 kfree(vmx->guest_msrs);
2570uninit_vcpu:
2571 kvm_vcpu_uninit(&vmx->vcpu);
2572free_vcpu:
a4770347 2573 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 2574 return ERR_PTR(err);
6aa8b732
AK		 2575}
2576
002c7f7c
YS		 2577static void __init vmx_check_processor_compat(void *rtn)
2578{
2579 struct vmcs_config vmcs_conf;
2580
2581 *(int *)rtn = 0;
2582 if (setup_vmcs_config(&vmcs_conf) < 0)
2583 *(int *)rtn = -EIO;
2584 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2585 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2586 smp_processor_id());
2587 *(int *)rtn = -EIO;
2588 }
2589}
2590
cbdd1bea 2591static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 2592 .cpu_has_kvm_support = cpu_has_kvm_support,
2593 .disabled_by_bios = vmx_disabled_by_bios,
2594 .hardware_setup = hardware_setup,
2595 .hardware_unsetup = hardware_unsetup,
002c7f7c 2596 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 2597 .hardware_enable = hardware_enable,
2598 .hardware_disable = hardware_disable,
2599
2600 .vcpu_create = vmx_create_vcpu,
2601 .vcpu_free = vmx_free_vcpu,
04d2cc77 2602 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 2603
04d2cc77 2604 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 2605 .vcpu_load = vmx_vcpu_load,
2606 .vcpu_put = vmx_vcpu_put,
774c47f1 2607 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2608
2609 .set_guest_debug = set_guest_debug,
04d2cc77 2610 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 2611 .get_msr = vmx_get_msr,
2612 .set_msr = vmx_set_msr,
2613 .get_segment_base = vmx_get_segment_base,
2614 .get_segment = vmx_get_segment,
2615 .set_segment = vmx_set_segment,
6aa8b732 2616 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2617 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2618 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2619 .set_cr3 = vmx_set_cr3,
2620 .set_cr4 = vmx_set_cr4,
05b3e0c2 2621#ifdef CONFIG_X86_64
6aa8b732
AK		 2622 .set_efer = vmx_set_efer,
2623#endif
2624 .get_idt = vmx_get_idt,
2625 .set_idt = vmx_set_idt,
2626 .get_gdt = vmx_get_gdt,
2627 .set_gdt = vmx_set_gdt,
2628 .cache_regs = vcpu_load_rsp_rip,
2629 .decache_regs = vcpu_put_rsp_rip,
2630 .get_rflags = vmx_get_rflags,
2631 .set_rflags = vmx_set_rflags,
2632
2633 .tlb_flush = vmx_flush_tlb,
2634 .inject_page_fault = vmx_inject_page_fault,
2635
2636 .inject_gp = vmx_inject_gp,
2637
2638 .run = vmx_vcpu_run,
04d2cc77 2639 .handle_exit = kvm_handle_exit,
6aa8b732 2640 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2641 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 2642 .get_irq = vmx_get_irq,
2643 .set_irq = vmx_inject_irq,
04d2cc77
AK		 2644 .inject_pending_irq = vmx_intr_assist,
2645 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 2646
2647 .set_tss_addr = vmx_set_tss_addr,
6aa8b732
AK		 2648};
2649
2650static int __init vmx_init(void)
2651{
fdef3ad1
HQ		 2652 void *iova;
2653 int r;
2654
2655 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2656 if (!vmx_io_bitmap_a)
2657 return -ENOMEM;
2658
2659 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2660 if (!vmx_io_bitmap_b) {
2661 r = -ENOMEM;
2662 goto out;
2663 }
2664
2665 /*
2666 * Allow direct access to the PC debug port (it is often used for I/O
2667 * delays, but the vmexits simply slow things down).
2668 */
2669 iova = kmap(vmx_io_bitmap_a);
2670 memset(iova, 0xff, PAGE_SIZE);
2671 clear_bit(0x80, iova);
cd0536d7 2672 kunmap(vmx_io_bitmap_a);
fdef3ad1
HQ		 2673
2674 iova = kmap(vmx_io_bitmap_b);
2675 memset(iova, 0xff, PAGE_SIZE);
cd0536d7 2676 kunmap(vmx_io_bitmap_b);
fdef3ad1 2677
cb498ea2 2678 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1
HQ		 2679 if (r)
2680 goto out1;
2681
c7addb90
AK		 2682 if (bypass_guest_pf)
2683 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2684
fdef3ad1
HQ		 2685 return 0;
2686
2687out1:
2688 __free_page(vmx_io_bitmap_b);
2689out:
2690 __free_page(vmx_io_bitmap_a);
2691 return r;
6aa8b732
AK		 2692}
2693
2694static void __exit vmx_exit(void)
2695{
fdef3ad1
HQ		 2696 __free_page(vmx_io_bitmap_b);
2697 __free_page(vmx_io_bitmap_a);
2698
cb498ea2 2699 kvm_exit();
6aa8b732
AK		 2700}
2701
2702module_init(vmx_init)
2703module_exit(vmx_exit)
Linux kernel - Deliverables
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