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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * | |
9 | * Authors: | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include "kvm.h" | |
19 | #include "vmx.h" | |
20 | #include "kvm_vmx.h" | |
21 | #include <linux/module.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/highmem.h> | |
07031e14 | 24 | #include <linux/profile.h> |
6aa8b732 | 25 | #include <asm/io.h> |
3b3be0d1 | 26 | #include <asm/desc.h> |
6aa8b732 AK |
27 | |
28 | #include "segment_descriptor.h" | |
29 | ||
6aa8b732 AK |
30 | |
31 | MODULE_AUTHOR("Qumranet"); | |
32 | MODULE_LICENSE("GPL"); | |
33 | ||
34 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); | |
35 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
36 | ||
05b3e0c2 | 37 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
38 | #define HOST_IS_64 1 |
39 | #else | |
40 | #define HOST_IS_64 0 | |
41 | #endif | |
42 | ||
43 | static struct vmcs_descriptor { | |
44 | int size; | |
45 | int order; | |
46 | u32 revision_id; | |
47 | } vmcs_descriptor; | |
48 | ||
49 | #define VMX_SEGMENT_FIELD(seg) \ | |
50 | [VCPU_SREG_##seg] = { \ | |
51 | .selector = GUEST_##seg##_SELECTOR, \ | |
52 | .base = GUEST_##seg##_BASE, \ | |
53 | .limit = GUEST_##seg##_LIMIT, \ | |
54 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
55 | } | |
56 | ||
57 | static struct kvm_vmx_segment_field { | |
58 | unsigned selector; | |
59 | unsigned base; | |
60 | unsigned limit; | |
61 | unsigned ar_bytes; | |
62 | } kvm_vmx_segment_fields[] = { | |
63 | VMX_SEGMENT_FIELD(CS), | |
64 | VMX_SEGMENT_FIELD(DS), | |
65 | VMX_SEGMENT_FIELD(ES), | |
66 | VMX_SEGMENT_FIELD(FS), | |
67 | VMX_SEGMENT_FIELD(GS), | |
68 | VMX_SEGMENT_FIELD(SS), | |
69 | VMX_SEGMENT_FIELD(TR), | |
70 | VMX_SEGMENT_FIELD(LDTR), | |
71 | }; | |
72 | ||
73 | static const u32 vmx_msr_index[] = { | |
05b3e0c2 | 74 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
75 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE, |
76 | #endif | |
77 | MSR_EFER, MSR_K6_STAR, | |
78 | }; | |
79 | #define NR_VMX_MSR (sizeof(vmx_msr_index) / sizeof(*vmx_msr_index)) | |
80 | ||
6aa8b732 AK |
81 | static inline int is_page_fault(u32 intr_info) |
82 | { | |
83 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
84 | INTR_INFO_VALID_MASK)) == | |
85 | (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); | |
86 | } | |
87 | ||
88 | static inline int is_external_interrupt(u32 intr_info) | |
89 | { | |
90 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
91 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
92 | } | |
93 | ||
7725f0ba AK |
94 | static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr) |
95 | { | |
96 | int i; | |
97 | ||
98 | for (i = 0; i < vcpu->nmsrs; ++i) | |
99 | if (vcpu->guest_msrs[i].index == msr) | |
100 | return &vcpu->guest_msrs[i]; | |
8b6d44c7 | 101 | return NULL; |
7725f0ba AK |
102 | } |
103 | ||
6aa8b732 AK |
104 | static void vmcs_clear(struct vmcs *vmcs) |
105 | { | |
106 | u64 phys_addr = __pa(vmcs); | |
107 | u8 error; | |
108 | ||
109 | asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0" | |
110 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
111 | : "cc", "memory"); | |
112 | if (error) | |
113 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
114 | vmcs, phys_addr); | |
115 | } | |
116 | ||
117 | static void __vcpu_clear(void *arg) | |
118 | { | |
119 | struct kvm_vcpu *vcpu = arg; | |
d3b2c338 | 120 | int cpu = raw_smp_processor_id(); |
6aa8b732 AK |
121 | |
122 | if (vcpu->cpu == cpu) | |
123 | vmcs_clear(vcpu->vmcs); | |
124 | if (per_cpu(current_vmcs, cpu) == vcpu->vmcs) | |
125 | per_cpu(current_vmcs, cpu) = NULL; | |
126 | } | |
127 | ||
8d0be2b3 AK |
128 | static void vcpu_clear(struct kvm_vcpu *vcpu) |
129 | { | |
130 | if (vcpu->cpu != raw_smp_processor_id() && vcpu->cpu != -1) | |
131 | smp_call_function_single(vcpu->cpu, __vcpu_clear, vcpu, 0, 1); | |
132 | else | |
133 | __vcpu_clear(vcpu); | |
134 | vcpu->launched = 0; | |
135 | } | |
136 | ||
6aa8b732 AK |
137 | static unsigned long vmcs_readl(unsigned long field) |
138 | { | |
139 | unsigned long value; | |
140 | ||
141 | asm volatile (ASM_VMX_VMREAD_RDX_RAX | |
142 | : "=a"(value) : "d"(field) : "cc"); | |
143 | return value; | |
144 | } | |
145 | ||
146 | static u16 vmcs_read16(unsigned long field) | |
147 | { | |
148 | return vmcs_readl(field); | |
149 | } | |
150 | ||
151 | static u32 vmcs_read32(unsigned long field) | |
152 | { | |
153 | return vmcs_readl(field); | |
154 | } | |
155 | ||
156 | static u64 vmcs_read64(unsigned long field) | |
157 | { | |
05b3e0c2 | 158 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
159 | return vmcs_readl(field); |
160 | #else | |
161 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
162 | #endif | |
163 | } | |
164 | ||
e52de1b8 AK |
165 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
166 | { | |
167 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
168 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
169 | dump_stack(); | |
170 | } | |
171 | ||
6aa8b732 AK |
172 | static void vmcs_writel(unsigned long field, unsigned long value) |
173 | { | |
174 | u8 error; | |
175 | ||
176 | asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0" | |
177 | : "=q"(error) : "a"(value), "d"(field) : "cc" ); | |
e52de1b8 AK |
178 | if (unlikely(error)) |
179 | vmwrite_error(field, value); | |
6aa8b732 AK |
180 | } |
181 | ||
182 | static void vmcs_write16(unsigned long field, u16 value) | |
183 | { | |
184 | vmcs_writel(field, value); | |
185 | } | |
186 | ||
187 | static void vmcs_write32(unsigned long field, u32 value) | |
188 | { | |
189 | vmcs_writel(field, value); | |
190 | } | |
191 | ||
192 | static void vmcs_write64(unsigned long field, u64 value) | |
193 | { | |
05b3e0c2 | 194 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
195 | vmcs_writel(field, value); |
196 | #else | |
197 | vmcs_writel(field, value); | |
198 | asm volatile (""); | |
199 | vmcs_writel(field+1, value >> 32); | |
200 | #endif | |
201 | } | |
202 | ||
203 | /* | |
204 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
205 | * vcpu mutex is already taken. | |
206 | */ | |
207 | static struct kvm_vcpu *vmx_vcpu_load(struct kvm_vcpu *vcpu) | |
208 | { | |
209 | u64 phys_addr = __pa(vcpu->vmcs); | |
210 | int cpu; | |
211 | ||
212 | cpu = get_cpu(); | |
213 | ||
8d0be2b3 AK |
214 | if (vcpu->cpu != cpu) |
215 | vcpu_clear(vcpu); | |
6aa8b732 AK |
216 | |
217 | if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) { | |
218 | u8 error; | |
219 | ||
220 | per_cpu(current_vmcs, cpu) = vcpu->vmcs; | |
221 | asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0" | |
222 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
223 | : "cc"); | |
224 | if (error) | |
225 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
226 | vcpu->vmcs, phys_addr); | |
227 | } | |
228 | ||
229 | if (vcpu->cpu != cpu) { | |
230 | struct descriptor_table dt; | |
231 | unsigned long sysenter_esp; | |
232 | ||
233 | vcpu->cpu = cpu; | |
234 | /* | |
235 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
236 | * processors. | |
237 | */ | |
238 | vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */ | |
239 | get_gdt(&dt); | |
240 | vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ | |
241 | ||
242 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
243 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
244 | } | |
245 | return vcpu; | |
246 | } | |
247 | ||
248 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
249 | { | |
250 | put_cpu(); | |
251 | } | |
252 | ||
774c47f1 AK |
253 | static void vmx_vcpu_decache(struct kvm_vcpu *vcpu) |
254 | { | |
255 | vcpu_clear(vcpu); | |
256 | } | |
257 | ||
6aa8b732 AK |
258 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
259 | { | |
260 | return vmcs_readl(GUEST_RFLAGS); | |
261 | } | |
262 | ||
263 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
264 | { | |
265 | vmcs_writel(GUEST_RFLAGS, rflags); | |
266 | } | |
267 | ||
268 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
269 | { | |
270 | unsigned long rip; | |
271 | u32 interruptibility; | |
272 | ||
273 | rip = vmcs_readl(GUEST_RIP); | |
274 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
275 | vmcs_writel(GUEST_RIP, rip); | |
276 | ||
277 | /* | |
278 | * We emulated an instruction, so temporary interrupt blocking | |
279 | * should be removed, if set. | |
280 | */ | |
281 | interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
282 | if (interruptibility & 3) | |
283 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
284 | interruptibility & ~3); | |
c1150d8c | 285 | vcpu->interrupt_window_open = 1; |
6aa8b732 AK |
286 | } |
287 | ||
288 | static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code) | |
289 | { | |
290 | printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n", | |
291 | vmcs_readl(GUEST_RIP)); | |
292 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); | |
293 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
294 | GP_VECTOR | | |
295 | INTR_TYPE_EXCEPTION | | |
296 | INTR_INFO_DELIEVER_CODE_MASK | | |
297 | INTR_INFO_VALID_MASK); | |
298 | } | |
299 | ||
300 | /* | |
301 | * reads and returns guest's timestamp counter "register" | |
302 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
303 | */ | |
304 | static u64 guest_read_tsc(void) | |
305 | { | |
306 | u64 host_tsc, tsc_offset; | |
307 | ||
308 | rdtscll(host_tsc); | |
309 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
310 | return host_tsc + tsc_offset; | |
311 | } | |
312 | ||
313 | /* | |
314 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
315 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
316 | */ | |
317 | static void guest_write_tsc(u64 guest_tsc) | |
318 | { | |
319 | u64 host_tsc; | |
320 | ||
321 | rdtscll(host_tsc); | |
322 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); | |
323 | } | |
324 | ||
325 | static void reload_tss(void) | |
326 | { | |
05b3e0c2 | 327 | #ifndef CONFIG_X86_64 |
6aa8b732 AK |
328 | |
329 | /* | |
330 | * VT restores TR but not its size. Useless. | |
331 | */ | |
332 | struct descriptor_table gdt; | |
333 | struct segment_descriptor *descs; | |
334 | ||
335 | get_gdt(&gdt); | |
336 | descs = (void *)gdt.base; | |
337 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ | |
338 | load_TR_desc(); | |
339 | #endif | |
340 | } | |
341 | ||
342 | /* | |
343 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
344 | * Returns 0 on success, non-0 otherwise. | |
345 | * Assumes vcpu_load() was already called. | |
346 | */ | |
347 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
348 | { | |
349 | u64 data; | |
350 | struct vmx_msr_entry *msr; | |
351 | ||
352 | if (!pdata) { | |
353 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
354 | return -EINVAL; | |
355 | } | |
356 | ||
357 | switch (msr_index) { | |
05b3e0c2 | 358 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
359 | case MSR_FS_BASE: |
360 | data = vmcs_readl(GUEST_FS_BASE); | |
361 | break; | |
362 | case MSR_GS_BASE: | |
363 | data = vmcs_readl(GUEST_GS_BASE); | |
364 | break; | |
365 | case MSR_EFER: | |
3bab1f5d | 366 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
367 | #endif |
368 | case MSR_IA32_TIME_STAMP_COUNTER: | |
369 | data = guest_read_tsc(); | |
370 | break; | |
371 | case MSR_IA32_SYSENTER_CS: | |
372 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
373 | break; | |
374 | case MSR_IA32_SYSENTER_EIP: | |
375 | data = vmcs_read32(GUEST_SYSENTER_EIP); | |
376 | break; | |
377 | case MSR_IA32_SYSENTER_ESP: | |
378 | data = vmcs_read32(GUEST_SYSENTER_ESP); | |
379 | break; | |
6aa8b732 AK |
380 | default: |
381 | msr = find_msr_entry(vcpu, msr_index); | |
3bab1f5d AK |
382 | if (msr) { |
383 | data = msr->data; | |
384 | break; | |
6aa8b732 | 385 | } |
3bab1f5d | 386 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
387 | } |
388 | ||
389 | *pdata = data; | |
390 | return 0; | |
391 | } | |
392 | ||
393 | /* | |
394 | * Writes msr value into into the appropriate "register". | |
395 | * Returns 0 on success, non-0 otherwise. | |
396 | * Assumes vcpu_load() was already called. | |
397 | */ | |
398 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
399 | { | |
400 | struct vmx_msr_entry *msr; | |
401 | switch (msr_index) { | |
05b3e0c2 | 402 | #ifdef CONFIG_X86_64 |
3bab1f5d AK |
403 | case MSR_EFER: |
404 | return kvm_set_msr_common(vcpu, msr_index, data); | |
6aa8b732 AK |
405 | case MSR_FS_BASE: |
406 | vmcs_writel(GUEST_FS_BASE, data); | |
407 | break; | |
408 | case MSR_GS_BASE: | |
409 | vmcs_writel(GUEST_GS_BASE, data); | |
410 | break; | |
411 | #endif | |
412 | case MSR_IA32_SYSENTER_CS: | |
413 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
414 | break; | |
415 | case MSR_IA32_SYSENTER_EIP: | |
416 | vmcs_write32(GUEST_SYSENTER_EIP, data); | |
417 | break; | |
418 | case MSR_IA32_SYSENTER_ESP: | |
419 | vmcs_write32(GUEST_SYSENTER_ESP, data); | |
420 | break; | |
6aa8b732 AK |
421 | case MSR_IA32_TIME_STAMP_COUNTER: { |
422 | guest_write_tsc(data); | |
423 | break; | |
424 | } | |
6aa8b732 AK |
425 | default: |
426 | msr = find_msr_entry(vcpu, msr_index); | |
3bab1f5d AK |
427 | if (msr) { |
428 | msr->data = data; | |
429 | break; | |
6aa8b732 | 430 | } |
3bab1f5d | 431 | return kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
432 | msr->data = data; |
433 | break; | |
434 | } | |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
439 | /* | |
440 | * Sync the rsp and rip registers into the vcpu structure. This allows | |
441 | * registers to be accessed by indexing vcpu->regs. | |
442 | */ | |
443 | static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu) | |
444 | { | |
445 | vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
446 | vcpu->rip = vmcs_readl(GUEST_RIP); | |
447 | } | |
448 | ||
449 | /* | |
450 | * Syncs rsp and rip back into the vmcs. Should be called after possible | |
451 | * modification. | |
452 | */ | |
453 | static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu) | |
454 | { | |
455 | vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]); | |
456 | vmcs_writel(GUEST_RIP, vcpu->rip); | |
457 | } | |
458 | ||
459 | static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
460 | { | |
461 | unsigned long dr7 = 0x400; | |
462 | u32 exception_bitmap; | |
463 | int old_singlestep; | |
464 | ||
465 | exception_bitmap = vmcs_read32(EXCEPTION_BITMAP); | |
466 | old_singlestep = vcpu->guest_debug.singlestep; | |
467 | ||
468 | vcpu->guest_debug.enabled = dbg->enabled; | |
469 | if (vcpu->guest_debug.enabled) { | |
470 | int i; | |
471 | ||
472 | dr7 |= 0x200; /* exact */ | |
473 | for (i = 0; i < 4; ++i) { | |
474 | if (!dbg->breakpoints[i].enabled) | |
475 | continue; | |
476 | vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address; | |
477 | dr7 |= 2 << (i*2); /* global enable */ | |
478 | dr7 |= 0 << (i*4+16); /* execution breakpoint */ | |
479 | } | |
480 | ||
481 | exception_bitmap |= (1u << 1); /* Trap debug exceptions */ | |
482 | ||
483 | vcpu->guest_debug.singlestep = dbg->singlestep; | |
484 | } else { | |
485 | exception_bitmap &= ~(1u << 1); /* Ignore debug exceptions */ | |
486 | vcpu->guest_debug.singlestep = 0; | |
487 | } | |
488 | ||
489 | if (old_singlestep && !vcpu->guest_debug.singlestep) { | |
490 | unsigned long flags; | |
491 | ||
492 | flags = vmcs_readl(GUEST_RFLAGS); | |
493 | flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
494 | vmcs_writel(GUEST_RFLAGS, flags); | |
495 | } | |
496 | ||
497 | vmcs_write32(EXCEPTION_BITMAP, exception_bitmap); | |
498 | vmcs_writel(GUEST_DR7, dr7); | |
499 | ||
500 | return 0; | |
501 | } | |
502 | ||
503 | static __init int cpu_has_kvm_support(void) | |
504 | { | |
505 | unsigned long ecx = cpuid_ecx(1); | |
506 | return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */ | |
507 | } | |
508 | ||
509 | static __init int vmx_disabled_by_bios(void) | |
510 | { | |
511 | u64 msr; | |
512 | ||
513 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
514 | return (msr & 5) == 1; /* locked but not enabled */ | |
515 | } | |
516 | ||
774c47f1 | 517 | static void hardware_enable(void *garbage) |
6aa8b732 AK |
518 | { |
519 | int cpu = raw_smp_processor_id(); | |
520 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
521 | u64 old; | |
522 | ||
523 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); | |
bfdc0c28 | 524 | if ((old & 5) != 5) |
6aa8b732 AK |
525 | /* enable and lock */ |
526 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5); | |
527 | write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */ | |
528 | asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr) | |
529 | : "memory", "cc"); | |
530 | } | |
531 | ||
532 | static void hardware_disable(void *garbage) | |
533 | { | |
534 | asm volatile (ASM_VMX_VMXOFF : : : "cc"); | |
535 | } | |
536 | ||
537 | static __init void setup_vmcs_descriptor(void) | |
538 | { | |
539 | u32 vmx_msr_low, vmx_msr_high; | |
540 | ||
c68876fd | 541 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
6aa8b732 AK |
542 | vmcs_descriptor.size = vmx_msr_high & 0x1fff; |
543 | vmcs_descriptor.order = get_order(vmcs_descriptor.size); | |
544 | vmcs_descriptor.revision_id = vmx_msr_low; | |
c68876fd | 545 | } |
6aa8b732 AK |
546 | |
547 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
548 | { | |
549 | int node = cpu_to_node(cpu); | |
550 | struct page *pages; | |
551 | struct vmcs *vmcs; | |
552 | ||
553 | pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order); | |
554 | if (!pages) | |
555 | return NULL; | |
556 | vmcs = page_address(pages); | |
557 | memset(vmcs, 0, vmcs_descriptor.size); | |
558 | vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */ | |
559 | return vmcs; | |
560 | } | |
561 | ||
562 | static struct vmcs *alloc_vmcs(void) | |
563 | { | |
d3b2c338 | 564 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
565 | } |
566 | ||
567 | static void free_vmcs(struct vmcs *vmcs) | |
568 | { | |
569 | free_pages((unsigned long)vmcs, vmcs_descriptor.order); | |
570 | } | |
571 | ||
572 | static __exit void free_kvm_area(void) | |
573 | { | |
574 | int cpu; | |
575 | ||
576 | for_each_online_cpu(cpu) | |
577 | free_vmcs(per_cpu(vmxarea, cpu)); | |
578 | } | |
579 | ||
580 | extern struct vmcs *alloc_vmcs_cpu(int cpu); | |
581 | ||
582 | static __init int alloc_kvm_area(void) | |
583 | { | |
584 | int cpu; | |
585 | ||
586 | for_each_online_cpu(cpu) { | |
587 | struct vmcs *vmcs; | |
588 | ||
589 | vmcs = alloc_vmcs_cpu(cpu); | |
590 | if (!vmcs) { | |
591 | free_kvm_area(); | |
592 | return -ENOMEM; | |
593 | } | |
594 | ||
595 | per_cpu(vmxarea, cpu) = vmcs; | |
596 | } | |
597 | return 0; | |
598 | } | |
599 | ||
600 | static __init int hardware_setup(void) | |
601 | { | |
602 | setup_vmcs_descriptor(); | |
603 | return alloc_kvm_area(); | |
604 | } | |
605 | ||
606 | static __exit void hardware_unsetup(void) | |
607 | { | |
608 | free_kvm_area(); | |
609 | } | |
610 | ||
611 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) | |
612 | { | |
613 | if (vcpu->rmode.active) | |
614 | vmcs_write32(EXCEPTION_BITMAP, ~0); | |
615 | else | |
616 | vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR); | |
617 | } | |
618 | ||
619 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) | |
620 | { | |
621 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
622 | ||
623 | if (vmcs_readl(sf->base) == save->base) { | |
624 | vmcs_write16(sf->selector, save->selector); | |
625 | vmcs_writel(sf->base, save->base); | |
626 | vmcs_write32(sf->limit, save->limit); | |
627 | vmcs_write32(sf->ar_bytes, save->ar); | |
628 | } else { | |
629 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
630 | << AR_DPL_SHIFT; | |
631 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
632 | } | |
633 | } | |
634 | ||
635 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
636 | { | |
637 | unsigned long flags; | |
638 | ||
639 | vcpu->rmode.active = 0; | |
640 | ||
641 | vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base); | |
642 | vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit); | |
643 | vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar); | |
644 | ||
645 | flags = vmcs_readl(GUEST_RFLAGS); | |
646 | flags &= ~(IOPL_MASK | X86_EFLAGS_VM); | |
647 | flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT); | |
648 | vmcs_writel(GUEST_RFLAGS, flags); | |
649 | ||
650 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) | | |
651 | (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK)); | |
652 | ||
653 | update_exception_bitmap(vcpu); | |
654 | ||
655 | fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es); | |
656 | fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds); | |
657 | fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs); | |
658 | fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs); | |
659 | ||
660 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
661 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
662 | ||
663 | vmcs_write16(GUEST_CS_SELECTOR, | |
664 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
665 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
666 | } | |
667 | ||
668 | static int rmode_tss_base(struct kvm* kvm) | |
669 | { | |
670 | gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3; | |
671 | return base_gfn << PAGE_SHIFT; | |
672 | } | |
673 | ||
674 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
675 | { | |
676 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
677 | ||
678 | save->selector = vmcs_read16(sf->selector); | |
679 | save->base = vmcs_readl(sf->base); | |
680 | save->limit = vmcs_read32(sf->limit); | |
681 | save->ar = vmcs_read32(sf->ar_bytes); | |
682 | vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4); | |
683 | vmcs_write32(sf->limit, 0xffff); | |
684 | vmcs_write32(sf->ar_bytes, 0xf3); | |
685 | } | |
686 | ||
687 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
688 | { | |
689 | unsigned long flags; | |
690 | ||
691 | vcpu->rmode.active = 1; | |
692 | ||
693 | vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE); | |
694 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); | |
695 | ||
696 | vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); | |
697 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); | |
698 | ||
699 | vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
700 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
701 | ||
702 | flags = vmcs_readl(GUEST_RFLAGS); | |
703 | vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT; | |
704 | ||
705 | flags |= IOPL_MASK | X86_EFLAGS_VM; | |
706 | ||
707 | vmcs_writel(GUEST_RFLAGS, flags); | |
708 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK); | |
709 | update_exception_bitmap(vcpu); | |
710 | ||
711 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); | |
712 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
713 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
714 | ||
715 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 716 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
6aa8b732 AK |
717 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
718 | ||
719 | fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es); | |
720 | fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds); | |
721 | fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs); | |
722 | fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs); | |
723 | } | |
724 | ||
05b3e0c2 | 725 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
726 | |
727 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
728 | { | |
729 | u32 guest_tr_ar; | |
730 | ||
731 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
732 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
733 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
734 | __FUNCTION__); | |
735 | vmcs_write32(GUEST_TR_AR_BYTES, | |
736 | (guest_tr_ar & ~AR_TYPE_MASK) | |
737 | | AR_TYPE_BUSY_64_TSS); | |
738 | } | |
739 | ||
740 | vcpu->shadow_efer |= EFER_LMA; | |
741 | ||
742 | find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME; | |
743 | vmcs_write32(VM_ENTRY_CONTROLS, | |
744 | vmcs_read32(VM_ENTRY_CONTROLS) | |
745 | | VM_ENTRY_CONTROLS_IA32E_MASK); | |
746 | } | |
747 | ||
748 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
749 | { | |
750 | vcpu->shadow_efer &= ~EFER_LMA; | |
751 | ||
752 | vmcs_write32(VM_ENTRY_CONTROLS, | |
753 | vmcs_read32(VM_ENTRY_CONTROLS) | |
754 | & ~VM_ENTRY_CONTROLS_IA32E_MASK); | |
755 | } | |
756 | ||
757 | #endif | |
758 | ||
399badf3 AK |
759 | static void vmx_decache_cr0_cr4_guest_bits(struct kvm_vcpu *vcpu) |
760 | { | |
761 | vcpu->cr0 &= KVM_GUEST_CR0_MASK; | |
762 | vcpu->cr0 |= vmcs_readl(GUEST_CR0) & ~KVM_GUEST_CR0_MASK; | |
763 | ||
764 | vcpu->cr4 &= KVM_GUEST_CR4_MASK; | |
765 | vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK; | |
766 | } | |
767 | ||
6aa8b732 AK |
768 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
769 | { | |
770 | if (vcpu->rmode.active && (cr0 & CR0_PE_MASK)) | |
771 | enter_pmode(vcpu); | |
772 | ||
773 | if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK)) | |
774 | enter_rmode(vcpu); | |
775 | ||
05b3e0c2 | 776 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
777 | if (vcpu->shadow_efer & EFER_LME) { |
778 | if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK)) | |
779 | enter_lmode(vcpu); | |
780 | if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK)) | |
781 | exit_lmode(vcpu); | |
782 | } | |
783 | #endif | |
784 | ||
785 | vmcs_writel(CR0_READ_SHADOW, cr0); | |
786 | vmcs_writel(GUEST_CR0, | |
787 | (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON); | |
788 | vcpu->cr0 = cr0; | |
789 | } | |
790 | ||
791 | /* | |
792 | * Used when restoring the VM to avoid corrupting segment registers | |
793 | */ | |
794 | static void vmx_set_cr0_no_modeswitch(struct kvm_vcpu *vcpu, unsigned long cr0) | |
795 | { | |
796 | vcpu->rmode.active = ((cr0 & CR0_PE_MASK) == 0); | |
797 | update_exception_bitmap(vcpu); | |
798 | vmcs_writel(CR0_READ_SHADOW, cr0); | |
799 | vmcs_writel(GUEST_CR0, | |
800 | (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON); | |
801 | vcpu->cr0 = cr0; | |
802 | } | |
803 | ||
804 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) | |
805 | { | |
806 | vmcs_writel(GUEST_CR3, cr3); | |
807 | } | |
808 | ||
809 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
810 | { | |
811 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
812 | vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ? | |
813 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON)); | |
814 | vcpu->cr4 = cr4; | |
815 | } | |
816 | ||
05b3e0c2 | 817 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
818 | |
819 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
820 | { | |
821 | struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER); | |
822 | ||
823 | vcpu->shadow_efer = efer; | |
824 | if (efer & EFER_LMA) { | |
825 | vmcs_write32(VM_ENTRY_CONTROLS, | |
826 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
827 | VM_ENTRY_CONTROLS_IA32E_MASK); | |
828 | msr->data = efer; | |
829 | ||
830 | } else { | |
831 | vmcs_write32(VM_ENTRY_CONTROLS, | |
832 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
833 | ~VM_ENTRY_CONTROLS_IA32E_MASK); | |
834 | ||
835 | msr->data = efer & ~EFER_LME; | |
836 | } | |
837 | } | |
838 | ||
839 | #endif | |
840 | ||
841 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
842 | { | |
843 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
844 | ||
845 | return vmcs_readl(sf->base); | |
846 | } | |
847 | ||
848 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
849 | struct kvm_segment *var, int seg) | |
850 | { | |
851 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
852 | u32 ar; | |
853 | ||
854 | var->base = vmcs_readl(sf->base); | |
855 | var->limit = vmcs_read32(sf->limit); | |
856 | var->selector = vmcs_read16(sf->selector); | |
857 | ar = vmcs_read32(sf->ar_bytes); | |
858 | if (ar & AR_UNUSABLE_MASK) | |
859 | ar = 0; | |
860 | var->type = ar & 15; | |
861 | var->s = (ar >> 4) & 1; | |
862 | var->dpl = (ar >> 5) & 3; | |
863 | var->present = (ar >> 7) & 1; | |
864 | var->avl = (ar >> 12) & 1; | |
865 | var->l = (ar >> 13) & 1; | |
866 | var->db = (ar >> 14) & 1; | |
867 | var->g = (ar >> 15) & 1; | |
868 | var->unusable = (ar >> 16) & 1; | |
869 | } | |
870 | ||
871 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
872 | struct kvm_segment *var, int seg) | |
873 | { | |
874 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
875 | u32 ar; | |
876 | ||
877 | vmcs_writel(sf->base, var->base); | |
878 | vmcs_write32(sf->limit, var->limit); | |
879 | vmcs_write16(sf->selector, var->selector); | |
880 | if (var->unusable) | |
881 | ar = 1 << 16; | |
882 | else { | |
883 | ar = var->type & 15; | |
884 | ar |= (var->s & 1) << 4; | |
885 | ar |= (var->dpl & 3) << 5; | |
886 | ar |= (var->present & 1) << 7; | |
887 | ar |= (var->avl & 1) << 12; | |
888 | ar |= (var->l & 1) << 13; | |
889 | ar |= (var->db & 1) << 14; | |
890 | ar |= (var->g & 1) << 15; | |
891 | } | |
f7fbf1fd UL |
892 | if (ar == 0) /* a 0 value means unusable */ |
893 | ar = AR_UNUSABLE_MASK; | |
6aa8b732 AK |
894 | vmcs_write32(sf->ar_bytes, ar); |
895 | } | |
896 | ||
6aa8b732 AK |
897 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
898 | { | |
899 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
900 | ||
901 | *db = (ar >> 14) & 1; | |
902 | *l = (ar >> 13) & 1; | |
903 | } | |
904 | ||
905 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
906 | { | |
907 | dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
908 | dt->base = vmcs_readl(GUEST_IDTR_BASE); | |
909 | } | |
910 | ||
911 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
912 | { | |
913 | vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); | |
914 | vmcs_writel(GUEST_IDTR_BASE, dt->base); | |
915 | } | |
916 | ||
917 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
918 | { | |
919 | dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
920 | dt->base = vmcs_readl(GUEST_GDTR_BASE); | |
921 | } | |
922 | ||
923 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
924 | { | |
925 | vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); | |
926 | vmcs_writel(GUEST_GDTR_BASE, dt->base); | |
927 | } | |
928 | ||
929 | static int init_rmode_tss(struct kvm* kvm) | |
930 | { | |
931 | struct page *p1, *p2, *p3; | |
932 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; | |
933 | char *page; | |
934 | ||
935 | p1 = _gfn_to_page(kvm, fn++); | |
936 | p2 = _gfn_to_page(kvm, fn++); | |
937 | p3 = _gfn_to_page(kvm, fn); | |
938 | ||
939 | if (!p1 || !p2 || !p3) { | |
940 | kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__); | |
941 | return 0; | |
942 | } | |
943 | ||
944 | page = kmap_atomic(p1, KM_USER0); | |
945 | memset(page, 0, PAGE_SIZE); | |
946 | *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; | |
947 | kunmap_atomic(page, KM_USER0); | |
948 | ||
949 | page = kmap_atomic(p2, KM_USER0); | |
950 | memset(page, 0, PAGE_SIZE); | |
951 | kunmap_atomic(page, KM_USER0); | |
952 | ||
953 | page = kmap_atomic(p3, KM_USER0); | |
954 | memset(page, 0, PAGE_SIZE); | |
955 | *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0; | |
956 | kunmap_atomic(page, KM_USER0); | |
957 | ||
958 | return 1; | |
959 | } | |
960 | ||
961 | static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val) | |
962 | { | |
963 | u32 msr_high, msr_low; | |
964 | ||
965 | rdmsr(msr, msr_low, msr_high); | |
966 | ||
967 | val &= msr_high; | |
968 | val |= msr_low; | |
969 | vmcs_write32(vmcs_field, val); | |
970 | } | |
971 | ||
972 | static void seg_setup(int seg) | |
973 | { | |
974 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
975 | ||
976 | vmcs_write16(sf->selector, 0); | |
977 | vmcs_writel(sf->base, 0); | |
978 | vmcs_write32(sf->limit, 0xffff); | |
979 | vmcs_write32(sf->ar_bytes, 0x93); | |
980 | } | |
981 | ||
982 | /* | |
983 | * Sets up the vmcs for emulated real mode. | |
984 | */ | |
985 | static int vmx_vcpu_setup(struct kvm_vcpu *vcpu) | |
986 | { | |
987 | u32 host_sysenter_cs; | |
988 | u32 junk; | |
989 | unsigned long a; | |
990 | struct descriptor_table dt; | |
991 | int i; | |
992 | int ret = 0; | |
993 | int nr_good_msrs; | |
994 | extern asmlinkage void kvm_vmx_return(void); | |
995 | ||
996 | if (!init_rmode_tss(vcpu->kvm)) { | |
997 | ret = -ENOMEM; | |
998 | goto out; | |
999 | } | |
1000 | ||
1001 | memset(vcpu->regs, 0, sizeof(vcpu->regs)); | |
1002 | vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val(); | |
1003 | vcpu->cr8 = 0; | |
1004 | vcpu->apic_base = 0xfee00000 | | |
1005 | /*for vcpu 0*/ MSR_IA32_APICBASE_BSP | | |
1006 | MSR_IA32_APICBASE_ENABLE; | |
1007 | ||
1008 | fx_init(vcpu); | |
1009 | ||
1010 | /* | |
1011 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
1012 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
1013 | */ | |
1014 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); | |
1015 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
1016 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); | |
1017 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1018 | ||
1019 | seg_setup(VCPU_SREG_DS); | |
1020 | seg_setup(VCPU_SREG_ES); | |
1021 | seg_setup(VCPU_SREG_FS); | |
1022 | seg_setup(VCPU_SREG_GS); | |
1023 | seg_setup(VCPU_SREG_SS); | |
1024 | ||
1025 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
1026 | vmcs_writel(GUEST_TR_BASE, 0); | |
1027 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
1028 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
1029 | ||
1030 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
1031 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
1032 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
1033 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
1034 | ||
1035 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
1036 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
1037 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
1038 | ||
1039 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
1040 | vmcs_writel(GUEST_RIP, 0xfff0); | |
1041 | vmcs_writel(GUEST_RSP, 0); | |
1042 | ||
6aa8b732 AK |
1043 | //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 |
1044 | vmcs_writel(GUEST_DR7, 0x400); | |
1045 | ||
1046 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
1047 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
1048 | ||
1049 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
1050 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
1051 | ||
1052 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
1053 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
1054 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
1055 | ||
1056 | /* I/O */ | |
1057 | vmcs_write64(IO_BITMAP_A, 0); | |
1058 | vmcs_write64(IO_BITMAP_B, 0); | |
1059 | ||
1060 | guest_write_tsc(0); | |
1061 | ||
1062 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ | |
1063 | ||
1064 | /* Special registers */ | |
1065 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
1066 | ||
1067 | /* Control */ | |
c68876fd | 1068 | vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS, |
6aa8b732 AK |
1069 | PIN_BASED_VM_EXEC_CONTROL, |
1070 | PIN_BASED_EXT_INTR_MASK /* 20.6.1 */ | |
1071 | | PIN_BASED_NMI_EXITING /* 20.6.1 */ | |
1072 | ); | |
c68876fd | 1073 | vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS, |
6aa8b732 AK |
1074 | CPU_BASED_VM_EXEC_CONTROL, |
1075 | CPU_BASED_HLT_EXITING /* 20.6.2 */ | |
1076 | | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */ | |
1077 | | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */ | |
1078 | | CPU_BASED_UNCOND_IO_EXITING /* 20.6.2 */ | |
6aa8b732 AK |
1079 | | CPU_BASED_MOV_DR_EXITING |
1080 | | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */ | |
1081 | ); | |
1082 | ||
1083 | vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR); | |
1084 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); | |
1085 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
1086 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ | |
1087 | ||
1088 | vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */ | |
1089 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
1090 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
1091 | ||
1092 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
1093 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1094 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1095 | vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */ | |
1096 | vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */ | |
1097 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
05b3e0c2 | 1098 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1099 | rdmsrl(MSR_FS_BASE, a); |
1100 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
1101 | rdmsrl(MSR_GS_BASE, a); | |
1102 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
1103 | #else | |
1104 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
1105 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
1106 | #endif | |
1107 | ||
1108 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
1109 | ||
1110 | get_idt(&dt); | |
1111 | vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ | |
1112 | ||
1113 | ||
1114 | vmcs_writel(HOST_RIP, (unsigned long)kvm_vmx_return); /* 22.2.5 */ | |
1115 | ||
1116 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
1117 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
1118 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
1119 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
1120 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
1121 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
1122 | ||
6aa8b732 AK |
1123 | for (i = 0; i < NR_VMX_MSR; ++i) { |
1124 | u32 index = vmx_msr_index[i]; | |
1125 | u32 data_low, data_high; | |
1126 | u64 data; | |
1127 | int j = vcpu->nmsrs; | |
1128 | ||
1129 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
1130 | continue; | |
432bd6cb AK |
1131 | if (wrmsr_safe(index, data_low, data_high) < 0) |
1132 | continue; | |
6aa8b732 AK |
1133 | data = data_low | ((u64)data_high << 32); |
1134 | vcpu->host_msrs[j].index = index; | |
1135 | vcpu->host_msrs[j].reserved = 0; | |
1136 | vcpu->host_msrs[j].data = data; | |
1137 | vcpu->guest_msrs[j] = vcpu->host_msrs[j]; | |
1138 | ++vcpu->nmsrs; | |
1139 | } | |
1140 | printk(KERN_DEBUG "kvm: msrs: %d\n", vcpu->nmsrs); | |
1141 | ||
1142 | nr_good_msrs = vcpu->nmsrs - NR_BAD_MSRS; | |
1143 | vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR, | |
1144 | virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS)); | |
1145 | vmcs_writel(VM_EXIT_MSR_STORE_ADDR, | |
1146 | virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS)); | |
1147 | vmcs_writel(VM_EXIT_MSR_LOAD_ADDR, | |
1148 | virt_to_phys(vcpu->host_msrs + NR_BAD_MSRS)); | |
c68876fd | 1149 | vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS, VM_EXIT_CONTROLS, |
6aa8b732 AK |
1150 | (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */ |
1151 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */ | |
1152 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */ | |
1153 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */ | |
1154 | ||
1155 | ||
1156 | /* 22.2.1, 20.8.1 */ | |
c68876fd | 1157 | vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS, |
6aa8b732 AK |
1158 | VM_ENTRY_CONTROLS, 0); |
1159 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ | |
1160 | ||
3b99ab24 | 1161 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1162 | vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0); |
1163 | vmcs_writel(TPR_THRESHOLD, 0); | |
3b99ab24 | 1164 | #endif |
6aa8b732 AK |
1165 | |
1166 | vmcs_writel(CR0_GUEST_HOST_MASK, KVM_GUEST_CR0_MASK); | |
1167 | vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK); | |
1168 | ||
1169 | vcpu->cr0 = 0x60000010; | |
1170 | vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode | |
1171 | vmx_set_cr4(vcpu, 0); | |
05b3e0c2 | 1172 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1173 | vmx_set_efer(vcpu, 0); |
1174 | #endif | |
1175 | ||
1176 | return 0; | |
1177 | ||
6aa8b732 AK |
1178 | out: |
1179 | return ret; | |
1180 | } | |
1181 | ||
1182 | static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq) | |
1183 | { | |
1184 | u16 ent[2]; | |
1185 | u16 cs; | |
1186 | u16 ip; | |
1187 | unsigned long flags; | |
1188 | unsigned long ss_base = vmcs_readl(GUEST_SS_BASE); | |
1189 | u16 sp = vmcs_readl(GUEST_RSP); | |
1190 | u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
1191 | ||
1192 | if (sp > ss_limit || sp - 6 > sp) { | |
1193 | vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n", | |
1194 | __FUNCTION__, | |
1195 | vmcs_readl(GUEST_RSP), | |
1196 | vmcs_readl(GUEST_SS_BASE), | |
1197 | vmcs_read32(GUEST_SS_LIMIT)); | |
1198 | return; | |
1199 | } | |
1200 | ||
1201 | if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) != | |
1202 | sizeof(ent)) { | |
1203 | vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__); | |
1204 | return; | |
1205 | } | |
1206 | ||
1207 | flags = vmcs_readl(GUEST_RFLAGS); | |
1208 | cs = vmcs_readl(GUEST_CS_BASE) >> 4; | |
1209 | ip = vmcs_readl(GUEST_RIP); | |
1210 | ||
1211 | ||
1212 | if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 || | |
1213 | kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 || | |
1214 | kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) { | |
1215 | vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__); | |
1216 | return; | |
1217 | } | |
1218 | ||
1219 | vmcs_writel(GUEST_RFLAGS, flags & | |
1220 | ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF)); | |
1221 | vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ; | |
1222 | vmcs_writel(GUEST_CS_BASE, ent[1] << 4); | |
1223 | vmcs_writel(GUEST_RIP, ent[0]); | |
1224 | vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6)); | |
1225 | } | |
1226 | ||
1227 | static void kvm_do_inject_irq(struct kvm_vcpu *vcpu) | |
1228 | { | |
1229 | int word_index = __ffs(vcpu->irq_summary); | |
1230 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
1231 | int irq = word_index * BITS_PER_LONG + bit_index; | |
1232 | ||
1233 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
1234 | if (!vcpu->irq_pending[word_index]) | |
1235 | clear_bit(word_index, &vcpu->irq_summary); | |
1236 | ||
1237 | if (vcpu->rmode.active) { | |
1238 | inject_rmode_irq(vcpu, irq); | |
1239 | return; | |
1240 | } | |
1241 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
1242 | irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1243 | } | |
1244 | ||
c1150d8c DL |
1245 | |
1246 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, | |
1247 | struct kvm_run *kvm_run) | |
6aa8b732 | 1248 | { |
c1150d8c DL |
1249 | u32 cpu_based_vm_exec_control; |
1250 | ||
1251 | vcpu->interrupt_window_open = | |
1252 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
1253 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
1254 | ||
1255 | if (vcpu->interrupt_window_open && | |
1256 | vcpu->irq_summary && | |
1257 | !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK)) | |
6aa8b732 | 1258 | /* |
c1150d8c | 1259 | * If interrupts enabled, and not blocked by sti or mov ss. Good. |
6aa8b732 AK |
1260 | */ |
1261 | kvm_do_inject_irq(vcpu); | |
c1150d8c DL |
1262 | |
1263 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
1264 | if (!vcpu->interrupt_window_open && | |
1265 | (vcpu->irq_summary || kvm_run->request_interrupt_window)) | |
6aa8b732 AK |
1266 | /* |
1267 | * Interrupts blocked. Wait for unblock. | |
1268 | */ | |
c1150d8c DL |
1269 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; |
1270 | else | |
1271 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
1272 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
6aa8b732 AK |
1273 | } |
1274 | ||
1275 | static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu) | |
1276 | { | |
1277 | struct kvm_guest_debug *dbg = &vcpu->guest_debug; | |
1278 | ||
1279 | set_debugreg(dbg->bp[0], 0); | |
1280 | set_debugreg(dbg->bp[1], 1); | |
1281 | set_debugreg(dbg->bp[2], 2); | |
1282 | set_debugreg(dbg->bp[3], 3); | |
1283 | ||
1284 | if (dbg->singlestep) { | |
1285 | unsigned long flags; | |
1286 | ||
1287 | flags = vmcs_readl(GUEST_RFLAGS); | |
1288 | flags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
1289 | vmcs_writel(GUEST_RFLAGS, flags); | |
1290 | } | |
1291 | } | |
1292 | ||
1293 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
1294 | int vec, u32 err_code) | |
1295 | { | |
1296 | if (!vcpu->rmode.active) | |
1297 | return 0; | |
1298 | ||
1299 | if (vec == GP_VECTOR && err_code == 0) | |
1300 | if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE) | |
1301 | return 1; | |
1302 | return 0; | |
1303 | } | |
1304 | ||
1305 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1306 | { | |
1307 | u32 intr_info, error_code; | |
1308 | unsigned long cr2, rip; | |
1309 | u32 vect_info; | |
1310 | enum emulation_result er; | |
e2dec939 | 1311 | int r; |
6aa8b732 AK |
1312 | |
1313 | vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
1314 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
1315 | ||
1316 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
1317 | !is_page_fault(intr_info)) { | |
1318 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " | |
1319 | "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info); | |
1320 | } | |
1321 | ||
1322 | if (is_external_interrupt(vect_info)) { | |
1323 | int irq = vect_info & VECTORING_INFO_VECTOR_MASK; | |
1324 | set_bit(irq, vcpu->irq_pending); | |
1325 | set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary); | |
1326 | } | |
1327 | ||
1328 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */ | |
1329 | asm ("int $2"); | |
1330 | return 1; | |
1331 | } | |
1332 | error_code = 0; | |
1333 | rip = vmcs_readl(GUEST_RIP); | |
1334 | if (intr_info & INTR_INFO_DELIEVER_CODE_MASK) | |
1335 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
1336 | if (is_page_fault(intr_info)) { | |
1337 | cr2 = vmcs_readl(EXIT_QUALIFICATION); | |
1338 | ||
1339 | spin_lock(&vcpu->kvm->lock); | |
e2dec939 AK |
1340 | r = kvm_mmu_page_fault(vcpu, cr2, error_code); |
1341 | if (r < 0) { | |
1342 | spin_unlock(&vcpu->kvm->lock); | |
1343 | return r; | |
1344 | } | |
1345 | if (!r) { | |
6aa8b732 AK |
1346 | spin_unlock(&vcpu->kvm->lock); |
1347 | return 1; | |
1348 | } | |
1349 | ||
1350 | er = emulate_instruction(vcpu, kvm_run, cr2, error_code); | |
1351 | spin_unlock(&vcpu->kvm->lock); | |
1352 | ||
1353 | switch (er) { | |
1354 | case EMULATE_DONE: | |
1355 | return 1; | |
1356 | case EMULATE_DO_MMIO: | |
1357 | ++kvm_stat.mmio_exits; | |
1358 | kvm_run->exit_reason = KVM_EXIT_MMIO; | |
1359 | return 0; | |
1360 | case EMULATE_FAIL: | |
1361 | vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__); | |
1362 | break; | |
1363 | default: | |
1364 | BUG(); | |
1365 | } | |
1366 | } | |
1367 | ||
1368 | if (vcpu->rmode.active && | |
1369 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, | |
1370 | error_code)) | |
1371 | return 1; | |
1372 | ||
1373 | if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) { | |
1374 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
1375 | return 0; | |
1376 | } | |
1377 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; | |
1378 | kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK; | |
1379 | kvm_run->ex.error_code = error_code; | |
1380 | return 0; | |
1381 | } | |
1382 | ||
1383 | static int handle_external_interrupt(struct kvm_vcpu *vcpu, | |
1384 | struct kvm_run *kvm_run) | |
1385 | { | |
1386 | ++kvm_stat.irq_exits; | |
1387 | return 1; | |
1388 | } | |
1389 | ||
988ad74f AK |
1390 | static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1391 | { | |
1392 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1393 | return 0; | |
1394 | } | |
6aa8b732 AK |
1395 | |
1396 | static int get_io_count(struct kvm_vcpu *vcpu, u64 *count) | |
1397 | { | |
1398 | u64 inst; | |
1399 | gva_t rip; | |
1400 | int countr_size; | |
1401 | int i, n; | |
1402 | ||
1403 | if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) { | |
1404 | countr_size = 2; | |
1405 | } else { | |
1406 | u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1407 | ||
1408 | countr_size = (cs_ar & AR_L_MASK) ? 8: | |
1409 | (cs_ar & AR_DB_MASK) ? 4: 2; | |
1410 | } | |
1411 | ||
1412 | rip = vmcs_readl(GUEST_RIP); | |
1413 | if (countr_size != 8) | |
1414 | rip += vmcs_readl(GUEST_CS_BASE); | |
1415 | ||
1416 | n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst); | |
1417 | ||
1418 | for (i = 0; i < n; i++) { | |
1419 | switch (((u8*)&inst)[i]) { | |
1420 | case 0xf0: | |
1421 | case 0xf2: | |
1422 | case 0xf3: | |
1423 | case 0x2e: | |
1424 | case 0x36: | |
1425 | case 0x3e: | |
1426 | case 0x26: | |
1427 | case 0x64: | |
1428 | case 0x65: | |
1429 | case 0x66: | |
1430 | break; | |
1431 | case 0x67: | |
1432 | countr_size = (countr_size == 2) ? 4: (countr_size >> 1); | |
1433 | default: | |
1434 | goto done; | |
1435 | } | |
1436 | } | |
1437 | return 0; | |
1438 | done: | |
1439 | countr_size *= 8; | |
1440 | *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size)); | |
1441 | return 1; | |
1442 | } | |
1443 | ||
1444 | static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1445 | { | |
1446 | u64 exit_qualification; | |
1447 | ||
1448 | ++kvm_stat.io_exits; | |
1449 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
1450 | kvm_run->exit_reason = KVM_EXIT_IO; | |
1451 | if (exit_qualification & 8) | |
1452 | kvm_run->io.direction = KVM_EXIT_IO_IN; | |
1453 | else | |
1454 | kvm_run->io.direction = KVM_EXIT_IO_OUT; | |
1455 | kvm_run->io.size = (exit_qualification & 7) + 1; | |
1456 | kvm_run->io.string = (exit_qualification & 16) != 0; | |
1457 | kvm_run->io.string_down | |
1458 | = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0; | |
1459 | kvm_run->io.rep = (exit_qualification & 32) != 0; | |
1460 | kvm_run->io.port = exit_qualification >> 16; | |
1461 | if (kvm_run->io.string) { | |
1462 | if (!get_io_count(vcpu, &kvm_run->io.count)) | |
1463 | return 1; | |
1464 | kvm_run->io.address = vmcs_readl(GUEST_LINEAR_ADDRESS); | |
1465 | } else | |
1466 | kvm_run->io.value = vcpu->regs[VCPU_REGS_RAX]; /* rax */ | |
1467 | return 0; | |
1468 | } | |
1469 | ||
6aa8b732 AK |
1470 | static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1471 | { | |
1472 | u64 exit_qualification; | |
1473 | int cr; | |
1474 | int reg; | |
1475 | ||
1476 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
1477 | cr = exit_qualification & 15; | |
1478 | reg = (exit_qualification >> 8) & 15; | |
1479 | switch ((exit_qualification >> 4) & 3) { | |
1480 | case 0: /* mov to cr */ | |
1481 | switch (cr) { | |
1482 | case 0: | |
1483 | vcpu_load_rsp_rip(vcpu); | |
1484 | set_cr0(vcpu, vcpu->regs[reg]); | |
1485 | skip_emulated_instruction(vcpu); | |
1486 | return 1; | |
1487 | case 3: | |
1488 | vcpu_load_rsp_rip(vcpu); | |
1489 | set_cr3(vcpu, vcpu->regs[reg]); | |
1490 | skip_emulated_instruction(vcpu); | |
1491 | return 1; | |
1492 | case 4: | |
1493 | vcpu_load_rsp_rip(vcpu); | |
1494 | set_cr4(vcpu, vcpu->regs[reg]); | |
1495 | skip_emulated_instruction(vcpu); | |
1496 | return 1; | |
1497 | case 8: | |
1498 | vcpu_load_rsp_rip(vcpu); | |
1499 | set_cr8(vcpu, vcpu->regs[reg]); | |
1500 | skip_emulated_instruction(vcpu); | |
1501 | return 1; | |
1502 | }; | |
1503 | break; | |
1504 | case 1: /*mov from cr*/ | |
1505 | switch (cr) { | |
1506 | case 3: | |
1507 | vcpu_load_rsp_rip(vcpu); | |
1508 | vcpu->regs[reg] = vcpu->cr3; | |
1509 | vcpu_put_rsp_rip(vcpu); | |
1510 | skip_emulated_instruction(vcpu); | |
1511 | return 1; | |
1512 | case 8: | |
1513 | printk(KERN_DEBUG "handle_cr: read CR8 " | |
1514 | "cpu erratum AA15\n"); | |
1515 | vcpu_load_rsp_rip(vcpu); | |
1516 | vcpu->regs[reg] = vcpu->cr8; | |
1517 | vcpu_put_rsp_rip(vcpu); | |
1518 | skip_emulated_instruction(vcpu); | |
1519 | return 1; | |
1520 | } | |
1521 | break; | |
1522 | case 3: /* lmsw */ | |
1523 | lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f); | |
1524 | ||
1525 | skip_emulated_instruction(vcpu); | |
1526 | return 1; | |
1527 | default: | |
1528 | break; | |
1529 | } | |
1530 | kvm_run->exit_reason = 0; | |
1531 | printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n", | |
1532 | (int)(exit_qualification >> 4) & 3, cr); | |
1533 | return 0; | |
1534 | } | |
1535 | ||
1536 | static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1537 | { | |
1538 | u64 exit_qualification; | |
1539 | unsigned long val; | |
1540 | int dr, reg; | |
1541 | ||
1542 | /* | |
1543 | * FIXME: this code assumes the host is debugging the guest. | |
1544 | * need to deal with guest debugging itself too. | |
1545 | */ | |
1546 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
1547 | dr = exit_qualification & 7; | |
1548 | reg = (exit_qualification >> 8) & 15; | |
1549 | vcpu_load_rsp_rip(vcpu); | |
1550 | if (exit_qualification & 16) { | |
1551 | /* mov from dr */ | |
1552 | switch (dr) { | |
1553 | case 6: | |
1554 | val = 0xffff0ff0; | |
1555 | break; | |
1556 | case 7: | |
1557 | val = 0x400; | |
1558 | break; | |
1559 | default: | |
1560 | val = 0; | |
1561 | } | |
1562 | vcpu->regs[reg] = val; | |
1563 | } else { | |
1564 | /* mov to dr */ | |
1565 | } | |
1566 | vcpu_put_rsp_rip(vcpu); | |
1567 | skip_emulated_instruction(vcpu); | |
1568 | return 1; | |
1569 | } | |
1570 | ||
1571 | static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1572 | { | |
1573 | kvm_run->exit_reason = KVM_EXIT_CPUID; | |
1574 | return 0; | |
1575 | } | |
1576 | ||
1577 | static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1578 | { | |
1579 | u32 ecx = vcpu->regs[VCPU_REGS_RCX]; | |
1580 | u64 data; | |
1581 | ||
1582 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
1583 | vmx_inject_gp(vcpu, 0); | |
1584 | return 1; | |
1585 | } | |
1586 | ||
1587 | /* FIXME: handling of bits 32:63 of rax, rdx */ | |
1588 | vcpu->regs[VCPU_REGS_RAX] = data & -1u; | |
1589 | vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
1590 | skip_emulated_instruction(vcpu); | |
1591 | return 1; | |
1592 | } | |
1593 | ||
1594 | static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1595 | { | |
1596 | u32 ecx = vcpu->regs[VCPU_REGS_RCX]; | |
1597 | u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u) | |
1598 | | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32); | |
1599 | ||
1600 | if (vmx_set_msr(vcpu, ecx, data) != 0) { | |
1601 | vmx_inject_gp(vcpu, 0); | |
1602 | return 1; | |
1603 | } | |
1604 | ||
1605 | skip_emulated_instruction(vcpu); | |
1606 | return 1; | |
1607 | } | |
1608 | ||
c1150d8c DL |
1609 | static void post_kvm_run_save(struct kvm_vcpu *vcpu, |
1610 | struct kvm_run *kvm_run) | |
1611 | { | |
1612 | kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0; | |
1613 | kvm_run->cr8 = vcpu->cr8; | |
1614 | kvm_run->apic_base = vcpu->apic_base; | |
1615 | kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open && | |
1616 | vcpu->irq_summary == 0); | |
1617 | } | |
1618 | ||
6aa8b732 AK |
1619 | static int handle_interrupt_window(struct kvm_vcpu *vcpu, |
1620 | struct kvm_run *kvm_run) | |
1621 | { | |
c1150d8c DL |
1622 | /* |
1623 | * If the user space waits to inject interrupts, exit as soon as | |
1624 | * possible | |
1625 | */ | |
1626 | if (kvm_run->request_interrupt_window && | |
022a9308 | 1627 | !vcpu->irq_summary) { |
c1150d8c DL |
1628 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1629 | ++kvm_stat.irq_window_exits; | |
1630 | return 0; | |
1631 | } | |
6aa8b732 AK |
1632 | return 1; |
1633 | } | |
1634 | ||
1635 | static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1636 | { | |
1637 | skip_emulated_instruction(vcpu); | |
c1150d8c | 1638 | if (vcpu->irq_summary) |
6aa8b732 AK |
1639 | return 1; |
1640 | ||
1641 | kvm_run->exit_reason = KVM_EXIT_HLT; | |
c1150d8c | 1642 | ++kvm_stat.halt_exits; |
6aa8b732 AK |
1643 | return 0; |
1644 | } | |
1645 | ||
1646 | /* | |
1647 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
1648 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
1649 | * to be done to userspace and return 0. | |
1650 | */ | |
1651 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, | |
1652 | struct kvm_run *kvm_run) = { | |
1653 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, | |
1654 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 1655 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
6aa8b732 | 1656 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
1657 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
1658 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
1659 | [EXIT_REASON_CPUID] = handle_cpuid, | |
1660 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
1661 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
1662 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
1663 | [EXIT_REASON_HLT] = handle_halt, | |
1664 | }; | |
1665 | ||
1666 | static const int kvm_vmx_max_exit_handlers = | |
1667 | sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers); | |
1668 | ||
1669 | /* | |
1670 | * The guest has exited. See if we can fix it or if we need userspace | |
1671 | * assistance. | |
1672 | */ | |
1673 | static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |
1674 | { | |
1675 | u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
1676 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); | |
1677 | ||
1678 | if ( (vectoring_info & VECTORING_INFO_VALID_MASK) && | |
1679 | exit_reason != EXIT_REASON_EXCEPTION_NMI ) | |
1680 | printk(KERN_WARNING "%s: unexpected, valid vectoring info and " | |
1681 | "exit reason is 0x%x\n", __FUNCTION__, exit_reason); | |
1682 | kvm_run->instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
1683 | if (exit_reason < kvm_vmx_max_exit_handlers | |
1684 | && kvm_vmx_exit_handlers[exit_reason]) | |
1685 | return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run); | |
1686 | else { | |
1687 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
1688 | kvm_run->hw.hardware_exit_reason = exit_reason; | |
1689 | } | |
1690 | return 0; | |
1691 | } | |
1692 | ||
c1150d8c DL |
1693 | /* |
1694 | * Check if userspace requested an interrupt window, and that the | |
1695 | * interrupt window is open. | |
1696 | * | |
1697 | * No need to exit to userspace if we already have an interrupt queued. | |
1698 | */ | |
1699 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu, | |
1700 | struct kvm_run *kvm_run) | |
1701 | { | |
1702 | return (!vcpu->irq_summary && | |
1703 | kvm_run->request_interrupt_window && | |
1704 | vcpu->interrupt_window_open && | |
1705 | (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)); | |
1706 | } | |
1707 | ||
6aa8b732 AK |
1708 | static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1709 | { | |
1710 | u8 fail; | |
1711 | u16 fs_sel, gs_sel, ldt_sel; | |
1712 | int fs_gs_ldt_reload_needed; | |
e2dec939 | 1713 | int r; |
6aa8b732 AK |
1714 | |
1715 | again: | |
1716 | /* | |
1717 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
1718 | * allow segment selectors with cpl > 0 or ti == 1. | |
1719 | */ | |
1720 | fs_sel = read_fs(); | |
1721 | gs_sel = read_gs(); | |
1722 | ldt_sel = read_ldt(); | |
1723 | fs_gs_ldt_reload_needed = (fs_sel & 7) | (gs_sel & 7) | ldt_sel; | |
1724 | if (!fs_gs_ldt_reload_needed) { | |
1725 | vmcs_write16(HOST_FS_SELECTOR, fs_sel); | |
1726 | vmcs_write16(HOST_GS_SELECTOR, gs_sel); | |
1727 | } else { | |
1728 | vmcs_write16(HOST_FS_SELECTOR, 0); | |
1729 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
1730 | } | |
1731 | ||
05b3e0c2 | 1732 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1733 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); |
1734 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
1735 | #else | |
1736 | vmcs_writel(HOST_FS_BASE, segment_base(fs_sel)); | |
1737 | vmcs_writel(HOST_GS_BASE, segment_base(gs_sel)); | |
1738 | #endif | |
1739 | ||
cccf748b AK |
1740 | if (!vcpu->mmio_read_completed) |
1741 | do_interrupt_requests(vcpu, kvm_run); | |
6aa8b732 AK |
1742 | |
1743 | if (vcpu->guest_debug.enabled) | |
1744 | kvm_guest_debug_pre(vcpu); | |
1745 | ||
1746 | fx_save(vcpu->host_fx_image); | |
1747 | fx_restore(vcpu->guest_fx_image); | |
1748 | ||
1749 | save_msrs(vcpu->host_msrs, vcpu->nmsrs); | |
1750 | load_msrs(vcpu->guest_msrs, NR_BAD_MSRS); | |
1751 | ||
1752 | asm ( | |
1753 | /* Store host registers */ | |
1754 | "pushf \n\t" | |
05b3e0c2 | 1755 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1756 | "push %%rax; push %%rbx; push %%rdx;" |
1757 | "push %%rsi; push %%rdi; push %%rbp;" | |
1758 | "push %%r8; push %%r9; push %%r10; push %%r11;" | |
1759 | "push %%r12; push %%r13; push %%r14; push %%r15;" | |
1760 | "push %%rcx \n\t" | |
1761 | ASM_VMX_VMWRITE_RSP_RDX "\n\t" | |
1762 | #else | |
1763 | "pusha; push %%ecx \n\t" | |
1764 | ASM_VMX_VMWRITE_RSP_RDX "\n\t" | |
1765 | #endif | |
1766 | /* Check if vmlaunch of vmresume is needed */ | |
1767 | "cmp $0, %1 \n\t" | |
1768 | /* Load guest registers. Don't clobber flags. */ | |
05b3e0c2 | 1769 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1770 | "mov %c[cr2](%3), %%rax \n\t" |
1771 | "mov %%rax, %%cr2 \n\t" | |
1772 | "mov %c[rax](%3), %%rax \n\t" | |
1773 | "mov %c[rbx](%3), %%rbx \n\t" | |
1774 | "mov %c[rdx](%3), %%rdx \n\t" | |
1775 | "mov %c[rsi](%3), %%rsi \n\t" | |
1776 | "mov %c[rdi](%3), %%rdi \n\t" | |
1777 | "mov %c[rbp](%3), %%rbp \n\t" | |
1778 | "mov %c[r8](%3), %%r8 \n\t" | |
1779 | "mov %c[r9](%3), %%r9 \n\t" | |
1780 | "mov %c[r10](%3), %%r10 \n\t" | |
1781 | "mov %c[r11](%3), %%r11 \n\t" | |
1782 | "mov %c[r12](%3), %%r12 \n\t" | |
1783 | "mov %c[r13](%3), %%r13 \n\t" | |
1784 | "mov %c[r14](%3), %%r14 \n\t" | |
1785 | "mov %c[r15](%3), %%r15 \n\t" | |
1786 | "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */ | |
1787 | #else | |
1788 | "mov %c[cr2](%3), %%eax \n\t" | |
1789 | "mov %%eax, %%cr2 \n\t" | |
1790 | "mov %c[rax](%3), %%eax \n\t" | |
1791 | "mov %c[rbx](%3), %%ebx \n\t" | |
1792 | "mov %c[rdx](%3), %%edx \n\t" | |
1793 | "mov %c[rsi](%3), %%esi \n\t" | |
1794 | "mov %c[rdi](%3), %%edi \n\t" | |
1795 | "mov %c[rbp](%3), %%ebp \n\t" | |
1796 | "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */ | |
1797 | #endif | |
1798 | /* Enter guest mode */ | |
1799 | "jne launched \n\t" | |
1800 | ASM_VMX_VMLAUNCH "\n\t" | |
1801 | "jmp kvm_vmx_return \n\t" | |
1802 | "launched: " ASM_VMX_VMRESUME "\n\t" | |
1803 | ".globl kvm_vmx_return \n\t" | |
1804 | "kvm_vmx_return: " | |
1805 | /* Save guest registers, load host registers, keep flags */ | |
05b3e0c2 | 1806 | #ifdef CONFIG_X86_64 |
96958231 | 1807 | "xchg %3, (%%rsp) \n\t" |
6aa8b732 AK |
1808 | "mov %%rax, %c[rax](%3) \n\t" |
1809 | "mov %%rbx, %c[rbx](%3) \n\t" | |
96958231 | 1810 | "pushq (%%rsp); popq %c[rcx](%3) \n\t" |
6aa8b732 AK |
1811 | "mov %%rdx, %c[rdx](%3) \n\t" |
1812 | "mov %%rsi, %c[rsi](%3) \n\t" | |
1813 | "mov %%rdi, %c[rdi](%3) \n\t" | |
1814 | "mov %%rbp, %c[rbp](%3) \n\t" | |
1815 | "mov %%r8, %c[r8](%3) \n\t" | |
1816 | "mov %%r9, %c[r9](%3) \n\t" | |
1817 | "mov %%r10, %c[r10](%3) \n\t" | |
1818 | "mov %%r11, %c[r11](%3) \n\t" | |
1819 | "mov %%r12, %c[r12](%3) \n\t" | |
1820 | "mov %%r13, %c[r13](%3) \n\t" | |
1821 | "mov %%r14, %c[r14](%3) \n\t" | |
1822 | "mov %%r15, %c[r15](%3) \n\t" | |
1823 | "mov %%cr2, %%rax \n\t" | |
1824 | "mov %%rax, %c[cr2](%3) \n\t" | |
96958231 | 1825 | "mov (%%rsp), %3 \n\t" |
6aa8b732 AK |
1826 | |
1827 | "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;" | |
1828 | "pop %%r11; pop %%r10; pop %%r9; pop %%r8;" | |
1829 | "pop %%rbp; pop %%rdi; pop %%rsi;" | |
1830 | "pop %%rdx; pop %%rbx; pop %%rax \n\t" | |
1831 | #else | |
96958231 | 1832 | "xchg %3, (%%esp) \n\t" |
6aa8b732 AK |
1833 | "mov %%eax, %c[rax](%3) \n\t" |
1834 | "mov %%ebx, %c[rbx](%3) \n\t" | |
96958231 | 1835 | "pushl (%%esp); popl %c[rcx](%3) \n\t" |
6aa8b732 AK |
1836 | "mov %%edx, %c[rdx](%3) \n\t" |
1837 | "mov %%esi, %c[rsi](%3) \n\t" | |
1838 | "mov %%edi, %c[rdi](%3) \n\t" | |
1839 | "mov %%ebp, %c[rbp](%3) \n\t" | |
1840 | "mov %%cr2, %%eax \n\t" | |
1841 | "mov %%eax, %c[cr2](%3) \n\t" | |
96958231 | 1842 | "mov (%%esp), %3 \n\t" |
6aa8b732 AK |
1843 | |
1844 | "pop %%ecx; popa \n\t" | |
1845 | #endif | |
1846 | "setbe %0 \n\t" | |
1847 | "popf \n\t" | |
e0015489 | 1848 | : "=q" (fail) |
6aa8b732 AK |
1849 | : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP), |
1850 | "c"(vcpu), | |
1851 | [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])), | |
1852 | [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])), | |
1853 | [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])), | |
1854 | [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])), | |
1855 | [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])), | |
1856 | [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])), | |
1857 | [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 1858 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1859 | [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])), |
1860 | [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])), | |
1861 | [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])), | |
1862 | [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])), | |
1863 | [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])), | |
1864 | [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])), | |
1865 | [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])), | |
1866 | [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])), | |
1867 | #endif | |
1868 | [cr2]"i"(offsetof(struct kvm_vcpu, cr2)) | |
1869 | : "cc", "memory" ); | |
1870 | ||
1871 | ++kvm_stat.exits; | |
1872 | ||
1873 | save_msrs(vcpu->guest_msrs, NR_BAD_MSRS); | |
1874 | load_msrs(vcpu->host_msrs, NR_BAD_MSRS); | |
1875 | ||
1876 | fx_save(vcpu->guest_fx_image); | |
1877 | fx_restore(vcpu->host_fx_image); | |
c1150d8c | 1878 | vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0; |
6aa8b732 | 1879 | |
6aa8b732 | 1880 | asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
6aa8b732 AK |
1881 | |
1882 | kvm_run->exit_type = 0; | |
1883 | if (fail) { | |
1884 | kvm_run->exit_type = KVM_EXIT_TYPE_FAIL_ENTRY; | |
1885 | kvm_run->exit_reason = vmcs_read32(VM_INSTRUCTION_ERROR); | |
e2dec939 | 1886 | r = 0; |
6aa8b732 AK |
1887 | } else { |
1888 | if (fs_gs_ldt_reload_needed) { | |
1889 | load_ldt(ldt_sel); | |
1890 | load_fs(fs_sel); | |
1891 | /* | |
1892 | * If we have to reload gs, we must take care to | |
1893 | * preserve our gs base. | |
1894 | */ | |
1895 | local_irq_disable(); | |
1896 | load_gs(gs_sel); | |
05b3e0c2 | 1897 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1898 | wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE)); |
1899 | #endif | |
1900 | local_irq_enable(); | |
1901 | ||
1902 | reload_tss(); | |
1903 | } | |
464d1a78 JF |
1904 | /* |
1905 | * Profile KVM exit RIPs: | |
1906 | */ | |
1907 | if (unlikely(prof_on == KVM_PROFILING)) | |
1908 | profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP)); | |
1909 | ||
6aa8b732 AK |
1910 | vcpu->launched = 1; |
1911 | kvm_run->exit_type = KVM_EXIT_TYPE_VM_EXIT; | |
e2dec939 AK |
1912 | r = kvm_handle_exit(kvm_run, vcpu); |
1913 | if (r > 0) { | |
6aa8b732 AK |
1914 | /* Give scheduler a change to reschedule. */ |
1915 | if (signal_pending(current)) { | |
1916 | ++kvm_stat.signal_exits; | |
c1150d8c DL |
1917 | post_kvm_run_save(vcpu, kvm_run); |
1918 | return -EINTR; | |
1919 | } | |
1920 | ||
1921 | if (dm_request_for_irq_injection(vcpu, kvm_run)) { | |
1922 | ++kvm_stat.request_irq_exits; | |
1923 | post_kvm_run_save(vcpu, kvm_run); | |
6aa8b732 AK |
1924 | return -EINTR; |
1925 | } | |
c1150d8c | 1926 | |
6aa8b732 AK |
1927 | kvm_resched(vcpu); |
1928 | goto again; | |
1929 | } | |
1930 | } | |
c1150d8c DL |
1931 | |
1932 | post_kvm_run_save(vcpu, kvm_run); | |
e2dec939 | 1933 | return r; |
6aa8b732 AK |
1934 | } |
1935 | ||
1936 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) | |
1937 | { | |
1938 | vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3)); | |
1939 | } | |
1940 | ||
1941 | static void vmx_inject_page_fault(struct kvm_vcpu *vcpu, | |
1942 | unsigned long addr, | |
1943 | u32 err_code) | |
1944 | { | |
1945 | u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
1946 | ||
1947 | ++kvm_stat.pf_guest; | |
1948 | ||
1949 | if (is_page_fault(vect_info)) { | |
1950 | printk(KERN_DEBUG "inject_page_fault: " | |
1951 | "double fault 0x%lx @ 0x%lx\n", | |
1952 | addr, vmcs_readl(GUEST_RIP)); | |
1953 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0); | |
1954 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
1955 | DF_VECTOR | | |
1956 | INTR_TYPE_EXCEPTION | | |
1957 | INTR_INFO_DELIEVER_CODE_MASK | | |
1958 | INTR_INFO_VALID_MASK); | |
1959 | return; | |
1960 | } | |
1961 | vcpu->cr2 = addr; | |
1962 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code); | |
1963 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
1964 | PF_VECTOR | | |
1965 | INTR_TYPE_EXCEPTION | | |
1966 | INTR_INFO_DELIEVER_CODE_MASK | | |
1967 | INTR_INFO_VALID_MASK); | |
1968 | ||
1969 | } | |
1970 | ||
1971 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) | |
1972 | { | |
1973 | if (vcpu->vmcs) { | |
1974 | on_each_cpu(__vcpu_clear, vcpu, 0, 1); | |
1975 | free_vmcs(vcpu->vmcs); | |
1976 | vcpu->vmcs = NULL; | |
1977 | } | |
1978 | } | |
1979 | ||
1980 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
1981 | { | |
1982 | vmx_free_vmcs(vcpu); | |
1983 | } | |
1984 | ||
1985 | static int vmx_create_vcpu(struct kvm_vcpu *vcpu) | |
1986 | { | |
1987 | struct vmcs *vmcs; | |
1988 | ||
965b58a5 IM |
1989 | vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
1990 | if (!vcpu->guest_msrs) | |
1991 | return -ENOMEM; | |
1992 | ||
1993 | vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
1994 | if (!vcpu->host_msrs) | |
1995 | goto out_free_guest_msrs; | |
1996 | ||
6aa8b732 AK |
1997 | vmcs = alloc_vmcs(); |
1998 | if (!vmcs) | |
965b58a5 IM |
1999 | goto out_free_msrs; |
2000 | ||
6aa8b732 AK |
2001 | vmcs_clear(vmcs); |
2002 | vcpu->vmcs = vmcs; | |
2003 | vcpu->launched = 0; | |
965b58a5 | 2004 | |
6aa8b732 | 2005 | return 0; |
965b58a5 IM |
2006 | |
2007 | out_free_msrs: | |
2008 | kfree(vcpu->host_msrs); | |
2009 | vcpu->host_msrs = NULL; | |
2010 | ||
2011 | out_free_guest_msrs: | |
2012 | kfree(vcpu->guest_msrs); | |
2013 | vcpu->guest_msrs = NULL; | |
2014 | ||
2015 | return -ENOMEM; | |
6aa8b732 AK |
2016 | } |
2017 | ||
2018 | static struct kvm_arch_ops vmx_arch_ops = { | |
2019 | .cpu_has_kvm_support = cpu_has_kvm_support, | |
2020 | .disabled_by_bios = vmx_disabled_by_bios, | |
2021 | .hardware_setup = hardware_setup, | |
2022 | .hardware_unsetup = hardware_unsetup, | |
2023 | .hardware_enable = hardware_enable, | |
2024 | .hardware_disable = hardware_disable, | |
2025 | ||
2026 | .vcpu_create = vmx_create_vcpu, | |
2027 | .vcpu_free = vmx_free_vcpu, | |
2028 | ||
2029 | .vcpu_load = vmx_vcpu_load, | |
2030 | .vcpu_put = vmx_vcpu_put, | |
774c47f1 | 2031 | .vcpu_decache = vmx_vcpu_decache, |
6aa8b732 AK |
2032 | |
2033 | .set_guest_debug = set_guest_debug, | |
2034 | .get_msr = vmx_get_msr, | |
2035 | .set_msr = vmx_set_msr, | |
2036 | .get_segment_base = vmx_get_segment_base, | |
2037 | .get_segment = vmx_get_segment, | |
2038 | .set_segment = vmx_set_segment, | |
6aa8b732 | 2039 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
399badf3 | 2040 | .decache_cr0_cr4_guest_bits = vmx_decache_cr0_cr4_guest_bits, |
6aa8b732 AK |
2041 | .set_cr0 = vmx_set_cr0, |
2042 | .set_cr0_no_modeswitch = vmx_set_cr0_no_modeswitch, | |
2043 | .set_cr3 = vmx_set_cr3, | |
2044 | .set_cr4 = vmx_set_cr4, | |
05b3e0c2 | 2045 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2046 | .set_efer = vmx_set_efer, |
2047 | #endif | |
2048 | .get_idt = vmx_get_idt, | |
2049 | .set_idt = vmx_set_idt, | |
2050 | .get_gdt = vmx_get_gdt, | |
2051 | .set_gdt = vmx_set_gdt, | |
2052 | .cache_regs = vcpu_load_rsp_rip, | |
2053 | .decache_regs = vcpu_put_rsp_rip, | |
2054 | .get_rflags = vmx_get_rflags, | |
2055 | .set_rflags = vmx_set_rflags, | |
2056 | ||
2057 | .tlb_flush = vmx_flush_tlb, | |
2058 | .inject_page_fault = vmx_inject_page_fault, | |
2059 | ||
2060 | .inject_gp = vmx_inject_gp, | |
2061 | ||
2062 | .run = vmx_vcpu_run, | |
2063 | .skip_emulated_instruction = skip_emulated_instruction, | |
2064 | .vcpu_setup = vmx_vcpu_setup, | |
2065 | }; | |
2066 | ||
2067 | static int __init vmx_init(void) | |
2068 | { | |
873a7c42 | 2069 | return kvm_init_arch(&vmx_arch_ops, THIS_MODULE); |
6aa8b732 AK |
2070 | } |
2071 | ||
2072 | static void __exit vmx_exit(void) | |
2073 | { | |
2074 | kvm_exit_arch(); | |
2075 | } | |
2076 | ||
2077 | module_init(vmx_init) | |
2078 | module_exit(vmx_exit) |