Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * | |
9 | * Authors: | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include "kvm.h" | |
19 | #include "vmx.h" | |
6aa8b732 | 20 | #include <linux/module.h> |
9d8f549d | 21 | #include <linux/kernel.h> |
6aa8b732 AK |
22 | #include <linux/mm.h> |
23 | #include <linux/highmem.h> | |
07031e14 | 24 | #include <linux/profile.h> |
e8edc6e0 | 25 | #include <linux/sched.h> |
6aa8b732 | 26 | #include <asm/io.h> |
3b3be0d1 | 27 | #include <asm/desc.h> |
6aa8b732 AK |
28 | |
29 | #include "segment_descriptor.h" | |
30 | ||
6aa8b732 AK |
31 | MODULE_AUTHOR("Qumranet"); |
32 | MODULE_LICENSE("GPL"); | |
33 | ||
34 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); | |
35 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
36 | ||
fdef3ad1 HQ |
37 | static struct page *vmx_io_bitmap_a; |
38 | static struct page *vmx_io_bitmap_b; | |
39 | ||
05b3e0c2 | 40 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
41 | #define HOST_IS_64 1 |
42 | #else | |
43 | #define HOST_IS_64 0 | |
44 | #endif | |
45 | ||
46 | static struct vmcs_descriptor { | |
47 | int size; | |
48 | int order; | |
49 | u32 revision_id; | |
50 | } vmcs_descriptor; | |
51 | ||
52 | #define VMX_SEGMENT_FIELD(seg) \ | |
53 | [VCPU_SREG_##seg] = { \ | |
54 | .selector = GUEST_##seg##_SELECTOR, \ | |
55 | .base = GUEST_##seg##_BASE, \ | |
56 | .limit = GUEST_##seg##_LIMIT, \ | |
57 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
58 | } | |
59 | ||
60 | static struct kvm_vmx_segment_field { | |
61 | unsigned selector; | |
62 | unsigned base; | |
63 | unsigned limit; | |
64 | unsigned ar_bytes; | |
65 | } kvm_vmx_segment_fields[] = { | |
66 | VMX_SEGMENT_FIELD(CS), | |
67 | VMX_SEGMENT_FIELD(DS), | |
68 | VMX_SEGMENT_FIELD(ES), | |
69 | VMX_SEGMENT_FIELD(FS), | |
70 | VMX_SEGMENT_FIELD(GS), | |
71 | VMX_SEGMENT_FIELD(SS), | |
72 | VMX_SEGMENT_FIELD(TR), | |
73 | VMX_SEGMENT_FIELD(LDTR), | |
74 | }; | |
75 | ||
4d56c8a7 AK |
76 | /* |
77 | * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it | |
78 | * away by decrementing the array size. | |
79 | */ | |
6aa8b732 | 80 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 81 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
82 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE, |
83 | #endif | |
84 | MSR_EFER, MSR_K6_STAR, | |
85 | }; | |
9d8f549d | 86 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 87 | |
2345df8c AK |
88 | #ifdef CONFIG_X86_64 |
89 | static unsigned msr_offset_kernel_gs_base; | |
e38aea3e | 90 | #define NR_64BIT_MSRS 4 |
35cc7f97 AK |
91 | /* |
92 | * avoid save/load MSR_SYSCALL_MASK and MSR_LSTAR by std vt | |
93 | * mechanism (cpu bug AA24) | |
94 | */ | |
95 | #define NR_BAD_MSRS 2 | |
e38aea3e AK |
96 | #else |
97 | #define NR_64BIT_MSRS 0 | |
35cc7f97 | 98 | #define NR_BAD_MSRS 0 |
2345df8c AK |
99 | #endif |
100 | ||
6aa8b732 AK |
101 | static inline int is_page_fault(u32 intr_info) |
102 | { | |
103 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
104 | INTR_INFO_VALID_MASK)) == | |
105 | (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); | |
106 | } | |
107 | ||
2ab455cc AL |
108 | static inline int is_no_device(u32 intr_info) |
109 | { | |
110 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
111 | INTR_INFO_VALID_MASK)) == | |
112 | (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); | |
113 | } | |
114 | ||
6aa8b732 AK |
115 | static inline int is_external_interrupt(u32 intr_info) |
116 | { | |
117 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
118 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
119 | } | |
120 | ||
7725f0ba AK |
121 | static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr) |
122 | { | |
123 | int i; | |
124 | ||
125 | for (i = 0; i < vcpu->nmsrs; ++i) | |
126 | if (vcpu->guest_msrs[i].index == msr) | |
127 | return &vcpu->guest_msrs[i]; | |
8b6d44c7 | 128 | return NULL; |
7725f0ba AK |
129 | } |
130 | ||
6aa8b732 AK |
131 | static void vmcs_clear(struct vmcs *vmcs) |
132 | { | |
133 | u64 phys_addr = __pa(vmcs); | |
134 | u8 error; | |
135 | ||
136 | asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0" | |
137 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
138 | : "cc", "memory"); | |
139 | if (error) | |
140 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
141 | vmcs, phys_addr); | |
142 | } | |
143 | ||
144 | static void __vcpu_clear(void *arg) | |
145 | { | |
146 | struct kvm_vcpu *vcpu = arg; | |
d3b2c338 | 147 | int cpu = raw_smp_processor_id(); |
6aa8b732 AK |
148 | |
149 | if (vcpu->cpu == cpu) | |
150 | vmcs_clear(vcpu->vmcs); | |
151 | if (per_cpu(current_vmcs, cpu) == vcpu->vmcs) | |
152 | per_cpu(current_vmcs, cpu) = NULL; | |
153 | } | |
154 | ||
8d0be2b3 AK |
155 | static void vcpu_clear(struct kvm_vcpu *vcpu) |
156 | { | |
157 | if (vcpu->cpu != raw_smp_processor_id() && vcpu->cpu != -1) | |
158 | smp_call_function_single(vcpu->cpu, __vcpu_clear, vcpu, 0, 1); | |
159 | else | |
160 | __vcpu_clear(vcpu); | |
161 | vcpu->launched = 0; | |
162 | } | |
163 | ||
6aa8b732 AK |
164 | static unsigned long vmcs_readl(unsigned long field) |
165 | { | |
166 | unsigned long value; | |
167 | ||
168 | asm volatile (ASM_VMX_VMREAD_RDX_RAX | |
169 | : "=a"(value) : "d"(field) : "cc"); | |
170 | return value; | |
171 | } | |
172 | ||
173 | static u16 vmcs_read16(unsigned long field) | |
174 | { | |
175 | return vmcs_readl(field); | |
176 | } | |
177 | ||
178 | static u32 vmcs_read32(unsigned long field) | |
179 | { | |
180 | return vmcs_readl(field); | |
181 | } | |
182 | ||
183 | static u64 vmcs_read64(unsigned long field) | |
184 | { | |
05b3e0c2 | 185 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
186 | return vmcs_readl(field); |
187 | #else | |
188 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
189 | #endif | |
190 | } | |
191 | ||
e52de1b8 AK |
192 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
193 | { | |
194 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
195 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
196 | dump_stack(); | |
197 | } | |
198 | ||
6aa8b732 AK |
199 | static void vmcs_writel(unsigned long field, unsigned long value) |
200 | { | |
201 | u8 error; | |
202 | ||
203 | asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0" | |
204 | : "=q"(error) : "a"(value), "d"(field) : "cc" ); | |
e52de1b8 AK |
205 | if (unlikely(error)) |
206 | vmwrite_error(field, value); | |
6aa8b732 AK |
207 | } |
208 | ||
209 | static void vmcs_write16(unsigned long field, u16 value) | |
210 | { | |
211 | vmcs_writel(field, value); | |
212 | } | |
213 | ||
214 | static void vmcs_write32(unsigned long field, u32 value) | |
215 | { | |
216 | vmcs_writel(field, value); | |
217 | } | |
218 | ||
219 | static void vmcs_write64(unsigned long field, u64 value) | |
220 | { | |
05b3e0c2 | 221 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
222 | vmcs_writel(field, value); |
223 | #else | |
224 | vmcs_writel(field, value); | |
225 | asm volatile (""); | |
226 | vmcs_writel(field+1, value >> 32); | |
227 | #endif | |
228 | } | |
229 | ||
2ab455cc AL |
230 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
231 | { | |
232 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
233 | } | |
234 | ||
235 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
236 | { | |
237 | vmcs_writel(field, vmcs_readl(field) | mask); | |
238 | } | |
239 | ||
abd3f2d6 AK |
240 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
241 | { | |
242 | u32 eb; | |
243 | ||
244 | eb = 1u << PF_VECTOR; | |
245 | if (!vcpu->fpu_active) | |
246 | eb |= 1u << NM_VECTOR; | |
247 | if (vcpu->guest_debug.enabled) | |
248 | eb |= 1u << 1; | |
249 | if (vcpu->rmode.active) | |
250 | eb = ~0; | |
251 | vmcs_write32(EXCEPTION_BITMAP, eb); | |
252 | } | |
253 | ||
33ed6329 AK |
254 | static void reload_tss(void) |
255 | { | |
256 | #ifndef CONFIG_X86_64 | |
257 | ||
258 | /* | |
259 | * VT restores TR but not its size. Useless. | |
260 | */ | |
261 | struct descriptor_table gdt; | |
262 | struct segment_descriptor *descs; | |
263 | ||
264 | get_gdt(&gdt); | |
265 | descs = (void *)gdt.base; | |
266 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ | |
267 | load_TR_desc(); | |
268 | #endif | |
269 | } | |
270 | ||
271 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) | |
272 | { | |
273 | struct vmx_host_state *hs = &vcpu->vmx_host_state; | |
274 | ||
275 | if (hs->loaded) | |
276 | return; | |
277 | ||
278 | hs->loaded = 1; | |
279 | /* | |
280 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
281 | * allow segment selectors with cpl > 0 or ti == 1. | |
282 | */ | |
283 | hs->ldt_sel = read_ldt(); | |
284 | hs->fs_gs_ldt_reload_needed = hs->ldt_sel; | |
285 | hs->fs_sel = read_fs(); | |
286 | if (!(hs->fs_sel & 7)) | |
287 | vmcs_write16(HOST_FS_SELECTOR, hs->fs_sel); | |
288 | else { | |
289 | vmcs_write16(HOST_FS_SELECTOR, 0); | |
290 | hs->fs_gs_ldt_reload_needed = 1; | |
291 | } | |
292 | hs->gs_sel = read_gs(); | |
293 | if (!(hs->gs_sel & 7)) | |
294 | vmcs_write16(HOST_GS_SELECTOR, hs->gs_sel); | |
295 | else { | |
296 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
297 | hs->fs_gs_ldt_reload_needed = 1; | |
298 | } | |
299 | ||
300 | #ifdef CONFIG_X86_64 | |
301 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
302 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
303 | #else | |
304 | vmcs_writel(HOST_FS_BASE, segment_base(hs->fs_sel)); | |
305 | vmcs_writel(HOST_GS_BASE, segment_base(hs->gs_sel)); | |
306 | #endif | |
707c0874 AK |
307 | |
308 | #ifdef CONFIG_X86_64 | |
309 | if (is_long_mode(vcpu)) { | |
310 | save_msrs(vcpu->host_msrs + msr_offset_kernel_gs_base, 1); | |
311 | load_msrs(vcpu->guest_msrs, NR_BAD_MSRS); | |
312 | } | |
313 | #endif | |
33ed6329 AK |
314 | } |
315 | ||
316 | static void vmx_load_host_state(struct kvm_vcpu *vcpu) | |
317 | { | |
318 | struct vmx_host_state *hs = &vcpu->vmx_host_state; | |
319 | ||
320 | if (!hs->loaded) | |
321 | return; | |
322 | ||
323 | hs->loaded = 0; | |
324 | if (hs->fs_gs_ldt_reload_needed) { | |
325 | load_ldt(hs->ldt_sel); | |
326 | load_fs(hs->fs_sel); | |
327 | /* | |
328 | * If we have to reload gs, we must take care to | |
329 | * preserve our gs base. | |
330 | */ | |
331 | local_irq_disable(); | |
332 | load_gs(hs->gs_sel); | |
333 | #ifdef CONFIG_X86_64 | |
334 | wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE)); | |
335 | #endif | |
336 | local_irq_enable(); | |
337 | ||
338 | reload_tss(); | |
339 | } | |
340 | #ifdef CONFIG_X86_64 | |
341 | if (is_long_mode(vcpu)) { | |
342 | save_msrs(vcpu->guest_msrs, NR_BAD_MSRS); | |
343 | load_msrs(vcpu->host_msrs, NR_BAD_MSRS); | |
344 | } | |
345 | #endif | |
346 | } | |
347 | ||
6aa8b732 AK |
348 | /* |
349 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
350 | * vcpu mutex is already taken. | |
351 | */ | |
bccf2150 | 352 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
353 | { |
354 | u64 phys_addr = __pa(vcpu->vmcs); | |
355 | int cpu; | |
356 | ||
357 | cpu = get_cpu(); | |
358 | ||
8d0be2b3 AK |
359 | if (vcpu->cpu != cpu) |
360 | vcpu_clear(vcpu); | |
6aa8b732 AK |
361 | |
362 | if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) { | |
363 | u8 error; | |
364 | ||
365 | per_cpu(current_vmcs, cpu) = vcpu->vmcs; | |
366 | asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0" | |
367 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
368 | : "cc"); | |
369 | if (error) | |
370 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
371 | vcpu->vmcs, phys_addr); | |
372 | } | |
373 | ||
374 | if (vcpu->cpu != cpu) { | |
375 | struct descriptor_table dt; | |
376 | unsigned long sysenter_esp; | |
377 | ||
378 | vcpu->cpu = cpu; | |
379 | /* | |
380 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
381 | * processors. | |
382 | */ | |
383 | vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */ | |
384 | get_gdt(&dt); | |
385 | vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ | |
386 | ||
387 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
388 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
389 | } | |
6aa8b732 AK |
390 | } |
391 | ||
392 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
393 | { | |
33ed6329 | 394 | vmx_load_host_state(vcpu); |
7702fd1f | 395 | kvm_put_guest_fpu(vcpu); |
6aa8b732 AK |
396 | put_cpu(); |
397 | } | |
398 | ||
5fd86fcf AK |
399 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
400 | { | |
401 | if (vcpu->fpu_active) | |
402 | return; | |
403 | vcpu->fpu_active = 1; | |
404 | vmcs_clear_bits(GUEST_CR0, CR0_TS_MASK); | |
405 | if (vcpu->cr0 & CR0_TS_MASK) | |
406 | vmcs_set_bits(GUEST_CR0, CR0_TS_MASK); | |
407 | update_exception_bitmap(vcpu); | |
408 | } | |
409 | ||
410 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) | |
411 | { | |
412 | if (!vcpu->fpu_active) | |
413 | return; | |
414 | vcpu->fpu_active = 0; | |
415 | vmcs_set_bits(GUEST_CR0, CR0_TS_MASK); | |
416 | update_exception_bitmap(vcpu); | |
417 | } | |
418 | ||
774c47f1 AK |
419 | static void vmx_vcpu_decache(struct kvm_vcpu *vcpu) |
420 | { | |
421 | vcpu_clear(vcpu); | |
422 | } | |
423 | ||
6aa8b732 AK |
424 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
425 | { | |
426 | return vmcs_readl(GUEST_RFLAGS); | |
427 | } | |
428 | ||
429 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
430 | { | |
431 | vmcs_writel(GUEST_RFLAGS, rflags); | |
432 | } | |
433 | ||
434 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
435 | { | |
436 | unsigned long rip; | |
437 | u32 interruptibility; | |
438 | ||
439 | rip = vmcs_readl(GUEST_RIP); | |
440 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
441 | vmcs_writel(GUEST_RIP, rip); | |
442 | ||
443 | /* | |
444 | * We emulated an instruction, so temporary interrupt blocking | |
445 | * should be removed, if set. | |
446 | */ | |
447 | interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
448 | if (interruptibility & 3) | |
449 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
450 | interruptibility & ~3); | |
c1150d8c | 451 | vcpu->interrupt_window_open = 1; |
6aa8b732 AK |
452 | } |
453 | ||
454 | static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code) | |
455 | { | |
456 | printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n", | |
457 | vmcs_readl(GUEST_RIP)); | |
458 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); | |
459 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
460 | GP_VECTOR | | |
461 | INTR_TYPE_EXCEPTION | | |
462 | INTR_INFO_DELIEVER_CODE_MASK | | |
463 | INTR_INFO_VALID_MASK); | |
464 | } | |
465 | ||
e38aea3e AK |
466 | /* |
467 | * Set up the vmcs to automatically save and restore system | |
468 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
469 | * mode, as fiddling with msrs is very expensive. | |
470 | */ | |
471 | static void setup_msrs(struct kvm_vcpu *vcpu) | |
472 | { | |
473 | int nr_skip, nr_good_msrs; | |
474 | ||
475 | if (is_long_mode(vcpu)) | |
476 | nr_skip = NR_BAD_MSRS; | |
477 | else | |
478 | nr_skip = NR_64BIT_MSRS; | |
479 | nr_good_msrs = vcpu->nmsrs - nr_skip; | |
480 | ||
4d56c8a7 AK |
481 | /* |
482 | * MSR_K6_STAR is only needed on long mode guests, and only | |
483 | * if efer.sce is enabled. | |
484 | */ | |
485 | if (find_msr_entry(vcpu, MSR_K6_STAR)) { | |
486 | --nr_good_msrs; | |
487 | #ifdef CONFIG_X86_64 | |
488 | if (is_long_mode(vcpu) && (vcpu->shadow_efer & EFER_SCE)) | |
489 | ++nr_good_msrs; | |
490 | #endif | |
491 | } | |
492 | ||
e38aea3e AK |
493 | vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR, |
494 | virt_to_phys(vcpu->guest_msrs + nr_skip)); | |
495 | vmcs_writel(VM_EXIT_MSR_STORE_ADDR, | |
496 | virt_to_phys(vcpu->guest_msrs + nr_skip)); | |
497 | vmcs_writel(VM_EXIT_MSR_LOAD_ADDR, | |
498 | virt_to_phys(vcpu->host_msrs + nr_skip)); | |
499 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */ | |
500 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */ | |
501 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */ | |
502 | } | |
503 | ||
6aa8b732 AK |
504 | /* |
505 | * reads and returns guest's timestamp counter "register" | |
506 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
507 | */ | |
508 | static u64 guest_read_tsc(void) | |
509 | { | |
510 | u64 host_tsc, tsc_offset; | |
511 | ||
512 | rdtscll(host_tsc); | |
513 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
514 | return host_tsc + tsc_offset; | |
515 | } | |
516 | ||
517 | /* | |
518 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
519 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
520 | */ | |
521 | static void guest_write_tsc(u64 guest_tsc) | |
522 | { | |
523 | u64 host_tsc; | |
524 | ||
525 | rdtscll(host_tsc); | |
526 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); | |
527 | } | |
528 | ||
6aa8b732 AK |
529 | /* |
530 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
531 | * Returns 0 on success, non-0 otherwise. | |
532 | * Assumes vcpu_load() was already called. | |
533 | */ | |
534 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
535 | { | |
536 | u64 data; | |
537 | struct vmx_msr_entry *msr; | |
538 | ||
539 | if (!pdata) { | |
540 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
541 | return -EINVAL; | |
542 | } | |
543 | ||
544 | switch (msr_index) { | |
05b3e0c2 | 545 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
546 | case MSR_FS_BASE: |
547 | data = vmcs_readl(GUEST_FS_BASE); | |
548 | break; | |
549 | case MSR_GS_BASE: | |
550 | data = vmcs_readl(GUEST_GS_BASE); | |
551 | break; | |
552 | case MSR_EFER: | |
3bab1f5d | 553 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
554 | #endif |
555 | case MSR_IA32_TIME_STAMP_COUNTER: | |
556 | data = guest_read_tsc(); | |
557 | break; | |
558 | case MSR_IA32_SYSENTER_CS: | |
559 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
560 | break; | |
561 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 562 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
563 | break; |
564 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 565 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 566 | break; |
6aa8b732 AK |
567 | default: |
568 | msr = find_msr_entry(vcpu, msr_index); | |
3bab1f5d AK |
569 | if (msr) { |
570 | data = msr->data; | |
571 | break; | |
6aa8b732 | 572 | } |
3bab1f5d | 573 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
574 | } |
575 | ||
576 | *pdata = data; | |
577 | return 0; | |
578 | } | |
579 | ||
580 | /* | |
581 | * Writes msr value into into the appropriate "register". | |
582 | * Returns 0 on success, non-0 otherwise. | |
583 | * Assumes vcpu_load() was already called. | |
584 | */ | |
585 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
586 | { | |
587 | struct vmx_msr_entry *msr; | |
588 | switch (msr_index) { | |
05b3e0c2 | 589 | #ifdef CONFIG_X86_64 |
3bab1f5d AK |
590 | case MSR_EFER: |
591 | return kvm_set_msr_common(vcpu, msr_index, data); | |
6aa8b732 AK |
592 | case MSR_FS_BASE: |
593 | vmcs_writel(GUEST_FS_BASE, data); | |
594 | break; | |
595 | case MSR_GS_BASE: | |
596 | vmcs_writel(GUEST_GS_BASE, data); | |
597 | break; | |
e6adf283 AK |
598 | case MSR_LSTAR: |
599 | case MSR_SYSCALL_MASK: | |
600 | msr = find_msr_entry(vcpu, msr_index); | |
601 | if (msr) | |
602 | msr->data = data; | |
eff708bc AK |
603 | if (vcpu->vmx_host_state.loaded) |
604 | load_msrs(vcpu->guest_msrs, NR_BAD_MSRS); | |
e6adf283 | 605 | break; |
6aa8b732 AK |
606 | #endif |
607 | case MSR_IA32_SYSENTER_CS: | |
608 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
609 | break; | |
610 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 611 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
612 | break; |
613 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 614 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 615 | break; |
d27d4aca | 616 | case MSR_IA32_TIME_STAMP_COUNTER: |
6aa8b732 AK |
617 | guest_write_tsc(data); |
618 | break; | |
6aa8b732 AK |
619 | default: |
620 | msr = find_msr_entry(vcpu, msr_index); | |
3bab1f5d AK |
621 | if (msr) { |
622 | msr->data = data; | |
623 | break; | |
6aa8b732 | 624 | } |
3bab1f5d | 625 | return kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
626 | msr->data = data; |
627 | break; | |
628 | } | |
629 | ||
630 | return 0; | |
631 | } | |
632 | ||
633 | /* | |
634 | * Sync the rsp and rip registers into the vcpu structure. This allows | |
635 | * registers to be accessed by indexing vcpu->regs. | |
636 | */ | |
637 | static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu) | |
638 | { | |
639 | vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
640 | vcpu->rip = vmcs_readl(GUEST_RIP); | |
641 | } | |
642 | ||
643 | /* | |
644 | * Syncs rsp and rip back into the vmcs. Should be called after possible | |
645 | * modification. | |
646 | */ | |
647 | static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu) | |
648 | { | |
649 | vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]); | |
650 | vmcs_writel(GUEST_RIP, vcpu->rip); | |
651 | } | |
652 | ||
653 | static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
654 | { | |
655 | unsigned long dr7 = 0x400; | |
6aa8b732 AK |
656 | int old_singlestep; |
657 | ||
6aa8b732 AK |
658 | old_singlestep = vcpu->guest_debug.singlestep; |
659 | ||
660 | vcpu->guest_debug.enabled = dbg->enabled; | |
661 | if (vcpu->guest_debug.enabled) { | |
662 | int i; | |
663 | ||
664 | dr7 |= 0x200; /* exact */ | |
665 | for (i = 0; i < 4; ++i) { | |
666 | if (!dbg->breakpoints[i].enabled) | |
667 | continue; | |
668 | vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address; | |
669 | dr7 |= 2 << (i*2); /* global enable */ | |
670 | dr7 |= 0 << (i*4+16); /* execution breakpoint */ | |
671 | } | |
672 | ||
6aa8b732 | 673 | vcpu->guest_debug.singlestep = dbg->singlestep; |
abd3f2d6 | 674 | } else |
6aa8b732 | 675 | vcpu->guest_debug.singlestep = 0; |
6aa8b732 AK |
676 | |
677 | if (old_singlestep && !vcpu->guest_debug.singlestep) { | |
678 | unsigned long flags; | |
679 | ||
680 | flags = vmcs_readl(GUEST_RFLAGS); | |
681 | flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
682 | vmcs_writel(GUEST_RFLAGS, flags); | |
683 | } | |
684 | ||
abd3f2d6 | 685 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
686 | vmcs_writel(GUEST_DR7, dr7); |
687 | ||
688 | return 0; | |
689 | } | |
690 | ||
691 | static __init int cpu_has_kvm_support(void) | |
692 | { | |
693 | unsigned long ecx = cpuid_ecx(1); | |
694 | return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */ | |
695 | } | |
696 | ||
697 | static __init int vmx_disabled_by_bios(void) | |
698 | { | |
699 | u64 msr; | |
700 | ||
701 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
702 | return (msr & 5) == 1; /* locked but not enabled */ | |
703 | } | |
704 | ||
774c47f1 | 705 | static void hardware_enable(void *garbage) |
6aa8b732 AK |
706 | { |
707 | int cpu = raw_smp_processor_id(); | |
708 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
709 | u64 old; | |
710 | ||
711 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); | |
bfdc0c28 | 712 | if ((old & 5) != 5) |
6aa8b732 AK |
713 | /* enable and lock */ |
714 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5); | |
715 | write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */ | |
716 | asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr) | |
717 | : "memory", "cc"); | |
718 | } | |
719 | ||
720 | static void hardware_disable(void *garbage) | |
721 | { | |
722 | asm volatile (ASM_VMX_VMXOFF : : : "cc"); | |
723 | } | |
724 | ||
725 | static __init void setup_vmcs_descriptor(void) | |
726 | { | |
727 | u32 vmx_msr_low, vmx_msr_high; | |
728 | ||
c68876fd | 729 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
6aa8b732 AK |
730 | vmcs_descriptor.size = vmx_msr_high & 0x1fff; |
731 | vmcs_descriptor.order = get_order(vmcs_descriptor.size); | |
732 | vmcs_descriptor.revision_id = vmx_msr_low; | |
c68876fd | 733 | } |
6aa8b732 AK |
734 | |
735 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
736 | { | |
737 | int node = cpu_to_node(cpu); | |
738 | struct page *pages; | |
739 | struct vmcs *vmcs; | |
740 | ||
741 | pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order); | |
742 | if (!pages) | |
743 | return NULL; | |
744 | vmcs = page_address(pages); | |
745 | memset(vmcs, 0, vmcs_descriptor.size); | |
746 | vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */ | |
747 | return vmcs; | |
748 | } | |
749 | ||
750 | static struct vmcs *alloc_vmcs(void) | |
751 | { | |
d3b2c338 | 752 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
753 | } |
754 | ||
755 | static void free_vmcs(struct vmcs *vmcs) | |
756 | { | |
757 | free_pages((unsigned long)vmcs, vmcs_descriptor.order); | |
758 | } | |
759 | ||
39959588 | 760 | static void free_kvm_area(void) |
6aa8b732 AK |
761 | { |
762 | int cpu; | |
763 | ||
764 | for_each_online_cpu(cpu) | |
765 | free_vmcs(per_cpu(vmxarea, cpu)); | |
766 | } | |
767 | ||
768 | extern struct vmcs *alloc_vmcs_cpu(int cpu); | |
769 | ||
770 | static __init int alloc_kvm_area(void) | |
771 | { | |
772 | int cpu; | |
773 | ||
774 | for_each_online_cpu(cpu) { | |
775 | struct vmcs *vmcs; | |
776 | ||
777 | vmcs = alloc_vmcs_cpu(cpu); | |
778 | if (!vmcs) { | |
779 | free_kvm_area(); | |
780 | return -ENOMEM; | |
781 | } | |
782 | ||
783 | per_cpu(vmxarea, cpu) = vmcs; | |
784 | } | |
785 | return 0; | |
786 | } | |
787 | ||
788 | static __init int hardware_setup(void) | |
789 | { | |
790 | setup_vmcs_descriptor(); | |
791 | return alloc_kvm_area(); | |
792 | } | |
793 | ||
794 | static __exit void hardware_unsetup(void) | |
795 | { | |
796 | free_kvm_area(); | |
797 | } | |
798 | ||
6aa8b732 AK |
799 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
800 | { | |
801 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
802 | ||
6af11b9e | 803 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
804 | vmcs_write16(sf->selector, save->selector); |
805 | vmcs_writel(sf->base, save->base); | |
806 | vmcs_write32(sf->limit, save->limit); | |
807 | vmcs_write32(sf->ar_bytes, save->ar); | |
808 | } else { | |
809 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
810 | << AR_DPL_SHIFT; | |
811 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
812 | } | |
813 | } | |
814 | ||
815 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
816 | { | |
817 | unsigned long flags; | |
818 | ||
819 | vcpu->rmode.active = 0; | |
820 | ||
821 | vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base); | |
822 | vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit); | |
823 | vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar); | |
824 | ||
825 | flags = vmcs_readl(GUEST_RFLAGS); | |
826 | flags &= ~(IOPL_MASK | X86_EFLAGS_VM); | |
827 | flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT); | |
828 | vmcs_writel(GUEST_RFLAGS, flags); | |
829 | ||
830 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) | | |
831 | (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK)); | |
832 | ||
833 | update_exception_bitmap(vcpu); | |
834 | ||
835 | fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es); | |
836 | fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds); | |
837 | fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs); | |
838 | fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs); | |
839 | ||
840 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
841 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
842 | ||
843 | vmcs_write16(GUEST_CS_SELECTOR, | |
844 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
845 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
846 | } | |
847 | ||
848 | static int rmode_tss_base(struct kvm* kvm) | |
849 | { | |
850 | gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3; | |
851 | return base_gfn << PAGE_SHIFT; | |
852 | } | |
853 | ||
854 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
855 | { | |
856 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
857 | ||
858 | save->selector = vmcs_read16(sf->selector); | |
859 | save->base = vmcs_readl(sf->base); | |
860 | save->limit = vmcs_read32(sf->limit); | |
861 | save->ar = vmcs_read32(sf->ar_bytes); | |
862 | vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4); | |
863 | vmcs_write32(sf->limit, 0xffff); | |
864 | vmcs_write32(sf->ar_bytes, 0xf3); | |
865 | } | |
866 | ||
867 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
868 | { | |
869 | unsigned long flags; | |
870 | ||
871 | vcpu->rmode.active = 1; | |
872 | ||
873 | vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE); | |
874 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); | |
875 | ||
876 | vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); | |
877 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); | |
878 | ||
879 | vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
880 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
881 | ||
882 | flags = vmcs_readl(GUEST_RFLAGS); | |
883 | vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT; | |
884 | ||
885 | flags |= IOPL_MASK | X86_EFLAGS_VM; | |
886 | ||
887 | vmcs_writel(GUEST_RFLAGS, flags); | |
888 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK); | |
889 | update_exception_bitmap(vcpu); | |
890 | ||
891 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); | |
892 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
893 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
894 | ||
895 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 896 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
897 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
898 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
899 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
900 | ||
901 | fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es); | |
902 | fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds); | |
903 | fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs); | |
904 | fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs); | |
905 | } | |
906 | ||
05b3e0c2 | 907 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
908 | |
909 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
910 | { | |
911 | u32 guest_tr_ar; | |
912 | ||
913 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
914 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
915 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
916 | __FUNCTION__); | |
917 | vmcs_write32(GUEST_TR_AR_BYTES, | |
918 | (guest_tr_ar & ~AR_TYPE_MASK) | |
919 | | AR_TYPE_BUSY_64_TSS); | |
920 | } | |
921 | ||
922 | vcpu->shadow_efer |= EFER_LMA; | |
923 | ||
924 | find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME; | |
925 | vmcs_write32(VM_ENTRY_CONTROLS, | |
926 | vmcs_read32(VM_ENTRY_CONTROLS) | |
927 | | VM_ENTRY_CONTROLS_IA32E_MASK); | |
928 | } | |
929 | ||
930 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
931 | { | |
932 | vcpu->shadow_efer &= ~EFER_LMA; | |
933 | ||
934 | vmcs_write32(VM_ENTRY_CONTROLS, | |
935 | vmcs_read32(VM_ENTRY_CONTROLS) | |
936 | & ~VM_ENTRY_CONTROLS_IA32E_MASK); | |
937 | } | |
938 | ||
939 | #endif | |
940 | ||
25c4c276 | 941 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 942 | { |
399badf3 AK |
943 | vcpu->cr4 &= KVM_GUEST_CR4_MASK; |
944 | vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK; | |
945 | } | |
946 | ||
6aa8b732 AK |
947 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
948 | { | |
5fd86fcf AK |
949 | vmx_fpu_deactivate(vcpu); |
950 | ||
6aa8b732 AK |
951 | if (vcpu->rmode.active && (cr0 & CR0_PE_MASK)) |
952 | enter_pmode(vcpu); | |
953 | ||
954 | if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK)) | |
955 | enter_rmode(vcpu); | |
956 | ||
05b3e0c2 | 957 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
958 | if (vcpu->shadow_efer & EFER_LME) { |
959 | if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK)) | |
960 | enter_lmode(vcpu); | |
961 | if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK)) | |
962 | exit_lmode(vcpu); | |
963 | } | |
964 | #endif | |
965 | ||
966 | vmcs_writel(CR0_READ_SHADOW, cr0); | |
967 | vmcs_writel(GUEST_CR0, | |
968 | (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON); | |
969 | vcpu->cr0 = cr0; | |
5fd86fcf AK |
970 | |
971 | if (!(cr0 & CR0_TS_MASK) || !(cr0 & CR0_PE_MASK)) | |
972 | vmx_fpu_activate(vcpu); | |
6aa8b732 AK |
973 | } |
974 | ||
6aa8b732 AK |
975 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
976 | { | |
977 | vmcs_writel(GUEST_CR3, cr3); | |
5fd86fcf AK |
978 | if (vcpu->cr0 & CR0_PE_MASK) |
979 | vmx_fpu_deactivate(vcpu); | |
6aa8b732 AK |
980 | } |
981 | ||
982 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
983 | { | |
984 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
985 | vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ? | |
986 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON)); | |
987 | vcpu->cr4 = cr4; | |
988 | } | |
989 | ||
05b3e0c2 | 990 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
991 | |
992 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
993 | { | |
994 | struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER); | |
995 | ||
996 | vcpu->shadow_efer = efer; | |
997 | if (efer & EFER_LMA) { | |
998 | vmcs_write32(VM_ENTRY_CONTROLS, | |
999 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1000 | VM_ENTRY_CONTROLS_IA32E_MASK); | |
1001 | msr->data = efer; | |
1002 | ||
1003 | } else { | |
1004 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1005 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1006 | ~VM_ENTRY_CONTROLS_IA32E_MASK); | |
1007 | ||
1008 | msr->data = efer & ~EFER_LME; | |
1009 | } | |
e38aea3e | 1010 | setup_msrs(vcpu); |
6aa8b732 AK |
1011 | } |
1012 | ||
1013 | #endif | |
1014 | ||
1015 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1016 | { | |
1017 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1018 | ||
1019 | return vmcs_readl(sf->base); | |
1020 | } | |
1021 | ||
1022 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1023 | struct kvm_segment *var, int seg) | |
1024 | { | |
1025 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1026 | u32 ar; | |
1027 | ||
1028 | var->base = vmcs_readl(sf->base); | |
1029 | var->limit = vmcs_read32(sf->limit); | |
1030 | var->selector = vmcs_read16(sf->selector); | |
1031 | ar = vmcs_read32(sf->ar_bytes); | |
1032 | if (ar & AR_UNUSABLE_MASK) | |
1033 | ar = 0; | |
1034 | var->type = ar & 15; | |
1035 | var->s = (ar >> 4) & 1; | |
1036 | var->dpl = (ar >> 5) & 3; | |
1037 | var->present = (ar >> 7) & 1; | |
1038 | var->avl = (ar >> 12) & 1; | |
1039 | var->l = (ar >> 13) & 1; | |
1040 | var->db = (ar >> 14) & 1; | |
1041 | var->g = (ar >> 15) & 1; | |
1042 | var->unusable = (ar >> 16) & 1; | |
1043 | } | |
1044 | ||
653e3108 | 1045 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 1046 | { |
6aa8b732 AK |
1047 | u32 ar; |
1048 | ||
653e3108 | 1049 | if (var->unusable) |
6aa8b732 AK |
1050 | ar = 1 << 16; |
1051 | else { | |
1052 | ar = var->type & 15; | |
1053 | ar |= (var->s & 1) << 4; | |
1054 | ar |= (var->dpl & 3) << 5; | |
1055 | ar |= (var->present & 1) << 7; | |
1056 | ar |= (var->avl & 1) << 12; | |
1057 | ar |= (var->l & 1) << 13; | |
1058 | ar |= (var->db & 1) << 14; | |
1059 | ar |= (var->g & 1) << 15; | |
1060 | } | |
f7fbf1fd UL |
1061 | if (ar == 0) /* a 0 value means unusable */ |
1062 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
1063 | |
1064 | return ar; | |
1065 | } | |
1066 | ||
1067 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
1068 | struct kvm_segment *var, int seg) | |
1069 | { | |
1070 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1071 | u32 ar; | |
1072 | ||
1073 | if (vcpu->rmode.active && seg == VCPU_SREG_TR) { | |
1074 | vcpu->rmode.tr.selector = var->selector; | |
1075 | vcpu->rmode.tr.base = var->base; | |
1076 | vcpu->rmode.tr.limit = var->limit; | |
1077 | vcpu->rmode.tr.ar = vmx_segment_access_rights(var); | |
1078 | return; | |
1079 | } | |
1080 | vmcs_writel(sf->base, var->base); | |
1081 | vmcs_write32(sf->limit, var->limit); | |
1082 | vmcs_write16(sf->selector, var->selector); | |
1083 | if (vcpu->rmode.active && var->s) { | |
1084 | /* | |
1085 | * Hack real-mode segments into vm86 compatibility. | |
1086 | */ | |
1087 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
1088 | vmcs_writel(sf->base, 0xf0000); | |
1089 | ar = 0xf3; | |
1090 | } else | |
1091 | ar = vmx_segment_access_rights(var); | |
6aa8b732 AK |
1092 | vmcs_write32(sf->ar_bytes, ar); |
1093 | } | |
1094 | ||
6aa8b732 AK |
1095 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
1096 | { | |
1097 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1098 | ||
1099 | *db = (ar >> 14) & 1; | |
1100 | *l = (ar >> 13) & 1; | |
1101 | } | |
1102 | ||
1103 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1104 | { | |
1105 | dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
1106 | dt->base = vmcs_readl(GUEST_IDTR_BASE); | |
1107 | } | |
1108 | ||
1109 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1110 | { | |
1111 | vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); | |
1112 | vmcs_writel(GUEST_IDTR_BASE, dt->base); | |
1113 | } | |
1114 | ||
1115 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1116 | { | |
1117 | dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
1118 | dt->base = vmcs_readl(GUEST_GDTR_BASE); | |
1119 | } | |
1120 | ||
1121 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1122 | { | |
1123 | vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); | |
1124 | vmcs_writel(GUEST_GDTR_BASE, dt->base); | |
1125 | } | |
1126 | ||
1127 | static int init_rmode_tss(struct kvm* kvm) | |
1128 | { | |
1129 | struct page *p1, *p2, *p3; | |
1130 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; | |
1131 | char *page; | |
1132 | ||
954bbbc2 AK |
1133 | p1 = gfn_to_page(kvm, fn++); |
1134 | p2 = gfn_to_page(kvm, fn++); | |
1135 | p3 = gfn_to_page(kvm, fn); | |
6aa8b732 AK |
1136 | |
1137 | if (!p1 || !p2 || !p3) { | |
1138 | kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__); | |
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | page = kmap_atomic(p1, KM_USER0); | |
1143 | memset(page, 0, PAGE_SIZE); | |
1144 | *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; | |
1145 | kunmap_atomic(page, KM_USER0); | |
1146 | ||
1147 | page = kmap_atomic(p2, KM_USER0); | |
1148 | memset(page, 0, PAGE_SIZE); | |
1149 | kunmap_atomic(page, KM_USER0); | |
1150 | ||
1151 | page = kmap_atomic(p3, KM_USER0); | |
1152 | memset(page, 0, PAGE_SIZE); | |
1153 | *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0; | |
1154 | kunmap_atomic(page, KM_USER0); | |
1155 | ||
1156 | return 1; | |
1157 | } | |
1158 | ||
1159 | static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val) | |
1160 | { | |
1161 | u32 msr_high, msr_low; | |
1162 | ||
1163 | rdmsr(msr, msr_low, msr_high); | |
1164 | ||
1165 | val &= msr_high; | |
1166 | val |= msr_low; | |
1167 | vmcs_write32(vmcs_field, val); | |
1168 | } | |
1169 | ||
1170 | static void seg_setup(int seg) | |
1171 | { | |
1172 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1173 | ||
1174 | vmcs_write16(sf->selector, 0); | |
1175 | vmcs_writel(sf->base, 0); | |
1176 | vmcs_write32(sf->limit, 0xffff); | |
1177 | vmcs_write32(sf->ar_bytes, 0x93); | |
1178 | } | |
1179 | ||
1180 | /* | |
1181 | * Sets up the vmcs for emulated real mode. | |
1182 | */ | |
1183 | static int vmx_vcpu_setup(struct kvm_vcpu *vcpu) | |
1184 | { | |
1185 | u32 host_sysenter_cs; | |
1186 | u32 junk; | |
1187 | unsigned long a; | |
1188 | struct descriptor_table dt; | |
1189 | int i; | |
1190 | int ret = 0; | |
cd2276a7 | 1191 | unsigned long kvm_vmx_return; |
6aa8b732 AK |
1192 | |
1193 | if (!init_rmode_tss(vcpu->kvm)) { | |
1194 | ret = -ENOMEM; | |
1195 | goto out; | |
1196 | } | |
1197 | ||
1198 | memset(vcpu->regs, 0, sizeof(vcpu->regs)); | |
1199 | vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val(); | |
1200 | vcpu->cr8 = 0; | |
1201 | vcpu->apic_base = 0xfee00000 | | |
1202 | /*for vcpu 0*/ MSR_IA32_APICBASE_BSP | | |
1203 | MSR_IA32_APICBASE_ENABLE; | |
1204 | ||
1205 | fx_init(vcpu); | |
1206 | ||
1207 | /* | |
1208 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
1209 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
1210 | */ | |
1211 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); | |
1212 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
1213 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); | |
1214 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1215 | ||
1216 | seg_setup(VCPU_SREG_DS); | |
1217 | seg_setup(VCPU_SREG_ES); | |
1218 | seg_setup(VCPU_SREG_FS); | |
1219 | seg_setup(VCPU_SREG_GS); | |
1220 | seg_setup(VCPU_SREG_SS); | |
1221 | ||
1222 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
1223 | vmcs_writel(GUEST_TR_BASE, 0); | |
1224 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
1225 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
1226 | ||
1227 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
1228 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
1229 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
1230 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
1231 | ||
1232 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
1233 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
1234 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
1235 | ||
1236 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
1237 | vmcs_writel(GUEST_RIP, 0xfff0); | |
1238 | vmcs_writel(GUEST_RSP, 0); | |
1239 | ||
6aa8b732 AK |
1240 | //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 |
1241 | vmcs_writel(GUEST_DR7, 0x400); | |
1242 | ||
1243 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
1244 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
1245 | ||
1246 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
1247 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
1248 | ||
1249 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
1250 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
1251 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
1252 | ||
1253 | /* I/O */ | |
fdef3ad1 HQ |
1254 | vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a)); |
1255 | vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b)); | |
6aa8b732 AK |
1256 | |
1257 | guest_write_tsc(0); | |
1258 | ||
1259 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ | |
1260 | ||
1261 | /* Special registers */ | |
1262 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
1263 | ||
1264 | /* Control */ | |
c68876fd | 1265 | vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS, |
6aa8b732 AK |
1266 | PIN_BASED_VM_EXEC_CONTROL, |
1267 | PIN_BASED_EXT_INTR_MASK /* 20.6.1 */ | |
1268 | | PIN_BASED_NMI_EXITING /* 20.6.1 */ | |
1269 | ); | |
c68876fd | 1270 | vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS, |
6aa8b732 AK |
1271 | CPU_BASED_VM_EXEC_CONTROL, |
1272 | CPU_BASED_HLT_EXITING /* 20.6.2 */ | |
1273 | | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */ | |
1274 | | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */ | |
fdef3ad1 | 1275 | | CPU_BASED_ACTIVATE_IO_BITMAP /* 20.6.2 */ |
6aa8b732 AK |
1276 | | CPU_BASED_MOV_DR_EXITING |
1277 | | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */ | |
1278 | ); | |
1279 | ||
6aa8b732 AK |
1280 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
1281 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
1282 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ | |
1283 | ||
1284 | vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */ | |
1285 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
1286 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
1287 | ||
1288 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
1289 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1290 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1291 | vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */ | |
1292 | vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */ | |
1293 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
05b3e0c2 | 1294 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1295 | rdmsrl(MSR_FS_BASE, a); |
1296 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
1297 | rdmsrl(MSR_GS_BASE, a); | |
1298 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
1299 | #else | |
1300 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
1301 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
1302 | #endif | |
1303 | ||
1304 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
1305 | ||
1306 | get_idt(&dt); | |
1307 | vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ | |
1308 | ||
cd2276a7 AK |
1309 | asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
1310 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ | |
6aa8b732 AK |
1311 | |
1312 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
1313 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
1314 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
1315 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
1316 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
1317 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
1318 | ||
6aa8b732 AK |
1319 | for (i = 0; i < NR_VMX_MSR; ++i) { |
1320 | u32 index = vmx_msr_index[i]; | |
1321 | u32 data_low, data_high; | |
1322 | u64 data; | |
1323 | int j = vcpu->nmsrs; | |
1324 | ||
1325 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
1326 | continue; | |
432bd6cb AK |
1327 | if (wrmsr_safe(index, data_low, data_high) < 0) |
1328 | continue; | |
6aa8b732 AK |
1329 | data = data_low | ((u64)data_high << 32); |
1330 | vcpu->host_msrs[j].index = index; | |
1331 | vcpu->host_msrs[j].reserved = 0; | |
1332 | vcpu->host_msrs[j].data = data; | |
1333 | vcpu->guest_msrs[j] = vcpu->host_msrs[j]; | |
2345df8c AK |
1334 | #ifdef CONFIG_X86_64 |
1335 | if (index == MSR_KERNEL_GS_BASE) | |
1336 | msr_offset_kernel_gs_base = j; | |
1337 | #endif | |
6aa8b732 AK |
1338 | ++vcpu->nmsrs; |
1339 | } | |
6aa8b732 | 1340 | |
e38aea3e AK |
1341 | setup_msrs(vcpu); |
1342 | ||
c68876fd | 1343 | vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS, VM_EXIT_CONTROLS, |
6aa8b732 | 1344 | (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */ |
6aa8b732 AK |
1345 | |
1346 | /* 22.2.1, 20.8.1 */ | |
c68876fd | 1347 | vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS, |
6aa8b732 AK |
1348 | VM_ENTRY_CONTROLS, 0); |
1349 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ | |
1350 | ||
3b99ab24 | 1351 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1352 | vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0); |
1353 | vmcs_writel(TPR_THRESHOLD, 0); | |
3b99ab24 | 1354 | #endif |
6aa8b732 | 1355 | |
25c4c276 | 1356 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
6aa8b732 AK |
1357 | vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK); |
1358 | ||
1359 | vcpu->cr0 = 0x60000010; | |
1360 | vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode | |
1361 | vmx_set_cr4(vcpu, 0); | |
05b3e0c2 | 1362 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1363 | vmx_set_efer(vcpu, 0); |
1364 | #endif | |
5fd86fcf | 1365 | vmx_fpu_activate(vcpu); |
abd3f2d6 | 1366 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
1367 | |
1368 | return 0; | |
1369 | ||
6aa8b732 AK |
1370 | out: |
1371 | return ret; | |
1372 | } | |
1373 | ||
1374 | static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq) | |
1375 | { | |
1376 | u16 ent[2]; | |
1377 | u16 cs; | |
1378 | u16 ip; | |
1379 | unsigned long flags; | |
1380 | unsigned long ss_base = vmcs_readl(GUEST_SS_BASE); | |
1381 | u16 sp = vmcs_readl(GUEST_RSP); | |
1382 | u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
1383 | ||
3964994b | 1384 | if (sp > ss_limit || sp < 6 ) { |
6aa8b732 AK |
1385 | vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n", |
1386 | __FUNCTION__, | |
1387 | vmcs_readl(GUEST_RSP), | |
1388 | vmcs_readl(GUEST_SS_BASE), | |
1389 | vmcs_read32(GUEST_SS_LIMIT)); | |
1390 | return; | |
1391 | } | |
1392 | ||
1393 | if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) != | |
1394 | sizeof(ent)) { | |
1395 | vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__); | |
1396 | return; | |
1397 | } | |
1398 | ||
1399 | flags = vmcs_readl(GUEST_RFLAGS); | |
1400 | cs = vmcs_readl(GUEST_CS_BASE) >> 4; | |
1401 | ip = vmcs_readl(GUEST_RIP); | |
1402 | ||
1403 | ||
1404 | if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 || | |
1405 | kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 || | |
1406 | kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) { | |
1407 | vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__); | |
1408 | return; | |
1409 | } | |
1410 | ||
1411 | vmcs_writel(GUEST_RFLAGS, flags & | |
1412 | ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF)); | |
1413 | vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ; | |
1414 | vmcs_writel(GUEST_CS_BASE, ent[1] << 4); | |
1415 | vmcs_writel(GUEST_RIP, ent[0]); | |
1416 | vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6)); | |
1417 | } | |
1418 | ||
1419 | static void kvm_do_inject_irq(struct kvm_vcpu *vcpu) | |
1420 | { | |
1421 | int word_index = __ffs(vcpu->irq_summary); | |
1422 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
1423 | int irq = word_index * BITS_PER_LONG + bit_index; | |
1424 | ||
1425 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
1426 | if (!vcpu->irq_pending[word_index]) | |
1427 | clear_bit(word_index, &vcpu->irq_summary); | |
1428 | ||
1429 | if (vcpu->rmode.active) { | |
1430 | inject_rmode_irq(vcpu, irq); | |
1431 | return; | |
1432 | } | |
1433 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
1434 | irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1435 | } | |
1436 | ||
c1150d8c DL |
1437 | |
1438 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, | |
1439 | struct kvm_run *kvm_run) | |
6aa8b732 | 1440 | { |
c1150d8c DL |
1441 | u32 cpu_based_vm_exec_control; |
1442 | ||
1443 | vcpu->interrupt_window_open = | |
1444 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
1445 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
1446 | ||
1447 | if (vcpu->interrupt_window_open && | |
1448 | vcpu->irq_summary && | |
1449 | !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK)) | |
6aa8b732 | 1450 | /* |
c1150d8c | 1451 | * If interrupts enabled, and not blocked by sti or mov ss. Good. |
6aa8b732 AK |
1452 | */ |
1453 | kvm_do_inject_irq(vcpu); | |
c1150d8c DL |
1454 | |
1455 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
1456 | if (!vcpu->interrupt_window_open && | |
1457 | (vcpu->irq_summary || kvm_run->request_interrupt_window)) | |
6aa8b732 AK |
1458 | /* |
1459 | * Interrupts blocked. Wait for unblock. | |
1460 | */ | |
c1150d8c DL |
1461 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; |
1462 | else | |
1463 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
1464 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
6aa8b732 AK |
1465 | } |
1466 | ||
1467 | static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu) | |
1468 | { | |
1469 | struct kvm_guest_debug *dbg = &vcpu->guest_debug; | |
1470 | ||
1471 | set_debugreg(dbg->bp[0], 0); | |
1472 | set_debugreg(dbg->bp[1], 1); | |
1473 | set_debugreg(dbg->bp[2], 2); | |
1474 | set_debugreg(dbg->bp[3], 3); | |
1475 | ||
1476 | if (dbg->singlestep) { | |
1477 | unsigned long flags; | |
1478 | ||
1479 | flags = vmcs_readl(GUEST_RFLAGS); | |
1480 | flags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
1481 | vmcs_writel(GUEST_RFLAGS, flags); | |
1482 | } | |
1483 | } | |
1484 | ||
1485 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
1486 | int vec, u32 err_code) | |
1487 | { | |
1488 | if (!vcpu->rmode.active) | |
1489 | return 0; | |
1490 | ||
b3f37707 NK |
1491 | /* |
1492 | * Instruction with address size override prefix opcode 0x67 | |
1493 | * Cause the #SS fault with 0 error code in VM86 mode. | |
1494 | */ | |
1495 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
6aa8b732 AK |
1496 | if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE) |
1497 | return 1; | |
1498 | return 0; | |
1499 | } | |
1500 | ||
1501 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1502 | { | |
1503 | u32 intr_info, error_code; | |
1504 | unsigned long cr2, rip; | |
1505 | u32 vect_info; | |
1506 | enum emulation_result er; | |
e2dec939 | 1507 | int r; |
6aa8b732 AK |
1508 | |
1509 | vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
1510 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
1511 | ||
1512 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
1513 | !is_page_fault(intr_info)) { | |
1514 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " | |
1515 | "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info); | |
1516 | } | |
1517 | ||
1518 | if (is_external_interrupt(vect_info)) { | |
1519 | int irq = vect_info & VECTORING_INFO_VECTOR_MASK; | |
1520 | set_bit(irq, vcpu->irq_pending); | |
1521 | set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary); | |
1522 | } | |
1523 | ||
1524 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */ | |
1525 | asm ("int $2"); | |
1526 | return 1; | |
1527 | } | |
2ab455cc AL |
1528 | |
1529 | if (is_no_device(intr_info)) { | |
5fd86fcf | 1530 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
1531 | return 1; |
1532 | } | |
1533 | ||
6aa8b732 AK |
1534 | error_code = 0; |
1535 | rip = vmcs_readl(GUEST_RIP); | |
1536 | if (intr_info & INTR_INFO_DELIEVER_CODE_MASK) | |
1537 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
1538 | if (is_page_fault(intr_info)) { | |
1539 | cr2 = vmcs_readl(EXIT_QUALIFICATION); | |
1540 | ||
1541 | spin_lock(&vcpu->kvm->lock); | |
e2dec939 AK |
1542 | r = kvm_mmu_page_fault(vcpu, cr2, error_code); |
1543 | if (r < 0) { | |
1544 | spin_unlock(&vcpu->kvm->lock); | |
1545 | return r; | |
1546 | } | |
1547 | if (!r) { | |
6aa8b732 AK |
1548 | spin_unlock(&vcpu->kvm->lock); |
1549 | return 1; | |
1550 | } | |
1551 | ||
1552 | er = emulate_instruction(vcpu, kvm_run, cr2, error_code); | |
1553 | spin_unlock(&vcpu->kvm->lock); | |
1554 | ||
1555 | switch (er) { | |
1556 | case EMULATE_DONE: | |
1557 | return 1; | |
1558 | case EMULATE_DO_MMIO: | |
1165f5fe | 1559 | ++vcpu->stat.mmio_exits; |
6aa8b732 AK |
1560 | kvm_run->exit_reason = KVM_EXIT_MMIO; |
1561 | return 0; | |
1562 | case EMULATE_FAIL: | |
1563 | vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__); | |
1564 | break; | |
1565 | default: | |
1566 | BUG(); | |
1567 | } | |
1568 | } | |
1569 | ||
1570 | if (vcpu->rmode.active && | |
1571 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, | |
1572 | error_code)) | |
1573 | return 1; | |
1574 | ||
1575 | if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) { | |
1576 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
1577 | return 0; | |
1578 | } | |
1579 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; | |
1580 | kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK; | |
1581 | kvm_run->ex.error_code = error_code; | |
1582 | return 0; | |
1583 | } | |
1584 | ||
1585 | static int handle_external_interrupt(struct kvm_vcpu *vcpu, | |
1586 | struct kvm_run *kvm_run) | |
1587 | { | |
1165f5fe | 1588 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
1589 | return 1; |
1590 | } | |
1591 | ||
988ad74f AK |
1592 | static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1593 | { | |
1594 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1595 | return 0; | |
1596 | } | |
6aa8b732 | 1597 | |
039576c0 | 1598 | static int get_io_count(struct kvm_vcpu *vcpu, unsigned long *count) |
6aa8b732 AK |
1599 | { |
1600 | u64 inst; | |
1601 | gva_t rip; | |
1602 | int countr_size; | |
1603 | int i, n; | |
1604 | ||
1605 | if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) { | |
1606 | countr_size = 2; | |
1607 | } else { | |
1608 | u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1609 | ||
1610 | countr_size = (cs_ar & AR_L_MASK) ? 8: | |
1611 | (cs_ar & AR_DB_MASK) ? 4: 2; | |
1612 | } | |
1613 | ||
1614 | rip = vmcs_readl(GUEST_RIP); | |
1615 | if (countr_size != 8) | |
1616 | rip += vmcs_readl(GUEST_CS_BASE); | |
1617 | ||
1618 | n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst); | |
1619 | ||
1620 | for (i = 0; i < n; i++) { | |
1621 | switch (((u8*)&inst)[i]) { | |
1622 | case 0xf0: | |
1623 | case 0xf2: | |
1624 | case 0xf3: | |
1625 | case 0x2e: | |
1626 | case 0x36: | |
1627 | case 0x3e: | |
1628 | case 0x26: | |
1629 | case 0x64: | |
1630 | case 0x65: | |
1631 | case 0x66: | |
1632 | break; | |
1633 | case 0x67: | |
1634 | countr_size = (countr_size == 2) ? 4: (countr_size >> 1); | |
1635 | default: | |
1636 | goto done; | |
1637 | } | |
1638 | } | |
1639 | return 0; | |
1640 | done: | |
1641 | countr_size *= 8; | |
1642 | *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size)); | |
039576c0 | 1643 | //printk("cx: %lx\n", vcpu->regs[VCPU_REGS_RCX]); |
6aa8b732 AK |
1644 | return 1; |
1645 | } | |
1646 | ||
1647 | static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1648 | { | |
1649 | u64 exit_qualification; | |
039576c0 AK |
1650 | int size, down, in, string, rep; |
1651 | unsigned port; | |
1652 | unsigned long count; | |
1653 | gva_t address; | |
6aa8b732 | 1654 | |
1165f5fe | 1655 | ++vcpu->stat.io_exits; |
6aa8b732 | 1656 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); |
039576c0 AK |
1657 | in = (exit_qualification & 8) != 0; |
1658 | size = (exit_qualification & 7) + 1; | |
1659 | string = (exit_qualification & 16) != 0; | |
1660 | down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0; | |
1661 | count = 1; | |
1662 | rep = (exit_qualification & 32) != 0; | |
1663 | port = exit_qualification >> 16; | |
1664 | address = 0; | |
1665 | if (string) { | |
1666 | if (rep && !get_io_count(vcpu, &count)) | |
6aa8b732 | 1667 | return 1; |
039576c0 AK |
1668 | address = vmcs_readl(GUEST_LINEAR_ADDRESS); |
1669 | } | |
1670 | return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down, | |
1671 | address, rep, port); | |
6aa8b732 AK |
1672 | } |
1673 | ||
102d8325 IM |
1674 | static void |
1675 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1676 | { | |
1677 | /* | |
1678 | * Patch in the VMCALL instruction: | |
1679 | */ | |
1680 | hypercall[0] = 0x0f; | |
1681 | hypercall[1] = 0x01; | |
1682 | hypercall[2] = 0xc1; | |
1683 | hypercall[3] = 0xc3; | |
1684 | } | |
1685 | ||
6aa8b732 AK |
1686 | static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1687 | { | |
1688 | u64 exit_qualification; | |
1689 | int cr; | |
1690 | int reg; | |
1691 | ||
1692 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
1693 | cr = exit_qualification & 15; | |
1694 | reg = (exit_qualification >> 8) & 15; | |
1695 | switch ((exit_qualification >> 4) & 3) { | |
1696 | case 0: /* mov to cr */ | |
1697 | switch (cr) { | |
1698 | case 0: | |
1699 | vcpu_load_rsp_rip(vcpu); | |
1700 | set_cr0(vcpu, vcpu->regs[reg]); | |
1701 | skip_emulated_instruction(vcpu); | |
1702 | return 1; | |
1703 | case 3: | |
1704 | vcpu_load_rsp_rip(vcpu); | |
1705 | set_cr3(vcpu, vcpu->regs[reg]); | |
1706 | skip_emulated_instruction(vcpu); | |
1707 | return 1; | |
1708 | case 4: | |
1709 | vcpu_load_rsp_rip(vcpu); | |
1710 | set_cr4(vcpu, vcpu->regs[reg]); | |
1711 | skip_emulated_instruction(vcpu); | |
1712 | return 1; | |
1713 | case 8: | |
1714 | vcpu_load_rsp_rip(vcpu); | |
1715 | set_cr8(vcpu, vcpu->regs[reg]); | |
1716 | skip_emulated_instruction(vcpu); | |
1717 | return 1; | |
1718 | }; | |
1719 | break; | |
25c4c276 AL |
1720 | case 2: /* clts */ |
1721 | vcpu_load_rsp_rip(vcpu); | |
5fd86fcf | 1722 | vmx_fpu_deactivate(vcpu); |
2ab455cc AL |
1723 | vcpu->cr0 &= ~CR0_TS_MASK; |
1724 | vmcs_writel(CR0_READ_SHADOW, vcpu->cr0); | |
5fd86fcf | 1725 | vmx_fpu_activate(vcpu); |
25c4c276 AL |
1726 | skip_emulated_instruction(vcpu); |
1727 | return 1; | |
6aa8b732 AK |
1728 | case 1: /*mov from cr*/ |
1729 | switch (cr) { | |
1730 | case 3: | |
1731 | vcpu_load_rsp_rip(vcpu); | |
1732 | vcpu->regs[reg] = vcpu->cr3; | |
1733 | vcpu_put_rsp_rip(vcpu); | |
1734 | skip_emulated_instruction(vcpu); | |
1735 | return 1; | |
1736 | case 8: | |
6aa8b732 AK |
1737 | vcpu_load_rsp_rip(vcpu); |
1738 | vcpu->regs[reg] = vcpu->cr8; | |
1739 | vcpu_put_rsp_rip(vcpu); | |
1740 | skip_emulated_instruction(vcpu); | |
1741 | return 1; | |
1742 | } | |
1743 | break; | |
1744 | case 3: /* lmsw */ | |
1745 | lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f); | |
1746 | ||
1747 | skip_emulated_instruction(vcpu); | |
1748 | return 1; | |
1749 | default: | |
1750 | break; | |
1751 | } | |
1752 | kvm_run->exit_reason = 0; | |
1753 | printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n", | |
1754 | (int)(exit_qualification >> 4) & 3, cr); | |
1755 | return 0; | |
1756 | } | |
1757 | ||
1758 | static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1759 | { | |
1760 | u64 exit_qualification; | |
1761 | unsigned long val; | |
1762 | int dr, reg; | |
1763 | ||
1764 | /* | |
1765 | * FIXME: this code assumes the host is debugging the guest. | |
1766 | * need to deal with guest debugging itself too. | |
1767 | */ | |
1768 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
1769 | dr = exit_qualification & 7; | |
1770 | reg = (exit_qualification >> 8) & 15; | |
1771 | vcpu_load_rsp_rip(vcpu); | |
1772 | if (exit_qualification & 16) { | |
1773 | /* mov from dr */ | |
1774 | switch (dr) { | |
1775 | case 6: | |
1776 | val = 0xffff0ff0; | |
1777 | break; | |
1778 | case 7: | |
1779 | val = 0x400; | |
1780 | break; | |
1781 | default: | |
1782 | val = 0; | |
1783 | } | |
1784 | vcpu->regs[reg] = val; | |
1785 | } else { | |
1786 | /* mov to dr */ | |
1787 | } | |
1788 | vcpu_put_rsp_rip(vcpu); | |
1789 | skip_emulated_instruction(vcpu); | |
1790 | return 1; | |
1791 | } | |
1792 | ||
1793 | static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1794 | { | |
06465c5a AK |
1795 | kvm_emulate_cpuid(vcpu); |
1796 | return 1; | |
6aa8b732 AK |
1797 | } |
1798 | ||
1799 | static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1800 | { | |
1801 | u32 ecx = vcpu->regs[VCPU_REGS_RCX]; | |
1802 | u64 data; | |
1803 | ||
1804 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
1805 | vmx_inject_gp(vcpu, 0); | |
1806 | return 1; | |
1807 | } | |
1808 | ||
1809 | /* FIXME: handling of bits 32:63 of rax, rdx */ | |
1810 | vcpu->regs[VCPU_REGS_RAX] = data & -1u; | |
1811 | vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
1812 | skip_emulated_instruction(vcpu); | |
1813 | return 1; | |
1814 | } | |
1815 | ||
1816 | static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1817 | { | |
1818 | u32 ecx = vcpu->regs[VCPU_REGS_RCX]; | |
1819 | u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u) | |
1820 | | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32); | |
1821 | ||
1822 | if (vmx_set_msr(vcpu, ecx, data) != 0) { | |
1823 | vmx_inject_gp(vcpu, 0); | |
1824 | return 1; | |
1825 | } | |
1826 | ||
1827 | skip_emulated_instruction(vcpu); | |
1828 | return 1; | |
1829 | } | |
1830 | ||
c1150d8c DL |
1831 | static void post_kvm_run_save(struct kvm_vcpu *vcpu, |
1832 | struct kvm_run *kvm_run) | |
1833 | { | |
1834 | kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0; | |
1835 | kvm_run->cr8 = vcpu->cr8; | |
1836 | kvm_run->apic_base = vcpu->apic_base; | |
1837 | kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open && | |
1838 | vcpu->irq_summary == 0); | |
1839 | } | |
1840 | ||
6aa8b732 AK |
1841 | static int handle_interrupt_window(struct kvm_vcpu *vcpu, |
1842 | struct kvm_run *kvm_run) | |
1843 | { | |
c1150d8c DL |
1844 | /* |
1845 | * If the user space waits to inject interrupts, exit as soon as | |
1846 | * possible | |
1847 | */ | |
1848 | if (kvm_run->request_interrupt_window && | |
022a9308 | 1849 | !vcpu->irq_summary) { |
c1150d8c | 1850 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1165f5fe | 1851 | ++vcpu->stat.irq_window_exits; |
c1150d8c DL |
1852 | return 0; |
1853 | } | |
6aa8b732 AK |
1854 | return 1; |
1855 | } | |
1856 | ||
1857 | static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1858 | { | |
1859 | skip_emulated_instruction(vcpu); | |
c1150d8c | 1860 | if (vcpu->irq_summary) |
6aa8b732 AK |
1861 | return 1; |
1862 | ||
1863 | kvm_run->exit_reason = KVM_EXIT_HLT; | |
1165f5fe | 1864 | ++vcpu->stat.halt_exits; |
6aa8b732 AK |
1865 | return 0; |
1866 | } | |
1867 | ||
c21415e8 IM |
1868 | static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1869 | { | |
510043da | 1870 | skip_emulated_instruction(vcpu); |
270fd9b9 | 1871 | return kvm_hypercall(vcpu, kvm_run); |
c21415e8 IM |
1872 | } |
1873 | ||
6aa8b732 AK |
1874 | /* |
1875 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
1876 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
1877 | * to be done to userspace and return 0. | |
1878 | */ | |
1879 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, | |
1880 | struct kvm_run *kvm_run) = { | |
1881 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, | |
1882 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 1883 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
6aa8b732 | 1884 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
1885 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
1886 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
1887 | [EXIT_REASON_CPUID] = handle_cpuid, | |
1888 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
1889 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
1890 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
1891 | [EXIT_REASON_HLT] = handle_halt, | |
c21415e8 | 1892 | [EXIT_REASON_VMCALL] = handle_vmcall, |
6aa8b732 AK |
1893 | }; |
1894 | ||
1895 | static const int kvm_vmx_max_exit_handlers = | |
1896 | sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers); | |
1897 | ||
1898 | /* | |
1899 | * The guest has exited. See if we can fix it or if we need userspace | |
1900 | * assistance. | |
1901 | */ | |
1902 | static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |
1903 | { | |
1904 | u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
1905 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); | |
1906 | ||
1907 | if ( (vectoring_info & VECTORING_INFO_VALID_MASK) && | |
1908 | exit_reason != EXIT_REASON_EXCEPTION_NMI ) | |
1909 | printk(KERN_WARNING "%s: unexpected, valid vectoring info and " | |
1910 | "exit reason is 0x%x\n", __FUNCTION__, exit_reason); | |
6aa8b732 AK |
1911 | if (exit_reason < kvm_vmx_max_exit_handlers |
1912 | && kvm_vmx_exit_handlers[exit_reason]) | |
1913 | return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run); | |
1914 | else { | |
1915 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
1916 | kvm_run->hw.hardware_exit_reason = exit_reason; | |
1917 | } | |
1918 | return 0; | |
1919 | } | |
1920 | ||
c1150d8c DL |
1921 | /* |
1922 | * Check if userspace requested an interrupt window, and that the | |
1923 | * interrupt window is open. | |
1924 | * | |
1925 | * No need to exit to userspace if we already have an interrupt queued. | |
1926 | */ | |
1927 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu, | |
1928 | struct kvm_run *kvm_run) | |
1929 | { | |
1930 | return (!vcpu->irq_summary && | |
1931 | kvm_run->request_interrupt_window && | |
1932 | vcpu->interrupt_window_open && | |
1933 | (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)); | |
1934 | } | |
1935 | ||
6aa8b732 AK |
1936 | static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1937 | { | |
1938 | u8 fail; | |
e2dec939 | 1939 | int r; |
6aa8b732 | 1940 | |
e6adf283 | 1941 | preempted: |
cccf748b AK |
1942 | if (!vcpu->mmio_read_completed) |
1943 | do_interrupt_requests(vcpu, kvm_run); | |
6aa8b732 AK |
1944 | |
1945 | if (vcpu->guest_debug.enabled) | |
1946 | kvm_guest_debug_pre(vcpu); | |
1947 | ||
e6adf283 | 1948 | again: |
33ed6329 | 1949 | vmx_save_host_state(vcpu); |
e6adf283 AK |
1950 | kvm_load_guest_fpu(vcpu); |
1951 | ||
1952 | /* | |
1953 | * Loading guest fpu may have cleared host cr0.ts | |
1954 | */ | |
1955 | vmcs_writel(HOST_CR0, read_cr0()); | |
1956 | ||
6aa8b732 AK |
1957 | asm ( |
1958 | /* Store host registers */ | |
1959 | "pushf \n\t" | |
05b3e0c2 | 1960 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1961 | "push %%rax; push %%rbx; push %%rdx;" |
1962 | "push %%rsi; push %%rdi; push %%rbp;" | |
1963 | "push %%r8; push %%r9; push %%r10; push %%r11;" | |
1964 | "push %%r12; push %%r13; push %%r14; push %%r15;" | |
1965 | "push %%rcx \n\t" | |
1966 | ASM_VMX_VMWRITE_RSP_RDX "\n\t" | |
1967 | #else | |
1968 | "pusha; push %%ecx \n\t" | |
1969 | ASM_VMX_VMWRITE_RSP_RDX "\n\t" | |
1970 | #endif | |
1971 | /* Check if vmlaunch of vmresume is needed */ | |
1972 | "cmp $0, %1 \n\t" | |
1973 | /* Load guest registers. Don't clobber flags. */ | |
05b3e0c2 | 1974 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1975 | "mov %c[cr2](%3), %%rax \n\t" |
1976 | "mov %%rax, %%cr2 \n\t" | |
1977 | "mov %c[rax](%3), %%rax \n\t" | |
1978 | "mov %c[rbx](%3), %%rbx \n\t" | |
1979 | "mov %c[rdx](%3), %%rdx \n\t" | |
1980 | "mov %c[rsi](%3), %%rsi \n\t" | |
1981 | "mov %c[rdi](%3), %%rdi \n\t" | |
1982 | "mov %c[rbp](%3), %%rbp \n\t" | |
1983 | "mov %c[r8](%3), %%r8 \n\t" | |
1984 | "mov %c[r9](%3), %%r9 \n\t" | |
1985 | "mov %c[r10](%3), %%r10 \n\t" | |
1986 | "mov %c[r11](%3), %%r11 \n\t" | |
1987 | "mov %c[r12](%3), %%r12 \n\t" | |
1988 | "mov %c[r13](%3), %%r13 \n\t" | |
1989 | "mov %c[r14](%3), %%r14 \n\t" | |
1990 | "mov %c[r15](%3), %%r15 \n\t" | |
1991 | "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */ | |
1992 | #else | |
1993 | "mov %c[cr2](%3), %%eax \n\t" | |
1994 | "mov %%eax, %%cr2 \n\t" | |
1995 | "mov %c[rax](%3), %%eax \n\t" | |
1996 | "mov %c[rbx](%3), %%ebx \n\t" | |
1997 | "mov %c[rdx](%3), %%edx \n\t" | |
1998 | "mov %c[rsi](%3), %%esi \n\t" | |
1999 | "mov %c[rdi](%3), %%edi \n\t" | |
2000 | "mov %c[rbp](%3), %%ebp \n\t" | |
2001 | "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */ | |
2002 | #endif | |
2003 | /* Enter guest mode */ | |
cd2276a7 | 2004 | "jne .Llaunched \n\t" |
6aa8b732 | 2005 | ASM_VMX_VMLAUNCH "\n\t" |
cd2276a7 AK |
2006 | "jmp .Lkvm_vmx_return \n\t" |
2007 | ".Llaunched: " ASM_VMX_VMRESUME "\n\t" | |
2008 | ".Lkvm_vmx_return: " | |
6aa8b732 | 2009 | /* Save guest registers, load host registers, keep flags */ |
05b3e0c2 | 2010 | #ifdef CONFIG_X86_64 |
96958231 | 2011 | "xchg %3, (%%rsp) \n\t" |
6aa8b732 AK |
2012 | "mov %%rax, %c[rax](%3) \n\t" |
2013 | "mov %%rbx, %c[rbx](%3) \n\t" | |
96958231 | 2014 | "pushq (%%rsp); popq %c[rcx](%3) \n\t" |
6aa8b732 AK |
2015 | "mov %%rdx, %c[rdx](%3) \n\t" |
2016 | "mov %%rsi, %c[rsi](%3) \n\t" | |
2017 | "mov %%rdi, %c[rdi](%3) \n\t" | |
2018 | "mov %%rbp, %c[rbp](%3) \n\t" | |
2019 | "mov %%r8, %c[r8](%3) \n\t" | |
2020 | "mov %%r9, %c[r9](%3) \n\t" | |
2021 | "mov %%r10, %c[r10](%3) \n\t" | |
2022 | "mov %%r11, %c[r11](%3) \n\t" | |
2023 | "mov %%r12, %c[r12](%3) \n\t" | |
2024 | "mov %%r13, %c[r13](%3) \n\t" | |
2025 | "mov %%r14, %c[r14](%3) \n\t" | |
2026 | "mov %%r15, %c[r15](%3) \n\t" | |
2027 | "mov %%cr2, %%rax \n\t" | |
2028 | "mov %%rax, %c[cr2](%3) \n\t" | |
96958231 | 2029 | "mov (%%rsp), %3 \n\t" |
6aa8b732 AK |
2030 | |
2031 | "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;" | |
2032 | "pop %%r11; pop %%r10; pop %%r9; pop %%r8;" | |
2033 | "pop %%rbp; pop %%rdi; pop %%rsi;" | |
2034 | "pop %%rdx; pop %%rbx; pop %%rax \n\t" | |
2035 | #else | |
96958231 | 2036 | "xchg %3, (%%esp) \n\t" |
6aa8b732 AK |
2037 | "mov %%eax, %c[rax](%3) \n\t" |
2038 | "mov %%ebx, %c[rbx](%3) \n\t" | |
96958231 | 2039 | "pushl (%%esp); popl %c[rcx](%3) \n\t" |
6aa8b732 AK |
2040 | "mov %%edx, %c[rdx](%3) \n\t" |
2041 | "mov %%esi, %c[rsi](%3) \n\t" | |
2042 | "mov %%edi, %c[rdi](%3) \n\t" | |
2043 | "mov %%ebp, %c[rbp](%3) \n\t" | |
2044 | "mov %%cr2, %%eax \n\t" | |
2045 | "mov %%eax, %c[cr2](%3) \n\t" | |
96958231 | 2046 | "mov (%%esp), %3 \n\t" |
6aa8b732 AK |
2047 | |
2048 | "pop %%ecx; popa \n\t" | |
2049 | #endif | |
2050 | "setbe %0 \n\t" | |
2051 | "popf \n\t" | |
e0015489 | 2052 | : "=q" (fail) |
6aa8b732 AK |
2053 | : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP), |
2054 | "c"(vcpu), | |
2055 | [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])), | |
2056 | [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])), | |
2057 | [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])), | |
2058 | [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])), | |
2059 | [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])), | |
2060 | [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])), | |
2061 | [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 2062 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2063 | [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])), |
2064 | [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])), | |
2065 | [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])), | |
2066 | [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])), | |
2067 | [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])), | |
2068 | [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])), | |
2069 | [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])), | |
2070 | [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])), | |
2071 | #endif | |
2072 | [cr2]"i"(offsetof(struct kvm_vcpu, cr2)) | |
2073 | : "cc", "memory" ); | |
2074 | ||
1165f5fe | 2075 | ++vcpu->stat.exits; |
6aa8b732 | 2076 | |
c1150d8c | 2077 | vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0; |
6aa8b732 | 2078 | |
6aa8b732 | 2079 | asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
6aa8b732 | 2080 | |
05e0c8c3 | 2081 | if (unlikely(fail)) { |
8eb7d334 AK |
2082 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
2083 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2084 | = vmcs_read32(VM_INSTRUCTION_ERROR); | |
e2dec939 | 2085 | r = 0; |
05e0c8c3 AK |
2086 | goto out; |
2087 | } | |
2088 | /* | |
2089 | * Profile KVM exit RIPs: | |
2090 | */ | |
2091 | if (unlikely(prof_on == KVM_PROFILING)) | |
2092 | profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP)); | |
2093 | ||
2094 | vcpu->launched = 1; | |
2095 | r = kvm_handle_exit(kvm_run, vcpu); | |
2096 | if (r > 0) { | |
2097 | /* Give scheduler a change to reschedule. */ | |
2098 | if (signal_pending(current)) { | |
2099 | r = -EINTR; | |
2100 | kvm_run->exit_reason = KVM_EXIT_INTR; | |
2101 | ++vcpu->stat.signal_exits; | |
2102 | goto out; | |
2103 | } | |
2104 | ||
2105 | if (dm_request_for_irq_injection(vcpu, kvm_run)) { | |
2106 | r = -EINTR; | |
2107 | kvm_run->exit_reason = KVM_EXIT_INTR; | |
2108 | ++vcpu->stat.request_irq_exits; | |
2109 | goto out; | |
2110 | } | |
2111 | if (!need_resched()) { | |
2112 | ++vcpu->stat.light_exits; | |
2113 | goto again; | |
6aa8b732 AK |
2114 | } |
2115 | } | |
c1150d8c | 2116 | |
e6adf283 | 2117 | out: |
e6adf283 AK |
2118 | if (r > 0) { |
2119 | kvm_resched(vcpu); | |
2120 | goto preempted; | |
2121 | } | |
2122 | ||
c1150d8c | 2123 | post_kvm_run_save(vcpu, kvm_run); |
e2dec939 | 2124 | return r; |
6aa8b732 AK |
2125 | } |
2126 | ||
2127 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) | |
2128 | { | |
2129 | vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3)); | |
2130 | } | |
2131 | ||
2132 | static void vmx_inject_page_fault(struct kvm_vcpu *vcpu, | |
2133 | unsigned long addr, | |
2134 | u32 err_code) | |
2135 | { | |
2136 | u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
2137 | ||
1165f5fe | 2138 | ++vcpu->stat.pf_guest; |
6aa8b732 AK |
2139 | |
2140 | if (is_page_fault(vect_info)) { | |
2141 | printk(KERN_DEBUG "inject_page_fault: " | |
2142 | "double fault 0x%lx @ 0x%lx\n", | |
2143 | addr, vmcs_readl(GUEST_RIP)); | |
2144 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0); | |
2145 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2146 | DF_VECTOR | | |
2147 | INTR_TYPE_EXCEPTION | | |
2148 | INTR_INFO_DELIEVER_CODE_MASK | | |
2149 | INTR_INFO_VALID_MASK); | |
2150 | return; | |
2151 | } | |
2152 | vcpu->cr2 = addr; | |
2153 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code); | |
2154 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2155 | PF_VECTOR | | |
2156 | INTR_TYPE_EXCEPTION | | |
2157 | INTR_INFO_DELIEVER_CODE_MASK | | |
2158 | INTR_INFO_VALID_MASK); | |
2159 | ||
2160 | } | |
2161 | ||
2162 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) | |
2163 | { | |
2164 | if (vcpu->vmcs) { | |
2165 | on_each_cpu(__vcpu_clear, vcpu, 0, 1); | |
2166 | free_vmcs(vcpu->vmcs); | |
2167 | vcpu->vmcs = NULL; | |
2168 | } | |
2169 | } | |
2170 | ||
2171 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
2172 | { | |
2173 | vmx_free_vmcs(vcpu); | |
2174 | } | |
2175 | ||
2176 | static int vmx_create_vcpu(struct kvm_vcpu *vcpu) | |
2177 | { | |
2178 | struct vmcs *vmcs; | |
2179 | ||
965b58a5 IM |
2180 | vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
2181 | if (!vcpu->guest_msrs) | |
2182 | return -ENOMEM; | |
2183 | ||
2184 | vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
2185 | if (!vcpu->host_msrs) | |
2186 | goto out_free_guest_msrs; | |
2187 | ||
6aa8b732 AK |
2188 | vmcs = alloc_vmcs(); |
2189 | if (!vmcs) | |
965b58a5 IM |
2190 | goto out_free_msrs; |
2191 | ||
6aa8b732 AK |
2192 | vmcs_clear(vmcs); |
2193 | vcpu->vmcs = vmcs; | |
2194 | vcpu->launched = 0; | |
965b58a5 | 2195 | |
6aa8b732 | 2196 | return 0; |
965b58a5 IM |
2197 | |
2198 | out_free_msrs: | |
2199 | kfree(vcpu->host_msrs); | |
2200 | vcpu->host_msrs = NULL; | |
2201 | ||
2202 | out_free_guest_msrs: | |
2203 | kfree(vcpu->guest_msrs); | |
2204 | vcpu->guest_msrs = NULL; | |
2205 | ||
2206 | return -ENOMEM; | |
6aa8b732 AK |
2207 | } |
2208 | ||
2209 | static struct kvm_arch_ops vmx_arch_ops = { | |
2210 | .cpu_has_kvm_support = cpu_has_kvm_support, | |
2211 | .disabled_by_bios = vmx_disabled_by_bios, | |
2212 | .hardware_setup = hardware_setup, | |
2213 | .hardware_unsetup = hardware_unsetup, | |
2214 | .hardware_enable = hardware_enable, | |
2215 | .hardware_disable = hardware_disable, | |
2216 | ||
2217 | .vcpu_create = vmx_create_vcpu, | |
2218 | .vcpu_free = vmx_free_vcpu, | |
2219 | ||
2220 | .vcpu_load = vmx_vcpu_load, | |
2221 | .vcpu_put = vmx_vcpu_put, | |
774c47f1 | 2222 | .vcpu_decache = vmx_vcpu_decache, |
6aa8b732 AK |
2223 | |
2224 | .set_guest_debug = set_guest_debug, | |
2225 | .get_msr = vmx_get_msr, | |
2226 | .set_msr = vmx_set_msr, | |
2227 | .get_segment_base = vmx_get_segment_base, | |
2228 | .get_segment = vmx_get_segment, | |
2229 | .set_segment = vmx_set_segment, | |
6aa8b732 | 2230 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
25c4c276 | 2231 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 2232 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
2233 | .set_cr3 = vmx_set_cr3, |
2234 | .set_cr4 = vmx_set_cr4, | |
05b3e0c2 | 2235 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2236 | .set_efer = vmx_set_efer, |
2237 | #endif | |
2238 | .get_idt = vmx_get_idt, | |
2239 | .set_idt = vmx_set_idt, | |
2240 | .get_gdt = vmx_get_gdt, | |
2241 | .set_gdt = vmx_set_gdt, | |
2242 | .cache_regs = vcpu_load_rsp_rip, | |
2243 | .decache_regs = vcpu_put_rsp_rip, | |
2244 | .get_rflags = vmx_get_rflags, | |
2245 | .set_rflags = vmx_set_rflags, | |
2246 | ||
2247 | .tlb_flush = vmx_flush_tlb, | |
2248 | .inject_page_fault = vmx_inject_page_fault, | |
2249 | ||
2250 | .inject_gp = vmx_inject_gp, | |
2251 | ||
2252 | .run = vmx_vcpu_run, | |
2253 | .skip_emulated_instruction = skip_emulated_instruction, | |
2254 | .vcpu_setup = vmx_vcpu_setup, | |
102d8325 | 2255 | .patch_hypercall = vmx_patch_hypercall, |
6aa8b732 AK |
2256 | }; |
2257 | ||
2258 | static int __init vmx_init(void) | |
2259 | { | |
fdef3ad1 HQ |
2260 | void *iova; |
2261 | int r; | |
2262 | ||
2263 | vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
2264 | if (!vmx_io_bitmap_a) | |
2265 | return -ENOMEM; | |
2266 | ||
2267 | vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
2268 | if (!vmx_io_bitmap_b) { | |
2269 | r = -ENOMEM; | |
2270 | goto out; | |
2271 | } | |
2272 | ||
2273 | /* | |
2274 | * Allow direct access to the PC debug port (it is often used for I/O | |
2275 | * delays, but the vmexits simply slow things down). | |
2276 | */ | |
2277 | iova = kmap(vmx_io_bitmap_a); | |
2278 | memset(iova, 0xff, PAGE_SIZE); | |
2279 | clear_bit(0x80, iova); | |
cd0536d7 | 2280 | kunmap(vmx_io_bitmap_a); |
fdef3ad1 HQ |
2281 | |
2282 | iova = kmap(vmx_io_bitmap_b); | |
2283 | memset(iova, 0xff, PAGE_SIZE); | |
cd0536d7 | 2284 | kunmap(vmx_io_bitmap_b); |
fdef3ad1 HQ |
2285 | |
2286 | r = kvm_init_arch(&vmx_arch_ops, THIS_MODULE); | |
2287 | if (r) | |
2288 | goto out1; | |
2289 | ||
2290 | return 0; | |
2291 | ||
2292 | out1: | |
2293 | __free_page(vmx_io_bitmap_b); | |
2294 | out: | |
2295 | __free_page(vmx_io_bitmap_a); | |
2296 | return r; | |
6aa8b732 AK |
2297 | } |
2298 | ||
2299 | static void __exit vmx_exit(void) | |
2300 | { | |
fdef3ad1 HQ |
2301 | __free_page(vmx_io_bitmap_b); |
2302 | __free_page(vmx_io_bitmap_a); | |
2303 | ||
6aa8b732 AK |
2304 | kvm_exit_arch(); |
2305 | } | |
2306 | ||
2307 | module_init(vmx_init) | |
2308 | module_exit(vmx_exit) |