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[media] drxk: pass drxk priv struct instead of I2C adapter to i2c calls
[deliverable/linux.git] / drivers / media / dvb / frontends / drxk_hard.c
CommitLineData
43dd07f7
RM		 1/*
2 * drxk_hard: DRX-K DVB-C/T demodulator driver
3 *
4 * Copyright (C) 2010-2011 Digital Devices GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/firmware.h>
30#include <linux/i2c.h>
43dd07f7
RM		 31#include <asm/div64.h>
32
33#include "dvb_frontend.h"
34#include "drxk.h"
35#include "drxk_hard.h"
36
37static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
38static int PowerDownQAM(struct drxk_state *state);
ebc7de22
OE		 39static int SetDVBTStandard(struct drxk_state *state,
40 enum OperationMode oMode);
41static int SetQAMStandard(struct drxk_state *state,
42 enum OperationMode oMode);
43static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
43dd07f7 44 s32 tunerFreqOffset);
ebc7de22
OE		 45static int SetDVBTStandard(struct drxk_state *state,
46 enum OperationMode oMode);
43dd07f7 47static int DVBTStart(struct drxk_state *state);
ebc7de22
OE		 48static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
49 s32 tunerFreqOffset);
43dd07f7
RM		 50static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
51static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
52static int SwitchAntennaToQAM(struct drxk_state *state);
53static int SwitchAntennaToDVBT(struct drxk_state *state);
54
55static bool IsDVBT(struct drxk_state *state)
56{
57 return state->m_OperationMode == OM_DVBT;
58}
59
60static bool IsQAM(struct drxk_state *state)
61{
62 return state->m_OperationMode == OM_QAM_ITU_A ||
ebc7de22
OE		 63 state->m_OperationMode == OM_QAM_ITU_B ||
64 state->m_OperationMode == OM_QAM_ITU_C;
43dd07f7
RM		 65}
66
67bool IsA1WithPatchCode(struct drxk_state *state)
68{
69 return state->m_DRXK_A1_PATCH_CODE;
70}
71
72bool IsA1WithRomCode(struct drxk_state *state)
73{
74 return state->m_DRXK_A1_ROM_CODE;
75}
76
77#define NOA1ROM 0
78
43dd07f7
RM		 79#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
80#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
81
82#define DEFAULT_MER_83 165
83#define DEFAULT_MER_93 250
84
85#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
86#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
87#endif
88
89#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
90#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
91#endif
92
43dd07f7
RM		 93#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
94#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
95
96#ifndef DRXK_KI_RAGC_ATV
97#define DRXK_KI_RAGC_ATV 4
98#endif
99#ifndef DRXK_KI_IAGC_ATV
100#define DRXK_KI_IAGC_ATV 6
101#endif
102#ifndef DRXK_KI_DAGC_ATV
103#define DRXK_KI_DAGC_ATV 7
104#endif
105
106#ifndef DRXK_KI_RAGC_QAM
107#define DRXK_KI_RAGC_QAM 3
108#endif
109#ifndef DRXK_KI_IAGC_QAM
110#define DRXK_KI_IAGC_QAM 4
111#endif
112#ifndef DRXK_KI_DAGC_QAM
113#define DRXK_KI_DAGC_QAM 7
114#endif
115#ifndef DRXK_KI_RAGC_DVBT
116#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
117#endif
118#ifndef DRXK_KI_IAGC_DVBT
119#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
120#endif
121#ifndef DRXK_KI_DAGC_DVBT
122#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
123#endif
124
125#ifndef DRXK_AGC_DAC_OFFSET
126#define DRXK_AGC_DAC_OFFSET (0x800)
127#endif
128
129#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
130#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
131#endif
132
133#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
134#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
135#endif
136
137#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
138#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
139#endif
140
141#ifndef DRXK_QAM_SYMBOLRATE_MAX
142#define DRXK_QAM_SYMBOLRATE_MAX (7233000)
143#endif
144
145#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
146#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
147#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
148#define DRXK_BL_ROM_OFFSET_TAPS_BG 24
149#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
150#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
151#define DRXK_BL_ROM_OFFSET_TAPS_FM 48
152#define DRXK_BL_ROM_OFFSET_UCODE 0
153
154#define DRXK_BLC_TIMEOUT 100
155
156#define DRXK_BLCC_NR_ELEMENTS_TAPS 2
157#define DRXK_BLCC_NR_ELEMENTS_UCODE 6
158
159#define DRXK_BLDC_NR_ELEMENTS_TAPS 28
160
161#ifndef DRXK_OFDM_NE_NOTCH_WIDTH
162#define DRXK_OFDM_NE_NOTCH_WIDTH (4)
163#endif
164
165#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
166#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
167#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
168#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
169#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
170
2da67501
MCC		 171static unsigned int debug;
172module_param(debug, int, 0644);
173MODULE_PARM_DESC(debug, "enable debug messages");
174
175#define dprintk(level, fmt, arg...) do { \
176if (debug >= level) \
177 printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
178} while (0)
179
180
b01fbc10 181static inline u32 MulDiv32(u32 a, u32 b, u32 c)
43dd07f7
RM		 182{
183 u64 tmp64;
184
ebc7de22 185 tmp64 = (u64) a * (u64) b;
43dd07f7
RM		 186 do_div(tmp64, c);
187
188 return (u32) tmp64;
189}
190
191inline u32 Frac28a(u32 a, u32 c)
192{
193 int i = 0;
194 u32 Q1 = 0;
195 u32 R0 = 0;
196
ebc7de22
OE		 197 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
198 Q1 = a / c; /* integer part, only the 4 least significant bits
199 will be visible in the result */
43dd07f7
RM		 200
201 /* division using radix 16, 7 nibbles in the result */
202 for (i = 0; i < 7; i++) {
203 Q1 = (Q1 << 4) | (R0 / c);
204 R0 = (R0 % c) << 4;
205 }
206 /* rounding */
207 if ((R0 >> 3) >= c)
208 Q1++;
209
210 return Q1;
211}
212
213static u32 Log10Times100(u32 x)
214{
215 static const u8 scale = 15;
216 static const u8 indexWidth = 5;
ebc7de22 217 u8 i = 0;
43dd07f7
RM		 218 u32 y = 0;
219 u32 d = 0;
220 u32 k = 0;
221 u32 r = 0;
222 /*
ebc7de22
OE		 223 log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
224 0 <= n < ((1<<INDEXWIDTH)+1)
225 */
43dd07f7
RM		 226
227 static const u32 log2lut[] = {
ebc7de22
OE		 228 0, /* 0.000000 */
229 290941, /* 290941.300628 */
230 573196, /* 573196.476418 */
231 847269, /* 847269.179851 */
232 1113620, /* 1113620.489452 */
233 1372674, /* 1372673.576986 */
234 1624818, /* 1624817.752104 */
235 1870412, /* 1870411.981536 */
236 2109788, /* 2109787.962654 */
237 2343253, /* 2343252.817465 */
238 2571091, /* 2571091.461923 */
239 2793569, /* 2793568.696416 */
240 3010931, /* 3010931.055901 */
241 3223408, /* 3223408.452106 */
242 3431216, /* 3431215.635215 */
243 3634553, /* 3634553.498355 */
244 3833610, /* 3833610.244726 */
245 4028562, /* 4028562.434393 */
246 4219576, /* 4219575.925308 */
247 4406807, /* 4406806.721144 */
248 4590402, /* 4590401.736809 */
249 4770499, /* 4770499.491025 */
250 4947231, /* 4947230.734179 */
251 5120719, /* 5120719.018555 */
252 5291081, /* 5291081.217197 */
253 5458428, /* 5458427.996830 */
254 5622864, /* 5622864.249668 */
255 5784489, /* 5784489.488298 */
256 5943398, /* 5943398.207380 */
257 6099680, /* 6099680.215452 */
258 6253421, /* 6253420.939751 */
259 6404702, /* 6404701.706649 */
260 6553600, /* 6553600.000000 */
43dd07f7
RM		 261 };
262
263
264 if (x == 0)
ebc7de22 265 return 0;
43dd07f7
RM		 266
267 /* Scale x (normalize) */
268 /* computing y in log(x/y) = log(x) - log(y) */
269 if ((x & ((0xffffffff) << (scale + 1))) == 0) {
270 for (k = scale; k > 0; k--) {
ebc7de22 271 if (x & (((u32) 1) << scale))
43dd07f7
RM		 272 break;
273 x <<= 1;
274 }
275 } else {
ebc7de22
OE		 276 for (k = scale; k < 31; k++) {
277 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
43dd07f7
RM		 278 break;
279 x >>= 1;
ebc7de22 280 }
43dd07f7
RM		 281 }
282 /*
ebc7de22
OE		 283 Now x has binary point between bit[scale] and bit[scale-1]
284 and 1.0 <= x < 2.0 */
43dd07f7
RM		 285
286 /* correction for divison: log(x) = log(x/y)+log(y) */
ebc7de22 287 y = k * ((((u32) 1) << scale) * 200);
43dd07f7
RM		 288
289 /* remove integer part */
ebc7de22 290 x &= ((((u32) 1) << scale) - 1);
43dd07f7
RM		 291 /* get index */
292 i = (u8) (x >> (scale - indexWidth));
293 /* compute delta (x - a) */
ebc7de22 294 d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
43dd07f7
RM		 295 /* compute log, multiplication (d* (..)) must be within range ! */
296 y += log2lut[i] +
ebc7de22 297 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
43dd07f7 298 /* Conver to log10() */
ebc7de22 299 y /= 108853; /* (log2(10) << scale) */
43dd07f7
RM		 300 r = (y >> 1);
301 /* rounding */
ebc7de22 302 if (y & ((u32) 1))
43dd07f7 303 r++;
ebc7de22 304 return r;
43dd07f7
RM		 305}
306
307/****************************************************************************/
308/* I2C **********************************************************************/
309/****************************************************************************/
310
2a5f6720
MCC		 311static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
312 unsigned len)
313{
314 return i2c_transfer(state->i2c, msgs, len);
315}
316
317static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
43dd07f7 318{
ebc7de22
OE		 319 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
320 .buf = val, .len = 1}
321 };
be44eb28 322
2a5f6720 323 return drxk_i2c_transfer(state, msgs, 1);
43dd07f7
RM		 324}
325
2a5f6720 326static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
43dd07f7 327{
be44eb28 328 int status;
ebc7de22
OE		 329 struct i2c_msg msg = {
330 .addr = adr, .flags = 0, .buf = data, .len = len };
43dd07f7 331
2da67501
MCC		 332 dprintk(3, ":");
333 if (debug > 2) {
334 int i;
335 for (i = 0; i < len; i++)
336 printk(KERN_CONT " %02x", data[i]);
337 printk(KERN_CONT "\n");
338 }
2a5f6720 339 status = drxk_i2c_transfer(state, &msg, 1);
be44eb28
MCC		 340 if (status >= 0 && status != 1)
341 status = -EIO;
342
343 if (status < 0)
e0e6ecaf 344 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
be44eb28
MCC		 345
346 return status;
43dd07f7
RM		 347}
348
2a5f6720 349static int i2c_read(struct drxk_state *state,
43dd07f7
RM		 350 u8 adr, u8 *msg, int len, u8 *answ, int alen)
351{
be44eb28 352 int status;
e4f4f875
MCC		 353 struct i2c_msg msgs[2] = {
354 {.addr = adr, .flags = 0,
ebc7de22 355 .buf = msg, .len = len},
e4f4f875
MCC		 356 {.addr = adr, .flags = I2C_M_RD,
357 .buf = answ, .len = alen}
ebc7de22 358 };
f07a0bc1 359
2a5f6720 360 status = drxk_i2c_transfer(state, msgs, 2);
be44eb28 361 if (status != 2) {
2da67501
MCC		 362 if (debug > 2)
363 printk(KERN_CONT ": ERROR!\n");
be44eb28
MCC		 364 if (status >= 0)
365 status = -EIO;
2da67501 366
e0e6ecaf 367 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
be44eb28 368 return status;
43dd07f7 369 }
2da67501
MCC		 370 if (debug > 2) {
371 int i;
0d3e6fe7 372 dprintk(2, ": read from");
2da67501
MCC		 373 for (i = 0; i < len; i++)
374 printk(KERN_CONT " %02x", msg[i]);
0d3e6fe7 375 printk(KERN_CONT ", value = ");
f07a0bc1
MCC		 376 for (i = 0; i < alen; i++)
377 printk(KERN_CONT " %02x", answ[i]);
2da67501
MCC		 378 printk(KERN_CONT "\n");
379 }
43dd07f7
RM		 380 return 0;
381}
382
5e66b878 383static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
43dd07f7 384{
be44eb28 385 int status;
ebc7de22 386 u8 adr = state->demod_address, mm1[4], mm2[2], len;
e076c92e
MCC		 387
388 if (state->single_master)
389 flags |= 0xC0;
390
43dd07f7
RM		 391 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
392 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
393 mm1[1] = ((reg >> 16) & 0xFF);
394 mm1[2] = ((reg >> 24) & 0xFF) | flags;
395 mm1[3] = ((reg >> 7) & 0xFF);
396 len = 4;
397 } else {
398 mm1[0] = ((reg << 1) & 0xFF);
399 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
400 len = 2;
401 }
2da67501 402 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
2a5f6720 403 status = i2c_read(state, adr, mm1, len, mm2, 2);
be44eb28
MCC		 404 if (status < 0)
405 return status;
43dd07f7
RM		 406 if (data)
407 *data = mm2[0] | (mm2[1] << 8);
2da67501 408
43dd07f7
RM		 409 return 0;
410}
411
5e66b878 412static int read16(struct drxk_state *state, u32 reg, u16 *data)
43dd07f7 413{
5e66b878 414 return read16_flags(state, reg, data, 0);
43dd07f7
RM		 415}
416
5e66b878 417static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
43dd07f7 418{
be44eb28 419 int status;
43dd07f7 420 u8 adr = state->demod_address, mm1[4], mm2[4], len;
e076c92e
MCC		 421
422 if (state->single_master)
423 flags |= 0xC0;
424
43dd07f7
RM		 425 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
426 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
427 mm1[1] = ((reg >> 16) & 0xFF);
428 mm1[2] = ((reg >> 24) & 0xFF) | flags;
429 mm1[3] = ((reg >> 7) & 0xFF);
430 len = 4;
431 } else {
432 mm1[0] = ((reg << 1) & 0xFF);
433 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
434 len = 2;
435 }
2da67501 436 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
2a5f6720 437 status = i2c_read(state, adr, mm1, len, mm2, 4);
be44eb28
MCC		 438 if (status < 0)
439 return status;
43dd07f7
RM		 440 if (data)
441 *data = mm2[0] | (mm2[1] << 8) |
ebc7de22 442 (mm2[2] << 16) | (mm2[3] << 24);
2da67501 443
43dd07f7
RM		 444 return 0;
445}
446
5e66b878
MCC		 447static int read32(struct drxk_state *state, u32 reg, u32 *data)
448{
449 return read32_flags(state, reg, data, 0);
450}
451
452static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
43dd07f7
RM		 453{
454 u8 adr = state->demod_address, mm[6], len;
e076c92e
MCC		 455
456 if (state->single_master)
457 flags |= 0xC0;
43dd07f7
RM		 458 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
459 mm[0] = (((reg << 1) & 0xFF) | 0x01);
460 mm[1] = ((reg >> 16) & 0xFF);
461 mm[2] = ((reg >> 24) & 0xFF) | flags;
462 mm[3] = ((reg >> 7) & 0xFF);
463 len = 4;
464 } else {
465 mm[0] = ((reg << 1) & 0xFF);
466 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
467 len = 2;
468 }
469 mm[len] = data & 0xff;
ebc7de22 470 mm[len + 1] = (data >> 8) & 0xff;
2da67501
MCC		 471
472 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
2a5f6720 473 return i2c_write(state, adr, mm, len + 2);
43dd07f7
RM		 474}
475
5e66b878 476static int write16(struct drxk_state *state, u32 reg, u16 data)
43dd07f7 477{
5e66b878 478 return write16_flags(state, reg, data, 0);
43dd07f7
RM		 479}
480
5e66b878 481static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
43dd07f7
RM		 482{
483 u8 adr = state->demod_address, mm[8], len;
e076c92e
MCC		 484
485 if (state->single_master)
486 flags |= 0xC0;
43dd07f7
RM		 487 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
488 mm[0] = (((reg << 1) & 0xFF) | 0x01);
489 mm[1] = ((reg >> 16) & 0xFF);
490 mm[2] = ((reg >> 24) & 0xFF) | flags;
491 mm[3] = ((reg >> 7) & 0xFF);
492 len = 4;
493 } else {
494 mm[0] = ((reg << 1) & 0xFF);
495 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
496 len = 2;
497 }
498 mm[len] = data & 0xff;
ebc7de22
OE		 499 mm[len + 1] = (data >> 8) & 0xff;
500 mm[len + 2] = (data >> 16) & 0xff;
501 mm[len + 3] = (data >> 24) & 0xff;
2da67501 502 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
be44eb28 503
2a5f6720 504 return i2c_write(state, adr, mm, len + 4);
43dd07f7
RM		 505}
506
5e66b878
MCC		 507static int write32(struct drxk_state *state, u32 reg, u32 data)
508{
509 return write32_flags(state, reg, data, 0);
510}
511
512static int write_block(struct drxk_state *state, u32 Address,
513 const int BlockSize, const u8 pBlock[])
43dd07f7
RM		 514{
515 int status = 0, BlkSize = BlockSize;
5e66b878 516 u8 Flags = 0;
e076c92e
MCC		 517
518 if (state->single_master)
519 Flags |= 0xC0;
520
ebc7de22 521 while (BlkSize > 0) {
43dd07f7 522 int Chunk = BlkSize > state->m_ChunkSize ?
ebc7de22 523 state->m_ChunkSize : BlkSize;
43dd07f7
RM		 524 u8 *AdrBuf = &state->Chunk[0];
525 u32 AdrLength = 0;
526
ebc7de22
OE		 527 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
528 AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
529 AdrBuf[1] = ((Address >> 16) & 0xFF);
530 AdrBuf[2] = ((Address >> 24) & 0xFF);
531 AdrBuf[3] = ((Address >> 7) & 0xFF);
43dd07f7
RM		 532 AdrBuf[2] |= Flags;
533 AdrLength = 4;
534 if (Chunk == state->m_ChunkSize)
535 Chunk -= 2;
ebc7de22 536 } else {
43dd07f7
RM		 537 AdrBuf[0] = ((Address << 1) & 0xFF);
538 AdrBuf[1] = (((Address >> 16) & 0x0F) |
539 ((Address >> 18) & 0xF0));
540 AdrLength = 2;
541 }
542 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
2da67501
MCC		 543 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
544 if (debug > 1) {
545 int i;
546 if (pBlock)
547 for (i = 0; i < Chunk; i++)
548 printk(KERN_CONT " %02x", pBlock[i]);
549 printk(KERN_CONT "\n");
550 }
2a5f6720 551 status = i2c_write(state, state->demod_address,
ebc7de22
OE		 552 &state->Chunk[0], Chunk + AdrLength);
553 if (status < 0) {
e0e6ecaf
MCC		 554 printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
555 __func__, Address);
43dd07f7
RM		 556 break;
557 }
558 pBlock += Chunk;
559 Address += (Chunk >> 1);
560 BlkSize -= Chunk;
561 }
ebc7de22 562 return status;
43dd07f7
RM		 563}
564
565#ifndef DRXK_MAX_RETRIES_POWERUP
566#define DRXK_MAX_RETRIES_POWERUP 20
567#endif
568
569int PowerUpDevice(struct drxk_state *state)
570{
571 int status;
572 u8 data = 0;
573 u16 retryCount = 0;
574
2da67501
MCC		 575 dprintk(1, "\n");
576
2a5f6720 577 status = i2c_read1(state, state->demod_address, &data);
be44eb28 578 if (status < 0) {
43dd07f7
RM		 579 do {
580 data = 0;
2a5f6720 581 status = i2c_write(state, state->demod_address,
be44eb28 582 &data, 1);
43dd07f7 583 msleep(10);
ebc7de22 584 retryCount++;
be44eb28
MCC		 585 if (status < 0)
586 continue;
2a5f6720 587 status = i2c_read1(state, state->demod_address,
be44eb28
MCC		 588 &data);
589 } while (status < 0 &&
43dd07f7 590 (retryCount < DRXK_MAX_RETRIES_POWERUP));
be44eb28
MCC		 591 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
592 goto error;
593 }
594
595 /* Make sure all clk domains are active */
596 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
597 if (status < 0)
598 goto error;
599 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
600 if (status < 0)
601 goto error;
602 /* Enable pll lock tests */
603 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
604 if (status < 0)
605 goto error;
606
607 state->m_currentPowerMode = DRX_POWER_UP;
608
609error:
610 if (status < 0)
611 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
612
43dd07f7
RM		 613 return status;
614}
615
616
617static int init_state(struct drxk_state *state)
618{
147e110b
MCC		 619 /*
620 * FIXME: most (all?) of the values bellow should be moved into
621 * struct drxk_config, as they are probably board-specific
622 */
ebc7de22
OE		 623 u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
624 u32 ulVSBIfAgcOutputLevel = 0;
625 u32 ulVSBIfAgcMinLevel = 0;
626 u32 ulVSBIfAgcMaxLevel = 0x7FFF;
627 u32 ulVSBIfAgcSpeed = 3;
628
629 u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
630 u32 ulVSBRfAgcOutputLevel = 0;
631 u32 ulVSBRfAgcMinLevel = 0;
632 u32 ulVSBRfAgcMaxLevel = 0x7FFF;
633 u32 ulVSBRfAgcSpeed = 3;
634 u32 ulVSBRfAgcTop = 9500;
635 u32 ulVSBRfAgcCutOffCurrent = 4000;
636
637 u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
638 u32 ulATVIfAgcOutputLevel = 0;
639 u32 ulATVIfAgcMinLevel = 0;
640 u32 ulATVIfAgcMaxLevel = 0;
641 u32 ulATVIfAgcSpeed = 3;
642
643 u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
644 u32 ulATVRfAgcOutputLevel = 0;
645 u32 ulATVRfAgcMinLevel = 0;
646 u32 ulATVRfAgcMaxLevel = 0;
647 u32 ulATVRfAgcTop = 9500;
648 u32 ulATVRfAgcCutOffCurrent = 4000;
649 u32 ulATVRfAgcSpeed = 3;
43dd07f7
RM		 650
651 u32 ulQual83 = DEFAULT_MER_83;
652 u32 ulQual93 = DEFAULT_MER_93;
653
43dd07f7
RM		 654 u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
655 u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
656
657 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
658 /* io_pad_cfg_mode output mode is drive always */
659 /* io_pad_cfg_drive is set to power 2 (23 mA) */
660 u32 ulGPIOCfg = 0x0113;
43dd07f7
RM		 661 u32 ulInvertTSClock = 0;
662 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
43dd07f7
RM		 663 u32 ulDVBTBitrate = 50000000;
664 u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
665
666 u32 ulInsertRSByte = 0;
667
668 u32 ulRfMirror = 1;
669 u32 ulPowerDown = 0;
670
2da67501
MCC		 671 dprintk(1, "\n");
672
43dd07f7 673 state->m_hasLNA = false;
ebc7de22
OE		 674 state->m_hasDVBT = false;
675 state->m_hasDVBC = false;
676 state->m_hasATV = false;
43dd07f7
RM		 677 state->m_hasOOB = false;
678 state->m_hasAudio = false;
679
82e7dbbd 680 if (!state->m_ChunkSize)
de72405f 681 state->m_ChunkSize = 124;
43dd07f7
RM		 682
683 state->m_oscClockFreq = 0;
684 state->m_smartAntInverted = false;
685 state->m_bPDownOpenBridge = false;
686
687 /* real system clock frequency in kHz */
ebc7de22 688 state->m_sysClockFreq = 151875;
43dd07f7
RM		 689 /* Timing div, 250ns/Psys */
690 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
691 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
692 HI_I2C_DELAY) / 1000;
693 /* Clipping */
694 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
695 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
696 state->m_HICfgWakeUpKey = (state->demod_address << 1);
697 /* port/bridge/power down ctrl */
698 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
699
700 state->m_bPowerDown = (ulPowerDown != 0);
701
702 state->m_DRXK_A1_PATCH_CODE = false;
703 state->m_DRXK_A1_ROM_CODE = false;
704 state->m_DRXK_A2_ROM_CODE = false;
705 state->m_DRXK_A3_ROM_CODE = false;
706 state->m_DRXK_A2_PATCH_CODE = false;
707 state->m_DRXK_A3_PATCH_CODE = false;
708
709 /* Init AGC and PGA parameters */
710 /* VSB IF */
ebc7de22
OE		 711 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
712 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
713 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
714 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
715 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
43dd07f7
RM		 716 state->m_vsbPgaCfg = 140;
717
718 /* VSB RF */
ebc7de22
OE		 719 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
720 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
721 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
722 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
723 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
724 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
725 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
726 state->m_vsbPreSawCfg.reference = 0x07;
727 state->m_vsbPreSawCfg.usePreSaw = true;
43dd07f7
RM		 728
729 state->m_Quality83percent = DEFAULT_MER_83;
730 state->m_Quality93percent = DEFAULT_MER_93;
731 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
732 state->m_Quality83percent = ulQual83;
733 state->m_Quality93percent = ulQual93;
734 }
735
736 /* ATV IF */
ebc7de22
OE		 737 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
738 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
739 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
740 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
741 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
43dd07f7
RM		 742
743 /* ATV RF */
ebc7de22
OE		 744 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
745 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
746 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
747 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
748 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
749 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
750 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
751 state->m_atvPreSawCfg.reference = 0x04;
752 state->m_atvPreSawCfg.usePreSaw = true;
43dd07f7
RM		 753
754
755 /* DVBT RF */
ebc7de22
OE		 756 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
757 state->m_dvbtRfAgcCfg.outputLevel = 0;
758 state->m_dvbtRfAgcCfg.minOutputLevel = 0;
759 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
760 state->m_dvbtRfAgcCfg.top = 0x2100;
761 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
762 state->m_dvbtRfAgcCfg.speed = 1;
43dd07f7
RM		 763
764
765 /* DVBT IF */
ebc7de22
OE		 766 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
767 state->m_dvbtIfAgcCfg.outputLevel = 0;
768 state->m_dvbtIfAgcCfg.minOutputLevel = 0;
769 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
770 state->m_dvbtIfAgcCfg.top = 13424;
771 state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
772 state->m_dvbtIfAgcCfg.speed = 3;
43dd07f7 773 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
ebc7de22
OE		 774 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
775 /* state->m_dvbtPgaCfg = 140; */
43dd07f7 776
ebc7de22
OE		 777 state->m_dvbtPreSawCfg.reference = 4;
778 state->m_dvbtPreSawCfg.usePreSaw = false;
43dd07f7
RM		 779
780 /* QAM RF */
ebc7de22
OE		 781 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
782 state->m_qamRfAgcCfg.outputLevel = 0;
783 state->m_qamRfAgcCfg.minOutputLevel = 6023;
784 state->m_qamRfAgcCfg.maxOutputLevel = 27000;
785 state->m_qamRfAgcCfg.top = 0x2380;
786 state->m_qamRfAgcCfg.cutOffCurrent = 4000;
787 state->m_qamRfAgcCfg.speed = 3;
43dd07f7
RM		 788
789 /* QAM IF */
ebc7de22
OE		 790 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
791 state->m_qamIfAgcCfg.outputLevel = 0;
792 state->m_qamIfAgcCfg.minOutputLevel = 0;
793 state->m_qamIfAgcCfg.maxOutputLevel = 9000;
794 state->m_qamIfAgcCfg.top = 0x0511;
795 state->m_qamIfAgcCfg.cutOffCurrent = 0;
796 state->m_qamIfAgcCfg.speed = 3;
797 state->m_qamIfAgcCfg.IngainTgtMax = 5119;
43dd07f7
RM		 798 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
799
ebc7de22
OE		 800 state->m_qamPgaCfg = 140;
801 state->m_qamPreSawCfg.reference = 4;
802 state->m_qamPreSawCfg.usePreSaw = false;
43dd07f7
RM		 803
804 state->m_OperationMode = OM_NONE;
805 state->m_DrxkState = DRXK_UNINITIALIZED;
806
807 /* MPEG output configuration */
ebc7de22
OE		 808 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
809 state->m_insertRSByte = false; /* If TRUE; insert RS byte */
ebc7de22
OE		 810 state->m_invertDATA = false; /* If TRUE; invert DATA signals */
811 state->m_invertERR = false; /* If TRUE; invert ERR signal */
812 state->m_invertSTR = false; /* If TRUE; invert STR signals */
813 state->m_invertVAL = false; /* If TRUE; invert VAL signals */
814 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
67f04617 815
43dd07f7
RM		 816 /* If TRUE; static MPEG clockrate will be used;
817 otherwise clockrate will adapt to the bitrate of the TS */
818
819 state->m_DVBTBitrate = ulDVBTBitrate;
820 state->m_DVBCBitrate = ulDVBCBitrate;
821
822 state->m_TSDataStrength = (ulTSDataStrength & 0x07);
43dd07f7
RM		 823
824 /* Maximum bitrate in b/s in case static clockrate is selected */
825 state->m_mpegTsStaticBitrate = 19392658;
826 state->m_disableTEIhandling = false;
827
828 if (ulInsertRSByte)
829 state->m_insertRSByte = true;
830
831 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
832 if (ulMpegLockTimeOut < 10000)
833 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
834 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
835 if (ulDemodLockTimeOut < 10000)
836 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
837
ebc7de22
OE		 838 /* QAM defaults */
839 state->m_Constellation = DRX_CONSTELLATION_AUTO;
43dd07f7 840 state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
ebc7de22
OE		 841 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
842 state->m_fecRsPrescale = 1;
43dd07f7
RM		 843
844 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
845 state->m_agcFastClipCtrlDelay = 0;
846
847 state->m_GPIOCfg = (ulGPIOCfg);
43dd07f7 848
43dd07f7
RM		 849 state->m_bPowerDown = false;
850 state->m_currentPowerMode = DRX_POWER_DOWN;
851
43dd07f7
RM		 852 state->m_rfmirror = (ulRfMirror == 0);
853 state->m_IfAgcPol = false;
854 return 0;
855}
856
857static int DRXX_Open(struct drxk_state *state)
858{
859 int status = 0;
860 u32 jtag = 0;
861 u16 bid = 0;
862 u16 key = 0;
863
2da67501 864 dprintk(1, "\n");
be44eb28
MCC		 865 /* stop lock indicator process */
866 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
867 if (status < 0)
868 goto error;
869 /* Check device id */
870 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
871 if (status < 0)
872 goto error;
873 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
874 if (status < 0)
875 goto error;
876 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
877 if (status < 0)
878 goto error;
879 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
880 if (status < 0)
881 goto error;
882 status = write16(state, SIO_TOP_COMM_KEY__A, key);
883error:
884 if (status < 0)
885 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 886 return status;
887}
888
889static int GetDeviceCapabilities(struct drxk_state *state)
890{
ebc7de22 891 u16 sioPdrOhwCfg = 0;
43dd07f7
RM		 892 u32 sioTopJtagidLo = 0;
893 int status;
9c6e1828 894 const char *spin = "";
43dd07f7 895
2da67501 896 dprintk(1, "\n");
43dd07f7 897
be44eb28
MCC		 898 /* driver 0.9.0 */
899 /* stop lock indicator process */
900 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
901 if (status < 0)
902 goto error;
903 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
904 if (status < 0)
905 goto error;
906 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
907 if (status < 0)
908 goto error;
909 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
910 if (status < 0)
911 goto error;
43dd07f7 912
be44eb28
MCC		 913 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
914 case 0:
915 /* ignore (bypass ?) */
916 break;
917 case 1:
918 /* 27 MHz */
919 state->m_oscClockFreq = 27000;
920 break;
921 case 2:
922 /* 20.25 MHz */
923 state->m_oscClockFreq = 20250;
924 break;
925 case 3:
926 /* 4 MHz */
927 state->m_oscClockFreq = 20250;
928 break;
929 default:
930 printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n");
931 return -EINVAL;
932 }
933 /*
934 Determine device capabilities
935 Based on pinning v14
936 */
937 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
938 if (status < 0)
939 goto error;
0d3e6fe7
MCC		 940
941printk(KERN_ERR "drxk: status = 0x%08x\n", sioTopJtagidLo);
942
be44eb28
MCC		 943 /* driver 0.9.0 */
944 switch ((sioTopJtagidLo >> 29) & 0xF) {
945 case 0:
946 state->m_deviceSpin = DRXK_SPIN_A1;
9c6e1828 947 spin = "A1";
be44eb28
MCC		 948 break;
949 case 2:
950 state->m_deviceSpin = DRXK_SPIN_A2;
9c6e1828 951 spin = "A2";
be44eb28
MCC		 952 break;
953 case 3:
954 state->m_deviceSpin = DRXK_SPIN_A3;
9c6e1828 955 spin = "A3";
be44eb28
MCC		 956 break;
957 default:
958 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
959 status = -EINVAL;
0d3e6fe7
MCC		 960 printk(KERN_ERR "drxk: Spin %d unknown\n",
961 (sioTopJtagidLo >> 29) & 0xF);
be44eb28
MCC		 962 goto error2;
963 }
964 switch ((sioTopJtagidLo >> 12) & 0xFF) {
965 case 0x13:
966 /* typeId = DRX3913K_TYPE_ID */
967 state->m_hasLNA = false;
968 state->m_hasOOB = false;
969 state->m_hasATV = false;
970 state->m_hasAudio = false;
971 state->m_hasDVBT = true;
972 state->m_hasDVBC = true;
973 state->m_hasSAWSW = true;
974 state->m_hasGPIO2 = false;
975 state->m_hasGPIO1 = false;
976 state->m_hasIRQN = false;
977 break;
978 case 0x15:
979 /* typeId = DRX3915K_TYPE_ID */
980 state->m_hasLNA = false;
981 state->m_hasOOB = false;
982 state->m_hasATV = true;
983 state->m_hasAudio = false;
984 state->m_hasDVBT = true;
985 state->m_hasDVBC = false;
986 state->m_hasSAWSW = true;
987 state->m_hasGPIO2 = true;
988 state->m_hasGPIO1 = true;
989 state->m_hasIRQN = false;
990 break;
991 case 0x16:
992 /* typeId = DRX3916K_TYPE_ID */
993 state->m_hasLNA = false;
994 state->m_hasOOB = false;
995 state->m_hasATV = true;
996 state->m_hasAudio = false;
997 state->m_hasDVBT = true;
998 state->m_hasDVBC = false;
999 state->m_hasSAWSW = true;
1000 state->m_hasGPIO2 = true;
1001 state->m_hasGPIO1 = true;
1002 state->m_hasIRQN = false;
1003 break;
1004 case 0x18:
1005 /* typeId = DRX3918K_TYPE_ID */
1006 state->m_hasLNA = false;
1007 state->m_hasOOB = false;
1008 state->m_hasATV = true;
1009 state->m_hasAudio = true;
1010 state->m_hasDVBT = true;
1011 state->m_hasDVBC = false;
1012 state->m_hasSAWSW = true;
1013 state->m_hasGPIO2 = true;
1014 state->m_hasGPIO1 = true;
1015 state->m_hasIRQN = false;
1016 break;
1017 case 0x21:
1018 /* typeId = DRX3921K_TYPE_ID */
1019 state->m_hasLNA = false;
1020 state->m_hasOOB = false;
1021 state->m_hasATV = true;
1022 state->m_hasAudio = true;
1023 state->m_hasDVBT = true;
1024 state->m_hasDVBC = true;
1025 state->m_hasSAWSW = true;
1026 state->m_hasGPIO2 = true;
1027 state->m_hasGPIO1 = true;
1028 state->m_hasIRQN = false;
1029 break;
1030 case 0x23:
1031 /* typeId = DRX3923K_TYPE_ID */
1032 state->m_hasLNA = false;
1033 state->m_hasOOB = false;
1034 state->m_hasATV = true;
1035 state->m_hasAudio = true;
1036 state->m_hasDVBT = true;
1037 state->m_hasDVBC = true;
1038 state->m_hasSAWSW = true;
1039 state->m_hasGPIO2 = true;
1040 state->m_hasGPIO1 = true;
1041 state->m_hasIRQN = false;
1042 break;
1043 case 0x25:
1044 /* typeId = DRX3925K_TYPE_ID */
1045 state->m_hasLNA = false;
1046 state->m_hasOOB = false;
1047 state->m_hasATV = true;
1048 state->m_hasAudio = true;
1049 state->m_hasDVBT = true;
1050 state->m_hasDVBC = true;
1051 state->m_hasSAWSW = true;
1052 state->m_hasGPIO2 = true;
1053 state->m_hasGPIO1 = true;
1054 state->m_hasIRQN = false;
1055 break;
1056 case 0x26:
1057 /* typeId = DRX3926K_TYPE_ID */
1058 state->m_hasLNA = false;
1059 state->m_hasOOB = false;
1060 state->m_hasATV = true;
1061 state->m_hasAudio = false;
1062 state->m_hasDVBT = true;
1063 state->m_hasDVBC = true;
1064 state->m_hasSAWSW = true;
1065 state->m_hasGPIO2 = true;
1066 state->m_hasGPIO1 = true;
1067 state->m_hasIRQN = false;
1068 break;
1069 default:
f07a0bc1 1070 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
be44eb28
MCC		 1071 ((sioTopJtagidLo >> 12) & 0xFF));
1072 status = -EINVAL;
1073 goto error2;
1074 }
1075
9c6e1828
MCC		 1076 printk(KERN_INFO
1077 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1078 ((sioTopJtagidLo >> 12) & 0xFF), spin,
1079 state->m_oscClockFreq / 1000,
1080 state->m_oscClockFreq % 1000);
1081
be44eb28
MCC		 1082error:
1083 if (status < 0)
1084 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1085
1086error2:
43dd07f7
RM		 1087 return status;
1088}
1089
1090static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1091{
1092 int status;
1093 bool powerdown_cmd;
1094
2da67501
MCC		 1095 dprintk(1, "\n");
1096
43dd07f7 1097 /* Write command */
5e66b878 1098 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
43dd07f7 1099 if (status < 0)
be44eb28 1100 goto error;
43dd07f7
RM		 1101 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1102 msleep(1);
1103
1104 powerdown_cmd =
ebc7de22
OE		 1105 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1106 ((state->m_HICfgCtrl) &
1107 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1108 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
43dd07f7
RM		 1109 if (powerdown_cmd == false) {
1110 /* Wait until command rdy */
1111 u32 retryCount = 0;
1112 u16 waitCmd;
1113
1114 do {
1115 msleep(1);
1116 retryCount += 1;
5e66b878
MCC		 1117 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1118 &waitCmd);
ebc7de22
OE		 1119 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1120 && (waitCmd != 0));
be44eb28
MCC		 1121 if (status < 0)
1122 goto error;
1123 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
43dd07f7 1124 }
be44eb28
MCC		 1125error:
1126 if (status < 0)
1127 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1128
43dd07f7
RM		 1129 return status;
1130}
1131
1132static int HI_CfgCommand(struct drxk_state *state)
1133{
1134 int status;
1135
2da67501
MCC		 1136 dprintk(1, "\n");
1137
43dd07f7 1138 mutex_lock(&state->mutex);
43dd07f7 1139
be44eb28
MCC		 1140 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1141 if (status < 0)
1142 goto error;
1143 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1144 if (status < 0)
1145 goto error;
1146 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1147 if (status < 0)
1148 goto error;
1149 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1150 if (status < 0)
1151 goto error;
1152 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1153 if (status < 0)
1154 goto error;
1155 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1156 if (status < 0)
1157 goto error;
1158 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1159 if (status < 0)
1160 goto error;
1161
1162 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1163error:
43dd07f7 1164 mutex_unlock(&state->mutex);
be44eb28
MCC		 1165 if (status < 0)
1166 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1167 return status;
1168}
1169
1170static int InitHI(struct drxk_state *state)
1171{
2da67501
MCC		 1172 dprintk(1, "\n");
1173
ebc7de22 1174 state->m_HICfgWakeUpKey = (state->demod_address << 1);
43dd07f7
RM		 1175 state->m_HICfgTimeout = 0x96FF;
1176 /* port/bridge/power down ctrl */
1177 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
be44eb28 1178
ebc7de22 1179 return HI_CfgCommand(state);
43dd07f7
RM		 1180}
1181
1182static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1183{
1184 int status = -1;
ebc7de22
OE		 1185 u16 sioPdrMclkCfg = 0;
1186 u16 sioPdrMdxCfg = 0;
d5856813 1187 u16 err_cfg = 0;
43dd07f7 1188
534e0481
MCC		 1189 dprintk(1, ": mpeg %s, %s mode\n",
1190 mpegEnable ? "enable" : "disable",
1191 state->m_enableParallel ? "parallel" : "serial");
43dd07f7 1192
be44eb28
MCC		 1193 /* stop lock indicator process */
1194 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1195 if (status < 0)
1196 goto error;
1197
1198 /* MPEG TS pad configuration */
1199 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1200 if (status < 0)
1201 goto error;
1202
1203 if (mpegEnable == false) {
1204 /* Set MPEG TS pads to inputmode */
1205 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
ea90f011 1206 if (status < 0)
be44eb28
MCC		 1207 goto error;
1208 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1209 if (status < 0)
1210 goto error;
1211 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1212 if (status < 0)
1213 goto error;
1214 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1215 if (status < 0)
1216 goto error;
1217 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1218 if (status < 0)
1219 goto error;
1220 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1221 if (status < 0)
1222 goto error;
1223 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1224 if (status < 0)
1225 goto error;
1226 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1227 if (status < 0)
1228 goto error;
1229 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1230 if (status < 0)
1231 goto error;
1232 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1233 if (status < 0)
1234 goto error;
1235 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1236 if (status < 0)
1237 goto error;
1238 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1239 if (status < 0)
1240 goto error;
1241 } else {
1242 /* Enable MPEG output */
1243 sioPdrMdxCfg =
1244 ((state->m_TSDataStrength <<
1245 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1246 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1247 SIO_PDR_MCLK_CFG_DRIVE__B) |
1248 0x0003);
43dd07f7 1249
be44eb28
MCC		 1250 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1251 if (status < 0)
1252 goto error;
d5856813
MCC		 1253
1254 if (state->enable_merr_cfg)
1255 err_cfg = sioPdrMdxCfg;
1256
1257 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
be44eb28
MCC		 1258 if (status < 0)
1259 goto error;
d5856813 1260 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
be44eb28
MCC		 1261 if (status < 0)
1262 goto error;
d5856813 1263
be44eb28
MCC		 1264 if (state->m_enableParallel == true) {
1265 /* paralel -> enable MD1 to MD7 */
1266 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
ea90f011 1267 if (status < 0)
be44eb28
MCC		 1268 goto error;
1269 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
ea90f011 1270 if (status < 0)
be44eb28
MCC		 1271 goto error;
1272 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
ea90f011 1273 if (status < 0)
be44eb28
MCC		 1274 goto error;
1275 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
ea90f011 1276 if (status < 0)
be44eb28
MCC		 1277 goto error;
1278 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
ea90f011 1279 if (status < 0)
be44eb28
MCC		 1280 goto error;
1281 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1282 if (status < 0)
1283 goto error;
1284 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1285 if (status < 0)
1286 goto error;
1287 } else {
1288 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1289 SIO_PDR_MD0_CFG_DRIVE__B)
1290 | 0x0003);
1291 /* serial -> disable MD1 to MD7 */
5e66b878 1292 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
ea90f011 1293 if (status < 0)
be44eb28 1294 goto error;
5e66b878 1295 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
ea90f011 1296 if (status < 0)
be44eb28 1297 goto error;
5e66b878 1298 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
ea90f011 1299 if (status < 0)
be44eb28 1300 goto error;
5e66b878 1301 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
ea90f011 1302 if (status < 0)
be44eb28 1303 goto error;
5e66b878 1304 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
ea90f011 1305 if (status < 0)
be44eb28 1306 goto error;
5e66b878 1307 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
ea90f011 1308 if (status < 0)
be44eb28 1309 goto error;
5e66b878 1310 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
ea90f011 1311 if (status < 0)
be44eb28 1312 goto error;
43dd07f7 1313 }
be44eb28 1314 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
ea90f011 1315 if (status < 0)
be44eb28
MCC		 1316 goto error;
1317 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
ea90f011 1318 if (status < 0)
be44eb28
MCC		 1319 goto error;
1320 }
1321 /* Enable MB output over MPEG pads and ctl input */
1322 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1323 if (status < 0)
1324 goto error;
1325 /* Write nomagic word to enable pdr reg write */
1326 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1327error:
1328 if (status < 0)
1329 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1330 return status;
1331}
1332
1333static int MPEGTSDisable(struct drxk_state *state)
1334{
2da67501
MCC		 1335 dprintk(1, "\n");
1336
43dd07f7
RM		 1337 return MPEGTSConfigurePins(state, false);
1338}
1339
1340static int BLChainCmd(struct drxk_state *state,
1341 u16 romOffset, u16 nrOfElements, u32 timeOut)
1342{
1343 u16 blStatus = 0;
1344 int status;
1345 unsigned long end;
1346
2da67501 1347 dprintk(1, "\n");
43dd07f7 1348 mutex_lock(&state->mutex);
be44eb28
MCC		 1349 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1350 if (status < 0)
1351 goto error;
1352 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1353 if (status < 0)
1354 goto error;
1355 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1356 if (status < 0)
1357 goto error;
1358 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1359 if (status < 0)
1360 goto error;
1361
1362 end = jiffies + msecs_to_jiffies(timeOut);
43dd07f7 1363 do {
be44eb28
MCC		 1364 msleep(1);
1365 status = read16(state, SIO_BL_STATUS__A, &blStatus);
ea90f011 1366 if (status < 0)
be44eb28
MCC		 1367 goto error;
1368 } while ((blStatus == 0x1) &&
1369 ((time_is_after_jiffies(end))));
43dd07f7 1370
be44eb28
MCC		 1371 if (blStatus == 0x1) {
1372 printk(KERN_ERR "drxk: SIO not ready\n");
1373 status = -EINVAL;
1374 goto error2;
1375 }
1376error:
1377 if (status < 0)
1378 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1379error2:
43dd07f7
RM		 1380 mutex_unlock(&state->mutex);
1381 return status;
1382}
1383
1384
1385static int DownloadMicrocode(struct drxk_state *state,
ebc7de22 1386 const u8 pMCImage[], u32 Length)
43dd07f7
RM		 1387{
1388 const u8 *pSrc = pMCImage;
43dd07f7
RM		 1389 u32 Address;
1390 u16 nBlocks;
1391 u16 BlockSize;
43dd07f7
RM		 1392 u32 offset = 0;
1393 u32 i;
1bd09ddc 1394 int status = 0;
43dd07f7 1395
2da67501
MCC		 1396 dprintk(1, "\n");
1397
5becbc58
HV		 1398 /* down the drain (we don't care about MAGIC_WORD) */
1399#if 0
1400 /* For future reference */
43dd07f7 1401 Drain = (pSrc[0] << 8) | pSrc[1];
5becbc58 1402#endif
ebc7de22
OE		 1403 pSrc += sizeof(u16);
1404 offset += sizeof(u16);
43dd07f7 1405 nBlocks = (pSrc[0] << 8) | pSrc[1];
ebc7de22
OE		 1406 pSrc += sizeof(u16);
1407 offset += sizeof(u16);
43dd07f7
RM		 1408
1409 for (i = 0; i < nBlocks; i += 1) {
1410 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
ebc7de22
OE		 1411 (pSrc[2] << 8) | pSrc[3];
1412 pSrc += sizeof(u32);
1413 offset += sizeof(u32);
43dd07f7
RM		 1414
1415 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
ebc7de22
OE		 1416 pSrc += sizeof(u16);
1417 offset += sizeof(u16);
43dd07f7 1418
5becbc58
HV		 1419#if 0
1420 /* For future reference */
43dd07f7 1421 Flags = (pSrc[0] << 8) | pSrc[1];
5becbc58 1422#endif
ebc7de22
OE		 1423 pSrc += sizeof(u16);
1424 offset += sizeof(u16);
43dd07f7 1425
5becbc58
HV		 1426#if 0
1427 /* For future reference */
43dd07f7 1428 BlockCRC = (pSrc[0] << 8) | pSrc[1];
5becbc58 1429#endif
ebc7de22
OE		 1430 pSrc += sizeof(u16);
1431 offset += sizeof(u16);
bcd2ebb7
MCC		 1432
1433 if (offset + BlockSize > Length) {
1434 printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1435 return -EINVAL;
1436 }
1437
5e66b878 1438 status = write_block(state, Address, BlockSize, pSrc);
39624f7e
MCC		 1439 if (status < 0) {
1440 printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
43dd07f7 1441 break;
39624f7e 1442 }
43dd07f7
RM		 1443 pSrc += BlockSize;
1444 offset += BlockSize;
1445 }
1446 return status;
1447}
1448
1449static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1450{
1451 int status;
ebc7de22
OE		 1452 u16 data = 0;
1453 u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
43dd07f7
RM		 1454 u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1455 unsigned long end;
1456
2da67501
MCC		 1457 dprintk(1, "\n");
1458
43dd07f7 1459 if (enable == false) {
ebc7de22 1460 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
43dd07f7
RM		 1461 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1462 }
1463
be44eb28
MCC		 1464 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1465 if (status >= 0 && data == desiredStatus) {
43dd07f7
RM		 1466 /* tokenring already has correct status */
1467 return status;
1468 }
1469 /* Disable/enable dvbt tokenring bridge */
be44eb28 1470 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
43dd07f7 1471
ebc7de22 1472 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
ea90f011 1473 do {
5e66b878 1474 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
be44eb28 1475 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
ea90f011 1476 break;
be44eb28
MCC		 1477 msleep(1);
1478 } while (1);
43dd07f7 1479 if (data != desiredStatus) {
e0e6ecaf 1480 printk(KERN_ERR "drxk: SIO not ready\n");
be44eb28 1481 return -EINVAL;
43dd07f7
RM		 1482 }
1483 return status;
1484}
1485
1486static int MPEGTSStop(struct drxk_state *state)
1487{
1488 int status = 0;
1489 u16 fecOcSncMode = 0;
1490 u16 fecOcIprMode = 0;
1491
2da67501
MCC		 1492 dprintk(1, "\n");
1493
be44eb28
MCC		 1494 /* Gracefull shutdown (byte boundaries) */
1495 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1496 if (status < 0)
1497 goto error;
1498 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1499 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1500 if (status < 0)
1501 goto error;
1502
1503 /* Suppress MCLK during absence of data */
1504 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1505 if (status < 0)
1506 goto error;
1507 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1508 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1509
1510error:
1511 if (status < 0)
1512 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7 1513
43dd07f7
RM		 1514 return status;
1515}
1516
1517static int scu_command(struct drxk_state *state,
1518 u16 cmd, u8 parameterLen,
ebc7de22 1519 u16 *parameter, u8 resultLen, u16 *result)
43dd07f7
RM		 1520{
1521#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1522#error DRXK register mapping no longer compatible with this routine!
1523#endif
1524 u16 curCmd = 0;
be44eb28 1525 int status = -EINVAL;
43dd07f7 1526 unsigned long end;
be44eb28
MCC		 1527 u8 buffer[34];
1528 int cnt = 0, ii;
7558977a
MCC		 1529 const char *p;
1530 char errname[30];
43dd07f7 1531
2da67501
MCC		 1532 dprintk(1, "\n");
1533
43dd07f7 1534 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
e4459e16
AK		 1535 ((resultLen > 0) && (result == NULL))) {
1536 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1537 return status;
1538 }
43dd07f7
RM		 1539
1540 mutex_lock(&state->mutex);
be44eb28
MCC		 1541
1542 /* assume that the command register is ready
1543 since it is checked afterwards */
1544 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1545 buffer[cnt++] = (parameter[ii] & 0xFF);
1546 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1547 }
1548 buffer[cnt++] = (cmd & 0xFF);
1549 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1550
1551 write_block(state, SCU_RAM_PARAM_0__A -
1552 (parameterLen - 1), cnt, buffer);
1553 /* Wait until SCU has processed command */
1554 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
43dd07f7 1555 do {
be44eb28
MCC		 1556 msleep(1);
1557 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1558 if (status < 0)
1559 goto error;
1560 } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1561 if (curCmd != DRX_SCU_READY) {
1562 printk(KERN_ERR "drxk: SCU not ready\n");
1563 status = -EIO;
1564 goto error2;
1565 }
1566 /* read results */
1567 if ((resultLen > 0) && (result != NULL)) {
1568 s16 err;
1569 int ii;
43dd07f7 1570
be44eb28
MCC		 1571 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1572 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
ea90f011 1573 if (status < 0)
be44eb28 1574 goto error;
43dd07f7 1575 }
be44eb28
MCC		 1576
1577 /* Check if an error was reported by SCU */
1578 err = (s16)result[0];
7558977a
MCC		 1579 if (err >= 0)
1580 goto error;
be44eb28 1581
7558977a
MCC		 1582 /* check for the known error codes */
1583 switch (err) {
1584 case SCU_RESULT_UNKCMD:
1585 p = "SCU_RESULT_UNKCMD";
1586 break;
1587 case SCU_RESULT_UNKSTD:
1588 p = "SCU_RESULT_UNKSTD";
1589 break;
1590 case SCU_RESULT_SIZE:
1591 p = "SCU_RESULT_SIZE";
1592 break;
1593 case SCU_RESULT_INVPAR:
1594 p = "SCU_RESULT_INVPAR";
1595 break;
1596 default: /* Other negative values are errors */
1597 sprintf(errname, "ERROR: %d\n", err);
1598 p = errname;
43dd07f7 1599 }
7558977a
MCC		 1600 printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1601 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1602 status = -EINVAL;
1603 goto error2;
be44eb28
MCC		 1604 }
1605
1606error:
ebc7de22 1607 if (status < 0)
be44eb28 1608 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
be44eb28
MCC		 1609error2:
1610 mutex_unlock(&state->mutex);
43dd07f7
RM		 1611 return status;
1612}
1613
1614static int SetIqmAf(struct drxk_state *state, bool active)
1615{
1616 u16 data = 0;
1617 int status;
1618
2da67501
MCC		 1619 dprintk(1, "\n");
1620
be44eb28
MCC		 1621 /* Configure IQM */
1622 status = read16(state, IQM_AF_STDBY__A, &data);
1623 if (status < 0)
1624 goto error;
1625
1626 if (!active) {
1627 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1628 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1629 | IQM_AF_STDBY_STDBY_PD_STANDBY
1630 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1631 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1632 } else {
1633 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1634 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1635 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1636 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1637 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1638 );
1639 }
1640 status = write16(state, IQM_AF_STDBY__A, data);
1641
1642error:
1643 if (status < 0)
1644 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1645 return status;
1646}
1647
ebc7de22 1648static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
43dd07f7
RM		 1649{
1650 int status = 0;
ebc7de22 1651 u16 sioCcPwdMode = 0;
43dd07f7 1652
2da67501
MCC		 1653 dprintk(1, "\n");
1654
43dd07f7
RM		 1655 /* Check arguments */
1656 if (mode == NULL)
be44eb28 1657 return -EINVAL;
43dd07f7
RM		 1658
1659 switch (*mode) {
1660 case DRX_POWER_UP:
1661 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1662 break;
1663 case DRXK_POWER_DOWN_OFDM:
1664 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1665 break;
1666 case DRXK_POWER_DOWN_CORE:
1667 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1668 break;
1669 case DRXK_POWER_DOWN_PLL:
1670 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1671 break;
1672 case DRX_POWER_DOWN:
1673 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1674 break;
1675 default:
1676 /* Unknow sleep mode */
be44eb28 1677 return -EINVAL;
43dd07f7
RM		 1678 }
1679
1680 /* If already in requested power mode, do nothing */
1681 if (state->m_currentPowerMode == *mode)
1682 return 0;
1683
1684 /* For next steps make sure to start from DRX_POWER_UP mode */
ebc7de22 1685 if (state->m_currentPowerMode != DRX_POWER_UP) {
be44eb28
MCC		 1686 status = PowerUpDevice(state);
1687 if (status < 0)
1688 goto error;
1689 status = DVBTEnableOFDMTokenRing(state, true);
1690 if (status < 0)
1691 goto error;
43dd07f7
RM		 1692 }
1693
1694 if (*mode == DRX_POWER_UP) {
1695 /* Restore analog & pin configuartion */
1696 } else {
1697 /* Power down to requested mode */
1698 /* Backup some register settings */
1699 /* Set pins with possible pull-ups connected
1700 to them in input mode */
1701 /* Analog power down */
1702 /* ADC power down */
1703 /* Power down device */
1704 /* stop all comm_exec */
1705 /* Stop and power down previous standard */
be44eb28
MCC		 1706 switch (state->m_OperationMode) {
1707 case OM_DVBT:
1708 status = MPEGTSStop(state);
ea90f011 1709 if (status < 0)
be44eb28
MCC		 1710 goto error;
1711 status = PowerDownDVBT(state, false);
ea90f011 1712 if (status < 0)
be44eb28
MCC		 1713 goto error;
1714 break;
1715 case OM_QAM_ITU_A:
1716 case OM_QAM_ITU_C:
1717 status = MPEGTSStop(state);
ea90f011 1718 if (status < 0)
be44eb28
MCC		 1719 goto error;
1720 status = PowerDownQAM(state);
1721 if (status < 0)
1722 goto error;
1723 break;
1724 default:
1725 break;
1726 }
1727 status = DVBTEnableOFDMTokenRing(state, false);
1728 if (status < 0)
1729 goto error;
1730 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1731 if (status < 0)
1732 goto error;
1733 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1734 if (status < 0)
1735 goto error;
43dd07f7 1736
be44eb28
MCC		 1737 if (*mode != DRXK_POWER_DOWN_OFDM) {
1738 state->m_HICfgCtrl |=
1739 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1740 status = HI_CfgCommand(state);
1741 if (status < 0)
1742 goto error;
1743 }
43dd07f7
RM		 1744 }
1745 state->m_currentPowerMode = *mode;
be44eb28
MCC		 1746
1747error:
1748 if (status < 0)
1749 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1750
ebc7de22 1751 return status;
43dd07f7
RM		 1752}
1753
1754static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1755{
ebc7de22 1756 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
43dd07f7
RM		 1757 u16 cmdResult = 0;
1758 u16 data = 0;
1759 int status;
1760
2da67501
MCC		 1761 dprintk(1, "\n");
1762
be44eb28
MCC		 1763 status = read16(state, SCU_COMM_EXEC__A, &data);
1764 if (status < 0)
1765 goto error;
1766 if (data == SCU_COMM_EXEC_ACTIVE) {
1767 /* Send OFDM stop command */
1768 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
ea90f011 1769 if (status < 0)
be44eb28
MCC		 1770 goto error;
1771 /* Send OFDM reset command */
1772 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
ea90f011 1773 if (status < 0)
be44eb28
MCC		 1774 goto error;
1775 }
43dd07f7 1776
be44eb28
MCC		 1777 /* Reset datapath for OFDM, processors first */
1778 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1779 if (status < 0)
1780 goto error;
1781 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1782 if (status < 0)
1783 goto error;
1784 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1785 if (status < 0)
1786 goto error;
43dd07f7 1787
be44eb28
MCC		 1788 /* powerdown AFE */
1789 status = SetIqmAf(state, false);
1790 if (status < 0)
1791 goto error;
1792
1793 /* powerdown to OFDM mode */
1794 if (setPowerMode) {
1795 status = CtrlPowerMode(state, &powerMode);
1796 if (status < 0)
1797 goto error;
1798 }
1799error:
1800 if (status < 0)
1801 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1802 return status;
1803}
1804
ebc7de22
OE		 1805static int SetOperationMode(struct drxk_state *state,
1806 enum OperationMode oMode)
43dd07f7
RM		 1807{
1808 int status = 0;
1809
2da67501 1810 dprintk(1, "\n");
43dd07f7 1811 /*
ebc7de22
OE		 1812 Stop and power down previous standard
1813 TODO investigate total power down instead of partial
1814 power down depending on "previous" standard.
1815 */
43dd07f7 1816
be44eb28
MCC		 1817 /* disable HW lock indicator */
1818 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1819 if (status < 0)
1820 goto error;
43dd07f7 1821
f1b82970
MCC		 1822 /* Device is already at the required mode */
1823 if (state->m_OperationMode == oMode)
1824 return 0;
1825
1826 switch (state->m_OperationMode) {
1827 /* OM_NONE was added for start up */
1828 case OM_NONE:
1829 break;
1830 case OM_DVBT:
1831 status = MPEGTSStop(state);
1832 if (status < 0)
be44eb28 1833 goto error;
f1b82970
MCC		 1834 status = PowerDownDVBT(state, true);
1835 if (status < 0)
1836 goto error;
1837 state->m_OperationMode = OM_NONE;
1838 break;
1839 case OM_QAM_ITU_A: /* fallthrough */
1840 case OM_QAM_ITU_C:
1841 status = MPEGTSStop(state);
1842 if (status < 0)
1843 goto error;
1844 status = PowerDownQAM(state);
1845 if (status < 0)
1846 goto error;
1847 state->m_OperationMode = OM_NONE;
1848 break;
1849 case OM_QAM_ITU_B:
1850 default:
1851 status = -EINVAL;
1852 goto error;
1853 }
be44eb28 1854
f1b82970
MCC		 1855 /*
1856 Power up new standard
1857 */
1858 switch (oMode) {
1859 case OM_DVBT:
48763e2c 1860 dprintk(1, ": DVB-T\n");
f1b82970
MCC		 1861 state->m_OperationMode = oMode;
1862 status = SetDVBTStandard(state, oMode);
1863 if (status < 0)
1864 goto error;
1865 break;
1866 case OM_QAM_ITU_A: /* fallthrough */
1867 case OM_QAM_ITU_C:
48763e2c
MCC		 1868 dprintk(1, ": DVB-C Annex %c\n",
1869 (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C');
f1b82970
MCC		 1870 state->m_OperationMode = oMode;
1871 status = SetQAMStandard(state, oMode);
1872 if (status < 0)
1873 goto error;
1874 break;
1875 case OM_QAM_ITU_B:
1876 default:
1877 status = -EINVAL;
be44eb28
MCC		 1878 }
1879error:
1880 if (status < 0)
1881 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1882 return status;
43dd07f7
RM		 1883}
1884
1885static int Start(struct drxk_state *state, s32 offsetFreq,
1886 s32 IntermediateFrequency)
1887{
be44eb28
MCC		 1888 int status = -EINVAL;
1889
1890 u16 IFreqkHz;
1891 s32 OffsetkHz = offsetFreq / 1000;
43dd07f7 1892
2da67501 1893 dprintk(1, "\n");
be44eb28
MCC		 1894 if (state->m_DrxkState != DRXK_STOPPED &&
1895 state->m_DrxkState != DRXK_DTV_STARTED)
1896 goto error;
43dd07f7 1897
ed5452a2 1898 state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON);
43dd07f7 1899
be44eb28
MCC		 1900 if (IntermediateFrequency < 0) {
1901 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1902 IntermediateFrequency = -IntermediateFrequency;
1903 }
43dd07f7 1904
be44eb28
MCC		 1905 switch (state->m_OperationMode) {
1906 case OM_QAM_ITU_A:
1907 case OM_QAM_ITU_C:
1908 IFreqkHz = (IntermediateFrequency / 1000);
1909 status = SetQAM(state, IFreqkHz, OffsetkHz);
1910 if (status < 0)
1911 goto error;
1912 state->m_DrxkState = DRXK_DTV_STARTED;
1913 break;
1914 case OM_DVBT:
1915 IFreqkHz = (IntermediateFrequency / 1000);
1916 status = MPEGTSStop(state);
1917 if (status < 0)
1918 goto error;
1919 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1920 if (status < 0)
1921 goto error;
1922 status = DVBTStart(state);
1923 if (status < 0)
1924 goto error;
1925 state->m_DrxkState = DRXK_DTV_STARTED;
1926 break;
1927 default:
1928 break;
1929 }
1930error:
1931 if (status < 0)
1932 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1933 return status;
1934}
1935
1936static int ShutDown(struct drxk_state *state)
1937{
2da67501
MCC		 1938 dprintk(1, "\n");
1939
43dd07f7
RM		 1940 MPEGTSStop(state);
1941 return 0;
1942}
1943
ebc7de22
OE		 1944static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1945 u32 Time)
43dd07f7 1946{
be44eb28 1947 int status = -EINVAL;
43dd07f7 1948
2da67501
MCC		 1949 dprintk(1, "\n");
1950
43dd07f7 1951 if (pLockStatus == NULL)
be44eb28 1952 goto error;
43dd07f7
RM		 1953
1954 *pLockStatus = NOT_LOCKED;
1955
1956 /* define the SCU command code */
1957 switch (state->m_OperationMode) {
1958 case OM_QAM_ITU_A:
1959 case OM_QAM_ITU_B:
1960 case OM_QAM_ITU_C:
1961 status = GetQAMLockStatus(state, pLockStatus);
1962 break;
1963 case OM_DVBT:
1964 status = GetDVBTLockStatus(state, pLockStatus);
1965 break;
1966 default:
1967 break;
1968 }
be44eb28
MCC		 1969error:
1970 if (status < 0)
1971 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1972 return status;
1973}
1974
1975static int MPEGTSStart(struct drxk_state *state)
1976{
be44eb28 1977 int status;
43dd07f7
RM		 1978
1979 u16 fecOcSncMode = 0;
1980
be44eb28
MCC		 1981 /* Allow OC to sync again */
1982 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1983 if (status < 0)
1984 goto error;
1985 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1986 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1987 if (status < 0)
1988 goto error;
1989 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1990error:
1991 if (status < 0)
1992 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1993 return status;
1994}
1995
1996static int MPEGTSDtoInit(struct drxk_state *state)
1997{
be44eb28 1998 int status;
43dd07f7 1999
2da67501
MCC		 2000 dprintk(1, "\n");
2001
be44eb28
MCC		 2002 /* Rate integration settings */
2003 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
2004 if (status < 0)
2005 goto error;
2006 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
2007 if (status < 0)
2008 goto error;
2009 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
2010 if (status < 0)
2011 goto error;
2012 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
2013 if (status < 0)
2014 goto error;
2015 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
2016 if (status < 0)
2017 goto error;
2018 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
2019 if (status < 0)
2020 goto error;
2021 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
2022 if (status < 0)
2023 goto error;
2024 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
2025 if (status < 0)
2026 goto error;
2027
2028 /* Additional configuration */
2029 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
2030 if (status < 0)
2031 goto error;
2032 status = write16(state, FEC_OC_SNC_LWM__A, 2);
2033 if (status < 0)
2034 goto error;
2035 status = write16(state, FEC_OC_SNC_HWM__A, 12);
2036error:
2037 if (status < 0)
2038 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7 2039
43dd07f7
RM		 2040 return status;
2041}
2042
ebc7de22
OE		 2043static int MPEGTSDtoSetup(struct drxk_state *state,
2044 enum OperationMode oMode)
43dd07f7 2045{
be44eb28 2046 int status;
43dd07f7 2047
ebc7de22
OE		 2048 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
2049 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
2050 u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
2051 u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
2052 u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
2053 u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
2054 u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
43dd07f7
RM		 2055 u16 fecOcTmdMode = 0;
2056 u16 fecOcTmdIntUpdRate = 0;
ebc7de22 2057 u32 maxBitRate = 0;
43dd07f7
RM		 2058 bool staticCLK = false;
2059
2da67501
MCC		 2060 dprintk(1, "\n");
2061
be44eb28
MCC		 2062 /* Check insertion of the Reed-Solomon parity bytes */
2063 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2064 if (status < 0)
2065 goto error;
2066 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2067 if (status < 0)
2068 goto error;
2069 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2070 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2071 if (state->m_insertRSByte == true) {
2072 /* enable parity symbol forward */
2073 fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2074 /* MVAL disable during parity bytes */
2075 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2076 /* TS burst length to 204 */
2077 fecOcDtoBurstLen = 204;
2078 }
43dd07f7 2079
be44eb28
MCC		 2080 /* Check serial or parrallel output */
2081 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2082 if (state->m_enableParallel == false) {
2083 /* MPEG data output is serial -> set ipr_mode[0] */
2084 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2085 }
43dd07f7 2086
be44eb28
MCC		 2087 switch (oMode) {
2088 case OM_DVBT:
2089 maxBitRate = state->m_DVBTBitrate;
2090 fecOcTmdMode = 3;
2091 fecOcRcnCtlRate = 0xC00000;
2092 staticCLK = state->m_DVBTStaticCLK;
2093 break;
2094 case OM_QAM_ITU_A: /* fallthrough */
2095 case OM_QAM_ITU_C:
2096 fecOcTmdMode = 0x0004;
2097 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
2098 maxBitRate = state->m_DVBCBitrate;
2099 staticCLK = state->m_DVBCStaticCLK;
2100 break;
2101 default:
2102 status = -EINVAL;
2103 } /* switch (standard) */
2104 if (status < 0)
2105 goto error;
2106
2107 /* Configure DTO's */
2108 if (staticCLK) {
2109 u32 bitRate = 0;
2110
2111 /* Rational DTO for MCLK source (static MCLK rate),
2112 Dynamic DTO for optimal grouping
2113 (avoid intra-packet gaps),
2114 DTO offset enable to sync TS burst with MSTRT */
2115 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2116 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2117 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2118 FEC_OC_FCT_MODE_VIRT_ENA__M);
2119
2120 /* Check user defined bitrate */
2121 bitRate = maxBitRate;
2122 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
2123 bitRate = 75900000UL;
43dd07f7 2124 }
be44eb28
MCC		 2125 /* Rational DTO period:
2126 dto_period = (Fsys / bitrate) - 2
2127
2128 Result should be floored,
2129 to make sure >= requested bitrate
2130 */
2131 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2132 * 1000) / bitRate);
2133 if (fecOcDtoPeriod <= 2)
2134 fecOcDtoPeriod = 0;
2135 else
2136 fecOcDtoPeriod -= 2;
2137 fecOcTmdIntUpdRate = 8;
2138 } else {
2139 /* (commonAttr->staticCLK == false) => dynamic mode */
2140 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2141 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2142 fecOcTmdIntUpdRate = 5;
2143 }
43dd07f7 2144
be44eb28
MCC		 2145 /* Write appropriate registers with requested configuration */
2146 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2147 if (status < 0)
2148 goto error;
2149 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2150 if (status < 0)
2151 goto error;
2152 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2153 if (status < 0)
2154 goto error;
2155 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2156 if (status < 0)
2157 goto error;
2158 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2159 if (status < 0)
2160 goto error;
2161 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2162 if (status < 0)
2163 goto error;
43dd07f7 2164
be44eb28
MCC		 2165 /* Rate integration settings */
2166 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2167 if (status < 0)
2168 goto error;
2169 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2170 if (status < 0)
2171 goto error;
2172 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2173error:
2174 if (status < 0)
2175 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2176 return status;
2177}
2178
2179static int MPEGTSConfigurePolarity(struct drxk_state *state)
2180{
ebc7de22 2181 u16 fecOcRegIprInvert = 0;
43dd07f7
RM		 2182
2183 /* Data mask for the output data byte */
2184 u16 InvertDataMask =
ebc7de22
OE		 2185 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2186 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2187 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2188 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
43dd07f7 2189
be44eb28
MCC		 2190 dprintk(1, "\n");
2191
43dd07f7
RM		 2192 /* Control selective inversion of output bits */
2193 fecOcRegIprInvert &= (~(InvertDataMask));
2194 if (state->m_invertDATA == true)
2195 fecOcRegIprInvert |= InvertDataMask;
2196 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2197 if (state->m_invertERR == true)
2198 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2199 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2200 if (state->m_invertSTR == true)
2201 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2202 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2203 if (state->m_invertVAL == true)
2204 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2205 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2206 if (state->m_invertCLK == true)
2207 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
be44eb28
MCC		 2208
2209 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
43dd07f7
RM		 2210}
2211
2212#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2213
2214static int SetAgcRf(struct drxk_state *state,
2215 struct SCfgAgc *pAgcCfg, bool isDTV)
2216{
be44eb28
MCC		 2217 int status = -EINVAL;
2218 u16 data = 0;
43dd07f7
RM		 2219 struct SCfgAgc *pIfAgcSettings;
2220
2da67501
MCC		 2221 dprintk(1, "\n");
2222
43dd07f7 2223 if (pAgcCfg == NULL)
be44eb28 2224 goto error;
43dd07f7 2225
be44eb28
MCC		 2226 switch (pAgcCfg->ctrlMode) {
2227 case DRXK_AGC_CTRL_AUTO:
2228 /* Enable RF AGC DAC */
2229 status = read16(state, IQM_AF_STDBY__A, &data);
2230 if (status < 0)
2231 goto error;
2232 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2233 status = write16(state, IQM_AF_STDBY__A, data);
2234 if (status < 0)
2235 goto error;
2236 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2237 if (status < 0)
2238 goto error;
43dd07f7 2239
be44eb28
MCC		 2240 /* Enable SCU RF AGC loop */
2241 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
43dd07f7 2242
be44eb28
MCC		 2243 /* Polarity */
2244 if (state->m_RfAgcPol)
2245 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2246 else
2247 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2248 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2249 if (status < 0)
2250 goto error;
43dd07f7 2251
be44eb28
MCC		 2252 /* Set speed (using complementary reduction value) */
2253 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2254 if (status < 0)
2255 goto error;
43dd07f7 2256
be44eb28
MCC		 2257 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2258 data |= (~(pAgcCfg->speed <<
2259 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2260 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
43dd07f7 2261
be44eb28
MCC		 2262 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2263 if (status < 0)
2264 goto error;
43dd07f7 2265
be44eb28
MCC		 2266 if (IsDVBT(state))
2267 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2268 else if (IsQAM(state))
2269 pIfAgcSettings = &state->m_qamIfAgcCfg;
2270 else
2271 pIfAgcSettings = &state->m_atvIfAgcCfg;
2272 if (pIfAgcSettings == NULL) {
2273 status = -EINVAL;
2274 goto error;
2275 }
43dd07f7 2276
be44eb28
MCC		 2277 /* Set TOP, only if IF-AGC is in AUTO mode */
2278 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2279 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
ea90f011 2280 if (status < 0)
be44eb28 2281 goto error;
43dd07f7 2282
be44eb28
MCC		 2283 /* Cut-Off current */
2284 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2285 if (status < 0)
2286 goto error;
43dd07f7 2287
be44eb28
MCC		 2288 /* Max. output level */
2289 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2290 if (status < 0)
2291 goto error;
43dd07f7 2292
be44eb28 2293 break;
43dd07f7 2294
be44eb28
MCC		 2295 case DRXK_AGC_CTRL_USER:
2296 /* Enable RF AGC DAC */
2297 status = read16(state, IQM_AF_STDBY__A, &data);
2298 if (status < 0)
2299 goto error;
2300 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2301 status = write16(state, IQM_AF_STDBY__A, data);
2302 if (status < 0)
2303 goto error;
43dd07f7 2304
be44eb28
MCC		 2305 /* Disable SCU RF AGC loop */
2306 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2307 if (status < 0)
2308 goto error;
2309 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2310 if (state->m_RfAgcPol)
2311 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2312 else
2313 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2314 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2315 if (status < 0)
2316 goto error;
43dd07f7 2317
be44eb28
MCC		 2318 /* SCU c.o.c. to 0, enabling full control range */
2319 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2320 if (status < 0)
2321 goto error;
43dd07f7 2322
be44eb28
MCC		 2323 /* Write value to output pin */
2324 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2325 if (status < 0)
2326 goto error;
2327 break;
43dd07f7 2328
be44eb28
MCC		 2329 case DRXK_AGC_CTRL_OFF:
2330 /* Disable RF AGC DAC */
2331 status = read16(state, IQM_AF_STDBY__A, &data);
2332 if (status < 0)
2333 goto error;
2334 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2335 status = write16(state, IQM_AF_STDBY__A, data);
2336 if (status < 0)
2337 goto error;
43dd07f7 2338
be44eb28
MCC		 2339 /* Disable SCU RF AGC loop */
2340 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2341 if (status < 0)
2342 goto error;
2343 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2344 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2345 if (status < 0)
2346 goto error;
2347 break;
43dd07f7 2348
be44eb28
MCC		 2349 default:
2350 status = -EINVAL;
43dd07f7 2351
be44eb28
MCC		 2352 }
2353error:
2354 if (status < 0)
2355 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2356 return status;
2357}
2358
2359#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2360
ebc7de22
OE		 2361static int SetAgcIf(struct drxk_state *state,
2362 struct SCfgAgc *pAgcCfg, bool isDTV)
43dd07f7
RM		 2363{
2364 u16 data = 0;
2365 int status = 0;
2366 struct SCfgAgc *pRfAgcSettings;
2367
2da67501
MCC		 2368 dprintk(1, "\n");
2369
be44eb28
MCC		 2370 switch (pAgcCfg->ctrlMode) {
2371 case DRXK_AGC_CTRL_AUTO:
43dd07f7 2372
be44eb28
MCC		 2373 /* Enable IF AGC DAC */
2374 status = read16(state, IQM_AF_STDBY__A, &data);
2375 if (status < 0)
2376 goto error;
2377 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2378 status = write16(state, IQM_AF_STDBY__A, data);
2379 if (status < 0)
2380 goto error;
43dd07f7 2381
be44eb28
MCC		 2382 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2383 if (status < 0)
2384 goto error;
43dd07f7 2385
be44eb28
MCC		 2386 /* Enable SCU IF AGC loop */
2387 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
43dd07f7 2388
be44eb28
MCC		 2389 /* Polarity */
2390 if (state->m_IfAgcPol)
2391 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2392 else
2393 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2394 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2395 if (status < 0)
2396 goto error;
43dd07f7 2397
be44eb28
MCC		 2398 /* Set speed (using complementary reduction value) */
2399 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2400 if (status < 0)
2401 goto error;
2402 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2403 data |= (~(pAgcCfg->speed <<
2404 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2405 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
43dd07f7 2406
be44eb28
MCC		 2407 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2408 if (status < 0)
2409 goto error;
43dd07f7 2410
be44eb28
MCC		 2411 if (IsQAM(state))
2412 pRfAgcSettings = &state->m_qamRfAgcCfg;
2413 else
2414 pRfAgcSettings = &state->m_atvRfAgcCfg;
2415 if (pRfAgcSettings == NULL)
2416 return -1;
2417 /* Restore TOP */
2418 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2419 if (status < 0)
2420 goto error;
2421 break;
43dd07f7 2422
be44eb28 2423 case DRXK_AGC_CTRL_USER:
43dd07f7 2424
be44eb28
MCC		 2425 /* Enable IF AGC DAC */
2426 status = read16(state, IQM_AF_STDBY__A, &data);
2427 if (status < 0)
2428 goto error;
2429 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2430 status = write16(state, IQM_AF_STDBY__A, data);
2431 if (status < 0)
2432 goto error;
43dd07f7 2433
be44eb28
MCC		 2434 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2435 if (status < 0)
2436 goto error;
43dd07f7 2437
be44eb28
MCC		 2438 /* Disable SCU IF AGC loop */
2439 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
43dd07f7 2440
be44eb28
MCC		 2441 /* Polarity */
2442 if (state->m_IfAgcPol)
2443 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2444 else
2445 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2446 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2447 if (status < 0)
2448 goto error;
43dd07f7 2449
be44eb28
MCC		 2450 /* Write value to output pin */
2451 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2452 if (status < 0)
2453 goto error;
2454 break;
43dd07f7 2455
be44eb28 2456 case DRXK_AGC_CTRL_OFF:
43dd07f7 2457
be44eb28
MCC		 2458 /* Disable If AGC DAC */
2459 status = read16(state, IQM_AF_STDBY__A, &data);
ea90f011 2460 if (status < 0)
be44eb28
MCC		 2461 goto error;
2462 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2463 status = write16(state, IQM_AF_STDBY__A, data);
2464 if (status < 0)
2465 goto error;
43dd07f7 2466
be44eb28
MCC		 2467 /* Disable SCU IF AGC loop */
2468 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2469 if (status < 0)
2470 goto error;
2471 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2472 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2473 if (status < 0)
2474 goto error;
2475 break;
2476 } /* switch (agcSettingsIf->ctrlMode) */
43dd07f7 2477
be44eb28
MCC		 2478 /* always set the top to support
2479 configurations without if-loop */
2480 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2481error:
2482 if (status < 0)
2483 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2484 return status;
2485}
2486
2487static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2488{
2489 u16 agcDacLvl;
be44eb28
MCC		 2490 int status;
2491 u16 Level = 0;
43dd07f7 2492
2da67501
MCC		 2493 dprintk(1, "\n");
2494
be44eb28
MCC		 2495 status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2496 if (status < 0) {
2497 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2498 return status;
2499 }
2500
43dd07f7
RM		 2501 *pValue = 0;
2502
be44eb28
MCC		 2503 if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2504 Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2505 if (Level < 14000)
2506 *pValue = (14000 - Level) / 4;
2507 else
2508 *pValue = 0;
2509
43dd07f7
RM		 2510 return status;
2511}
2512
ebc7de22
OE		 2513static int GetQAMSignalToNoise(struct drxk_state *state,
2514 s32 *pSignalToNoise)
43dd07f7
RM		 2515{
2516 int status = 0;
be44eb28
MCC		 2517 u16 qamSlErrPower = 0; /* accum. error between
2518 raw and sliced symbols */
2519 u32 qamSlSigPower = 0; /* used for MER, depends of
ed5452a2 2520 QAM modulation */
be44eb28 2521 u32 qamSlMer = 0; /* QAM MER */
43dd07f7 2522
2da67501
MCC		 2523 dprintk(1, "\n");
2524
be44eb28 2525 /* MER calculation */
43dd07f7 2526
be44eb28
MCC		 2527 /* get the register value needed for MER */
2528 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2529 if (status < 0) {
2530 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2531 return -EINVAL;
2532 }
2533
ed5452a2 2534 switch (state->props.modulation) {
be44eb28
MCC		 2535 case QAM_16:
2536 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2537 break;
2538 case QAM_32:
2539 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2540 break;
2541 case QAM_64:
2542 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2543 break;
2544 case QAM_128:
2545 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2546 break;
2547 default:
2548 case QAM_256:
2549 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2550 break;
2551 }
2552
2553 if (qamSlErrPower > 0) {
2554 qamSlMer = Log10Times100(qamSlSigPower) -
2555 Log10Times100((u32) qamSlErrPower);
2556 }
2557 *pSignalToNoise = qamSlMer;
43dd07f7 2558
43dd07f7
RM		 2559 return status;
2560}
2561
ebc7de22
OE		 2562static int GetDVBTSignalToNoise(struct drxk_state *state,
2563 s32 *pSignalToNoise)
43dd07f7 2564{
be44eb28 2565 int status;
ebc7de22
OE		 2566 u16 regData = 0;
2567 u32 EqRegTdSqrErrI = 0;
2568 u32 EqRegTdSqrErrQ = 0;
2569 u16 EqRegTdSqrErrExp = 0;
2570 u16 EqRegTdTpsPwrOfs = 0;
2571 u16 EqRegTdReqSmbCnt = 0;
2572 u32 tpsCnt = 0;
2573 u32 SqrErrIQ = 0;
2574 u32 a = 0;
2575 u32 b = 0;
2576 u32 c = 0;
2577 u32 iMER = 0;
43dd07f7
RM		 2578 u16 transmissionParams = 0;
2579
2da67501 2580 dprintk(1, "\n");
43dd07f7 2581
be44eb28
MCC		 2582 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2583 if (status < 0)
2584 goto error;
2585 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2586 if (status < 0)
2587 goto error;
2588 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2589 if (status < 0)
2590 goto error;
2591 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData);
2592 if (status < 0)
2593 goto error;
2594 /* Extend SQR_ERR_I operational range */
2595 EqRegTdSqrErrI = (u32) regData;
2596 if ((EqRegTdSqrErrExp > 11) &&
2597 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2598 EqRegTdSqrErrI += 0x00010000UL;
2599 }
2600 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData);
2601 if (status < 0)
2602 goto error;
2603 /* Extend SQR_ERR_Q operational range */
2604 EqRegTdSqrErrQ = (u32) regData;
2605 if ((EqRegTdSqrErrExp > 11) &&
2606 (EqRegTdSqrErrQ < 0x00000FFFUL))
2607 EqRegTdSqrErrQ += 0x00010000UL;
2608
2609 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2610 if (status < 0)
2611 goto error;
2612
2613 /* Check input data for MER */
2614
2615 /* MER calculation (in 0.1 dB) without math.h */
2616 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2617 iMER = 0;
2618 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2619 /* No error at all, this must be the HW reset value
2620 * Apparently no first measurement yet
2621 * Set MER to 0.0 */
2622 iMER = 0;
2623 } else {
2624 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2625 EqRegTdSqrErrExp;
2626 if ((transmissionParams &
2627 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2628 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2629 tpsCnt = 17;
2630 else
2631 tpsCnt = 68;
2632
2633 /* IMER = 100 * log10 (x)
2634 where x = (EqRegTdTpsPwrOfs^2 *
2635 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2636
2637 => IMER = a + b -c
2638 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2639 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2640 c = 100 * log10 (SqrErrIQ)
2641 */
2642
2643 /* log(x) x = 9bits * 9bits->18 bits */
2644 a = Log10Times100(EqRegTdTpsPwrOfs *
2645 EqRegTdTpsPwrOfs);
2646 /* log(x) x = 16bits * 7bits->23 bits */
2647 b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2648 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2649 c = Log10Times100(SqrErrIQ);
2650
2651 iMER = a + b;
2652 /* No negative MER, clip to zero */
2653 if (iMER > c)
2654 iMER -= c;
2655 else
43dd07f7 2656 iMER = 0;
be44eb28
MCC		 2657 }
2658 *pSignalToNoise = iMER;
43dd07f7 2659
be44eb28
MCC		 2660error:
2661 if (status < 0)
2662 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2663 return status;
2664}
2665
2666static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2667{
2da67501
MCC		 2668 dprintk(1, "\n");
2669
43dd07f7 2670 *pSignalToNoise = 0;
ebc7de22 2671 switch (state->m_OperationMode) {
43dd07f7
RM		 2672 case OM_DVBT:
2673 return GetDVBTSignalToNoise(state, pSignalToNoise);
2674 case OM_QAM_ITU_A:
2675 case OM_QAM_ITU_C:
2676 return GetQAMSignalToNoise(state, pSignalToNoise);
2677 default:
2678 break;
2679 }
2680 return 0;
2681}
2682
2683#if 0
2684static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2685{
2686 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2687 int status = 0;
2688
2da67501
MCC		 2689 dprintk(1, "\n");
2690
ebc7de22
OE		 2691 static s32 QE_SN[] = {
2692 51, /* QPSK 1/2 */
2693 69, /* QPSK 2/3 */
2694 79, /* QPSK 3/4 */
2695 89, /* QPSK 5/6 */
2696 97, /* QPSK 7/8 */
2697 108, /* 16-QAM 1/2 */
2698 131, /* 16-QAM 2/3 */
2699 146, /* 16-QAM 3/4 */
2700 156, /* 16-QAM 5/6 */
2701 160, /* 16-QAM 7/8 */
2702 165, /* 64-QAM 1/2 */
2703 187, /* 64-QAM 2/3 */
2704 202, /* 64-QAM 3/4 */
2705 216, /* 64-QAM 5/6 */
2706 225, /* 64-QAM 7/8 */
2707 };
43dd07f7
RM		 2708
2709 *pQuality = 0;
2710
2711 do {
2712 s32 SignalToNoise = 0;
2713 u16 Constellation = 0;
2714 u16 CodeRate = 0;
2715 u32 SignalToNoiseRel;
2716 u32 BERQuality;
2717
ea90f011
MCC		 2718 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2719 if (status < 0)
2720 break;
5e66b878 2721 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
ea90f011
MCC		 2722 if (status < 0)
2723 break;
43dd07f7
RM		 2724 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2725
5e66b878 2726 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
ea90f011
MCC		 2727 if (status < 0)
2728 break;
43dd07f7
RM		 2729 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2730
2731 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2732 CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2733 break;
2734 SignalToNoiseRel = SignalToNoise -
ebc7de22 2735 QE_SN[Constellation * 5 + CodeRate];
43dd07f7
RM		 2736 BERQuality = 100;
2737
ebc7de22
OE		 2738 if (SignalToNoiseRel < -70)
2739 *pQuality = 0;
43dd07f7
RM		 2740 else if (SignalToNoiseRel < 30)
2741 *pQuality = ((SignalToNoiseRel + 70) *
2742 BERQuality) / 100;
2743 else
2744 *pQuality = BERQuality;
ebc7de22 2745 } while (0);
43dd07f7
RM		 2746 return 0;
2747};
2748
ebc7de22 2749static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
43dd07f7
RM		 2750{
2751 int status = 0;
2752 *pQuality = 0;
2753
2da67501
MCC		 2754 dprintk(1, "\n");
2755
43dd07f7
RM		 2756 do {
2757 u32 SignalToNoise = 0;
2758 u32 BERQuality = 100;
2759 u32 SignalToNoiseRel = 0;
2760
ea90f011
MCC		 2761 status = GetQAMSignalToNoise(state, &SignalToNoise);
2762 if (status < 0)
2763 break;
43dd07f7 2764
ed5452a2 2765 switch (state->props.modulation) {
43dd07f7
RM		 2766 case QAM_16:
2767 SignalToNoiseRel = SignalToNoise - 200;
2768 break;
2769 case QAM_32:
2770 SignalToNoiseRel = SignalToNoise - 230;
ebc7de22 2771 break; /* Not in NorDig */
43dd07f7
RM		 2772 case QAM_64:
2773 SignalToNoiseRel = SignalToNoise - 260;
2774 break;
2775 case QAM_128:
2776 SignalToNoiseRel = SignalToNoise - 290;
2777 break;
2778 default:
2779 case QAM_256:
2780 SignalToNoiseRel = SignalToNoise - 320;
2781 break;
2782 }
2783
2784 if (SignalToNoiseRel < -70)
2785 *pQuality = 0;
2786 else if (SignalToNoiseRel < 30)
2787 *pQuality = ((SignalToNoiseRel + 70) *
2788 BERQuality) / 100;
2789 else
2790 *pQuality = BERQuality;
ebc7de22 2791 } while (0);
43dd07f7
RM		 2792
2793 return status;
2794}
2795
2796static int GetQuality(struct drxk_state *state, s32 *pQuality)
2797{
2da67501
MCC		 2798 dprintk(1, "\n");
2799
ebc7de22
OE		 2800 switch (state->m_OperationMode) {
2801 case OM_DVBT:
43dd07f7 2802 return GetDVBTQuality(state, pQuality);
ebc7de22 2803 case OM_QAM_ITU_A:
43dd07f7
RM		 2804 return GetDVBCQuality(state, pQuality);
2805 default:
2806 break;
2807 }
2808
2809 return 0;
2810}
2811#endif
2812
2813/* Free data ram in SIO HI */
2814#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2815#define SIO_HI_RA_RAM_USR_END__A 0x420060
2816
2817#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2818#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2819#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2820#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2821
2822#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2823#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2824#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2825
2826static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2827{
be44eb28 2828 int status = -EINVAL;
43dd07f7 2829
2da67501
MCC		 2830 dprintk(1, "\n");
2831
43dd07f7 2832 if (state->m_DrxkState == DRXK_UNINITIALIZED)
be44eb28 2833 goto error;
43dd07f7 2834 if (state->m_DrxkState == DRXK_POWERED_DOWN)
be44eb28 2835 goto error;
43dd07f7 2836
f1fe1b75
MCC		 2837 if (state->no_i2c_bridge)
2838 return 0;
43dd07f7 2839
be44eb28
MCC		 2840 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2841 if (status < 0)
2842 goto error;
2843 if (bEnableBridge) {
2844 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
ea90f011 2845 if (status < 0)
be44eb28
MCC		 2846 goto error;
2847 } else {
2848 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2849 if (status < 0)
2850 goto error;
2851 }
2852
2853 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2854
2855error:
2856 if (status < 0)
2857 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2858 return status;
2859}
2860
ebc7de22
OE		 2861static int SetPreSaw(struct drxk_state *state,
2862 struct SCfgPreSaw *pPreSawCfg)
43dd07f7 2863{
be44eb28 2864 int status = -EINVAL;
43dd07f7 2865
2da67501
MCC		 2866 dprintk(1, "\n");
2867
ebc7de22
OE		 2868 if ((pPreSawCfg == NULL)
2869 || (pPreSawCfg->reference > IQM_AF_PDREF__M))
be44eb28 2870 goto error;
43dd07f7 2871
5e66b878 2872 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
be44eb28
MCC		 2873error:
2874 if (status < 0)
2875 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2876 return status;
2877}
2878
2879static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
ebc7de22 2880 u16 romOffset, u16 nrOfElements, u32 timeOut)
43dd07f7 2881{
ebc7de22
OE		 2882 u16 blStatus = 0;
2883 u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2884 u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2885 int status;
43dd07f7
RM		 2886 unsigned long end;
2887
2da67501
MCC		 2888 dprintk(1, "\n");
2889
43dd07f7 2890 mutex_lock(&state->mutex);
be44eb28
MCC		 2891 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2892 if (status < 0)
2893 goto error;
2894 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2895 if (status < 0)
2896 goto error;
2897 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2898 if (status < 0)
2899 goto error;
2900 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2901 if (status < 0)
2902 goto error;
2903 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2904 if (status < 0)
2905 goto error;
2906 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2907 if (status < 0)
2908 goto error;
2909
2910 end = jiffies + msecs_to_jiffies(timeOut);
43dd07f7 2911 do {
be44eb28 2912 status = read16(state, SIO_BL_STATUS__A, &blStatus);
ea90f011 2913 if (status < 0)
be44eb28
MCC		 2914 goto error;
2915 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2916 if (blStatus == 0x1) {
2917 printk(KERN_ERR "drxk: SIO not ready\n");
2918 status = -EINVAL;
2919 goto error2;
2920 }
2921error:
2922 if (status < 0)
2923 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2924error2:
43dd07f7
RM		 2925 mutex_unlock(&state->mutex);
2926 return status;
2927
2928}
2929
ebc7de22 2930static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
43dd07f7
RM		 2931{
2932 u16 data = 0;
2933 int status;
2934
2da67501
MCC		 2935 dprintk(1, "\n");
2936
be44eb28
MCC		 2937 /* Start measurement */
2938 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2939 if (status < 0)
2940 goto error;
2941 status = write16(state, IQM_AF_START_LOCK__A, 1);
2942 if (status < 0)
2943 goto error;
43dd07f7 2944
be44eb28
MCC		 2945 *count = 0;
2946 status = read16(state, IQM_AF_PHASE0__A, &data);
2947 if (status < 0)
2948 goto error;
2949 if (data == 127)
2950 *count = *count + 1;
2951 status = read16(state, IQM_AF_PHASE1__A, &data);
2952 if (status < 0)
2953 goto error;
2954 if (data == 127)
2955 *count = *count + 1;
2956 status = read16(state, IQM_AF_PHASE2__A, &data);
2957 if (status < 0)
2958 goto error;
2959 if (data == 127)
2960 *count = *count + 1;
2961
2962error:
2963 if (status < 0)
2964 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2965 return status;
2966}
2967
2968static int ADCSynchronization(struct drxk_state *state)
2969{
2970 u16 count = 0;
2971 int status;
2972
2da67501
MCC		 2973 dprintk(1, "\n");
2974
be44eb28
MCC		 2975 status = ADCSyncMeasurement(state, &count);
2976 if (status < 0)
2977 goto error;
43dd07f7 2978
be44eb28
MCC		 2979 if (count == 1) {
2980 /* Try sampling on a diffrent edge */
2981 u16 clkNeg = 0;
43dd07f7 2982
be44eb28
MCC		 2983 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2984 if (status < 0)
2985 goto error;
2986 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2987 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2988 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2989 clkNeg |=
2990 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2991 } else {
2992 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2993 clkNeg |=
2994 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
43dd07f7 2995 }
be44eb28
MCC		 2996 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2997 if (status < 0)
2998 goto error;
2999 status = ADCSyncMeasurement(state, &count);
3000 if (status < 0)
3001 goto error;
3002 }
43dd07f7 3003
be44eb28
MCC		 3004 if (count < 2)
3005 status = -EINVAL;
3006error:
3007 if (status < 0)
3008 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3009 return status;
3010}
3011
3012static int SetFrequencyShifter(struct drxk_state *state,
3013 u16 intermediateFreqkHz,
ebc7de22 3014 s32 tunerFreqOffset, bool isDTV)
43dd07f7
RM		 3015{
3016 bool selectPosImage = false;
ebc7de22 3017 u32 rfFreqResidual = tunerFreqOffset;
43dd07f7
RM		 3018 u32 fmFrequencyShift = 0;
3019 bool tunerMirror = !state->m_bMirrorFreqSpect;
3020 u32 adcFreq;
3021 bool adcFlip;
3022 int status;
3023 u32 ifFreqActual;
ebc7de22 3024 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
43dd07f7
RM		 3025 u32 frequencyShift;
3026 bool imageToSelect;
3027
2da67501
MCC		 3028 dprintk(1, "\n");
3029
43dd07f7 3030 /*
ebc7de22
OE		 3031 Program frequency shifter
3032 No need to account for mirroring on RF
3033 */
43dd07f7
RM		 3034 if (isDTV) {
3035 if ((state->m_OperationMode == OM_QAM_ITU_A) ||
3036 (state->m_OperationMode == OM_QAM_ITU_C) ||
3037 (state->m_OperationMode == OM_DVBT))
ebc7de22
OE		 3038 selectPosImage = true;
3039 else
3040 selectPosImage = false;
43dd07f7
RM		 3041 }
3042 if (tunerMirror)
3043 /* tuner doesn't mirror */
3044 ifFreqActual = intermediateFreqkHz +
ebc7de22 3045 rfFreqResidual + fmFrequencyShift;
43dd07f7
RM		 3046 else
3047 /* tuner mirrors */
3048 ifFreqActual = intermediateFreqkHz -
ebc7de22 3049 rfFreqResidual - fmFrequencyShift;
43dd07f7
RM		 3050 if (ifFreqActual > samplingFrequency / 2) {
3051 /* adc mirrors */
3052 adcFreq = samplingFrequency - ifFreqActual;
3053 adcFlip = true;
3054 } else {
3055 /* adc doesn't mirror */
3056 adcFreq = ifFreqActual;
3057 adcFlip = false;
3058 }
3059
3060 frequencyShift = adcFreq;
3061 imageToSelect = state->m_rfmirror ^ tunerMirror ^
ebc7de22
OE		 3062 adcFlip ^ selectPosImage;
3063 state->m_IqmFsRateOfs =
3064 Frac28a((frequencyShift), samplingFrequency);
43dd07f7
RM		 3065
3066 if (imageToSelect)
3067 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
3068
3069 /* Program frequency shifter with tuner offset compensation */
3070 /* frequencyShift += tunerFreqOffset; TODO */
5e66b878
MCC		 3071 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3072 state->m_IqmFsRateOfs);
be44eb28
MCC		 3073 if (status < 0)
3074 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3075 return status;
3076}
3077
3078static int InitAGC(struct drxk_state *state, bool isDTV)
3079{
ebc7de22
OE		 3080 u16 ingainTgt = 0;
3081 u16 ingainTgtMin = 0;
3082 u16 ingainTgtMax = 0;
3083 u16 clpCyclen = 0;
3084 u16 clpSumMin = 0;
3085 u16 clpDirTo = 0;
3086 u16 snsSumMin = 0;
3087 u16 snsSumMax = 0;
3088 u16 clpSumMax = 0;
3089 u16 snsDirTo = 0;
3090 u16 kiInnergainMin = 0;
3091 u16 ifIaccuHiTgt = 0;
43dd07f7
RM		 3092 u16 ifIaccuHiTgtMin = 0;
3093 u16 ifIaccuHiTgtMax = 0;
ebc7de22
OE		 3094 u16 data = 0;
3095 u16 fastClpCtrlDelay = 0;
3096 u16 clpCtrlMode = 0;
43dd07f7
RM		 3097 int status = 0;
3098
2da67501
MCC		 3099 dprintk(1, "\n");
3100
be44eb28
MCC		 3101 /* Common settings */
3102 snsSumMax = 1023;
3103 ifIaccuHiTgtMin = 2047;
3104 clpCyclen = 500;
3105 clpSumMax = 1023;
3106
f1b82970
MCC		 3107 /* AGCInit() not available for DVBT; init done in microcode */
3108 if (!IsQAM(state)) {
3109 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode);
3110 return -EINVAL;
be44eb28 3111 }
f1b82970
MCC		 3112
3113 /* FIXME: Analog TV AGC require different settings */
3114
3115 /* Standard specific settings */
3116 clpSumMin = 8;
3117 clpDirTo = (u16) -9;
3118 clpCtrlMode = 0;
3119 snsSumMin = 8;
3120 snsDirTo = (u16) -9;
3121 kiInnergainMin = (u16) -1030;
3122 ifIaccuHiTgtMax = 0x2380;
3123 ifIaccuHiTgt = 0x2380;
3124 ingainTgtMin = 0x0511;
3125 ingainTgt = 0x0511;
3126 ingainTgtMax = 5119;
3127 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay;
3128
be44eb28
MCC		 3129 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3130 if (status < 0)
3131 goto error;
ea90f011 3132
be44eb28
MCC		 3133 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3134 if (status < 0)
3135 goto error;
3136 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3137 if (status < 0)
3138 goto error;
3139 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3140 if (status < 0)
3141 goto error;
3142 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3143 if (status < 0)
3144 goto error;
3145 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3146 if (status < 0)
3147 goto error;
3148 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3149 if (status < 0)
3150 goto error;
3151 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3152 if (status < 0)
3153 goto error;
3154 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3155 if (status < 0)
3156 goto error;
3157 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3158 if (status < 0)
3159 goto error;
3160 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3161 if (status < 0)
3162 goto error;
3163 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3164 if (status < 0)
3165 goto error;
3166 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3167 if (status < 0)
3168 goto error;
ea90f011 3169
be44eb28
MCC		 3170 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3171 if (status < 0)
3172 goto error;
3173 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3174 if (status < 0)
3175 goto error;
3176 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3177 if (status < 0)
3178 goto error;
ea90f011 3179
be44eb28
MCC		 3180 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3181 if (status < 0)
3182 goto error;
3183 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3184 if (status < 0)
3185 goto error;
3186 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3187 if (status < 0)
3188 goto error;
ea90f011 3189
be44eb28
MCC		 3190 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3191 if (status < 0)
3192 goto error;
3193 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3194 if (status < 0)
3195 goto error;
3196 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3197 if (status < 0)
3198 goto error;
3199 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3200 if (status < 0)
3201 goto error;
3202 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3203 if (status < 0)
3204 goto error;
3205 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3206 if (status < 0)
3207 goto error;
3208 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3209 if (status < 0)
3210 goto error;
3211 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3212 if (status < 0)
3213 goto error;
3214 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3215 if (status < 0)
3216 goto error;
3217 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3218 if (status < 0)
3219 goto error;
3220 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3221 if (status < 0)
3222 goto error;
3223 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3224 if (status < 0)
3225 goto error;
3226 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3227 if (status < 0)
3228 goto error;
3229 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3230 if (status < 0)
3231 goto error;
3232 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3233 if (status < 0)
3234 goto error;
3235 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3236 if (status < 0)
3237 goto error;
3238 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3239 if (status < 0)
3240 goto error;
3241 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3242 if (status < 0)
3243 goto error;
3244 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3245 if (status < 0)
3246 goto error;
43dd07f7 3247
be44eb28
MCC		 3248 /* Initialize inner-loop KI gain factors */
3249 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3250 if (status < 0)
3251 goto error;
f1b82970
MCC		 3252
3253 data = 0x0657;
3254 data &= ~SCU_RAM_AGC_KI_RF__M;
3255 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3256 data &= ~SCU_RAM_AGC_KI_IF__M;
3257 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3258
be44eb28
MCC		 3259 status = write16(state, SCU_RAM_AGC_KI__A, data);
3260error:
3261 if (status < 0)
3262 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3263 return status;
3264}
3265
ebc7de22 3266static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
43dd07f7
RM		 3267{
3268 int status;
3269
2da67501 3270 dprintk(1, "\n");
be44eb28
MCC		 3271 if (packetErr == NULL)
3272 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3273 else
3274 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3275 if (status < 0)
3276 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3277 return status;
3278}
3279
3280static int DVBTScCommand(struct drxk_state *state,
3281 u16 cmd, u16 subcmd,
3282 u16 param0, u16 param1, u16 param2,
3283 u16 param3, u16 param4)
3284{
ebc7de22
OE		 3285 u16 curCmd = 0;
3286 u16 errCode = 0;
43dd07f7 3287 u16 retryCnt = 0;
ebc7de22
OE		 3288 u16 scExec = 0;
3289 int status;
43dd07f7 3290
2da67501 3291 dprintk(1, "\n");
5e66b878 3292 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
43dd07f7
RM		 3293 if (scExec != 1) {
3294 /* SC is not running */
be44eb28 3295 status = -EINVAL;
43dd07f7 3296 }
be44eb28
MCC		 3297 if (status < 0)
3298 goto error;
43dd07f7
RM		 3299
3300 /* Wait until sc is ready to receive command */
ebc7de22 3301 retryCnt = 0;
43dd07f7
RM		 3302 do {
3303 msleep(1);
5e66b878 3304 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
43dd07f7
RM		 3305 retryCnt++;
3306 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
be44eb28
MCC		 3307 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3308 goto error;
3309
43dd07f7
RM		 3310 /* Write sub-command */
3311 switch (cmd) {
3312 /* All commands using sub-cmd */
3313 case OFDM_SC_RA_RAM_CMD_PROC_START:
3314 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3315 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
be44eb28
MCC		 3316 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3317 if (status < 0)
3318 goto error;
43dd07f7
RM		 3319 break;
3320 default:
3321 /* Do nothing */
3322 break;
be44eb28 3323 }
43dd07f7
RM		 3324
3325 /* Write needed parameters and the command */
3326 switch (cmd) {
3327 /* All commands using 5 parameters */
3328 /* All commands using 4 parameters */
3329 /* All commands using 3 parameters */
3330 /* All commands using 2 parameters */
3331 case OFDM_SC_RA_RAM_CMD_PROC_START:
3332 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3333 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
be44eb28 3334 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
43dd07f7
RM		 3335 /* All commands using 1 parameters */
3336 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3337 case OFDM_SC_RA_RAM_CMD_USER_IO:
be44eb28 3338 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
43dd07f7
RM		 3339 /* All commands using 0 parameters */
3340 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3341 case OFDM_SC_RA_RAM_CMD_NULL:
3342 /* Write command */
5e66b878 3343 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
43dd07f7
RM		 3344 break;
3345 default:
3346 /* Unknown command */
be44eb28
MCC		 3347 status = -EINVAL;
3348 }
3349 if (status < 0)
3350 goto error;
43dd07f7
RM		 3351
3352 /* Wait until sc is ready processing command */
3353 retryCnt = 0;
ebc7de22 3354 do {
43dd07f7 3355 msleep(1);
5e66b878 3356 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
43dd07f7 3357 retryCnt++;
ebc7de22 3358 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
be44eb28
MCC		 3359 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3360 goto error;
43dd07f7
RM		 3361
3362 /* Check for illegal cmd */
5e66b878 3363 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
ebc7de22 3364 if (errCode == 0xFFFF) {
43dd07f7 3365 /* illegal command */
be44eb28 3366 status = -EINVAL;
43dd07f7 3367 }
be44eb28
MCC		 3368 if (status < 0)
3369 goto error;
43dd07f7
RM		 3370
3371 /* Retreive results parameters from SC */
3372 switch (cmd) {
3373 /* All commands yielding 5 results */
3374 /* All commands yielding 4 results */
3375 /* All commands yielding 3 results */
3376 /* All commands yielding 2 results */
3377 /* All commands yielding 1 result */
3378 case OFDM_SC_RA_RAM_CMD_USER_IO:
3379 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
be44eb28 3380 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
43dd07f7
RM		 3381 /* All commands yielding 0 results */
3382 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3383 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3384 case OFDM_SC_RA_RAM_CMD_PROC_START:
3385 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3386 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3387 case OFDM_SC_RA_RAM_CMD_NULL:
3388 break;
3389 default:
3390 /* Unknown command */
be44eb28 3391 status = -EINVAL;
43dd07f7 3392 break;
ebc7de22 3393 } /* switch (cmd->cmd) */
be44eb28
MCC		 3394error:
3395 if (status < 0)
3396 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3397 return status;
3398}
3399
ebc7de22 3400static int PowerUpDVBT(struct drxk_state *state)
43dd07f7 3401{
ebc7de22 3402 enum DRXPowerMode powerMode = DRX_POWER_UP;
43dd07f7
RM		 3403 int status;
3404
2da67501 3405 dprintk(1, "\n");
be44eb28
MCC		 3406 status = CtrlPowerMode(state, &powerMode);
3407 if (status < 0)
3408 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3409 return status;
3410}
3411
ebc7de22 3412static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
43dd07f7 3413{
ebc7de22
OE		 3414 int status;
3415
2da67501 3416 dprintk(1, "\n");
ebc7de22 3417 if (*enabled == true)
5e66b878 3418 status = write16(state, IQM_CF_BYPASSDET__A, 0);
ebc7de22 3419 else
5e66b878 3420 status = write16(state, IQM_CF_BYPASSDET__A, 1);
be44eb28
MCC		 3421 if (status < 0)
3422 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 3423 return status;
43dd07f7 3424}
ebc7de22
OE		 3425
3426#define DEFAULT_FR_THRES_8K 4000
3427static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
43dd07f7
RM		 3428{
3429
ebc7de22
OE		 3430 int status;
3431
2da67501 3432 dprintk(1, "\n");
ebc7de22
OE		 3433 if (*enabled == true) {
3434 /* write mask to 1 */
5e66b878 3435 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
ebc7de22
OE		 3436 DEFAULT_FR_THRES_8K);
3437 } else {
3438 /* write mask to 0 */
5e66b878 3439 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
ebc7de22 3440 }
be44eb28
MCC		 3441 if (status < 0)
3442 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22
OE		 3443
3444 return status;
43dd07f7
RM		 3445}
3446
ebc7de22
OE		 3447static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3448 struct DRXKCfgDvbtEchoThres_t *echoThres)
43dd07f7 3449{
ebc7de22 3450 u16 data = 0;
43dd07f7 3451 int status;
43dd07f7 3452
2da67501 3453 dprintk(1, "\n");
be44eb28
MCC		 3454 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3455 if (status < 0)
3456 goto error;
3457
3458 switch (echoThres->fftMode) {
3459 case DRX_FFTMODE_2K:
3460 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3461 data |= ((echoThres->threshold <<
3462 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3463 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
320ed23e 3464 break;
be44eb28
MCC		 3465 case DRX_FFTMODE_8K:
3466 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3467 data |= ((echoThres->threshold <<
3468 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3469 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
320ed23e 3470 break;
be44eb28
MCC		 3471 default:
3472 return -EINVAL;
be44eb28 3473 }
ebc7de22 3474
be44eb28
MCC		 3475 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3476error:
3477 if (status < 0)
3478 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 3479 return status;
43dd07f7
RM		 3480}
3481
3482static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
ebc7de22 3483 enum DRXKCfgDvbtSqiSpeed *speed)
43dd07f7 3484{
be44eb28 3485 int status = -EINVAL;
43dd07f7 3486
2da67501
MCC		 3487 dprintk(1, "\n");
3488
43dd07f7
RM		 3489 switch (*speed) {
3490 case DRXK_DVBT_SQI_SPEED_FAST:
3491 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3492 case DRXK_DVBT_SQI_SPEED_SLOW:
3493 break;
3494 default:
be44eb28 3495 goto error;
43dd07f7 3496 }
5e66b878 3497 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
ebc7de22 3498 (u16) *speed);
be44eb28
MCC		 3499error:
3500 if (status < 0)
3501 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3502 return status;
3503}
3504
3505/*============================================================================*/
3506
3507/**
3508* \brief Activate DVBT specific presets
3509* \param demod instance of demodulator.
3510* \return DRXStatus_t.
3511*
3512* Called in DVBTSetStandard
3513*
3514*/
ebc7de22 3515static int DVBTActivatePresets(struct drxk_state *state)
43dd07f7 3516{
ebc7de22 3517 int status;
be44eb28
MCC		 3518 bool setincenable = false;
3519 bool setfrenable = true;
ebc7de22
OE		 3520
3521 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3522 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3523
2da67501 3524 dprintk(1, "\n");
be44eb28
MCC		 3525 status = DVBTCtrlSetIncEnable(state, &setincenable);
3526 if (status < 0)
3527 goto error;
3528 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3529 if (status < 0)
3530 goto error;
3531 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3532 if (status < 0)
3533 goto error;
3534 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3535 if (status < 0)
3536 goto error;
3537 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3538error:
3539 if (status < 0)
3540 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 3541 return status;
43dd07f7 3542}
ebc7de22 3543
43dd07f7
RM		 3544/*============================================================================*/
3545
3546/**
3547* \brief Initialize channelswitch-independent settings for DVBT.
3548* \param demod instance of demodulator.
3549* \return DRXStatus_t.
3550*
3551* For ROM code channel filter taps are loaded from the bootloader. For microcode
3552* the DVB-T taps from the drxk_filters.h are used.
3553*/
ebc7de22
OE		 3554static int SetDVBTStandard(struct drxk_state *state,
3555 enum OperationMode oMode)
43dd07f7 3556{
ebc7de22
OE		 3557 u16 cmdResult = 0;
3558 u16 data = 0;
3559 int status;
43dd07f7 3560
2da67501 3561 dprintk(1, "\n");
43dd07f7 3562
2da67501 3563 PowerUpDVBT(state);
be44eb28
MCC		 3564 /* added antenna switch */
3565 SwitchAntennaToDVBT(state);
3566 /* send OFDM reset command */
3567 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3568 if (status < 0)
3569 goto error;
43dd07f7 3570
be44eb28
MCC		 3571 /* send OFDM setenv command */
3572 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3573 if (status < 0)
3574 goto error;
43dd07f7 3575
be44eb28
MCC		 3576 /* reset datapath for OFDM, processors first */
3577 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3578 if (status < 0)
3579 goto error;
3580 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3581 if (status < 0)
3582 goto error;
3583 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3584 if (status < 0)
3585 goto error;
43dd07f7 3586
be44eb28
MCC		 3587 /* IQM setup */
3588 /* synchronize on ofdstate->m_festart */
3589 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3590 if (status < 0)
3591 goto error;
3592 /* window size for clipping ADC detection */
3593 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3594 if (status < 0)
3595 goto error;
3596 /* window size for for sense pre-SAW detection */
3597 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3598 if (status < 0)
3599 goto error;
3600 /* sense threshold for sense pre-SAW detection */
3601 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3602 if (status < 0)
3603 goto error;
3604 status = SetIqmAf(state, true);
3605 if (status < 0)
3606 goto error;
43dd07f7 3607
be44eb28
MCC		 3608 status = write16(state, IQM_AF_AGC_RF__A, 0);
3609 if (status < 0)
3610 goto error;
43dd07f7 3611
be44eb28
MCC		 3612 /* Impulse noise cruncher setup */
3613 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3614 if (status < 0)
3615 goto error;
3616 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3617 if (status < 0)
3618 goto error;
3619 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3620 if (status < 0)
3621 goto error;
43dd07f7 3622
be44eb28
MCC		 3623 status = write16(state, IQM_RC_STRETCH__A, 16);
3624 if (status < 0)
3625 goto error;
3626 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3627 if (status < 0)
3628 goto error;
3629 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3630 if (status < 0)
3631 goto error;
3632 status = write16(state, IQM_CF_SCALE__A, 1600);
3633 if (status < 0)
3634 goto error;
3635 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3636 if (status < 0)
3637 goto error;
43dd07f7 3638
be44eb28
MCC		 3639 /* virtual clipping threshold for clipping ADC detection */
3640 status = write16(state, IQM_AF_CLP_TH__A, 448);
3641 if (status < 0)
3642 goto error;
3643 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3644 if (status < 0)
3645 goto error;
43dd07f7 3646
be44eb28
MCC		 3647 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3648 if (status < 0)
3649 goto error;
43dd07f7 3650
be44eb28
MCC		 3651 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3652 if (status < 0)
3653 goto error;
3654 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3655 if (status < 0)
3656 goto error;
3657 /* enable power measurement interrupt */
3658 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3659 if (status < 0)
3660 goto error;
3661 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3662 if (status < 0)
3663 goto error;
43dd07f7 3664
be44eb28
MCC		 3665 /* IQM will not be reset from here, sync ADC and update/init AGC */
3666 status = ADCSynchronization(state);
3667 if (status < 0)
3668 goto error;
3669 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3670 if (status < 0)
3671 goto error;
43dd07f7 3672
be44eb28
MCC		 3673 /* Halt SCU to enable safe non-atomic accesses */
3674 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3675 if (status < 0)
3676 goto error;
43dd07f7 3677
be44eb28
MCC		 3678 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3679 if (status < 0)
3680 goto error;
3681 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3682 if (status < 0)
3683 goto error;
43dd07f7 3684
be44eb28
MCC		 3685 /* Set Noise Estimation notch width and enable DC fix */
3686 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3687 if (status < 0)
3688 goto error;
3689 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3690 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3691 if (status < 0)
3692 goto error;
43dd07f7 3693
be44eb28
MCC		 3694 /* Activate SCU to enable SCU commands */
3695 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3696 if (status < 0)
3697 goto error;
43dd07f7 3698
be44eb28
MCC		 3699 if (!state->m_DRXK_A3_ROM_CODE) {
3700 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3701 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3702 if (status < 0)
3703 goto error;
3704 }
43dd07f7 3705
be44eb28 3706 /* OFDM_SC setup */
43dd07f7 3707#ifdef COMPILE_FOR_NONRT
be44eb28
MCC		 3708 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3709 if (status < 0)
3710 goto error;
3711 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3712 if (status < 0)
3713 goto error;
43dd07f7
RM		 3714#endif
3715
be44eb28
MCC		 3716 /* FEC setup */
3717 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3718 if (status < 0)
3719 goto error;
43dd07f7
RM		 3720
3721
3722#ifdef COMPILE_FOR_NONRT
be44eb28
MCC		 3723 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3724 if (status < 0)
3725 goto error;
43dd07f7 3726#else
be44eb28
MCC		 3727 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3728 if (status < 0)
3729 goto error;
43dd07f7 3730#endif
be44eb28
MCC		 3731 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3732 if (status < 0)
3733 goto error;
43dd07f7 3734
be44eb28
MCC		 3735 /* Setup MPEG bus */
3736 status = MPEGTSDtoSetup(state, OM_DVBT);
ebc7de22 3737 if (status < 0)
be44eb28
MCC		 3738 goto error;
3739 /* Set DVBT Presets */
3740 status = DVBTActivatePresets(state);
3741 if (status < 0)
3742 goto error;
43dd07f7 3743
be44eb28
MCC		 3744error:
3745 if (status < 0)
3746 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3747 return status;
3748}
3749
3750/*============================================================================*/
3751/**
3752* \brief Start dvbt demodulating for channel.
3753* \param demod instance of demodulator.
3754* \return DRXStatus_t.
3755*/
3756static int DVBTStart(struct drxk_state *state)
3757{
ebc7de22
OE		 3758 u16 param1;
3759 int status;
3760 /* DRXKOfdmScCmd_t scCmd; */
3761
2da67501 3762 dprintk(1, "\n");
ebc7de22
OE		 3763 /* Start correct processes to get in lock */
3764 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
be44eb28
MCC		 3765 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3766 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3767 if (status < 0)
3768 goto error;
3769 /* Start FEC OC */
3770 status = MPEGTSStart(state);
3771 if (status < 0)
3772 goto error;
3773 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3774 if (status < 0)
3775 goto error;
3776error:
3777 if (status < 0)
3778 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 3779 return status;
43dd07f7
RM		 3780}
3781
3782
3783/*============================================================================*/
3784
3785/**
3786* \brief Set up dvbt demodulator for channel.
3787* \param demod instance of demodulator.
3788* \return DRXStatus_t.
3789* // original DVBTSetChannel()
3790*/
ebc7de22
OE		 3791static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3792 s32 tunerFreqOffset)
43dd07f7 3793{
ebc7de22
OE		 3794 u16 cmdResult = 0;
3795 u16 transmissionParams = 0;
3796 u16 operationMode = 0;
3797 u32 iqmRcRateOfs = 0;
3798 u32 bandwidth = 0;
3799 u16 param1;
43dd07f7
RM		 3800 int status;
3801
be44eb28 3802 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
43dd07f7 3803
be44eb28
MCC		 3804 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3805 if (status < 0)
3806 goto error;
43dd07f7 3807
be44eb28
MCC		 3808 /* Halt SCU to enable safe non-atomic accesses */
3809 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3810 if (status < 0)
3811 goto error;
43dd07f7 3812
be44eb28
MCC		 3813 /* Stop processors */
3814 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3815 if (status < 0)
3816 goto error;
3817 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3818 if (status < 0)
3819 goto error;
43dd07f7 3820
be44eb28
MCC		 3821 /* Mandatory fix, always stop CP, required to set spl offset back to
3822 hardware default (is set to 0 by ucode during pilot detection */
3823 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3824 if (status < 0)
3825 goto error;
43dd07f7 3826
be44eb28 3827 /*== Write channel settings to device =====================================*/
43dd07f7 3828
be44eb28 3829 /* mode */
ed5452a2 3830 switch (state->props.transmission_mode) {
be44eb28
MCC		 3831 case TRANSMISSION_MODE_AUTO:
3832 default:
3833 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3834 /* fall through , try first guess DRX_FFTMODE_8K */
3835 case TRANSMISSION_MODE_8K:
3836 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
320ed23e 3837 break;
be44eb28
MCC		 3838 case TRANSMISSION_MODE_2K:
3839 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
320ed23e 3840 break;
be44eb28 3841 }
43dd07f7 3842
be44eb28 3843 /* guard */
ed5452a2 3844 switch (state->props.guard_interval) {
be44eb28
MCC		 3845 default:
3846 case GUARD_INTERVAL_AUTO:
3847 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3848 /* fall through , try first guess DRX_GUARD_1DIV4 */
3849 case GUARD_INTERVAL_1_4:
3850 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
320ed23e 3851 break;
be44eb28
MCC		 3852 case GUARD_INTERVAL_1_32:
3853 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
320ed23e 3854 break;
be44eb28
MCC		 3855 case GUARD_INTERVAL_1_16:
3856 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
320ed23e 3857 break;
be44eb28
MCC		 3858 case GUARD_INTERVAL_1_8:
3859 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
320ed23e 3860 break;
be44eb28 3861 }
43dd07f7 3862
be44eb28 3863 /* hierarchy */
ed5452a2 3864 switch (state->props.hierarchy) {
be44eb28
MCC		 3865 case HIERARCHY_AUTO:
3866 case HIERARCHY_NONE:
3867 default:
3868 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3869 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3870 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3871 /* break; */
3872 case HIERARCHY_1:
3873 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3874 break;
3875 case HIERARCHY_2:
3876 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3877 break;
3878 case HIERARCHY_4:
3879 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3880 break;
3881 }
3882
3883
ed5452a2
MCC		 3884 /* modulation */
3885 switch (state->props.modulation) {
be44eb28
MCC		 3886 case QAM_AUTO:
3887 default:
3888 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3889 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3890 case QAM_64:
3891 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3892 break;
3893 case QPSK:
3894 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3895 break;
3896 case QAM_16:
3897 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3898 break;
3899 }
43dd07f7 3900#if 0
be44eb28
MCC		 3901 /* No hierachical channels support in BDA */
3902 /* Priority (only for hierarchical channels) */
3903 switch (channel->priority) {
3904 case DRX_PRIORITY_LOW:
3905 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3906 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3907 OFDM_EC_SB_PRIOR_LO);
3908 break;
3909 case DRX_PRIORITY_HIGH:
43dd07f7 3910 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
be44eb28
MCC		 3911 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3912 OFDM_EC_SB_PRIOR_HI));
3913 break;
3914 case DRX_PRIORITY_UNKNOWN: /* fall through */
3915 default:
3916 status = -EINVAL;
3917 goto error;
3918 }
3919#else
3920 /* Set Priorty high */
3921 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3922 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3923 if (status < 0)
3924 goto error;
43dd07f7
RM		 3925#endif
3926
be44eb28 3927 /* coderate */
ed5452a2 3928 switch (state->props.code_rate_HP) {
be44eb28
MCC		 3929 case FEC_AUTO:
3930 default:
3931 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3932 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3933 case FEC_2_3:
3934 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3935 break;
3936 case FEC_1_2:
3937 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3938 break;
3939 case FEC_3_4:
3940 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3941 break;
3942 case FEC_5_6:
3943 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3944 break;
3945 case FEC_7_8:
3946 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3947 break;
3948 }
43dd07f7 3949
be44eb28
MCC		 3950 /* SAW filter selection: normaly not necesarry, but if wanted
3951 the application can select a SAW filter via the driver by using UIOs */
3952 /* First determine real bandwidth (Hz) */
3953 /* Also set delay for impulse noise cruncher */
3954 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3955 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3956 functions */
ed5452a2
MCC		 3957 switch (state->props.bandwidth_hz) {
3958 case 0:
3959 state->props.bandwidth_hz = 8000000;
3960 /* fall though */
3961 case 8000000:
be44eb28
MCC		 3962 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3963 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3964 if (status < 0)
3965 goto error;
3966 /* cochannel protection for PAL 8 MHz */
3967 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3968 if (status < 0)
3969 goto error;
3970 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3971 if (status < 0)
3972 goto error;
3973 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3974 if (status < 0)
3975 goto error;
3976 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3977 if (status < 0)
3978 goto error;
3979 break;
ed5452a2 3980 case 7000000:
be44eb28
MCC		 3981 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3982 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3983 if (status < 0)
3984 goto error;
3985 /* cochannel protection for PAL 7 MHz */
3986 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3987 if (status < 0)
3988 goto error;
3989 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3990 if (status < 0)
3991 goto error;
3992 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3993 if (status < 0)
3994 goto error;
3995 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3996 if (status < 0)
3997 goto error;
3998 break;
ed5452a2 3999 case 6000000:
be44eb28
MCC		 4000 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
4001 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
4002 if (status < 0)
4003 goto error;
4004 /* cochannel protection for NTSC 6 MHz */
4005 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
4006 if (status < 0)
4007 goto error;
4008 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
4009 if (status < 0)
4010 goto error;
4011 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
4012 if (status < 0)
4013 goto error;
4014 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
4015 if (status < 0)
4016 goto error;
4017 break;
4018 default:
4019 status = -EINVAL;
4020 goto error;
4021 }
43dd07f7 4022
be44eb28
MCC		 4023 if (iqmRcRateOfs == 0) {
4024 /* Now compute IQM_RC_RATE_OFS
4025 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4026 =>
4027 ((SysFreq / BandWidth) * (2^21)) - (2^23)
4028 */
4029 /* (SysFreq / BandWidth) * (2^28) */
4030 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
4031 => assert(MAX(sysClk) < 16*MIN(bandwidth))
4032 => assert(109714272 > 48000000) = true so Frac 28 can be used */
4033 iqmRcRateOfs = Frac28a((u32)
4034 ((state->m_sysClockFreq *
4035 1000) / 3), bandwidth);
4036 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4037 if ((iqmRcRateOfs & 0x7fL) >= 0x40)
4038 iqmRcRateOfs += 0x80L;
4039 iqmRcRateOfs = iqmRcRateOfs >> 7;
4040 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
4041 iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
4042 }
43dd07f7 4043
be44eb28
MCC		 4044 iqmRcRateOfs &=
4045 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4046 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4047 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4048 if (status < 0)
4049 goto error;
43dd07f7 4050
be44eb28 4051 /* Bandwidth setting done */
43dd07f7 4052
ea90f011 4053#if 0
be44eb28
MCC		 4054 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4055 if (status < 0)
4056 goto error;
ea90f011 4057#endif
be44eb28
MCC		 4058 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4059 if (status < 0)
4060 goto error;
43dd07f7 4061
be44eb28 4062 /*== Start SC, write channel settings to SC ===============================*/
43dd07f7 4063
be44eb28
MCC		 4064 /* Activate SCU to enable SCU commands */
4065 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4066 if (status < 0)
4067 goto error;
43dd07f7 4068
be44eb28
MCC		 4069 /* Enable SC after setting all other parameters */
4070 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4071 if (status < 0)
4072 goto error;
4073 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4074 if (status < 0)
4075 goto error;
43dd07f7 4076
43dd07f7 4077
be44eb28
MCC		 4078 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4079 if (status < 0)
4080 goto error;
4081
4082 /* Write SC parameter registers, set all AUTO flags in operation mode */
4083 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4084 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4085 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4086 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4087 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4088 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4089 0, transmissionParams, param1, 0, 0, 0);
4090 if (status < 0)
4091 goto error;
43dd07f7 4092
be44eb28
MCC		 4093 if (!state->m_DRXK_A3_ROM_CODE)
4094 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4095error:
4096 if (status < 0)
4097 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 4098
4099 return status;
4100}
4101
4102
4103/*============================================================================*/
4104
4105/**
4106* \brief Retreive lock status .
4107* \param demod Pointer to demodulator instance.
4108* \param lockStat Pointer to lock status structure.
4109* \return DRXStatus_t.
4110*
4111*/
4112static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4113{
ebc7de22
OE		 4114 int status;
4115 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4116 OFDM_SC_RA_RAM_LOCK_FEC__M);
4117 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4118 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4119
4120 u16 ScRaRamLock = 0;
4121 u16 ScCommExec = 0;
4122
2da67501
MCC		 4123 dprintk(1, "\n");
4124
be44eb28 4125 *pLockStatus = NOT_LOCKED;
ebc7de22
OE		 4126 /* driver 0.9.0 */
4127 /* Check if SC is running */
5e66b878 4128 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
be44eb28
MCC		 4129 if (status < 0)
4130 goto end;
4131 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
4132 goto end;
ebc7de22 4133
5e66b878 4134 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
be44eb28
MCC		 4135 if (status < 0)
4136 goto end;
ebc7de22
OE		 4137
4138 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4139 *pLockStatus = MPEG_LOCK;
4140 else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4141 *pLockStatus = FEC_LOCK;
4142 else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4143 *pLockStatus = DEMOD_LOCK;
4144 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4145 *pLockStatus = NEVER_LOCK;
be44eb28
MCC		 4146end:
4147 if (status < 0)
4148 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22
OE		 4149
4150 return status;
43dd07f7
RM		 4151}
4152
ebc7de22 4153static int PowerUpQAM(struct drxk_state *state)
43dd07f7 4154{
ebc7de22 4155 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
be44eb28 4156 int status;
43dd07f7 4157
2da67501 4158 dprintk(1, "\n");
be44eb28
MCC		 4159 status = CtrlPowerMode(state, &powerMode);
4160 if (status < 0)
4161 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7 4162
ebc7de22 4163 return status;
43dd07f7
RM		 4164}
4165
4166
ebc7de22 4167/** Power Down QAM */
43dd07f7
RM		 4168static int PowerDownQAM(struct drxk_state *state)
4169{
ebc7de22
OE		 4170 u16 data = 0;
4171 u16 cmdResult;
4172 int status = 0;
4173
2da67501 4174 dprintk(1, "\n");
be44eb28
MCC		 4175 status = read16(state, SCU_COMM_EXEC__A, &data);
4176 if (status < 0)
4177 goto error;
4178 if (data == SCU_COMM_EXEC_ACTIVE) {
4179 /*
4180 STOP demodulator
4181 QAM and HW blocks
4182 */
4183 /* stop all comstate->m_exec */
4184 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
ea90f011 4185 if (status < 0)
be44eb28
MCC		 4186 goto error;
4187 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
ea90f011 4188 if (status < 0)
be44eb28
MCC		 4189 goto error;
4190 }
4191 /* powerdown AFE */
4192 status = SetIqmAf(state, false);
4193
4194error:
4195 if (status < 0)
4196 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22
OE		 4197
4198 return status;
43dd07f7 4199}
ebc7de22 4200
43dd07f7
RM		 4201/*============================================================================*/
4202
4203/**
4204* \brief Setup of the QAM Measurement intervals for signal quality
4205* \param demod instance of demod.
ed5452a2 4206* \param modulation current modulation.
43dd07f7
RM		 4207* \return DRXStatus_t.
4208*
4209* NOTE:
4210* Take into account that for certain settings the errorcounters can overflow.
4211* The implementation does not check this.
4212*
4213*/
4214static int SetQAMMeasurement(struct drxk_state *state,
ed5452a2 4215 enum EDrxkConstellation modulation,
43dd07f7
RM		 4216 u32 symbolRate)
4217{
ebc7de22
OE		 4218 u32 fecBitsDesired = 0; /* BER accounting period */
4219 u32 fecRsPeriodTotal = 0; /* Total period */
4220 u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
4221 u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
43dd07f7
RM		 4222 int status = 0;
4223
2da67501 4224 dprintk(1, "\n");
43dd07f7 4225
2da67501 4226 fecRsPrescale = 1;
be44eb28
MCC		 4227 /* fecBitsDesired = symbolRate [kHz] *
4228 FrameLenght [ms] *
ed5452a2 4229 (modulation + 1) *
be44eb28
MCC		 4230 SyncLoss (== 1) *
4231 ViterbiLoss (==1)
4232 */
ed5452a2 4233 switch (modulation) {
be44eb28
MCC		 4234 case DRX_CONSTELLATION_QAM16:
4235 fecBitsDesired = 4 * symbolRate;
4236 break;
4237 case DRX_CONSTELLATION_QAM32:
4238 fecBitsDesired = 5 * symbolRate;
4239 break;
4240 case DRX_CONSTELLATION_QAM64:
4241 fecBitsDesired = 6 * symbolRate;
4242 break;
4243 case DRX_CONSTELLATION_QAM128:
4244 fecBitsDesired = 7 * symbolRate;
4245 break;
4246 case DRX_CONSTELLATION_QAM256:
4247 fecBitsDesired = 8 * symbolRate;
4248 break;
4249 default:
4250 status = -EINVAL;
4251 }
4252 if (status < 0)
4253 goto error;
43dd07f7 4254
be44eb28
MCC		 4255 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4256 fecBitsDesired *= 500; /* meas. period [ms] */
43dd07f7 4257
be44eb28
MCC		 4258 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4259 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4260 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
43dd07f7 4261
be44eb28
MCC		 4262 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4263 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4264 if (fecRsPrescale == 0) {
4265 /* Divide by zero (though impossible) */
4266 status = -EINVAL;
ea90f011 4267 if (status < 0)
be44eb28
MCC		 4268 goto error;
4269 }
4270 fecRsPeriod =
4271 ((u16) fecRsPeriodTotal +
4272 (fecRsPrescale >> 1)) / fecRsPrescale;
43dd07f7 4273
be44eb28
MCC		 4274 /* write corresponding registers */
4275 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
ebc7de22 4276 if (status < 0)
be44eb28
MCC		 4277 goto error;
4278 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4279 if (status < 0)
4280 goto error;
4281 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4282error:
4283 if (status < 0)
4284 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 4285 return status;
4286}
4287
ebc7de22 4288static int SetQAM16(struct drxk_state *state)
43dd07f7 4289{
ebc7de22
OE		 4290 int status = 0;
4291
2da67501 4292 dprintk(1, "\n");
be44eb28
MCC		 4293 /* QAM Equalizer Setup */
4294 /* Equalizer */
4295 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4296 if (status < 0)
4297 goto error;
4298 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4299 if (status < 0)
4300 goto error;
4301 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4302 if (status < 0)
4303 goto error;
4304 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4305 if (status < 0)
4306 goto error;
4307 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4308 if (status < 0)
4309 goto error;
4310 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4311 if (status < 0)
4312 goto error;
4313 /* Decision Feedback Equalizer */
4314 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4315 if (status < 0)
4316 goto error;
4317 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4318 if (status < 0)
4319 goto error;
4320 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4321 if (status < 0)
4322 goto error;
4323 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4324 if (status < 0)
4325 goto error;
4326 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4327 if (status < 0)
4328 goto error;
4329 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4330 if (status < 0)
4331 goto error;
ebc7de22 4332
be44eb28
MCC		 4333 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4334 if (status < 0)
4335 goto error;
4336 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4337 if (status < 0)
4338 goto error;
4339 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4340 if (status < 0)
4341 goto error;
ebc7de22 4342
be44eb28
MCC		 4343 /* QAM Slicer Settings */
4344 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4345 if (status < 0)
4346 goto error;
ebc7de22 4347
be44eb28
MCC		 4348 /* QAM Loop Controller Coeficients */
4349 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4350 if (status < 0)
4351 goto error;
4352 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4353 if (status < 0)
4354 goto error;
4355 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4356 if (status < 0)
4357 goto error;
4358 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4359 if (status < 0)
4360 goto error;
4361 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4362 if (status < 0)
4363 goto error;
4364 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4365 if (status < 0)
4366 goto error;
4367 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4368 if (status < 0)
4369 goto error;
4370 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4371 if (status < 0)
4372 goto error;
ea90f011 4373
be44eb28
MCC		 4374 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4375 if (status < 0)
4376 goto error;
4377 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4378 if (status < 0)
4379 goto error;
4380 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4381 if (status < 0)
4382 goto error;
4383 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4384 if (status < 0)
4385 goto error;
4386 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4387 if (status < 0)
4388 goto error;
4389 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4390 if (status < 0)
4391 goto error;
4392 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4393 if (status < 0)
4394 goto error;
4395 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4396 if (status < 0)
4397 goto error;
4398 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4399 if (status < 0)
4400 goto error;
4401 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4402 if (status < 0)
4403 goto error;
4404 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4405 if (status < 0)
4406 goto error;
4407 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4408 if (status < 0)
4409 goto error;
ebc7de22
OE		 4410
4411
be44eb28 4412 /* QAM State Machine (FSM) Thresholds */
ebc7de22 4413
be44eb28
MCC		 4414 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4415 if (status < 0)
4416 goto error;
4417 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4418 if (status < 0)
4419 goto error;
4420 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4421 if (status < 0)
4422 goto error;
4423 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4424 if (status < 0)
4425 goto error;
4426 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4427 if (status < 0)
4428 goto error;
4429 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4430 if (status < 0)
4431 goto error;
ebc7de22 4432
be44eb28
MCC		 4433 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4434 if (status < 0)
4435 goto error;
4436 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4437 if (status < 0)
4438 goto error;
4439 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4440 if (status < 0)
4441 goto error;
ebc7de22
OE		 4442
4443
be44eb28 4444 /* QAM FSM Tracking Parameters */
ebc7de22 4445
be44eb28
MCC		 4446 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4447 if (status < 0)
4448 goto error;
4449 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4450 if (status < 0)
4451 goto error;
4452 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4453 if (status < 0)
4454 goto error;
4455 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4456 if (status < 0)
4457 goto error;
4458 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4459 if (status < 0)
4460 goto error;
4461 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4462 if (status < 0)
4463 goto error;
4464 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4465 if (status < 0)
4466 goto error;
ebc7de22 4467
be44eb28
MCC		 4468error:
4469 if (status < 0)
4470 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 4471 return status;
43dd07f7
RM		 4472}
4473
4474/*============================================================================*/
4475
4476/**
4477* \brief QAM32 specific setup
4478* \param demod instance of demod.
4479* \return DRXStatus_t.
4480*/
ebc7de22 4481static int SetQAM32(struct drxk_state *state)
43dd07f7 4482{
ebc7de22
OE		 4483 int status = 0;
4484
2da67501 4485 dprintk(1, "\n");
ebc7de22 4486
be44eb28
MCC		 4487 /* QAM Equalizer Setup */
4488 /* Equalizer */
4489 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4490 if (status < 0)
4491 goto error;
4492 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4493 if (status < 0)
4494 goto error;
4495 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4496 if (status < 0)
4497 goto error;
4498 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4499 if (status < 0)
4500 goto error;
4501 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4502 if (status < 0)
4503 goto error;
4504 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4505 if (status < 0)
4506 goto error;
ebc7de22 4507
be44eb28
MCC		 4508 /* Decision Feedback Equalizer */
4509 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4510 if (status < 0)
4511 goto error;
4512 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4513 if (status < 0)
4514 goto error;
4515 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4516 if (status < 0)
4517 goto error;
4518 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4519 if (status < 0)
4520 goto error;
4521 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4522 if (status < 0)
4523 goto error;
4524 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4525 if (status < 0)
4526 goto error;
ebc7de22 4527
be44eb28
MCC		 4528 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4529 if (status < 0)
4530 goto error;
4531 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4532 if (status < 0)
4533 goto error;
4534 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4535 if (status < 0)
4536 goto error;
ebc7de22 4537
be44eb28 4538 /* QAM Slicer Settings */
ebc7de22 4539
be44eb28
MCC		 4540 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4541 if (status < 0)
4542 goto error;
ebc7de22 4543
ebc7de22 4544
be44eb28 4545 /* QAM Loop Controller Coeficients */
ea90f011 4546
be44eb28
MCC		 4547 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4548 if (status < 0)
4549 goto error;
4550 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4551 if (status < 0)
4552 goto error;
4553 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4554 if (status < 0)
4555 goto error;
4556 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4557 if (status < 0)
4558 goto error;
4559 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4560 if (status < 0)
4561 goto error;
4562 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4563 if (status < 0)
4564 goto error;
4565 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4566 if (status < 0)
4567 goto error;
4568 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4569 if (status < 0)
4570 goto error;
ebc7de22 4571
be44eb28
MCC		 4572 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4573 if (status < 0)
4574 goto error;
4575 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4576 if (status < 0)
4577 goto error;
4578 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4579 if (status < 0)
4580 goto error;
4581 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4582 if (status < 0)
4583 goto error;
4584 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4585 if (status < 0)
4586 goto error;
4587 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4588 if (status < 0)
4589 goto error;
4590 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4591 if (status < 0)
4592 goto error;
4593 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4594 if (status < 0)
4595 goto error;
4596 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4597 if (status < 0)
4598 goto error;
4599 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4600 if (status < 0)
4601 goto error;
4602 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4603 if (status < 0)
4604 goto error;
4605 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4606 if (status < 0)
4607 goto error;
ebc7de22 4608
ebc7de22 4609
be44eb28 4610 /* QAM State Machine (FSM) Thresholds */
ebc7de22 4611
be44eb28
MCC		 4612 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4613 if (status < 0)
4614 goto error;
4615 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4616 if (status < 0)
4617 goto error;
4618 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4619 if (status < 0)
4620 goto error;
4621 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4622 if (status < 0)
4623 goto error;
4624 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4625 if (status < 0)
4626 goto error;
4627 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4628 if (status < 0)
4629 goto error;
ebc7de22 4630
be44eb28
MCC		 4631 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4632 if (status < 0)
4633 goto error;
4634 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4635 if (status < 0)
4636 goto error;
4637 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4638 if (status < 0)
4639 goto error;
ebc7de22 4640
ebc7de22 4641
be44eb28 4642 /* QAM FSM Tracking Parameters */
ebc7de22 4643
be44eb28
MCC		 4644 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4645 if (status < 0)
4646 goto error;
4647 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4648 if (status < 0)
4649 goto error;
4650 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4651 if (status < 0)
4652 goto error;
4653 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4654 if (status < 0)
4655 goto error;
4656 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4657 if (status < 0)
4658 goto error;
4659 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4660 if (status < 0)
4661 goto error;
4662 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4663error:
4664 if (status < 0)
4665 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 4666 return status;
43dd07f7
RM		 4667}
4668
4669/*============================================================================*/
4670
4671/**
4672* \brief QAM64 specific setup
4673* \param demod instance of demod.
4674* \return DRXStatus_t.
4675*/
ebc7de22 4676static int SetQAM64(struct drxk_state *state)
43dd07f7 4677{
ebc7de22
OE		 4678 int status = 0;
4679
2da67501 4680 dprintk(1, "\n");
be44eb28
MCC		 4681 /* QAM Equalizer Setup */
4682 /* Equalizer */
4683 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4684 if (status < 0)
4685 goto error;
4686 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4687 if (status < 0)
4688 goto error;
4689 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4690 if (status < 0)
4691 goto error;
4692 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4693 if (status < 0)
4694 goto error;
4695 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4696 if (status < 0)
4697 goto error;
4698 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4699 if (status < 0)
4700 goto error;
ebc7de22 4701
be44eb28
MCC		 4702 /* Decision Feedback Equalizer */
4703 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4704 if (status < 0)
4705 goto error;
4706 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4707 if (status < 0)
4708 goto error;
4709 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4710 if (status < 0)
4711 goto error;
4712 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4713 if (status < 0)
4714 goto error;
4715 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4716 if (status < 0)
4717 goto error;
4718 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4719 if (status < 0)
4720 goto error;
ebc7de22 4721
be44eb28
MCC		 4722 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4723 if (status < 0)
4724 goto error;
4725 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4726 if (status < 0)
4727 goto error;
4728 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4729 if (status < 0)
4730 goto error;
ebc7de22 4731
be44eb28
MCC		 4732 /* QAM Slicer Settings */
4733 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4734 if (status < 0)
4735 goto error;
ebc7de22
OE		 4736
4737
be44eb28 4738 /* QAM Loop Controller Coeficients */
ebc7de22 4739
be44eb28
MCC		 4740 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4741 if (status < 0)
4742 goto error;
4743 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4744 if (status < 0)
4745 goto error;
4746 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4747 if (status < 0)
4748 goto error;
4749 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4750 if (status < 0)
4751 goto error;
4752 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4753 if (status < 0)
4754 goto error;
4755 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4756 if (status < 0)
4757 goto error;
4758 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4759 if (status < 0)
4760 goto error;
4761 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4762 if (status < 0)
4763 goto error;
ea90f011 4764
be44eb28
MCC		 4765 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4766 if (status < 0)
4767 goto error;
4768 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4769 if (status < 0)
4770 goto error;
4771 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4772 if (status < 0)
4773 goto error;
4774 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4775 if (status < 0)
4776 goto error;
4777 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4778 if (status < 0)
4779 goto error;
4780 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4781 if (status < 0)
4782 goto error;
4783 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4784 if (status < 0)
4785 goto error;
4786 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4787 if (status < 0)
4788 goto error;
4789 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4790 if (status < 0)
4791 goto error;
4792 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4793 if (status < 0)
4794 goto error;
4795 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4796 if (status < 0)
4797 goto error;
4798 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4799 if (status < 0)
4800 goto error;
ebc7de22
OE		 4801
4802
be44eb28 4803 /* QAM State Machine (FSM) Thresholds */
ebc7de22 4804
be44eb28
MCC		 4805 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4806 if (status < 0)
4807 goto error;
4808 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4809 if (status < 0)
4810 goto error;
4811 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4812 if (status < 0)
4813 goto error;
4814 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4815 if (status < 0)
4816 goto error;
4817 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4818 if (status < 0)
4819 goto error;
4820 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4821 if (status < 0)
4822 goto error;
ebc7de22 4823
be44eb28
MCC		 4824 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4825 if (status < 0)
4826 goto error;
4827 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4828 if (status < 0)
4829 goto error;
4830 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4831 if (status < 0)
4832 goto error;
ebc7de22
OE		 4833
4834
be44eb28 4835 /* QAM FSM Tracking Parameters */
ebc7de22 4836
be44eb28
MCC		 4837 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4838 if (status < 0)
4839 goto error;
4840 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4841 if (status < 0)
4842 goto error;
4843 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4844 if (status < 0)
4845 goto error;
4846 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4847 if (status < 0)
4848 goto error;
4849 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4850 if (status < 0)
4851 goto error;
4852 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4853 if (status < 0)
4854 goto error;
4855 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4856error:
4857 if (status < 0)
4858 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22
OE		 4859
4860 return status;
43dd07f7
RM		 4861}
4862
4863/*============================================================================*/
4864
4865/**
4866* \brief QAM128 specific setup
4867* \param demod: instance of demod.
4868* \return DRXStatus_t.
4869*/
4870static int SetQAM128(struct drxk_state *state)
4871{
ebc7de22
OE		 4872 int status = 0;
4873
2da67501 4874 dprintk(1, "\n");
be44eb28
MCC		 4875 /* QAM Equalizer Setup */
4876 /* Equalizer */
4877 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4878 if (status < 0)
4879 goto error;
4880 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4881 if (status < 0)
4882 goto error;
4883 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4884 if (status < 0)
4885 goto error;
4886 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4887 if (status < 0)
4888 goto error;
4889 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4890 if (status < 0)
4891 goto error;
4892 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4893 if (status < 0)
4894 goto error;
ebc7de22 4895
be44eb28
MCC		 4896 /* Decision Feedback Equalizer */
4897 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4898 if (status < 0)
4899 goto error;
4900 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4901 if (status < 0)
4902 goto error;
4903 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4904 if (status < 0)
4905 goto error;
4906 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4907 if (status < 0)
4908 goto error;
4909 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4910 if (status < 0)
4911 goto error;
4912 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4913 if (status < 0)
4914 goto error;
ebc7de22 4915
be44eb28
MCC		 4916 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4917 if (status < 0)
4918 goto error;
4919 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4920 if (status < 0)
4921 goto error;
4922 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4923 if (status < 0)
4924 goto error;
ebc7de22 4925
ebc7de22 4926
be44eb28 4927 /* QAM Slicer Settings */
ebc7de22 4928
be44eb28
MCC		 4929 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4930 if (status < 0)
4931 goto error;
ebc7de22 4932
ebc7de22 4933
be44eb28 4934 /* QAM Loop Controller Coeficients */
ea90f011 4935
be44eb28
MCC		 4936 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4937 if (status < 0)
4938 goto error;
4939 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4940 if (status < 0)
4941 goto error;
4942 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4943 if (status < 0)
4944 goto error;
4945 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4946 if (status < 0)
4947 goto error;
4948 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4949 if (status < 0)
4950 goto error;
4951 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4952 if (status < 0)
4953 goto error;
4954 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4955 if (status < 0)
4956 goto error;
4957 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4958 if (status < 0)
4959 goto error;
4960
4961 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4962 if (status < 0)
4963 goto error;
4964 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4965 if (status < 0)
4966 goto error;
4967 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4968 if (status < 0)
4969 goto error;
4970 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4971 if (status < 0)
4972 goto error;
4973 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4974 if (status < 0)
4975 goto error;
4976 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4977 if (status < 0)
4978 goto error;
4979 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4980 if (status < 0)
4981 goto error;
4982 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4983 if (status < 0)
4984 goto error;
4985 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4986 if (status < 0)
4987 goto error;
4988 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4989 if (status < 0)
4990 goto error;
4991 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4992 if (status < 0)
4993 goto error;
4994 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4995 if (status < 0)
4996 goto error;
ebc7de22
OE		 4997
4998
be44eb28 4999 /* QAM State Machine (FSM) Thresholds */
ebc7de22 5000
be44eb28
MCC		 5001 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5002 if (status < 0)
5003 goto error;
5004 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5005 if (status < 0)
5006 goto error;
5007 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5008 if (status < 0)
5009 goto error;
5010 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5011 if (status < 0)
5012 goto error;
5013 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
5014 if (status < 0)
5015 goto error;
5016 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5017 if (status < 0)
5018 goto error;
ebc7de22 5019
be44eb28
MCC		 5020 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5021 if (status < 0)
5022 goto error;
5023 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5024 if (status < 0)
5025 goto error;
ebc7de22 5026
be44eb28
MCC		 5027 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5028 if (status < 0)
5029 goto error;
ebc7de22 5030
be44eb28 5031 /* QAM FSM Tracking Parameters */
ebc7de22 5032
be44eb28
MCC		 5033 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5034 if (status < 0)
5035 goto error;
5036 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5037 if (status < 0)
5038 goto error;
5039 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5040 if (status < 0)
5041 goto error;
5042 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5043 if (status < 0)
5044 goto error;
5045 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5046 if (status < 0)
5047 goto error;
5048 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5049 if (status < 0)
5050 goto error;
5051 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5052error:
5053 if (status < 0)
5054 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22
OE		 5055
5056 return status;
43dd07f7
RM		 5057}
5058
5059/*============================================================================*/
5060
5061/**
5062* \brief QAM256 specific setup
5063* \param demod: instance of demod.
5064* \return DRXStatus_t.
5065*/
5066static int SetQAM256(struct drxk_state *state)
5067{
ebc7de22
OE		 5068 int status = 0;
5069
2da67501 5070 dprintk(1, "\n");
be44eb28
MCC		 5071 /* QAM Equalizer Setup */
5072 /* Equalizer */
5073 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5074 if (status < 0)
5075 goto error;
5076 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5077 if (status < 0)
5078 goto error;
5079 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5080 if (status < 0)
5081 goto error;
5082 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5083 if (status < 0)
5084 goto error;
5085 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5086 if (status < 0)
5087 goto error;
5088 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5089 if (status < 0)
5090 goto error;
ebc7de22 5091
be44eb28
MCC		 5092 /* Decision Feedback Equalizer */
5093 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5094 if (status < 0)
5095 goto error;
5096 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5097 if (status < 0)
5098 goto error;
5099 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5100 if (status < 0)
5101 goto error;
5102 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5103 if (status < 0)
5104 goto error;
5105 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5106 if (status < 0)
5107 goto error;
5108 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5109 if (status < 0)
5110 goto error;
ebc7de22 5111
be44eb28
MCC		 5112 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5113 if (status < 0)
5114 goto error;
5115 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5116 if (status < 0)
5117 goto error;
5118 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5119 if (status < 0)
5120 goto error;
ebc7de22 5121
be44eb28 5122 /* QAM Slicer Settings */
ebc7de22 5123
be44eb28
MCC		 5124 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5125 if (status < 0)
5126 goto error;
ebc7de22 5127
ebc7de22 5128
be44eb28 5129 /* QAM Loop Controller Coeficients */
ea90f011 5130
be44eb28
MCC		 5131 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5132 if (status < 0)
5133 goto error;
5134 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5135 if (status < 0)
5136 goto error;
5137 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5138 if (status < 0)
5139 goto error;
5140 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5141 if (status < 0)
5142 goto error;
5143 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5144 if (status < 0)
5145 goto error;
5146 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5147 if (status < 0)
5148 goto error;
5149 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5150 if (status < 0)
5151 goto error;
5152 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5153 if (status < 0)
5154 goto error;
ebc7de22 5155
be44eb28
MCC		 5156 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5157 if (status < 0)
5158 goto error;
5159 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5160 if (status < 0)
5161 goto error;
5162 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5163 if (status < 0)
5164 goto error;
5165 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5166 if (status < 0)
5167 goto error;
5168 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5169 if (status < 0)
5170 goto error;
5171 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5172 if (status < 0)
5173 goto error;
5174 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5175 if (status < 0)
5176 goto error;
5177 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5178 if (status < 0)
5179 goto error;
5180 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5181 if (status < 0)
5182 goto error;
5183 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5184 if (status < 0)
5185 goto error;
5186 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5187 if (status < 0)
5188 goto error;
5189 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5190 if (status < 0)
5191 goto error;
ebc7de22 5192
ebc7de22 5193
be44eb28 5194 /* QAM State Machine (FSM) Thresholds */
ebc7de22 5195
be44eb28
MCC		 5196 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5197 if (status < 0)
5198 goto error;
5199 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5200 if (status < 0)
5201 goto error;
5202 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5203 if (status < 0)
5204 goto error;
5205 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5206 if (status < 0)
5207 goto error;
5208 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5209 if (status < 0)
5210 goto error;
5211 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5212 if (status < 0)
5213 goto error;
ebc7de22 5214
be44eb28
MCC		 5215 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5216 if (status < 0)
5217 goto error;
5218 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5219 if (status < 0)
5220 goto error;
5221 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5222 if (status < 0)
5223 goto error;
ebc7de22 5224
ebc7de22 5225
be44eb28 5226 /* QAM FSM Tracking Parameters */
ebc7de22 5227
be44eb28
MCC		 5228 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5229 if (status < 0)
5230 goto error;
5231 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5232 if (status < 0)
5233 goto error;
5234 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5235 if (status < 0)
5236 goto error;
5237 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5238 if (status < 0)
5239 goto error;
5240 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5241 if (status < 0)
5242 goto error;
5243 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5244 if (status < 0)
5245 goto error;
5246 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5247error:
5248 if (status < 0)
5249 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5250 return status;
43dd07f7
RM		 5251}
5252
5253
5254/*============================================================================*/
5255/**
5256* \brief Reset QAM block.
5257* \param demod: instance of demod.
5258* \param channel: pointer to channel data.
5259* \return DRXStatus_t.
5260*/
5261static int QAMResetQAM(struct drxk_state *state)
5262{
ebc7de22
OE		 5263 int status;
5264 u16 cmdResult;
43dd07f7 5265
2da67501 5266 dprintk(1, "\n");
be44eb28
MCC		 5267 /* Stop QAM comstate->m_exec */
5268 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5269 if (status < 0)
5270 goto error;
43dd07f7 5271
be44eb28
MCC		 5272 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5273error:
5274 if (status < 0)
5275 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5276 return status;
43dd07f7
RM		 5277}
5278
5279/*============================================================================*/
5280
5281/**
5282* \brief Set QAM symbolrate.
5283* \param demod: instance of demod.
5284* \param channel: pointer to channel data.
5285* \return DRXStatus_t.
5286*/
5287static int QAMSetSymbolrate(struct drxk_state *state)
5288{
ebc7de22
OE		 5289 u32 adcFrequency = 0;
5290 u32 symbFreq = 0;
5291 u32 iqmRcRate = 0;
5292 u16 ratesel = 0;
5293 u32 lcSymbRate = 0;
5294 int status;
5295
2da67501 5296 dprintk(1, "\n");
be44eb28
MCC		 5297 /* Select & calculate correct IQM rate */
5298 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5299 ratesel = 0;
ed5452a2
MCC		 5300 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
5301 if (state->props.symbol_rate <= 1188750)
be44eb28 5302 ratesel = 3;
ed5452a2 5303 else if (state->props.symbol_rate <= 2377500)
be44eb28 5304 ratesel = 2;
ed5452a2 5305 else if (state->props.symbol_rate <= 4755000)
be44eb28
MCC		 5306 ratesel = 1;
5307 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5308 if (status < 0)
5309 goto error;
ebc7de22 5310
be44eb28
MCC		 5311 /*
5312 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5313 */
ed5452a2 5314 symbFreq = state->props.symbol_rate * (1 << ratesel);
be44eb28
MCC		 5315 if (symbFreq == 0) {
5316 /* Divide by zero */
5317 status = -EINVAL;
5318 goto error;
5319 }
5320 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5321 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5322 (1 << 23);
5323 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5324 if (status < 0)
5325 goto error;
5326 state->m_iqmRcRate = iqmRcRate;
5327 /*
5328 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5329 */
ed5452a2 5330 symbFreq = state->props.symbol_rate;
be44eb28
MCC		 5331 if (adcFrequency == 0) {
5332 /* Divide by zero */
5333 status = -EINVAL;
5334 goto error;
5335 }
5336 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5337 (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5338 16);
5339 if (lcSymbRate > 511)
5340 lcSymbRate = 511;
5341 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5342
5343error:
5344 if (status < 0)
5345 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5346 return status;
43dd07f7
RM		 5347}
5348
5349/*============================================================================*/
5350
5351/**
5352* \brief Get QAM lock status.
5353* \param demod: instance of demod.
5354* \param channel: pointer to channel data.
5355* \return DRXStatus_t.
5356*/
5357
5358static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5359{
5360 int status;
ebc7de22 5361 u16 Result[2] = { 0, 0 };
43dd07f7 5362
2da67501 5363 dprintk(1, "\n");
be44eb28
MCC		 5364 *pLockStatus = NOT_LOCKED;
5365 status = scu_command(state,
ebc7de22
OE		 5366 SCU_RAM_COMMAND_STANDARD_QAM |
5367 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5368 Result);
5369 if (status < 0)
e0e6ecaf 5370 printk(KERN_ERR "drxk: %s status = %08x\n", __func__, status);
ebc7de22
OE		 5371
5372 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
43dd07f7 5373 /* 0x0000 NOT LOCKED */
ebc7de22 5374 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
43dd07f7
RM		 5375 /* 0x4000 DEMOD LOCKED */
5376 *pLockStatus = DEMOD_LOCK;
ebc7de22 5377 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
43dd07f7
RM		 5378 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5379 *pLockStatus = MPEG_LOCK;
ebc7de22 5380 } else {
43dd07f7
RM		 5381 /* 0xC000 NEVER LOCKED */
5382 /* (system will never be able to lock to the signal) */
5383 /* TODO: check this, intermediate & standard specific lock states are not
5384 taken into account here */
5385 *pLockStatus = NEVER_LOCK;
5386 }
5387 return status;
5388}
5389
5390#define QAM_MIRROR__M 0x03
5391#define QAM_MIRROR_NORMAL 0x00
5392#define QAM_MIRRORED 0x01
5393#define QAM_MIRROR_AUTO_ON 0x02
5394#define QAM_LOCKRANGE__M 0x10
5395#define QAM_LOCKRANGE_NORMAL 0x10
5396
ebc7de22
OE		 5397static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5398 s32 tunerFreqOffset)
43dd07f7 5399{
be44eb28 5400 int status;
ebc7de22
OE		 5401 u16 setParamParameters[4] = { 0, 0, 0, 0 };
5402 u16 cmdResult;
43dd07f7 5403
2da67501 5404 dprintk(1, "\n");
be44eb28 5405 /*
119faf90
MCC		 5406 * STEP 1: reset demodulator
5407 * resets FEC DI and FEC RS
5408 * resets QAM block
5409 * resets SCU variables
5410 */
be44eb28
MCC		 5411 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5412 if (status < 0)
5413 goto error;
5414 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5415 if (status < 0)
5416 goto error;
5417 status = QAMResetQAM(state);
5418 if (status < 0)
5419 goto error;
43dd07f7 5420
be44eb28 5421 /*
119faf90
MCC		 5422 * STEP 2: configure demodulator
5423 * -set params; resets IQM,QAM,FEC HW; initializes some
5424 * SCU variables
5425 */
be44eb28
MCC		 5426 status = QAMSetSymbolrate(state);
5427 if (status < 0)
5428 goto error;
5429
be44eb28 5430 /* Set params */
ed5452a2 5431 switch (state->props.modulation) {
be44eb28
MCC		 5432 case QAM_256:
5433 state->m_Constellation = DRX_CONSTELLATION_QAM256;
5434 break;
5435 case QAM_AUTO:
5436 case QAM_64:
5437 state->m_Constellation = DRX_CONSTELLATION_QAM64;
5438 break;
5439 case QAM_16:
5440 state->m_Constellation = DRX_CONSTELLATION_QAM16;
5441 break;
5442 case QAM_32:
5443 state->m_Constellation = DRX_CONSTELLATION_QAM32;
5444 break;
5445 case QAM_128:
5446 state->m_Constellation = DRX_CONSTELLATION_QAM128;
5447 break;
5448 default:
5449 status = -EINVAL;
5450 break;
5451 }
5452 if (status < 0)
5453 goto error;
ed5452a2 5454 setParamParameters[0] = state->m_Constellation; /* modulation */
be44eb28 5455 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
119faf90
MCC		 5456 if (state->m_OperationMode == OM_QAM_ITU_C)
5457 setParamParameters[2] = QAM_TOP_ANNEX_C;
5458 else
5459 setParamParameters[2] = QAM_TOP_ANNEX_A;
5460 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5461 /* Env parameters */
5462 /* check for LOCKRANGE Extented */
5463 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
43dd07f7 5464
be44eb28 5465 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult);
5eee2bb2
MCC		 5466 if (status < 0) {
5467 /* Fall-back to the simpler call */
5eee2bb2 5468 if (state->m_OperationMode == OM_QAM_ITU_C)
119faf90 5469 setParamParameters[0] = QAM_TOP_ANNEX_C;
5eee2bb2 5470 else
119faf90
MCC		 5471 setParamParameters[0] = QAM_TOP_ANNEX_A;
5472 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 1, setParamParameters, 1, &cmdResult);
5473 if (status < 0)
5474 goto error;
43dd07f7 5475
ed5452a2 5476 setParamParameters[0] = state->m_Constellation; /* modulation */
5eee2bb2 5477 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5eee2bb2
MCC		 5478 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult);
5479 }
5480 if (status < 0)
5481 goto error;
43dd07f7 5482
119faf90
MCC		 5483 /*
5484 * STEP 3: enable the system in a mode where the ADC provides valid
ed5452a2 5485 * signal setup modulation independent registers
119faf90 5486 */
ea90f011 5487#if 0
be44eb28
MCC		 5488 status = SetFrequency(channel, tunerFreqOffset));
5489 if (status < 0)
5490 goto error;
ea90f011 5491#endif
be44eb28
MCC		 5492 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5493 if (status < 0)
5494 goto error;
43dd07f7 5495
be44eb28 5496 /* Setup BER measurement */
ed5452a2 5497 status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate);
be44eb28
MCC		 5498 if (status < 0)
5499 goto error;
ebc7de22 5500
be44eb28
MCC		 5501 /* Reset default values */
5502 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5503 if (status < 0)
5504 goto error;
5505 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5506 if (status < 0)
5507 goto error;
ea90f011 5508
be44eb28
MCC		 5509 /* Reset default LC values */
5510 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5511 if (status < 0)
5512 goto error;
5513 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5514 if (status < 0)
5515 goto error;
5516 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5517 if (status < 0)
5518 goto error;
5519 status = write16(state, QAM_LC_MODE__A, 7);
5520 if (status < 0)
5521 goto error;
ebc7de22 5522
be44eb28
MCC		 5523 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5524 if (status < 0)
5525 goto error;
5526 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5527 if (status < 0)
5528 goto error;
5529 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5530 if (status < 0)
5531 goto error;
5532 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5533 if (status < 0)
5534 goto error;
5535 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5536 if (status < 0)
5537 goto error;
5538 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5539 if (status < 0)
5540 goto error;
5541 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5542 if (status < 0)
5543 goto error;
5544 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5545 if (status < 0)
5546 goto error;
5547 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5548 if (status < 0)
5549 goto error;
5550 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5551 if (status < 0)
5552 goto error;
5553 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5554 if (status < 0)
5555 goto error;
5556 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5557 if (status < 0)
5558 goto error;
5559 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5560 if (status < 0)
5561 goto error;
5562 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5563 if (status < 0)
5564 goto error;
5565 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5566 if (status < 0)
5567 goto error;
ebc7de22 5568
be44eb28
MCC		 5569 /* Mirroring, QAM-block starting point not inverted */
5570 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5571 if (status < 0)
5572 goto error;
ebc7de22 5573
be44eb28
MCC		 5574 /* Halt SCU to enable safe non-atomic accesses */
5575 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5576 if (status < 0)
5577 goto error;
ebc7de22 5578
ed5452a2
MCC		 5579 /* STEP 4: modulation specific setup */
5580 switch (state->props.modulation) {
be44eb28
MCC		 5581 case QAM_16:
5582 status = SetQAM16(state);
5583 break;
5584 case QAM_32:
5585 status = SetQAM32(state);
5586 break;
5587 case QAM_AUTO:
5588 case QAM_64:
5589 status = SetQAM64(state);
5590 break;
5591 case QAM_128:
5592 status = SetQAM128(state);
5593 break;
5594 case QAM_256:
5595 status = SetQAM256(state);
5596 break;
5597 default:
5598 status = -EINVAL;
5599 break;
5600 }
5601 if (status < 0)
5602 goto error;
ebc7de22 5603
be44eb28
MCC		 5604 /* Activate SCU to enable SCU commands */
5605 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5606 if (status < 0)
5607 goto error;
ebc7de22 5608
be44eb28 5609 /* Re-configure MPEG output, requires knowledge of channel bitrate */
ed5452a2 5610 /* extAttr->currentChannel.modulation = channel->modulation; */
be44eb28
MCC		 5611 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5612 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5613 if (status < 0)
5614 goto error;
ebc7de22 5615
be44eb28
MCC		 5616 /* Start processes */
5617 status = MPEGTSStart(state);
5618 if (status < 0)
5619 goto error;
5620 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5621 if (status < 0)
5622 goto error;
5623 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5624 if (status < 0)
5625 goto error;
5626 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5627 if (status < 0)
5628 goto error;
ebc7de22 5629
be44eb28
MCC		 5630 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5631 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5632 if (status < 0)
5633 goto error;
ebc7de22 5634
be44eb28
MCC		 5635 /* update global DRXK data container */
5636/*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
ebc7de22 5637
be44eb28 5638error:
ebc7de22 5639 if (status < 0)
be44eb28 5640 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5641 return status;
43dd07f7
RM		 5642}
5643
ebc7de22
OE		 5644static int SetQAMStandard(struct drxk_state *state,
5645 enum OperationMode oMode)
43dd07f7 5646{
be44eb28 5647 int status;
43dd07f7
RM		 5648#ifdef DRXK_QAM_TAPS
5649#define DRXK_QAMA_TAPS_SELECT
5650#include "drxk_filters.h"
5651#undef DRXK_QAMA_TAPS_SELECT
43dd07f7
RM		 5652#endif
5653
f1b82970
MCC		 5654 dprintk(1, "\n");
5655
be44eb28
MCC		 5656 /* added antenna switch */
5657 SwitchAntennaToQAM(state);
ebc7de22 5658
be44eb28
MCC		 5659 /* Ensure correct power-up mode */
5660 status = PowerUpQAM(state);
5661 if (status < 0)
5662 goto error;
5663 /* Reset QAM block */
5664 status = QAMResetQAM(state);
5665 if (status < 0)
5666 goto error;
ebc7de22 5667
be44eb28 5668 /* Setup IQM */
ebc7de22 5669
be44eb28
MCC		 5670 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5671 if (status < 0)
5672 goto error;
5673 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5674 if (status < 0)
5675 goto error;
ebc7de22 5676
be44eb28
MCC		 5677 /* Upload IQM Channel Filter settings by
5678 boot loader from ROM table */
5679 switch (oMode) {
5680 case OM_QAM_ITU_A:
5681 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5682 break;
5683 case OM_QAM_ITU_C:
5684 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
ea90f011 5685 if (status < 0)
be44eb28
MCC		 5686 goto error;
5687 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5688 break;
5689 default:
5690 status = -EINVAL;
5691 }
5692 if (status < 0)
5693 goto error;
ea90f011 5694
be44eb28
MCC		 5695 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5696 if (status < 0)
5697 goto error;
5698 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5699 if (status < 0)
5700 goto error;
5701 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5702 if (status < 0)
5703 goto error;
ea90f011 5704
be44eb28
MCC		 5705 status = write16(state, IQM_RC_STRETCH__A, 21);
5706 if (status < 0)
5707 goto error;
5708 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5709 if (status < 0)
5710 goto error;
5711 status = write16(state, IQM_AF_CLP_TH__A, 448);
5712 if (status < 0)
5713 goto error;
5714 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5715 if (status < 0)
5716 goto error;
5717 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5718 if (status < 0)
5719 goto error;
ea90f011 5720
be44eb28
MCC		 5721 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5722 if (status < 0)
5723 goto error;
5724 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5725 if (status < 0)
5726 goto error;
5727 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5728 if (status < 0)
5729 goto error;
5730 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5731 if (status < 0)
5732 goto error;
ebc7de22 5733
be44eb28
MCC		 5734 /* IQM Impulse Noise Processing Unit */
5735 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5736 if (status < 0)
5737 goto error;
5738 status = write16(state, IQM_CF_DATATH__A, 1000);
5739 if (status < 0)
5740 goto error;
5741 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5742 if (status < 0)
5743 goto error;
5744 status = write16(state, IQM_CF_DET_LCT__A, 0);
5745 if (status < 0)
5746 goto error;
5747 status = write16(state, IQM_CF_WND_LEN__A, 1);
5748 if (status < 0)
5749 goto error;
5750 status = write16(state, IQM_CF_PKDTH__A, 1);
5751 if (status < 0)
5752 goto error;
5753 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5754 if (status < 0)
5755 goto error;
ebc7de22 5756
be44eb28
MCC		 5757 /* turn on IQMAF. Must be done before setAgc**() */
5758 status = SetIqmAf(state, true);
5759 if (status < 0)
5760 goto error;
5761 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5762 if (status < 0)
5763 goto error;
ebc7de22 5764
be44eb28
MCC		 5765 /* IQM will not be reset from here, sync ADC and update/init AGC */
5766 status = ADCSynchronization(state);
5767 if (status < 0)
5768 goto error;
ebc7de22 5769
be44eb28
MCC		 5770 /* Set the FSM step period */
5771 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5772 if (status < 0)
5773 goto error;
ebc7de22 5774
be44eb28
MCC		 5775 /* Halt SCU to enable safe non-atomic accesses */
5776 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5777 if (status < 0)
5778 goto error;
ebc7de22 5779
be44eb28
MCC		 5780 /* No more resets of the IQM, current standard correctly set =>
5781 now AGCs can be configured. */
ebc7de22 5782
be44eb28
MCC		 5783 status = InitAGC(state, true);
5784 if (status < 0)
5785 goto error;
5786 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5787 if (status < 0)
5788 goto error;
ebc7de22 5789
be44eb28
MCC		 5790 /* Configure AGC's */
5791 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5792 if (status < 0)
5793 goto error;
5794 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5795 if (status < 0)
5796 goto error;
ebc7de22 5797
be44eb28
MCC		 5798 /* Activate SCU to enable SCU commands */
5799 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5800error:
5801 if (status < 0)
5802 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5803 return status;
43dd07f7
RM		 5804}
5805
5806static int WriteGPIO(struct drxk_state *state)
5807{
ebc7de22
OE		 5808 int status;
5809 u16 value = 0;
5810
2da67501 5811 dprintk(1, "\n");
be44eb28
MCC		 5812 /* stop lock indicator process */
5813 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5814 if (status < 0)
5815 goto error;
ebc7de22 5816
be44eb28
MCC		 5817 /* Write magic word to enable pdr reg write */
5818 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5819 if (status < 0)
5820 goto error;
ebc7de22 5821
be44eb28 5822 if (state->m_hasSAWSW) {
90796aca
MCC		 5823 if (state->UIO_mask & 0x0001) { /* UIO-1 */
5824 /* write to io pad configuration register - output mode */
5825 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5826 if (status < 0)
5827 goto error;
ebc7de22 5828
90796aca
MCC		 5829 /* use corresponding bit in io data output registar */
5830 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5831 if (status < 0)
5832 goto error;
5833 if ((state->m_GPIO & 0x0001) == 0)
5834 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5835 else
5836 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5837 /* write back to io data output register */
5838 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5839 if (status < 0)
5840 goto error;
5841 }
5842 if (state->UIO_mask & 0x0002) { /* UIO-2 */
5843 /* write to io pad configuration register - output mode */
14053443 5844 status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_GPIOCfg);
90796aca
MCC		 5845 if (status < 0)
5846 goto error;
be44eb28 5847
90796aca
MCC		 5848 /* use corresponding bit in io data output registar */
5849 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5850 if (status < 0)
5851 goto error;
5852 if ((state->m_GPIO & 0x0002) == 0)
5853 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5854 else
5855 value |= 0x4000; /* write one to 14th bit - 2st UIO */
5856 /* write back to io data output register */
5857 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5858 if (status < 0)
5859 goto error;
5860 }
5861 if (state->UIO_mask & 0x0004) { /* UIO-3 */
5862 /* write to io pad configuration register - output mode */
14053443 5863 status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_GPIOCfg);
90796aca
MCC		 5864 if (status < 0)
5865 goto error;
5866
5867 /* use corresponding bit in io data output registar */
5868 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5869 if (status < 0)
5870 goto error;
5871 if ((state->m_GPIO & 0x0004) == 0)
5872 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5873 else
5874 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5875 /* write back to io data output register */
5876 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5877 if (status < 0)
5878 goto error;
5879 }
be44eb28
MCC		 5880 }
5881 /* Write magic word to disable pdr reg write */
5882 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5883error:
5884 if (status < 0)
5885 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5886 return status;
43dd07f7
RM		 5887}
5888
5889static int SwitchAntennaToQAM(struct drxk_state *state)
5890{
147e110b 5891 int status = 0;
90796aca 5892 bool gpio_state;
ebc7de22 5893
2da67501 5894 dprintk(1, "\n");
147e110b 5895
90796aca
MCC		 5896 if (!state->antenna_gpio)
5897 return 0;
5898
5899 gpio_state = state->m_GPIO & state->antenna_gpio;
5900
5901 if (state->antenna_dvbt ^ gpio_state) {
5902 /* Antenna is on DVB-T mode. Switch */
5903 if (state->antenna_dvbt)
5904 state->m_GPIO &= ~state->antenna_gpio;
5905 else
5906 state->m_GPIO |= state->antenna_gpio;
5907 status = WriteGPIO(state);
ebc7de22 5908 }
be44eb28
MCC		 5909 if (status < 0)
5910 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5911 return status;
43dd07f7
RM		 5912}
5913
5914static int SwitchAntennaToDVBT(struct drxk_state *state)
5915{
147e110b 5916 int status = 0;
90796aca 5917 bool gpio_state;
ebc7de22 5918
2da67501 5919 dprintk(1, "\n");
90796aca
MCC		 5920
5921 if (!state->antenna_gpio)
5922 return 0;
5923
5924 gpio_state = state->m_GPIO & state->antenna_gpio;
5925
5926 if (!(state->antenna_dvbt ^ gpio_state)) {
5927 /* Antenna is on DVB-C mode. Switch */
5928 if (state->antenna_dvbt)
5929 state->m_GPIO |= state->antenna_gpio;
5930 else
5931 state->m_GPIO &= ~state->antenna_gpio;
5932 status = WriteGPIO(state);
43dd07f7 5933 }
be44eb28
MCC		 5934 if (status < 0)
5935 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 5936 return status;
5937}
5938
5939
5940static int PowerDownDevice(struct drxk_state *state)
5941{
5942 /* Power down to requested mode */
5943 /* Backup some register settings */
5944 /* Set pins with possible pull-ups connected to them in input mode */
5945 /* Analog power down */
5946 /* ADC power down */
5947 /* Power down device */
5948 int status;
2da67501
MCC		 5949
5950 dprintk(1, "\n");
be44eb28
MCC		 5951 if (state->m_bPDownOpenBridge) {
5952 /* Open I2C bridge before power down of DRXK */
5953 status = ConfigureI2CBridge(state, true);
ea90f011 5954 if (status < 0)
be44eb28
MCC		 5955 goto error;
5956 }
5957 /* driver 0.9.0 */
5958 status = DVBTEnableOFDMTokenRing(state, false);
5959 if (status < 0)
5960 goto error;
43dd07f7 5961
be44eb28 5962 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
ebc7de22 5963 if (status < 0)
be44eb28
MCC		 5964 goto error;
5965 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5966 if (status < 0)
5967 goto error;
5968 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5969 status = HI_CfgCommand(state);
5970error:
5971 if (status < 0)
5972 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5973
be44eb28 5974 return status;
43dd07f7
RM		 5975}
5976
43dd07f7
RM		 5977static int init_drxk(struct drxk_state *state)
5978{
177bc7da 5979 int status = 0, n = 0;
ebc7de22 5980 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
43dd07f7
RM		 5981 u16 driverVersion;
5982
2da67501 5983 dprintk(1, "\n");
43dd07f7 5984 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
be44eb28
MCC		 5985 status = PowerUpDevice(state);
5986 if (status < 0)
5987 goto error;
5988 status = DRXX_Open(state);
5989 if (status < 0)
5990 goto error;
5991 /* Soft reset of OFDM-, sys- and osc-clockdomain */
5992 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
5993 if (status < 0)
5994 goto error;
5995 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5996 if (status < 0)
5997 goto error;
5998 /* TODO is this needed, if yes how much delay in worst case scenario */
5999 msleep(1);
6000 state->m_DRXK_A3_PATCH_CODE = true;
6001 status = GetDeviceCapabilities(state);
6002 if (status < 0)
6003 goto error;
6004
6005 /* Bridge delay, uses oscilator clock */
6006 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6007 /* SDA brdige delay */
6008 state->m_HICfgBridgeDelay =
6009 (u16) ((state->m_oscClockFreq / 1000) *
6010 HI_I2C_BRIDGE_DELAY) / 1000;
6011 /* Clipping */
6012 if (state->m_HICfgBridgeDelay >
6013 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
ebc7de22 6014 state->m_HICfgBridgeDelay =
be44eb28
MCC		 6015 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6016 }
6017 /* SCL bridge delay, same as SDA for now */
6018 state->m_HICfgBridgeDelay +=
6019 state->m_HICfgBridgeDelay <<
6020 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6021
6022 status = InitHI(state);
6023 if (status < 0)
6024 goto error;
6025 /* disable various processes */
43dd07f7 6026#if NOA1ROM
be44eb28
MCC		 6027 if (!(state->m_DRXK_A1_ROM_CODE)
6028 && !(state->m_DRXK_A2_ROM_CODE))
43dd07f7 6029#endif
be44eb28
MCC		 6030 {
6031 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
ea90f011 6032 if (status < 0)
be44eb28
MCC		 6033 goto error;
6034 }
43dd07f7 6035
be44eb28
MCC		 6036 /* disable MPEG port */
6037 status = MPEGTSDisable(state);
6038 if (status < 0)
6039 goto error;
43dd07f7 6040
be44eb28
MCC		 6041 /* Stop AUD and SCU */
6042 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6043 if (status < 0)
6044 goto error;
6045 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6046 if (status < 0)
6047 goto error;
e4f4f875 6048
be44eb28
MCC		 6049 /* enable token-ring bus through OFDM block for possible ucode upload */
6050 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6051 if (status < 0)
6052 goto error;
43dd07f7 6053
be44eb28
MCC		 6054 /* include boot loader section */
6055 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6056 if (status < 0)
6057 goto error;
6058 status = BLChainCmd(state, 0, 6, 100);
6059 if (status < 0)
6060 goto error;
43dd07f7 6061
177bc7da
MCC		 6062 if (state->fw) {
6063 status = DownloadMicrocode(state, state->fw->data,
6064 state->fw->size);
6065 if (status < 0)
6066 goto error;
6067 }
43dd07f7 6068
be44eb28
MCC		 6069 /* disable token-ring bus through OFDM block for possible ucode upload */
6070 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6071 if (status < 0)
6072 goto error;
ebc7de22 6073
be44eb28
MCC		 6074 /* Run SCU for a little while to initialize microcode version numbers */
6075 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6076 if (status < 0)
6077 goto error;
6078 status = DRXX_Open(state);
6079 if (status < 0)
6080 goto error;
6081 /* added for test */
6082 msleep(30);
43dd07f7 6083
be44eb28
MCC		 6084 powerMode = DRXK_POWER_DOWN_OFDM;
6085 status = CtrlPowerMode(state, &powerMode);
6086 if (status < 0)
6087 goto error;
6088
6089 /* Stamp driver version number in SCU data RAM in BCD code
6090 Done to enable field application engineers to retreive drxdriver version
6091 via I2C from SCU RAM.
6092 Not using SCU command interface for SCU register access since no
6093 microcode may be present.
6094 */
6095 driverVersion =
6096 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6097 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6098 ((DRXK_VERSION_MAJOR % 10) << 4) +
6099 (DRXK_VERSION_MINOR % 10);
6100 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6101 if (status < 0)
6102 goto error;
6103 driverVersion =
6104 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6105 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6106 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6107 (DRXK_VERSION_PATCH % 10);
6108 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6109 if (status < 0)
6110 goto error;
6111
6112 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6113 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6114 DRXK_VERSION_PATCH);
6115
6116 /* Dirty fix of default values for ROM/PATCH microcode
6117 Dirty because this fix makes it impossible to setup suitable values
6118 before calling DRX_Open. This solution requires changes to RF AGC speed
6119 to be done via the CTRL function after calling DRX_Open */
6120
6121 /* m_dvbtRfAgcCfg.speed = 3; */
6122
6123 /* Reset driver debug flags to 0 */
6124 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6125 if (status < 0)
6126 goto error;
6127 /* driver 0.9.0 */
6128 /* Setup FEC OC:
6129 NOTE: No more full FEC resets allowed afterwards!! */
6130 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6131 if (status < 0)
6132 goto error;
6133 /* MPEGTS functions are still the same */
6134 status = MPEGTSDtoInit(state);
6135 if (status < 0)
6136 goto error;
6137 status = MPEGTSStop(state);
6138 if (status < 0)
6139 goto error;
6140 status = MPEGTSConfigurePolarity(state);
6141 if (status < 0)
6142 goto error;
6143 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6144 if (status < 0)
6145 goto error;
6146 /* added: configure GPIO */
6147 status = WriteGPIO(state);
6148 if (status < 0)
6149 goto error;
43dd07f7 6150
be44eb28 6151 state->m_DrxkState = DRXK_STOPPED;
43dd07f7 6152
be44eb28
MCC		 6153 if (state->m_bPowerDown) {
6154 status = PowerDownDevice(state);
ea90f011 6155 if (status < 0)
be44eb28
MCC		 6156 goto error;
6157 state->m_DrxkState = DRXK_POWERED_DOWN;
6158 } else
ebc7de22 6159 state->m_DrxkState = DRXK_STOPPED;
177bc7da
MCC		 6160
6161 /* Initialize the supported delivery systems */
6162 n = 0;
6163 if (state->m_hasDVBC) {
6164 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6165 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6166 strlcat(state->frontend.ops.info.name, " DVB-C",
6167 sizeof(state->frontend.ops.info.name));
6168 }
6169 if (state->m_hasDVBT) {
6170 state->frontend.ops.delsys[n++] = SYS_DVBT;
6171 strlcat(state->frontend.ops.info.name, " DVB-T",
6172 sizeof(state->frontend.ops.info.name));
6173 }
43dd07f7 6174 }
be44eb28
MCC		 6175error:
6176 if (status < 0)
6177 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7 6178
e716adac 6179 return status;
43dd07f7
RM		 6180}
6181
177bc7da
MCC		 6182static void load_firmware_cb(const struct firmware *fw,
6183 void *context)
6184{
6185 struct drxk_state *state = context;
6186
6187 if (!fw) {
6188 printk(KERN_ERR
6189 "drxk: Could not load firmware file %s.\n",
6190 state->microcode_name);
6191 printk(KERN_INFO
6192 "drxk: Copy %s to your hotplug directory!\n",
6193 state->microcode_name);
6194 state->microcode_name = NULL;
6195
6196 /*
6197 * As firmware is now load asynchronous, it is not possible
6198 * anymore to fail at frontend attach. We might silently
6199 * return here, and hope that the driver won't crash.
6200 * We might also change all DVB callbacks to return -ENODEV
6201 * if the device is not initialized.
6202 * As the DRX-K devices have their own internal firmware,
6203 * let's just hope that it will match a firmware revision
6204 * compatible with this driver and proceed.
6205 */
6206 }
6207 state->fw = fw;
6208
6209 init_drxk(state);
6210}
6211
fa4b2a17 6212static void drxk_release(struct dvb_frontend *fe)
43dd07f7 6213{
ebc7de22
OE		 6214 struct drxk_state *state = fe->demodulator_priv;
6215
2da67501 6216 dprintk(1, "\n");
177bc7da
MCC		 6217 if (state->fw)
6218 release_firmware(state->fw);
6219
43dd07f7
RM		 6220 kfree(state);
6221}
6222
fa4b2a17 6223static int drxk_sleep(struct dvb_frontend *fe)
43dd07f7 6224{
ebc7de22 6225 struct drxk_state *state = fe->demodulator_priv;
43dd07f7 6226
2da67501 6227 dprintk(1, "\n");
43dd07f7 6228 ShutDown(state);
43dd07f7
RM		 6229 return 0;
6230}
6231
ebc7de22 6232static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
43dd07f7
RM		 6233{
6234 struct drxk_state *state = fe->demodulator_priv;
6235
2da67501 6236 dprintk(1, "%s\n", enable ? "enable" : "disable");
43dd07f7
RM		 6237 return ConfigureI2CBridge(state, enable ? true : false);
6238}
6239
ed5452a2 6240static int drxk_set_parameters(struct dvb_frontend *fe)
43dd07f7 6241{
ed5452a2 6242 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6cb393c8 6243 u32 delsys = p->delivery_system, old_delsys;
43dd07f7
RM		 6244 struct drxk_state *state = fe->demodulator_priv;
6245 u32 IF;
6246
2da67501 6247 dprintk(1, "\n");
8513e144
MCC		 6248
6249 if (!fe->ops.tuner_ops.get_if_frequency) {
6250 printk(KERN_ERR
6251 "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6252 return -EINVAL;
6253 }
6254
fa4b2a17
MCC		 6255 if (fe->ops.i2c_gate_ctrl)
6256 fe->ops.i2c_gate_ctrl(fe, 1);
6257 if (fe->ops.tuner_ops.set_params)
6258 fe->ops.tuner_ops.set_params(fe);
6259 if (fe->ops.i2c_gate_ctrl)
6260 fe->ops.i2c_gate_ctrl(fe, 0);
6cb393c8
MCC		 6261
6262 old_delsys = state->props.delivery_system;
fa4b2a17
MCC		 6263 state->props = *p;
6264
6cb393c8
MCC		 6265 if (old_delsys != delsys) {
6266 ShutDown(state);
6267 switch (delsys) {
6268 case SYS_DVBC_ANNEX_A:
6269 case SYS_DVBC_ANNEX_C:
6270 if (!state->m_hasDVBC)
6271 return -EINVAL;
6272 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
6273 if (state->m_itut_annex_c)
6274 SetOperationMode(state, OM_QAM_ITU_C);
6275 else
6276 SetOperationMode(state, OM_QAM_ITU_A);
fa4b2a17 6277 break;
6cb393c8
MCC		 6278 case SYS_DVBT:
6279 if (!state->m_hasDVBT)
6280 return -EINVAL;
6281 SetOperationMode(state, OM_DVBT);
6282 break;
6283 default:
fa4b2a17 6284 return -EINVAL;
6cb393c8 6285 }
2440f7af 6286 }
8513e144 6287
8513e144 6288 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
43dd07f7
RM		 6289 Start(state, 0, IF);
6290
e0e6ecaf 6291 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
ebc7de22 6292
43dd07f7
RM		 6293 return 0;
6294}
6295
43dd07f7
RM		 6296static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6297{
6298 struct drxk_state *state = fe->demodulator_priv;
6299 u32 stat;
6300
2da67501 6301 dprintk(1, "\n");
ebc7de22 6302 *status = 0;
43dd07f7 6303 GetLockStatus(state, &stat, 0);
ebc7de22
OE		 6304 if (stat == MPEG_LOCK)
6305 *status |= 0x1f;
6306 if (stat == FEC_LOCK)
6307 *status |= 0x0f;
6308 if (stat == DEMOD_LOCK)
6309 *status |= 0x07;
43dd07f7
RM		 6310 return 0;
6311}
6312
6313static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber)
6314{
2da67501
MCC		 6315 dprintk(1, "\n");
6316
ebc7de22 6317 *ber = 0;
43dd07f7
RM		 6318 return 0;
6319}
6320
ebc7de22
OE		 6321static int drxk_read_signal_strength(struct dvb_frontend *fe,
6322 u16 *strength)
43dd07f7
RM		 6323{
6324 struct drxk_state *state = fe->demodulator_priv;
be44eb28 6325 u32 val = 0;
43dd07f7 6326
2da67501 6327 dprintk(1, "\n");
43dd07f7 6328 ReadIFAgc(state, &val);
ebc7de22 6329 *strength = val & 0xffff;
43dd07f7
RM		 6330 return 0;
6331}
6332
6333static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6334{
6335 struct drxk_state *state = fe->demodulator_priv;
6336 s32 snr2;
6337
2da67501 6338 dprintk(1, "\n");
43dd07f7 6339 GetSignalToNoise(state, &snr2);
ebc7de22 6340 *snr = snr2 & 0xffff;
43dd07f7
RM		 6341 return 0;
6342}
6343
6344static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6345{
6346 struct drxk_state *state = fe->demodulator_priv;
6347 u16 err;
6348
2da67501 6349 dprintk(1, "\n");
43dd07f7
RM		 6350 DVBTQAMGetAccPktErr(state, &err);
6351 *ucblocks = (u32) err;
6352 return 0;
6353}
6354
fa4b2a17 6355static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
ebc7de22 6356 *sets)
43dd07f7 6357{
fa4b2a17 6358 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2da67501
MCC		 6359
6360 dprintk(1, "\n");
fa4b2a17
MCC		 6361 switch (p->delivery_system) {
6362 case SYS_DVBC_ANNEX_A:
6363 case SYS_DVBC_ANNEX_C:
dc66d7f4 6364 case SYS_DVBT:
fa4b2a17
MCC		 6365 sets->min_delay_ms = 3000;
6366 sets->max_drift = 0;
6367 sets->step_size = 0;
6368 return 0;
6369 default:
fa4b2a17
MCC		 6370 return -EINVAL;
6371 }
43dd07f7
RM		 6372}
6373
fa4b2a17
MCC		 6374static struct dvb_frontend_ops drxk_ops = {
6375 /* .delsys will be filled dynamically */
43dd07f7 6376 .info = {
fa4b2a17
MCC		 6377 .name = "DRXK",
6378 .frequency_min = 47000000,
6379 .frequency_max = 865000000,
6380 /* For DVB-C */
6381 .symbol_rate_min = 870000,
6382 .symbol_rate_max = 11700000,
6383 /* For DVB-T */
6384 .frequency_stepsize = 166667,
6385
6386 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6387 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6388 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6389 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6390 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6391 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6392 },
6393
6394 .release = drxk_release,
6395 .sleep = drxk_sleep,
43dd07f7
RM		 6396 .i2c_gate_ctrl = drxk_gate_ctrl,
6397
ed5452a2 6398 .set_frontend = drxk_set_parameters,
fa4b2a17 6399 .get_tune_settings = drxk_get_tune_settings,
43dd07f7
RM		 6400
6401 .read_status = drxk_read_status,
6402 .read_ber = drxk_read_ber,
6403 .read_signal_strength = drxk_read_signal_strength,
6404 .read_snr = drxk_read_snr,
6405 .read_ucblocks = drxk_read_ucblocks,
6406};
6407
0fc55e81 6408struct dvb_frontend *drxk_attach(const struct drxk_config *config,
fa4b2a17 6409 struct i2c_adapter *i2c)
43dd07f7
RM		 6410{
6411 struct drxk_state *state = NULL;
0fc55e81 6412 u8 adr = config->adr;
177bc7da 6413 int status;
43dd07f7 6414
2da67501 6415 dprintk(1, "\n");
ebc7de22 6416 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
43dd07f7
RM		 6417 if (!state)
6418 return NULL;
6419
ebc7de22
OE		 6420 state->i2c = i2c;
6421 state->demod_address = adr;
e076c92e 6422 state->single_master = config->single_master;
e4f4f875 6423 state->microcode_name = config->microcode_name;
f1fe1b75 6424 state->no_i2c_bridge = config->no_i2c_bridge;
90796aca
MCC		 6425 state->antenna_gpio = config->antenna_gpio;
6426 state->antenna_dvbt = config->antenna_dvbt;
82e7dbbd 6427 state->m_ChunkSize = config->chunk_size;
d5856813 6428 state->enable_merr_cfg = config->enable_merr_cfg;
90796aca 6429
67f04617
MCC		 6430 if (config->dynamic_clk) {
6431 state->m_DVBTStaticCLK = 0;
6432 state->m_DVBCStaticCLK = 0;
6433 } else {
6434 state->m_DVBTStaticCLK = 1;
6435 state->m_DVBCStaticCLK = 1;
6436 }
6437
6fb65a66
MCC		 6438
6439 if (config->mpeg_out_clk_strength)
6440 state->m_TSClockkStrength = config->mpeg_out_clk_strength & 0x07;
6441 else
6442 state->m_TSClockkStrength = 0x06;
6443
534e0481
MCC		 6444 if (config->parallel_ts)
6445 state->m_enableParallel = true;
6446 else
6447 state->m_enableParallel = false;
6448
90796aca
MCC		 6449 /* NOTE: as more UIO bits will be used, add them to the mask */
6450 state->UIO_mask = config->antenna_gpio;
6451
6452 /* Default gpio to DVB-C */
6453 if (!state->antenna_dvbt && state->antenna_gpio)
6454 state->m_GPIO |= state->antenna_gpio;
6455 else
6456 state->m_GPIO &= ~state->antenna_gpio;
43dd07f7
RM		 6457
6458 mutex_init(&state->mutex);
43dd07f7 6459
fa4b2a17
MCC		 6460 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6461 state->frontend.demodulator_priv = state;
43dd07f7
RM		 6462
6463 init_state(state);
cf694b14 6464
177bc7da
MCC		 6465 /* Load firmware and initialize DRX-K */
6466 if (state->microcode_name) {
6467 status = request_firmware_nowait(THIS_MODULE, 1,
6468 state->microcode_name,
6469 state->i2c->dev.parent,
6470 GFP_KERNEL,
6471 state, load_firmware_cb);
6472 if (status < 0) {
6473 printk(KERN_ERR
6474 "drxk: failed to request a firmware\n");
6475 return NULL;
6476 }
6477 } else if (init_drxk(state) < 0)
6478 goto error;
0d3e6fe7 6479
fa4b2a17
MCC		 6480 printk(KERN_INFO "drxk: frontend initialized.\n");
6481 return &state->frontend;
43dd07f7
RM		 6482
6483error:
ebc7de22 6484 printk(KERN_ERR "drxk: not found\n");
43dd07f7
RM		 6485 kfree(state);
6486 return NULL;
6487}
ebc7de22 6488EXPORT_SYMBOL(drxk_attach);
43dd07f7
RM		 6489
6490MODULE_DESCRIPTION("DRX-K driver");
6491MODULE_AUTHOR("Ralph Metzler");
6492MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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