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[media] em28xx: initial support for HAUPPAUGE HVR-930C again
[deliverable/linux.git] / drivers / media / dvb / frontends / drxk_hard.c
CommitLineData
43dd07f7
RM		 1/*
2 * drxk_hard: DRX-K DVB-C/T demodulator driver
3 *
4 * Copyright (C) 2010-2011 Digital Devices GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/firmware.h>
30#include <linux/i2c.h>
31#include <linux/version.h>
32#include <asm/div64.h>
33
34#include "dvb_frontend.h"
35#include "drxk.h"
36#include "drxk_hard.h"
37
38static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
39static int PowerDownQAM(struct drxk_state *state);
ebc7de22
OE		 40static int SetDVBTStandard(struct drxk_state *state,
41 enum OperationMode oMode);
42static int SetQAMStandard(struct drxk_state *state,
43 enum OperationMode oMode);
44static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
43dd07f7 45 s32 tunerFreqOffset);
ebc7de22
OE		 46static int SetDVBTStandard(struct drxk_state *state,
47 enum OperationMode oMode);
43dd07f7 48static int DVBTStart(struct drxk_state *state);
ebc7de22
OE		 49static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
50 s32 tunerFreqOffset);
43dd07f7
RM		 51static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
52static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
53static int SwitchAntennaToQAM(struct drxk_state *state);
54static int SwitchAntennaToDVBT(struct drxk_state *state);
55
56static bool IsDVBT(struct drxk_state *state)
57{
58 return state->m_OperationMode == OM_DVBT;
59}
60
61static bool IsQAM(struct drxk_state *state)
62{
63 return state->m_OperationMode == OM_QAM_ITU_A ||
ebc7de22
OE		 64 state->m_OperationMode == OM_QAM_ITU_B ||
65 state->m_OperationMode == OM_QAM_ITU_C;
43dd07f7
RM		 66}
67
68bool IsA1WithPatchCode(struct drxk_state *state)
69{
70 return state->m_DRXK_A1_PATCH_CODE;
71}
72
73bool IsA1WithRomCode(struct drxk_state *state)
74{
75 return state->m_DRXK_A1_ROM_CODE;
76}
77
78#define NOA1ROM 0
79
43dd07f7
RM		 80#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
81#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
82
83#define DEFAULT_MER_83 165
84#define DEFAULT_MER_93 250
85
86#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
87#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
88#endif
89
90#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
91#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
92#endif
93
94#ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH
95#define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06)
96#endif
97
98#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
99#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
100
101#ifndef DRXK_KI_RAGC_ATV
102#define DRXK_KI_RAGC_ATV 4
103#endif
104#ifndef DRXK_KI_IAGC_ATV
105#define DRXK_KI_IAGC_ATV 6
106#endif
107#ifndef DRXK_KI_DAGC_ATV
108#define DRXK_KI_DAGC_ATV 7
109#endif
110
111#ifndef DRXK_KI_RAGC_QAM
112#define DRXK_KI_RAGC_QAM 3
113#endif
114#ifndef DRXK_KI_IAGC_QAM
115#define DRXK_KI_IAGC_QAM 4
116#endif
117#ifndef DRXK_KI_DAGC_QAM
118#define DRXK_KI_DAGC_QAM 7
119#endif
120#ifndef DRXK_KI_RAGC_DVBT
121#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
122#endif
123#ifndef DRXK_KI_IAGC_DVBT
124#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
125#endif
126#ifndef DRXK_KI_DAGC_DVBT
127#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
128#endif
129
130#ifndef DRXK_AGC_DAC_OFFSET
131#define DRXK_AGC_DAC_OFFSET (0x800)
132#endif
133
134#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
135#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
136#endif
137
138#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
139#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
140#endif
141
142#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
143#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
144#endif
145
146#ifndef DRXK_QAM_SYMBOLRATE_MAX
147#define DRXK_QAM_SYMBOLRATE_MAX (7233000)
148#endif
149
150#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
151#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
152#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
153#define DRXK_BL_ROM_OFFSET_TAPS_BG 24
154#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
155#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
156#define DRXK_BL_ROM_OFFSET_TAPS_FM 48
157#define DRXK_BL_ROM_OFFSET_UCODE 0
158
159#define DRXK_BLC_TIMEOUT 100
160
161#define DRXK_BLCC_NR_ELEMENTS_TAPS 2
162#define DRXK_BLCC_NR_ELEMENTS_UCODE 6
163
164#define DRXK_BLDC_NR_ELEMENTS_TAPS 28
165
166#ifndef DRXK_OFDM_NE_NOTCH_WIDTH
167#define DRXK_OFDM_NE_NOTCH_WIDTH (4)
168#endif
169
170#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
171#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
172#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
173#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
174#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
175
2da67501
MCC		 176static unsigned int debug;
177module_param(debug, int, 0644);
178MODULE_PARM_DESC(debug, "enable debug messages");
179
180#define dprintk(level, fmt, arg...) do { \
181if (debug >= level) \
182 printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
183} while (0)
184
185
b01fbc10 186static inline u32 MulDiv32(u32 a, u32 b, u32 c)
43dd07f7
RM		 187{
188 u64 tmp64;
189
ebc7de22 190 tmp64 = (u64) a * (u64) b;
43dd07f7
RM		 191 do_div(tmp64, c);
192
193 return (u32) tmp64;
194}
195
196inline u32 Frac28a(u32 a, u32 c)
197{
198 int i = 0;
199 u32 Q1 = 0;
200 u32 R0 = 0;
201
ebc7de22
OE		 202 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
203 Q1 = a / c; /* integer part, only the 4 least significant bits
204 will be visible in the result */
43dd07f7
RM		 205
206 /* division using radix 16, 7 nibbles in the result */
207 for (i = 0; i < 7; i++) {
208 Q1 = (Q1 << 4) | (R0 / c);
209 R0 = (R0 % c) << 4;
210 }
211 /* rounding */
212 if ((R0 >> 3) >= c)
213 Q1++;
214
215 return Q1;
216}
217
218static u32 Log10Times100(u32 x)
219{
220 static const u8 scale = 15;
221 static const u8 indexWidth = 5;
ebc7de22 222 u8 i = 0;
43dd07f7
RM		 223 u32 y = 0;
224 u32 d = 0;
225 u32 k = 0;
226 u32 r = 0;
227 /*
ebc7de22
OE		 228 log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
229 0 <= n < ((1<<INDEXWIDTH)+1)
230 */
43dd07f7
RM		 231
232 static const u32 log2lut[] = {
ebc7de22
OE		 233 0, /* 0.000000 */
234 290941, /* 290941.300628 */
235 573196, /* 573196.476418 */
236 847269, /* 847269.179851 */
237 1113620, /* 1113620.489452 */
238 1372674, /* 1372673.576986 */
239 1624818, /* 1624817.752104 */
240 1870412, /* 1870411.981536 */
241 2109788, /* 2109787.962654 */
242 2343253, /* 2343252.817465 */
243 2571091, /* 2571091.461923 */
244 2793569, /* 2793568.696416 */
245 3010931, /* 3010931.055901 */
246 3223408, /* 3223408.452106 */
247 3431216, /* 3431215.635215 */
248 3634553, /* 3634553.498355 */
249 3833610, /* 3833610.244726 */
250 4028562, /* 4028562.434393 */
251 4219576, /* 4219575.925308 */
252 4406807, /* 4406806.721144 */
253 4590402, /* 4590401.736809 */
254 4770499, /* 4770499.491025 */
255 4947231, /* 4947230.734179 */
256 5120719, /* 5120719.018555 */
257 5291081, /* 5291081.217197 */
258 5458428, /* 5458427.996830 */
259 5622864, /* 5622864.249668 */
260 5784489, /* 5784489.488298 */
261 5943398, /* 5943398.207380 */
262 6099680, /* 6099680.215452 */
263 6253421, /* 6253420.939751 */
264 6404702, /* 6404701.706649 */
265 6553600, /* 6553600.000000 */
43dd07f7
RM		 266 };
267
268
269 if (x == 0)
ebc7de22 270 return 0;
43dd07f7
RM		 271
272 /* Scale x (normalize) */
273 /* computing y in log(x/y) = log(x) - log(y) */
274 if ((x & ((0xffffffff) << (scale + 1))) == 0) {
275 for (k = scale; k > 0; k--) {
ebc7de22 276 if (x & (((u32) 1) << scale))
43dd07f7
RM		 277 break;
278 x <<= 1;
279 }
280 } else {
ebc7de22
OE		 281 for (k = scale; k < 31; k++) {
282 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
43dd07f7
RM		 283 break;
284 x >>= 1;
ebc7de22 285 }
43dd07f7
RM		 286 }
287 /*
ebc7de22
OE		 288 Now x has binary point between bit[scale] and bit[scale-1]
289 and 1.0 <= x < 2.0 */
43dd07f7
RM		 290
291 /* correction for divison: log(x) = log(x/y)+log(y) */
ebc7de22 292 y = k * ((((u32) 1) << scale) * 200);
43dd07f7
RM		 293
294 /* remove integer part */
ebc7de22 295 x &= ((((u32) 1) << scale) - 1);
43dd07f7
RM		 296 /* get index */
297 i = (u8) (x >> (scale - indexWidth));
298 /* compute delta (x - a) */
ebc7de22 299 d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
43dd07f7
RM		 300 /* compute log, multiplication (d* (..)) must be within range ! */
301 y += log2lut[i] +
ebc7de22 302 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
43dd07f7 303 /* Conver to log10() */
ebc7de22 304 y /= 108853; /* (log2(10) << scale) */
43dd07f7
RM		 305 r = (y >> 1);
306 /* rounding */
ebc7de22 307 if (y & ((u32) 1))
43dd07f7 308 r++;
ebc7de22 309 return r;
43dd07f7
RM		 310}
311
312/****************************************************************************/
313/* I2C **********************************************************************/
314/****************************************************************************/
315
316static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val)
317{
ebc7de22
OE		 318 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
319 .buf = val, .len = 1}
320 };
be44eb28
MCC		 321
322 return i2c_transfer(adapter, msgs, 1);
43dd07f7
RM		 323}
324
325static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
326{
be44eb28 327 int status;
ebc7de22
OE		 328 struct i2c_msg msg = {
329 .addr = adr, .flags = 0, .buf = data, .len = len };
43dd07f7 330
2da67501
MCC		 331 dprintk(3, ":");
332 if (debug > 2) {
333 int i;
334 for (i = 0; i < len; i++)
335 printk(KERN_CONT " %02x", data[i]);
336 printk(KERN_CONT "\n");
337 }
be44eb28
MCC		 338 status = i2c_transfer(adap, &msg, 1);
339 if (status >= 0 && status != 1)
340 status = -EIO;
341
342 if (status < 0)
e0e6ecaf 343 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
be44eb28
MCC		 344
345 return status;
43dd07f7
RM		 346}
347
348static int i2c_read(struct i2c_adapter *adap,
349 u8 adr, u8 *msg, int len, u8 *answ, int alen)
350{
be44eb28 351 int status;
e4f4f875
MCC		 352 struct i2c_msg msgs[2] = {
353 {.addr = adr, .flags = 0,
ebc7de22 354 .buf = msg, .len = len},
e4f4f875
MCC		 355 {.addr = adr, .flags = I2C_M_RD,
356 .buf = answ, .len = alen}
ebc7de22 357 };
f07a0bc1 358
be44eb28
MCC		 359 status = i2c_transfer(adap, msgs, 2);
360 if (status != 2) {
2da67501
MCC		 361 if (debug > 2)
362 printk(KERN_CONT ": ERROR!\n");
be44eb28
MCC		 363 if (status >= 0)
364 status = -EIO;
2da67501 365
e0e6ecaf 366 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
be44eb28 367 return status;
43dd07f7 368 }
2da67501
MCC		 369 if (debug > 2) {
370 int i;
f07a0bc1 371 dprintk(2, ": read from ");
2da67501
MCC		 372 for (i = 0; i < len; i++)
373 printk(KERN_CONT " %02x", msg[i]);
f07a0bc1
MCC		 374 printk(KERN_CONT "Value = ");
375 for (i = 0; i < alen; i++)
376 printk(KERN_CONT " %02x", answ[i]);
2da67501
MCC		 377 printk(KERN_CONT "\n");
378 }
43dd07f7
RM		 379 return 0;
380}
381
5e66b878 382static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
43dd07f7 383{
be44eb28 384 int status;
ebc7de22 385 u8 adr = state->demod_address, mm1[4], mm2[2], len;
e076c92e
MCC		 386
387 if (state->single_master)
388 flags |= 0xC0;
389
43dd07f7
RM		 390 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
391 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
392 mm1[1] = ((reg >> 16) & 0xFF);
393 mm1[2] = ((reg >> 24) & 0xFF) | flags;
394 mm1[3] = ((reg >> 7) & 0xFF);
395 len = 4;
396 } else {
397 mm1[0] = ((reg << 1) & 0xFF);
398 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
399 len = 2;
400 }
2da67501 401 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
be44eb28
MCC		 402 status = i2c_read(state->i2c, adr, mm1, len, mm2, 2);
403 if (status < 0)
404 return status;
43dd07f7
RM		 405 if (data)
406 *data = mm2[0] | (mm2[1] << 8);
2da67501 407
43dd07f7
RM		 408 return 0;
409}
410
5e66b878 411static int read16(struct drxk_state *state, u32 reg, u16 *data)
43dd07f7 412{
5e66b878 413 return read16_flags(state, reg, data, 0);
43dd07f7
RM		 414}
415
5e66b878 416static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
43dd07f7 417{
be44eb28 418 int status;
43dd07f7 419 u8 adr = state->demod_address, mm1[4], mm2[4], len;
e076c92e
MCC		 420
421 if (state->single_master)
422 flags |= 0xC0;
423
43dd07f7
RM		 424 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
425 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
426 mm1[1] = ((reg >> 16) & 0xFF);
427 mm1[2] = ((reg >> 24) & 0xFF) | flags;
428 mm1[3] = ((reg >> 7) & 0xFF);
429 len = 4;
430 } else {
431 mm1[0] = ((reg << 1) & 0xFF);
432 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
433 len = 2;
434 }
2da67501 435 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
be44eb28
MCC		 436 status = i2c_read(state->i2c, adr, mm1, len, mm2, 4);
437 if (status < 0)
438 return status;
43dd07f7
RM		 439 if (data)
440 *data = mm2[0] | (mm2[1] << 8) |
ebc7de22 441 (mm2[2] << 16) | (mm2[3] << 24);
2da67501 442
43dd07f7
RM		 443 return 0;
444}
445
5e66b878
MCC		 446static int read32(struct drxk_state *state, u32 reg, u32 *data)
447{
448 return read32_flags(state, reg, data, 0);
449}
450
451static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
43dd07f7
RM		 452{
453 u8 adr = state->demod_address, mm[6], len;
e076c92e
MCC		 454
455 if (state->single_master)
456 flags |= 0xC0;
43dd07f7
RM		 457 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
458 mm[0] = (((reg << 1) & 0xFF) | 0x01);
459 mm[1] = ((reg >> 16) & 0xFF);
460 mm[2] = ((reg >> 24) & 0xFF) | flags;
461 mm[3] = ((reg >> 7) & 0xFF);
462 len = 4;
463 } else {
464 mm[0] = ((reg << 1) & 0xFF);
465 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
466 len = 2;
467 }
468 mm[len] = data & 0xff;
ebc7de22 469 mm[len + 1] = (data >> 8) & 0xff;
2da67501
MCC		 470
471 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
be44eb28 472 return i2c_write(state->i2c, adr, mm, len + 2);
43dd07f7
RM		 473}
474
5e66b878 475static int write16(struct drxk_state *state, u32 reg, u16 data)
43dd07f7 476{
5e66b878 477 return write16_flags(state, reg, data, 0);
43dd07f7
RM		 478}
479
5e66b878 480static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
43dd07f7
RM		 481{
482 u8 adr = state->demod_address, mm[8], len;
e076c92e
MCC		 483
484 if (state->single_master)
485 flags |= 0xC0;
43dd07f7
RM		 486 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
487 mm[0] = (((reg << 1) & 0xFF) | 0x01);
488 mm[1] = ((reg >> 16) & 0xFF);
489 mm[2] = ((reg >> 24) & 0xFF) | flags;
490 mm[3] = ((reg >> 7) & 0xFF);
491 len = 4;
492 } else {
493 mm[0] = ((reg << 1) & 0xFF);
494 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
495 len = 2;
496 }
497 mm[len] = data & 0xff;
ebc7de22
OE		 498 mm[len + 1] = (data >> 8) & 0xff;
499 mm[len + 2] = (data >> 16) & 0xff;
500 mm[len + 3] = (data >> 24) & 0xff;
2da67501 501 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
be44eb28
MCC		 502
503 return i2c_write(state->i2c, adr, mm, len + 4);
43dd07f7
RM		 504}
505
5e66b878
MCC		 506static int write32(struct drxk_state *state, u32 reg, u32 data)
507{
508 return write32_flags(state, reg, data, 0);
509}
510
511static int write_block(struct drxk_state *state, u32 Address,
512 const int BlockSize, const u8 pBlock[])
43dd07f7
RM		 513{
514 int status = 0, BlkSize = BlockSize;
5e66b878 515 u8 Flags = 0;
e076c92e
MCC		 516
517 if (state->single_master)
518 Flags |= 0xC0;
519
ebc7de22 520 while (BlkSize > 0) {
43dd07f7 521 int Chunk = BlkSize > state->m_ChunkSize ?
ebc7de22 522 state->m_ChunkSize : BlkSize;
43dd07f7
RM		 523 u8 *AdrBuf = &state->Chunk[0];
524 u32 AdrLength = 0;
525
ebc7de22
OE		 526 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
527 AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
528 AdrBuf[1] = ((Address >> 16) & 0xFF);
529 AdrBuf[2] = ((Address >> 24) & 0xFF);
530 AdrBuf[3] = ((Address >> 7) & 0xFF);
43dd07f7
RM		 531 AdrBuf[2] |= Flags;
532 AdrLength = 4;
533 if (Chunk == state->m_ChunkSize)
534 Chunk -= 2;
ebc7de22 535 } else {
43dd07f7
RM		 536 AdrBuf[0] = ((Address << 1) & 0xFF);
537 AdrBuf[1] = (((Address >> 16) & 0x0F) |
538 ((Address >> 18) & 0xF0));
539 AdrLength = 2;
540 }
541 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
2da67501
MCC		 542 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
543 if (debug > 1) {
544 int i;
545 if (pBlock)
546 for (i = 0; i < Chunk; i++)
547 printk(KERN_CONT " %02x", pBlock[i]);
548 printk(KERN_CONT "\n");
549 }
43dd07f7 550 status = i2c_write(state->i2c, state->demod_address,
ebc7de22
OE		 551 &state->Chunk[0], Chunk + AdrLength);
552 if (status < 0) {
e0e6ecaf
MCC		 553 printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
554 __func__, Address);
43dd07f7
RM		 555 break;
556 }
557 pBlock += Chunk;
558 Address += (Chunk >> 1);
559 BlkSize -= Chunk;
560 }
ebc7de22 561 return status;
43dd07f7
RM		 562}
563
564#ifndef DRXK_MAX_RETRIES_POWERUP
565#define DRXK_MAX_RETRIES_POWERUP 20
566#endif
567
568int PowerUpDevice(struct drxk_state *state)
569{
570 int status;
571 u8 data = 0;
572 u16 retryCount = 0;
573
2da67501
MCC		 574 dprintk(1, "\n");
575
43dd07f7 576 status = i2c_read1(state->i2c, state->demod_address, &data);
be44eb28 577 if (status < 0) {
43dd07f7
RM		 578 do {
579 data = 0;
be44eb28
MCC		 580 status = i2c_write(state->i2c, state->demod_address,
581 &data, 1);
43dd07f7 582 msleep(10);
ebc7de22 583 retryCount++;
be44eb28
MCC		 584 if (status < 0)
585 continue;
586 status = i2c_read1(state->i2c, state->demod_address,
587 &data);
588 } while (status < 0 &&
43dd07f7 589 (retryCount < DRXK_MAX_RETRIES_POWERUP));
be44eb28
MCC		 590 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
591 goto error;
592 }
593
594 /* Make sure all clk domains are active */
595 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
596 if (status < 0)
597 goto error;
598 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
599 if (status < 0)
600 goto error;
601 /* Enable pll lock tests */
602 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
603 if (status < 0)
604 goto error;
605
606 state->m_currentPowerMode = DRX_POWER_UP;
607
608error:
609 if (status < 0)
610 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
611
43dd07f7
RM		 612 return status;
613}
614
615
616static int init_state(struct drxk_state *state)
617{
147e110b
MCC		 618 /*
619 * FIXME: most (all?) of the values bellow should be moved into
620 * struct drxk_config, as they are probably board-specific
621 */
ebc7de22
OE		 622 u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
623 u32 ulVSBIfAgcOutputLevel = 0;
624 u32 ulVSBIfAgcMinLevel = 0;
625 u32 ulVSBIfAgcMaxLevel = 0x7FFF;
626 u32 ulVSBIfAgcSpeed = 3;
627
628 u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
629 u32 ulVSBRfAgcOutputLevel = 0;
630 u32 ulVSBRfAgcMinLevel = 0;
631 u32 ulVSBRfAgcMaxLevel = 0x7FFF;
632 u32 ulVSBRfAgcSpeed = 3;
633 u32 ulVSBRfAgcTop = 9500;
634 u32 ulVSBRfAgcCutOffCurrent = 4000;
635
636 u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
637 u32 ulATVIfAgcOutputLevel = 0;
638 u32 ulATVIfAgcMinLevel = 0;
639 u32 ulATVIfAgcMaxLevel = 0;
640 u32 ulATVIfAgcSpeed = 3;
641
642 u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
643 u32 ulATVRfAgcOutputLevel = 0;
644 u32 ulATVRfAgcMinLevel = 0;
645 u32 ulATVRfAgcMaxLevel = 0;
646 u32 ulATVRfAgcTop = 9500;
647 u32 ulATVRfAgcCutOffCurrent = 4000;
648 u32 ulATVRfAgcSpeed = 3;
43dd07f7
RM		 649
650 u32 ulQual83 = DEFAULT_MER_83;
651 u32 ulQual93 = DEFAULT_MER_93;
652
653 u32 ulDVBTStaticTSClock = 1;
654 u32 ulDVBCStaticTSClock = 1;
655
656 u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
657 u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
658
659 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
660 /* io_pad_cfg_mode output mode is drive always */
661 /* io_pad_cfg_drive is set to power 2 (23 mA) */
662 u32 ulGPIOCfg = 0x0113;
43dd07f7
RM		 663 u32 ulSerialMode = 1;
664 u32 ulInvertTSClock = 0;
665 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
666 u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH;
667 u32 ulDVBTBitrate = 50000000;
668 u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
669
670 u32 ulInsertRSByte = 0;
671
672 u32 ulRfMirror = 1;
673 u32 ulPowerDown = 0;
674
2da67501
MCC		 675 dprintk(1, "\n");
676
43dd07f7 677 state->m_hasLNA = false;
ebc7de22
OE		 678 state->m_hasDVBT = false;
679 state->m_hasDVBC = false;
680 state->m_hasATV = false;
43dd07f7
RM		 681 state->m_hasOOB = false;
682 state->m_hasAudio = false;
683
82e7dbbd
EDP		 684 if (!state->m_ChunkSize)
685 state->m_ChunkSize = 124;
43dd07f7
RM		 686
687 state->m_oscClockFreq = 0;
688 state->m_smartAntInverted = false;
689 state->m_bPDownOpenBridge = false;
690
691 /* real system clock frequency in kHz */
ebc7de22 692 state->m_sysClockFreq = 151875;
43dd07f7
RM		 693 /* Timing div, 250ns/Psys */
694 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
695 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
696 HI_I2C_DELAY) / 1000;
697 /* Clipping */
698 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
699 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
700 state->m_HICfgWakeUpKey = (state->demod_address << 1);
701 /* port/bridge/power down ctrl */
702 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
703
704 state->m_bPowerDown = (ulPowerDown != 0);
705
706 state->m_DRXK_A1_PATCH_CODE = false;
707 state->m_DRXK_A1_ROM_CODE = false;
708 state->m_DRXK_A2_ROM_CODE = false;
709 state->m_DRXK_A3_ROM_CODE = false;
710 state->m_DRXK_A2_PATCH_CODE = false;
711 state->m_DRXK_A3_PATCH_CODE = false;
712
713 /* Init AGC and PGA parameters */
714 /* VSB IF */
ebc7de22
OE		 715 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
716 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
717 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
718 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
719 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
43dd07f7
RM		 720 state->m_vsbPgaCfg = 140;
721
722 /* VSB RF */
ebc7de22
OE		 723 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
724 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
725 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
726 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
727 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
728 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
729 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
730 state->m_vsbPreSawCfg.reference = 0x07;
731 state->m_vsbPreSawCfg.usePreSaw = true;
43dd07f7
RM		 732
733 state->m_Quality83percent = DEFAULT_MER_83;
734 state->m_Quality93percent = DEFAULT_MER_93;
735 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
736 state->m_Quality83percent = ulQual83;
737 state->m_Quality93percent = ulQual93;
738 }
739
740 /* ATV IF */
ebc7de22
OE		 741 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
742 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
743 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
744 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
745 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
43dd07f7
RM		 746
747 /* ATV RF */
ebc7de22
OE		 748 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
749 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
750 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
751 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
752 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
753 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
754 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
755 state->m_atvPreSawCfg.reference = 0x04;
756 state->m_atvPreSawCfg.usePreSaw = true;
43dd07f7
RM		 757
758
759 /* DVBT RF */
ebc7de22
OE		 760 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
761 state->m_dvbtRfAgcCfg.outputLevel = 0;
762 state->m_dvbtRfAgcCfg.minOutputLevel = 0;
763 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
764 state->m_dvbtRfAgcCfg.top = 0x2100;
765 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
766 state->m_dvbtRfAgcCfg.speed = 1;
43dd07f7
RM		 767
768
769 /* DVBT IF */
ebc7de22
OE		 770 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
771 state->m_dvbtIfAgcCfg.outputLevel = 0;
772 state->m_dvbtIfAgcCfg.minOutputLevel = 0;
773 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
774 state->m_dvbtIfAgcCfg.top = 13424;
775 state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
776 state->m_dvbtIfAgcCfg.speed = 3;
43dd07f7 777 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
ebc7de22
OE		 778 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
779 /* state->m_dvbtPgaCfg = 140; */
43dd07f7 780
ebc7de22
OE		 781 state->m_dvbtPreSawCfg.reference = 4;
782 state->m_dvbtPreSawCfg.usePreSaw = false;
43dd07f7
RM		 783
784 /* QAM RF */
ebc7de22
OE		 785 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
786 state->m_qamRfAgcCfg.outputLevel = 0;
787 state->m_qamRfAgcCfg.minOutputLevel = 6023;
788 state->m_qamRfAgcCfg.maxOutputLevel = 27000;
789 state->m_qamRfAgcCfg.top = 0x2380;
790 state->m_qamRfAgcCfg.cutOffCurrent = 4000;
791 state->m_qamRfAgcCfg.speed = 3;
43dd07f7
RM		 792
793 /* QAM IF */
ebc7de22
OE		 794 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
795 state->m_qamIfAgcCfg.outputLevel = 0;
796 state->m_qamIfAgcCfg.minOutputLevel = 0;
797 state->m_qamIfAgcCfg.maxOutputLevel = 9000;
798 state->m_qamIfAgcCfg.top = 0x0511;
799 state->m_qamIfAgcCfg.cutOffCurrent = 0;
800 state->m_qamIfAgcCfg.speed = 3;
801 state->m_qamIfAgcCfg.IngainTgtMax = 5119;
43dd07f7
RM		 802 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
803
ebc7de22
OE		 804 state->m_qamPgaCfg = 140;
805 state->m_qamPreSawCfg.reference = 4;
806 state->m_qamPreSawCfg.usePreSaw = false;
43dd07f7
RM		 807
808 state->m_OperationMode = OM_NONE;
809 state->m_DrxkState = DRXK_UNINITIALIZED;
810
811 /* MPEG output configuration */
ebc7de22
OE		 812 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
813 state->m_insertRSByte = false; /* If TRUE; insert RS byte */
814 state->m_enableParallel = true; /* If TRUE;
815 parallel out otherwise serial */
816 state->m_invertDATA = false; /* If TRUE; invert DATA signals */
817 state->m_invertERR = false; /* If TRUE; invert ERR signal */
818 state->m_invertSTR = false; /* If TRUE; invert STR signals */
819 state->m_invertVAL = false; /* If TRUE; invert VAL signals */
820 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
43dd07f7 821 state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0);
ebc7de22 822 state->m_DVBCStaticCLK = (ulDVBCStaticTSClock != 0);
43dd07f7
RM		 823 /* If TRUE; static MPEG clockrate will be used;
824 otherwise clockrate will adapt to the bitrate of the TS */
825
826 state->m_DVBTBitrate = ulDVBTBitrate;
827 state->m_DVBCBitrate = ulDVBCBitrate;
828
829 state->m_TSDataStrength = (ulTSDataStrength & 0x07);
830 state->m_TSClockkStrength = (ulTSClockkStrength & 0x07);
831
832 /* Maximum bitrate in b/s in case static clockrate is selected */
833 state->m_mpegTsStaticBitrate = 19392658;
834 state->m_disableTEIhandling = false;
835
836 if (ulInsertRSByte)
837 state->m_insertRSByte = true;
838
839 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
840 if (ulMpegLockTimeOut < 10000)
841 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
842 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
843 if (ulDemodLockTimeOut < 10000)
844 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
845
ebc7de22
OE		 846 /* QAM defaults */
847 state->m_Constellation = DRX_CONSTELLATION_AUTO;
43dd07f7 848 state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
ebc7de22
OE		 849 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
850 state->m_fecRsPrescale = 1;
43dd07f7
RM		 851
852 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
853 state->m_agcFastClipCtrlDelay = 0;
854
855 state->m_GPIOCfg = (ulGPIOCfg);
43dd07f7 856
43dd07f7
RM		 857 state->m_bPowerDown = false;
858 state->m_currentPowerMode = DRX_POWER_DOWN;
859
860 state->m_enableParallel = (ulSerialMode == 0);
861
862 state->m_rfmirror = (ulRfMirror == 0);
863 state->m_IfAgcPol = false;
864 return 0;
865}
866
867static int DRXX_Open(struct drxk_state *state)
868{
869 int status = 0;
870 u32 jtag = 0;
871 u16 bid = 0;
872 u16 key = 0;
873
2da67501 874 dprintk(1, "\n");
be44eb28
MCC		 875 /* stop lock indicator process */
876 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
877 if (status < 0)
878 goto error;
879 /* Check device id */
880 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
881 if (status < 0)
882 goto error;
883 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
884 if (status < 0)
885 goto error;
886 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
887 if (status < 0)
888 goto error;
889 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
890 if (status < 0)
891 goto error;
892 status = write16(state, SIO_TOP_COMM_KEY__A, key);
893error:
894 if (status < 0)
895 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 896 return status;
897}
898
899static int GetDeviceCapabilities(struct drxk_state *state)
900{
ebc7de22 901 u16 sioPdrOhwCfg = 0;
43dd07f7
RM		 902 u32 sioTopJtagidLo = 0;
903 int status;
9c6e1828 904 const char *spin = "";
43dd07f7 905
2da67501 906 dprintk(1, "\n");
43dd07f7 907
be44eb28
MCC		 908 /* driver 0.9.0 */
909 /* stop lock indicator process */
910 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
911 if (status < 0)
912 goto error;
913 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
914 if (status < 0)
915 goto error;
916 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
917 if (status < 0)
918 goto error;
919 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
920 if (status < 0)
921 goto error;
43dd07f7 922
be44eb28
MCC		 923 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
924 case 0:
925 /* ignore (bypass ?) */
926 break;
927 case 1:
928 /* 27 MHz */
929 state->m_oscClockFreq = 27000;
930 break;
931 case 2:
932 /* 20.25 MHz */
933 state->m_oscClockFreq = 20250;
934 break;
935 case 3:
936 /* 4 MHz */
937 state->m_oscClockFreq = 20250;
938 break;
939 default:
940 printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n");
941 return -EINVAL;
942 }
943 /*
944 Determine device capabilities
945 Based on pinning v14
946 */
947 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
948 if (status < 0)
949 goto error;
950 /* driver 0.9.0 */
951 switch ((sioTopJtagidLo >> 29) & 0xF) {
952 case 0:
953 state->m_deviceSpin = DRXK_SPIN_A1;
9c6e1828 954 spin = "A1";
be44eb28
MCC		 955 break;
956 case 2:
957 state->m_deviceSpin = DRXK_SPIN_A2;
9c6e1828 958 spin = "A2";
be44eb28
MCC		 959 break;
960 case 3:
961 state->m_deviceSpin = DRXK_SPIN_A3;
9c6e1828 962 spin = "A3";
be44eb28
MCC		 963 break;
964 default:
965 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
966 status = -EINVAL;
967 printk(KERN_ERR "drxk: Spin unknown\n");
968 goto error2;
969 }
970 switch ((sioTopJtagidLo >> 12) & 0xFF) {
971 case 0x13:
972 /* typeId = DRX3913K_TYPE_ID */
973 state->m_hasLNA = false;
974 state->m_hasOOB = false;
975 state->m_hasATV = false;
976 state->m_hasAudio = false;
977 state->m_hasDVBT = true;
978 state->m_hasDVBC = true;
979 state->m_hasSAWSW = true;
980 state->m_hasGPIO2 = false;
981 state->m_hasGPIO1 = false;
982 state->m_hasIRQN = false;
983 break;
984 case 0x15:
985 /* typeId = DRX3915K_TYPE_ID */
986 state->m_hasLNA = false;
987 state->m_hasOOB = false;
988 state->m_hasATV = true;
989 state->m_hasAudio = false;
990 state->m_hasDVBT = true;
991 state->m_hasDVBC = false;
992 state->m_hasSAWSW = true;
993 state->m_hasGPIO2 = true;
994 state->m_hasGPIO1 = true;
995 state->m_hasIRQN = false;
996 break;
997 case 0x16:
998 /* typeId = DRX3916K_TYPE_ID */
999 state->m_hasLNA = false;
1000 state->m_hasOOB = false;
1001 state->m_hasATV = true;
1002 state->m_hasAudio = false;
1003 state->m_hasDVBT = true;
1004 state->m_hasDVBC = false;
1005 state->m_hasSAWSW = true;
1006 state->m_hasGPIO2 = true;
1007 state->m_hasGPIO1 = true;
1008 state->m_hasIRQN = false;
1009 break;
1010 case 0x18:
1011 /* typeId = DRX3918K_TYPE_ID */
1012 state->m_hasLNA = false;
1013 state->m_hasOOB = false;
1014 state->m_hasATV = true;
1015 state->m_hasAudio = true;
1016 state->m_hasDVBT = true;
1017 state->m_hasDVBC = false;
1018 state->m_hasSAWSW = true;
1019 state->m_hasGPIO2 = true;
1020 state->m_hasGPIO1 = true;
1021 state->m_hasIRQN = false;
1022 break;
1023 case 0x21:
1024 /* typeId = DRX3921K_TYPE_ID */
1025 state->m_hasLNA = false;
1026 state->m_hasOOB = false;
1027 state->m_hasATV = true;
1028 state->m_hasAudio = true;
1029 state->m_hasDVBT = true;
1030 state->m_hasDVBC = true;
1031 state->m_hasSAWSW = true;
1032 state->m_hasGPIO2 = true;
1033 state->m_hasGPIO1 = true;
1034 state->m_hasIRQN = false;
1035 break;
1036 case 0x23:
1037 /* typeId = DRX3923K_TYPE_ID */
1038 state->m_hasLNA = false;
1039 state->m_hasOOB = false;
1040 state->m_hasATV = true;
1041 state->m_hasAudio = true;
1042 state->m_hasDVBT = true;
1043 state->m_hasDVBC = true;
1044 state->m_hasSAWSW = true;
1045 state->m_hasGPIO2 = true;
1046 state->m_hasGPIO1 = true;
1047 state->m_hasIRQN = false;
1048 break;
1049 case 0x25:
1050 /* typeId = DRX3925K_TYPE_ID */
1051 state->m_hasLNA = false;
1052 state->m_hasOOB = false;
1053 state->m_hasATV = true;
1054 state->m_hasAudio = true;
1055 state->m_hasDVBT = true;
1056 state->m_hasDVBC = true;
1057 state->m_hasSAWSW = true;
1058 state->m_hasGPIO2 = true;
1059 state->m_hasGPIO1 = true;
1060 state->m_hasIRQN = false;
1061 break;
1062 case 0x26:
1063 /* typeId = DRX3926K_TYPE_ID */
1064 state->m_hasLNA = false;
1065 state->m_hasOOB = false;
1066 state->m_hasATV = true;
1067 state->m_hasAudio = false;
1068 state->m_hasDVBT = true;
1069 state->m_hasDVBC = true;
1070 state->m_hasSAWSW = true;
1071 state->m_hasGPIO2 = true;
1072 state->m_hasGPIO1 = true;
1073 state->m_hasIRQN = false;
1074 break;
1075 default:
f07a0bc1 1076 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
be44eb28
MCC		 1077 ((sioTopJtagidLo >> 12) & 0xFF));
1078 status = -EINVAL;
1079 goto error2;
1080 }
1081
9c6e1828
MCC		 1082 printk(KERN_INFO
1083 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1084 ((sioTopJtagidLo >> 12) & 0xFF), spin,
1085 state->m_oscClockFreq / 1000,
1086 state->m_oscClockFreq % 1000);
1087
be44eb28
MCC		 1088error:
1089 if (status < 0)
1090 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1091
1092error2:
43dd07f7
RM		 1093 return status;
1094}
1095
1096static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1097{
1098 int status;
1099 bool powerdown_cmd;
1100
2da67501
MCC		 1101 dprintk(1, "\n");
1102
43dd07f7 1103 /* Write command */
5e66b878 1104 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
43dd07f7 1105 if (status < 0)
be44eb28 1106 goto error;
43dd07f7
RM		 1107 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1108 msleep(1);
1109
1110 powerdown_cmd =
ebc7de22
OE		 1111 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1112 ((state->m_HICfgCtrl) &
1113 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1114 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
43dd07f7
RM		 1115 if (powerdown_cmd == false) {
1116 /* Wait until command rdy */
1117 u32 retryCount = 0;
1118 u16 waitCmd;
1119
1120 do {
1121 msleep(1);
1122 retryCount += 1;
5e66b878
MCC		 1123 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1124 &waitCmd);
ebc7de22
OE		 1125 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1126 && (waitCmd != 0));
be44eb28
MCC		 1127 if (status < 0)
1128 goto error;
1129 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
43dd07f7 1130 }
be44eb28
MCC		 1131error:
1132 if (status < 0)
1133 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1134
43dd07f7
RM		 1135 return status;
1136}
1137
1138static int HI_CfgCommand(struct drxk_state *state)
1139{
1140 int status;
1141
2da67501
MCC		 1142 dprintk(1, "\n");
1143
43dd07f7 1144 mutex_lock(&state->mutex);
43dd07f7 1145
be44eb28
MCC		 1146 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1147 if (status < 0)
1148 goto error;
1149 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1150 if (status < 0)
1151 goto error;
1152 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1153 if (status < 0)
1154 goto error;
1155 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1156 if (status < 0)
1157 goto error;
1158 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1159 if (status < 0)
1160 goto error;
1161 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1162 if (status < 0)
1163 goto error;
1164 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1165 if (status < 0)
1166 goto error;
1167
1168 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1169error:
43dd07f7 1170 mutex_unlock(&state->mutex);
be44eb28
MCC		 1171 if (status < 0)
1172 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1173 return status;
1174}
1175
1176static int InitHI(struct drxk_state *state)
1177{
2da67501
MCC		 1178 dprintk(1, "\n");
1179
ebc7de22 1180 state->m_HICfgWakeUpKey = (state->demod_address << 1);
43dd07f7
RM		 1181 state->m_HICfgTimeout = 0x96FF;
1182 /* port/bridge/power down ctrl */
1183 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
be44eb28 1184
ebc7de22 1185 return HI_CfgCommand(state);
43dd07f7
RM		 1186}
1187
1188static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1189{
1190 int status = -1;
ebc7de22
OE		 1191 u16 sioPdrMclkCfg = 0;
1192 u16 sioPdrMdxCfg = 0;
43dd07f7 1193
2da67501 1194 dprintk(1, "\n");
43dd07f7 1195
be44eb28
MCC		 1196 /* stop lock indicator process */
1197 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1198 if (status < 0)
1199 goto error;
1200
1201 /* MPEG TS pad configuration */
1202 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1203 if (status < 0)
1204 goto error;
1205
1206 if (mpegEnable == false) {
1207 /* Set MPEG TS pads to inputmode */
1208 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
ea90f011 1209 if (status < 0)
be44eb28
MCC		 1210 goto error;
1211 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1212 if (status < 0)
1213 goto error;
1214 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1215 if (status < 0)
1216 goto error;
1217 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1218 if (status < 0)
1219 goto error;
1220 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1221 if (status < 0)
1222 goto error;
1223 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1224 if (status < 0)
1225 goto error;
1226 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1227 if (status < 0)
1228 goto error;
1229 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1230 if (status < 0)
1231 goto error;
1232 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1233 if (status < 0)
1234 goto error;
1235 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1236 if (status < 0)
1237 goto error;
1238 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1239 if (status < 0)
1240 goto error;
1241 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1242 if (status < 0)
1243 goto error;
1244 } else {
1245 /* Enable MPEG output */
1246 sioPdrMdxCfg =
1247 ((state->m_TSDataStrength <<
1248 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1249 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1250 SIO_PDR_MCLK_CFG_DRIVE__B) |
1251 0x0003);
43dd07f7 1252
be44eb28
MCC		 1253 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1254 if (status < 0)
1255 goto error;
1256 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); /* Disable */
1257 if (status < 0)
1258 goto error;
1259 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); /* Disable */
1260 if (status < 0)
1261 goto error;
1262 if (state->m_enableParallel == true) {
1263 /* paralel -> enable MD1 to MD7 */
1264 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
ea90f011 1265 if (status < 0)
be44eb28
MCC		 1266 goto error;
1267 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
ea90f011 1268 if (status < 0)
be44eb28
MCC		 1269 goto error;
1270 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
ea90f011 1271 if (status < 0)
be44eb28
MCC		 1272 goto error;
1273 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
ea90f011 1274 if (status < 0)
be44eb28
MCC		 1275 goto error;
1276 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
ea90f011 1277 if (status < 0)
be44eb28
MCC		 1278 goto error;
1279 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1280 if (status < 0)
1281 goto error;
1282 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1283 if (status < 0)
1284 goto error;
1285 } else {
1286 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1287 SIO_PDR_MD0_CFG_DRIVE__B)
1288 | 0x0003);
1289 /* serial -> disable MD1 to MD7 */
5e66b878 1290 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
ea90f011 1291 if (status < 0)
be44eb28 1292 goto error;
5e66b878 1293 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
ea90f011 1294 if (status < 0)
be44eb28 1295 goto error;
5e66b878 1296 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
ea90f011 1297 if (status < 0)
be44eb28 1298 goto error;
5e66b878 1299 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
ea90f011 1300 if (status < 0)
be44eb28 1301 goto error;
5e66b878 1302 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
ea90f011 1303 if (status < 0)
be44eb28 1304 goto error;
5e66b878 1305 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
ea90f011 1306 if (status < 0)
be44eb28 1307 goto error;
5e66b878 1308 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
ea90f011 1309 if (status < 0)
be44eb28 1310 goto error;
43dd07f7 1311 }
be44eb28 1312 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
ea90f011 1313 if (status < 0)
be44eb28
MCC		 1314 goto error;
1315 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
ea90f011 1316 if (status < 0)
be44eb28
MCC		 1317 goto error;
1318 }
1319 /* Enable MB output over MPEG pads and ctl input */
1320 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1321 if (status < 0)
1322 goto error;
1323 /* Write nomagic word to enable pdr reg write */
1324 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1325error:
1326 if (status < 0)
1327 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1328 return status;
1329}
1330
1331static int MPEGTSDisable(struct drxk_state *state)
1332{
2da67501
MCC		 1333 dprintk(1, "\n");
1334
43dd07f7
RM		 1335 return MPEGTSConfigurePins(state, false);
1336}
1337
1338static int BLChainCmd(struct drxk_state *state,
1339 u16 romOffset, u16 nrOfElements, u32 timeOut)
1340{
1341 u16 blStatus = 0;
1342 int status;
1343 unsigned long end;
1344
2da67501 1345 dprintk(1, "\n");
43dd07f7 1346 mutex_lock(&state->mutex);
be44eb28
MCC		 1347 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1348 if (status < 0)
1349 goto error;
1350 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1351 if (status < 0)
1352 goto error;
1353 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1354 if (status < 0)
1355 goto error;
1356 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1357 if (status < 0)
1358 goto error;
1359
1360 end = jiffies + msecs_to_jiffies(timeOut);
43dd07f7 1361 do {
be44eb28
MCC		 1362 msleep(1);
1363 status = read16(state, SIO_BL_STATUS__A, &blStatus);
ea90f011 1364 if (status < 0)
be44eb28
MCC		 1365 goto error;
1366 } while ((blStatus == 0x1) &&
1367 ((time_is_after_jiffies(end))));
43dd07f7 1368
be44eb28
MCC		 1369 if (blStatus == 0x1) {
1370 printk(KERN_ERR "drxk: SIO not ready\n");
1371 status = -EINVAL;
1372 goto error2;
1373 }
1374error:
1375 if (status < 0)
1376 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1377error2:
43dd07f7
RM		 1378 mutex_unlock(&state->mutex);
1379 return status;
1380}
1381
1382
1383static int DownloadMicrocode(struct drxk_state *state,
ebc7de22 1384 const u8 pMCImage[], u32 Length)
43dd07f7
RM		 1385{
1386 const u8 *pSrc = pMCImage;
1387 u16 Flags;
1388 u16 Drain;
1389 u32 Address;
1390 u16 nBlocks;
1391 u16 BlockSize;
1392 u16 BlockCRC;
1393 u32 offset = 0;
1394 u32 i;
1bd09ddc 1395 int status = 0;
43dd07f7 1396
2da67501
MCC		 1397 dprintk(1, "\n");
1398
43dd07f7
RM		 1399 /* down the drain (we don care about MAGIC_WORD) */
1400 Drain = (pSrc[0] << 8) | pSrc[1];
ebc7de22
OE		 1401 pSrc += sizeof(u16);
1402 offset += sizeof(u16);
43dd07f7 1403 nBlocks = (pSrc[0] << 8) | pSrc[1];
ebc7de22
OE		 1404 pSrc += sizeof(u16);
1405 offset += sizeof(u16);
43dd07f7
RM		 1406
1407 for (i = 0; i < nBlocks; i += 1) {
1408 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
ebc7de22
OE		 1409 (pSrc[2] << 8) | pSrc[3];
1410 pSrc += sizeof(u32);
1411 offset += sizeof(u32);
43dd07f7
RM		 1412
1413 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
ebc7de22
OE		 1414 pSrc += sizeof(u16);
1415 offset += sizeof(u16);
43dd07f7
RM		 1416
1417 Flags = (pSrc[0] << 8) | pSrc[1];
ebc7de22
OE		 1418 pSrc += sizeof(u16);
1419 offset += sizeof(u16);
43dd07f7
RM		 1420
1421 BlockCRC = (pSrc[0] << 8) | pSrc[1];
ebc7de22
OE		 1422 pSrc += sizeof(u16);
1423 offset += sizeof(u16);
bcd2ebb7
MCC		 1424
1425 if (offset + BlockSize > Length) {
1426 printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1427 return -EINVAL;
1428 }
1429
5e66b878 1430 status = write_block(state, Address, BlockSize, pSrc);
39624f7e
MCC		 1431 if (status < 0) {
1432 printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
43dd07f7 1433 break;
39624f7e 1434 }
43dd07f7
RM		 1435 pSrc += BlockSize;
1436 offset += BlockSize;
1437 }
1438 return status;
1439}
1440
1441static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1442{
1443 int status;
ebc7de22
OE		 1444 u16 data = 0;
1445 u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
43dd07f7
RM		 1446 u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1447 unsigned long end;
1448
2da67501
MCC		 1449 dprintk(1, "\n");
1450
43dd07f7 1451 if (enable == false) {
ebc7de22 1452 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
43dd07f7
RM		 1453 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1454 }
1455
be44eb28
MCC		 1456 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1457 if (status >= 0 && data == desiredStatus) {
43dd07f7
RM		 1458 /* tokenring already has correct status */
1459 return status;
1460 }
1461 /* Disable/enable dvbt tokenring bridge */
be44eb28 1462 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
43dd07f7 1463
ebc7de22 1464 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
ea90f011 1465 do {
5e66b878 1466 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
be44eb28 1467 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
ea90f011 1468 break;
be44eb28
MCC		 1469 msleep(1);
1470 } while (1);
43dd07f7 1471 if (data != desiredStatus) {
e0e6ecaf 1472 printk(KERN_ERR "drxk: SIO not ready\n");
be44eb28 1473 return -EINVAL;
43dd07f7
RM		 1474 }
1475 return status;
1476}
1477
1478static int MPEGTSStop(struct drxk_state *state)
1479{
1480 int status = 0;
1481 u16 fecOcSncMode = 0;
1482 u16 fecOcIprMode = 0;
1483
2da67501
MCC		 1484 dprintk(1, "\n");
1485
be44eb28
MCC		 1486 /* Gracefull shutdown (byte boundaries) */
1487 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1488 if (status < 0)
1489 goto error;
1490 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1491 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1492 if (status < 0)
1493 goto error;
1494
1495 /* Suppress MCLK during absence of data */
1496 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1497 if (status < 0)
1498 goto error;
1499 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1500 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1501
1502error:
1503 if (status < 0)
1504 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7 1505
43dd07f7
RM		 1506 return status;
1507}
1508
1509static int scu_command(struct drxk_state *state,
1510 u16 cmd, u8 parameterLen,
ebc7de22 1511 u16 *parameter, u8 resultLen, u16 *result)
43dd07f7
RM		 1512{
1513#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1514#error DRXK register mapping no longer compatible with this routine!
1515#endif
1516 u16 curCmd = 0;
be44eb28 1517 int status = -EINVAL;
43dd07f7 1518 unsigned long end;
be44eb28
MCC		 1519 u8 buffer[34];
1520 int cnt = 0, ii;
7558977a
MCC		 1521 const char *p;
1522 char errname[30];
43dd07f7 1523
2da67501
MCC		 1524 dprintk(1, "\n");
1525
43dd07f7
RM		 1526 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1527 ((resultLen > 0) && (result == NULL)))
be44eb28 1528 goto error;
43dd07f7
RM		 1529
1530 mutex_lock(&state->mutex);
be44eb28
MCC		 1531
1532 /* assume that the command register is ready
1533 since it is checked afterwards */
1534 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1535 buffer[cnt++] = (parameter[ii] & 0xFF);
1536 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1537 }
1538 buffer[cnt++] = (cmd & 0xFF);
1539 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1540
1541 write_block(state, SCU_RAM_PARAM_0__A -
1542 (parameterLen - 1), cnt, buffer);
1543 /* Wait until SCU has processed command */
1544 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
43dd07f7 1545 do {
be44eb28
MCC		 1546 msleep(1);
1547 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1548 if (status < 0)
1549 goto error;
1550 } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1551 if (curCmd != DRX_SCU_READY) {
1552 printk(KERN_ERR "drxk: SCU not ready\n");
1553 status = -EIO;
1554 goto error2;
1555 }
1556 /* read results */
1557 if ((resultLen > 0) && (result != NULL)) {
1558 s16 err;
1559 int ii;
43dd07f7 1560
be44eb28
MCC		 1561 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1562 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
ea90f011 1563 if (status < 0)
be44eb28 1564 goto error;
43dd07f7 1565 }
be44eb28
MCC		 1566
1567 /* Check if an error was reported by SCU */
1568 err = (s16)result[0];
7558977a
MCC		 1569 if (err >= 0)
1570 goto error;
be44eb28 1571
7558977a
MCC		 1572 /* check for the known error codes */
1573 switch (err) {
1574 case SCU_RESULT_UNKCMD:
1575 p = "SCU_RESULT_UNKCMD";
1576 break;
1577 case SCU_RESULT_UNKSTD:
1578 p = "SCU_RESULT_UNKSTD";
1579 break;
1580 case SCU_RESULT_SIZE:
1581 p = "SCU_RESULT_SIZE";
1582 break;
1583 case SCU_RESULT_INVPAR:
1584 p = "SCU_RESULT_INVPAR";
1585 break;
1586 default: /* Other negative values are errors */
1587 sprintf(errname, "ERROR: %d\n", err);
1588 p = errname;
43dd07f7 1589 }
7558977a
MCC		 1590 printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1591 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1592 status = -EINVAL;
1593 goto error2;
be44eb28
MCC		 1594 }
1595
1596error:
ebc7de22 1597 if (status < 0)
be44eb28 1598 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
be44eb28
MCC		 1599error2:
1600 mutex_unlock(&state->mutex);
43dd07f7
RM		 1601 return status;
1602}
1603
1604static int SetIqmAf(struct drxk_state *state, bool active)
1605{
1606 u16 data = 0;
1607 int status;
1608
2da67501
MCC		 1609 dprintk(1, "\n");
1610
be44eb28
MCC		 1611 /* Configure IQM */
1612 status = read16(state, IQM_AF_STDBY__A, &data);
1613 if (status < 0)
1614 goto error;
1615
1616 if (!active) {
1617 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1618 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1619 | IQM_AF_STDBY_STDBY_PD_STANDBY
1620 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1621 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1622 } else {
1623 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1624 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1625 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1626 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1627 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1628 );
1629 }
1630 status = write16(state, IQM_AF_STDBY__A, data);
1631
1632error:
1633 if (status < 0)
1634 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1635 return status;
1636}
1637
ebc7de22 1638static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
43dd07f7
RM		 1639{
1640 int status = 0;
ebc7de22 1641 u16 sioCcPwdMode = 0;
43dd07f7 1642
2da67501
MCC		 1643 dprintk(1, "\n");
1644
43dd07f7
RM		 1645 /* Check arguments */
1646 if (mode == NULL)
be44eb28 1647 return -EINVAL;
43dd07f7
RM		 1648
1649 switch (*mode) {
1650 case DRX_POWER_UP:
1651 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1652 break;
1653 case DRXK_POWER_DOWN_OFDM:
1654 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1655 break;
1656 case DRXK_POWER_DOWN_CORE:
1657 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1658 break;
1659 case DRXK_POWER_DOWN_PLL:
1660 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1661 break;
1662 case DRX_POWER_DOWN:
1663 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1664 break;
1665 default:
1666 /* Unknow sleep mode */
be44eb28 1667 return -EINVAL;
43dd07f7
RM		 1668 }
1669
1670 /* If already in requested power mode, do nothing */
1671 if (state->m_currentPowerMode == *mode)
1672 return 0;
1673
1674 /* For next steps make sure to start from DRX_POWER_UP mode */
ebc7de22 1675 if (state->m_currentPowerMode != DRX_POWER_UP) {
be44eb28
MCC		 1676 status = PowerUpDevice(state);
1677 if (status < 0)
1678 goto error;
1679 status = DVBTEnableOFDMTokenRing(state, true);
1680 if (status < 0)
1681 goto error;
43dd07f7
RM		 1682 }
1683
1684 if (*mode == DRX_POWER_UP) {
1685 /* Restore analog & pin configuartion */
1686 } else {
1687 /* Power down to requested mode */
1688 /* Backup some register settings */
1689 /* Set pins with possible pull-ups connected
1690 to them in input mode */
1691 /* Analog power down */
1692 /* ADC power down */
1693 /* Power down device */
1694 /* stop all comm_exec */
1695 /* Stop and power down previous standard */
be44eb28
MCC		 1696 switch (state->m_OperationMode) {
1697 case OM_DVBT:
1698 status = MPEGTSStop(state);
ea90f011 1699 if (status < 0)
be44eb28
MCC		 1700 goto error;
1701 status = PowerDownDVBT(state, false);
ea90f011 1702 if (status < 0)
be44eb28
MCC		 1703 goto error;
1704 break;
1705 case OM_QAM_ITU_A:
1706 case OM_QAM_ITU_C:
1707 status = MPEGTSStop(state);
ea90f011 1708 if (status < 0)
be44eb28
MCC		 1709 goto error;
1710 status = PowerDownQAM(state);
1711 if (status < 0)
1712 goto error;
1713 break;
1714 default:
1715 break;
1716 }
1717 status = DVBTEnableOFDMTokenRing(state, false);
1718 if (status < 0)
1719 goto error;
1720 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1721 if (status < 0)
1722 goto error;
1723 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1724 if (status < 0)
1725 goto error;
43dd07f7 1726
be44eb28
MCC		 1727 if (*mode != DRXK_POWER_DOWN_OFDM) {
1728 state->m_HICfgCtrl |=
1729 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1730 status = HI_CfgCommand(state);
1731 if (status < 0)
1732 goto error;
1733 }
43dd07f7
RM		 1734 }
1735 state->m_currentPowerMode = *mode;
be44eb28
MCC		 1736
1737error:
1738 if (status < 0)
1739 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1740
ebc7de22 1741 return status;
43dd07f7
RM		 1742}
1743
1744static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1745{
ebc7de22 1746 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
43dd07f7
RM		 1747 u16 cmdResult = 0;
1748 u16 data = 0;
1749 int status;
1750
2da67501
MCC		 1751 dprintk(1, "\n");
1752
be44eb28
MCC		 1753 status = read16(state, SCU_COMM_EXEC__A, &data);
1754 if (status < 0)
1755 goto error;
1756 if (data == SCU_COMM_EXEC_ACTIVE) {
1757 /* Send OFDM stop command */
1758 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
ea90f011 1759 if (status < 0)
be44eb28
MCC		 1760 goto error;
1761 /* Send OFDM reset command */
1762 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
ea90f011 1763 if (status < 0)
be44eb28
MCC		 1764 goto error;
1765 }
43dd07f7 1766
be44eb28
MCC		 1767 /* Reset datapath for OFDM, processors first */
1768 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1769 if (status < 0)
1770 goto error;
1771 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1772 if (status < 0)
1773 goto error;
1774 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1775 if (status < 0)
1776 goto error;
43dd07f7 1777
be44eb28
MCC		 1778 /* powerdown AFE */
1779 status = SetIqmAf(state, false);
1780 if (status < 0)
1781 goto error;
1782
1783 /* powerdown to OFDM mode */
1784 if (setPowerMode) {
1785 status = CtrlPowerMode(state, &powerMode);
1786 if (status < 0)
1787 goto error;
1788 }
1789error:
1790 if (status < 0)
1791 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1792 return status;
1793}
1794
ebc7de22
OE		 1795static int SetOperationMode(struct drxk_state *state,
1796 enum OperationMode oMode)
43dd07f7
RM		 1797{
1798 int status = 0;
1799
2da67501 1800 dprintk(1, "\n");
43dd07f7 1801 /*
ebc7de22
OE		 1802 Stop and power down previous standard
1803 TODO investigate total power down instead of partial
1804 power down depending on "previous" standard.
1805 */
43dd07f7 1806
be44eb28
MCC		 1807 /* disable HW lock indicator */
1808 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1809 if (status < 0)
1810 goto error;
43dd07f7 1811
f1b82970
MCC		 1812 /* Device is already at the required mode */
1813 if (state->m_OperationMode == oMode)
1814 return 0;
1815
1816 switch (state->m_OperationMode) {
1817 /* OM_NONE was added for start up */
1818 case OM_NONE:
1819 break;
1820 case OM_DVBT:
1821 status = MPEGTSStop(state);
1822 if (status < 0)
be44eb28 1823 goto error;
f1b82970
MCC		 1824 status = PowerDownDVBT(state, true);
1825 if (status < 0)
1826 goto error;
1827 state->m_OperationMode = OM_NONE;
1828 break;
1829 case OM_QAM_ITU_A: /* fallthrough */
1830 case OM_QAM_ITU_C:
1831 status = MPEGTSStop(state);
1832 if (status < 0)
1833 goto error;
1834 status = PowerDownQAM(state);
1835 if (status < 0)
1836 goto error;
1837 state->m_OperationMode = OM_NONE;
1838 break;
1839 case OM_QAM_ITU_B:
1840 default:
1841 status = -EINVAL;
1842 goto error;
1843 }
be44eb28 1844
f1b82970
MCC		 1845 /*
1846 Power up new standard
1847 */
1848 switch (oMode) {
1849 case OM_DVBT:
1850 state->m_OperationMode = oMode;
1851 status = SetDVBTStandard(state, oMode);
1852 if (status < 0)
1853 goto error;
1854 break;
1855 case OM_QAM_ITU_A: /* fallthrough */
1856 case OM_QAM_ITU_C:
1857 state->m_OperationMode = oMode;
1858 status = SetQAMStandard(state, oMode);
1859 if (status < 0)
1860 goto error;
1861 break;
1862 case OM_QAM_ITU_B:
1863 default:
1864 status = -EINVAL;
be44eb28
MCC		 1865 }
1866error:
1867 if (status < 0)
1868 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1869 return status;
43dd07f7
RM		 1870}
1871
1872static int Start(struct drxk_state *state, s32 offsetFreq,
1873 s32 IntermediateFrequency)
1874{
be44eb28
MCC		 1875 int status = -EINVAL;
1876
1877 u16 IFreqkHz;
1878 s32 OffsetkHz = offsetFreq / 1000;
43dd07f7 1879
2da67501 1880 dprintk(1, "\n");
be44eb28
MCC		 1881 if (state->m_DrxkState != DRXK_STOPPED &&
1882 state->m_DrxkState != DRXK_DTV_STARTED)
1883 goto error;
43dd07f7 1884
be44eb28 1885 state->m_bMirrorFreqSpect = (state->param.inversion == INVERSION_ON);
43dd07f7 1886
be44eb28
MCC		 1887 if (IntermediateFrequency < 0) {
1888 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1889 IntermediateFrequency = -IntermediateFrequency;
1890 }
43dd07f7 1891
be44eb28
MCC		 1892 switch (state->m_OperationMode) {
1893 case OM_QAM_ITU_A:
1894 case OM_QAM_ITU_C:
1895 IFreqkHz = (IntermediateFrequency / 1000);
1896 status = SetQAM(state, IFreqkHz, OffsetkHz);
1897 if (status < 0)
1898 goto error;
1899 state->m_DrxkState = DRXK_DTV_STARTED;
1900 break;
1901 case OM_DVBT:
1902 IFreqkHz = (IntermediateFrequency / 1000);
1903 status = MPEGTSStop(state);
1904 if (status < 0)
1905 goto error;
1906 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1907 if (status < 0)
1908 goto error;
1909 status = DVBTStart(state);
1910 if (status < 0)
1911 goto error;
1912 state->m_DrxkState = DRXK_DTV_STARTED;
1913 break;
1914 default:
1915 break;
1916 }
1917error:
1918 if (status < 0)
1919 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1920 return status;
1921}
1922
1923static int ShutDown(struct drxk_state *state)
1924{
2da67501
MCC		 1925 dprintk(1, "\n");
1926
43dd07f7
RM		 1927 MPEGTSStop(state);
1928 return 0;
1929}
1930
ebc7de22
OE		 1931static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1932 u32 Time)
43dd07f7 1933{
be44eb28 1934 int status = -EINVAL;
43dd07f7 1935
2da67501
MCC		 1936 dprintk(1, "\n");
1937
43dd07f7 1938 if (pLockStatus == NULL)
be44eb28 1939 goto error;
43dd07f7
RM		 1940
1941 *pLockStatus = NOT_LOCKED;
1942
1943 /* define the SCU command code */
1944 switch (state->m_OperationMode) {
1945 case OM_QAM_ITU_A:
1946 case OM_QAM_ITU_B:
1947 case OM_QAM_ITU_C:
1948 status = GetQAMLockStatus(state, pLockStatus);
1949 break;
1950 case OM_DVBT:
1951 status = GetDVBTLockStatus(state, pLockStatus);
1952 break;
1953 default:
1954 break;
1955 }
be44eb28
MCC		 1956error:
1957 if (status < 0)
1958 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1959 return status;
1960}
1961
1962static int MPEGTSStart(struct drxk_state *state)
1963{
be44eb28 1964 int status;
43dd07f7
RM		 1965
1966 u16 fecOcSncMode = 0;
1967
be44eb28
MCC		 1968 /* Allow OC to sync again */
1969 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1970 if (status < 0)
1971 goto error;
1972 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1973 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1974 if (status < 0)
1975 goto error;
1976 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1977error:
1978 if (status < 0)
1979 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 1980 return status;
1981}
1982
1983static int MPEGTSDtoInit(struct drxk_state *state)
1984{
be44eb28 1985 int status;
43dd07f7 1986
2da67501
MCC		 1987 dprintk(1, "\n");
1988
be44eb28
MCC		 1989 /* Rate integration settings */
1990 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1991 if (status < 0)
1992 goto error;
1993 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1994 if (status < 0)
1995 goto error;
1996 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1997 if (status < 0)
1998 goto error;
1999 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
2000 if (status < 0)
2001 goto error;
2002 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
2003 if (status < 0)
2004 goto error;
2005 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
2006 if (status < 0)
2007 goto error;
2008 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
2009 if (status < 0)
2010 goto error;
2011 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
2012 if (status < 0)
2013 goto error;
2014
2015 /* Additional configuration */
2016 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
2017 if (status < 0)
2018 goto error;
2019 status = write16(state, FEC_OC_SNC_LWM__A, 2);
2020 if (status < 0)
2021 goto error;
2022 status = write16(state, FEC_OC_SNC_HWM__A, 12);
2023error:
2024 if (status < 0)
2025 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7 2026
43dd07f7
RM		 2027 return status;
2028}
2029
ebc7de22
OE		 2030static int MPEGTSDtoSetup(struct drxk_state *state,
2031 enum OperationMode oMode)
43dd07f7 2032{
be44eb28 2033 int status;
43dd07f7 2034
ebc7de22
OE		 2035 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
2036 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
2037 u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
2038 u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
2039 u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
2040 u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
2041 u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
43dd07f7
RM		 2042 u16 fecOcTmdMode = 0;
2043 u16 fecOcTmdIntUpdRate = 0;
ebc7de22 2044 u32 maxBitRate = 0;
43dd07f7
RM		 2045 bool staticCLK = false;
2046
2da67501
MCC		 2047 dprintk(1, "\n");
2048
be44eb28
MCC		 2049 /* Check insertion of the Reed-Solomon parity bytes */
2050 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2051 if (status < 0)
2052 goto error;
2053 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2054 if (status < 0)
2055 goto error;
2056 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2057 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2058 if (state->m_insertRSByte == true) {
2059 /* enable parity symbol forward */
2060 fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2061 /* MVAL disable during parity bytes */
2062 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2063 /* TS burst length to 204 */
2064 fecOcDtoBurstLen = 204;
2065 }
43dd07f7 2066
be44eb28
MCC		 2067 /* Check serial or parrallel output */
2068 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2069 if (state->m_enableParallel == false) {
2070 /* MPEG data output is serial -> set ipr_mode[0] */
2071 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2072 }
43dd07f7 2073
be44eb28
MCC		 2074 switch (oMode) {
2075 case OM_DVBT:
2076 maxBitRate = state->m_DVBTBitrate;
2077 fecOcTmdMode = 3;
2078 fecOcRcnCtlRate = 0xC00000;
2079 staticCLK = state->m_DVBTStaticCLK;
2080 break;
2081 case OM_QAM_ITU_A: /* fallthrough */
2082 case OM_QAM_ITU_C:
2083 fecOcTmdMode = 0x0004;
2084 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
2085 maxBitRate = state->m_DVBCBitrate;
2086 staticCLK = state->m_DVBCStaticCLK;
2087 break;
2088 default:
2089 status = -EINVAL;
2090 } /* switch (standard) */
2091 if (status < 0)
2092 goto error;
2093
2094 /* Configure DTO's */
2095 if (staticCLK) {
2096 u32 bitRate = 0;
2097
2098 /* Rational DTO for MCLK source (static MCLK rate),
2099 Dynamic DTO for optimal grouping
2100 (avoid intra-packet gaps),
2101 DTO offset enable to sync TS burst with MSTRT */
2102 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2103 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2104 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2105 FEC_OC_FCT_MODE_VIRT_ENA__M);
2106
2107 /* Check user defined bitrate */
2108 bitRate = maxBitRate;
2109 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
2110 bitRate = 75900000UL;
43dd07f7 2111 }
be44eb28
MCC		 2112 /* Rational DTO period:
2113 dto_period = (Fsys / bitrate) - 2
2114
2115 Result should be floored,
2116 to make sure >= requested bitrate
2117 */
2118 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2119 * 1000) / bitRate);
2120 if (fecOcDtoPeriod <= 2)
2121 fecOcDtoPeriod = 0;
2122 else
2123 fecOcDtoPeriod -= 2;
2124 fecOcTmdIntUpdRate = 8;
2125 } else {
2126 /* (commonAttr->staticCLK == false) => dynamic mode */
2127 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2128 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2129 fecOcTmdIntUpdRate = 5;
2130 }
43dd07f7 2131
be44eb28
MCC		 2132 /* Write appropriate registers with requested configuration */
2133 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2134 if (status < 0)
2135 goto error;
2136 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2137 if (status < 0)
2138 goto error;
2139 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2140 if (status < 0)
2141 goto error;
2142 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2143 if (status < 0)
2144 goto error;
2145 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2146 if (status < 0)
2147 goto error;
2148 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2149 if (status < 0)
2150 goto error;
43dd07f7 2151
be44eb28
MCC		 2152 /* Rate integration settings */
2153 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2154 if (status < 0)
2155 goto error;
2156 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2157 if (status < 0)
2158 goto error;
2159 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2160error:
2161 if (status < 0)
2162 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2163 return status;
2164}
2165
2166static int MPEGTSConfigurePolarity(struct drxk_state *state)
2167{
ebc7de22 2168 u16 fecOcRegIprInvert = 0;
43dd07f7
RM		 2169
2170 /* Data mask for the output data byte */
2171 u16 InvertDataMask =
ebc7de22
OE		 2172 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2173 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2174 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2175 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
43dd07f7 2176
be44eb28
MCC		 2177 dprintk(1, "\n");
2178
43dd07f7
RM		 2179 /* Control selective inversion of output bits */
2180 fecOcRegIprInvert &= (~(InvertDataMask));
2181 if (state->m_invertDATA == true)
2182 fecOcRegIprInvert |= InvertDataMask;
2183 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2184 if (state->m_invertERR == true)
2185 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2186 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2187 if (state->m_invertSTR == true)
2188 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2189 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2190 if (state->m_invertVAL == true)
2191 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2192 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2193 if (state->m_invertCLK == true)
2194 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
be44eb28
MCC		 2195
2196 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
43dd07f7
RM		 2197}
2198
2199#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2200
2201static int SetAgcRf(struct drxk_state *state,
2202 struct SCfgAgc *pAgcCfg, bool isDTV)
2203{
be44eb28
MCC		 2204 int status = -EINVAL;
2205 u16 data = 0;
43dd07f7
RM		 2206 struct SCfgAgc *pIfAgcSettings;
2207
2da67501
MCC		 2208 dprintk(1, "\n");
2209
43dd07f7 2210 if (pAgcCfg == NULL)
be44eb28 2211 goto error;
43dd07f7 2212
be44eb28
MCC		 2213 switch (pAgcCfg->ctrlMode) {
2214 case DRXK_AGC_CTRL_AUTO:
2215 /* Enable RF AGC DAC */
2216 status = read16(state, IQM_AF_STDBY__A, &data);
2217 if (status < 0)
2218 goto error;
2219 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2220 status = write16(state, IQM_AF_STDBY__A, data);
2221 if (status < 0)
2222 goto error;
2223 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2224 if (status < 0)
2225 goto error;
43dd07f7 2226
be44eb28
MCC		 2227 /* Enable SCU RF AGC loop */
2228 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
43dd07f7 2229
be44eb28
MCC		 2230 /* Polarity */
2231 if (state->m_RfAgcPol)
2232 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2233 else
2234 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2235 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2236 if (status < 0)
2237 goto error;
43dd07f7 2238
be44eb28
MCC		 2239 /* Set speed (using complementary reduction value) */
2240 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2241 if (status < 0)
2242 goto error;
43dd07f7 2243
be44eb28
MCC		 2244 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2245 data |= (~(pAgcCfg->speed <<
2246 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2247 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
43dd07f7 2248
be44eb28
MCC		 2249 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2250 if (status < 0)
2251 goto error;
43dd07f7 2252
be44eb28
MCC		 2253 if (IsDVBT(state))
2254 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2255 else if (IsQAM(state))
2256 pIfAgcSettings = &state->m_qamIfAgcCfg;
2257 else
2258 pIfAgcSettings = &state->m_atvIfAgcCfg;
2259 if (pIfAgcSettings == NULL) {
2260 status = -EINVAL;
2261 goto error;
2262 }
43dd07f7 2263
be44eb28
MCC		 2264 /* Set TOP, only if IF-AGC is in AUTO mode */
2265 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2266 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
ea90f011 2267 if (status < 0)
be44eb28 2268 goto error;
43dd07f7 2269
be44eb28
MCC		 2270 /* Cut-Off current */
2271 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2272 if (status < 0)
2273 goto error;
43dd07f7 2274
be44eb28
MCC		 2275 /* Max. output level */
2276 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2277 if (status < 0)
2278 goto error;
43dd07f7 2279
be44eb28 2280 break;
43dd07f7 2281
be44eb28
MCC		 2282 case DRXK_AGC_CTRL_USER:
2283 /* Enable RF AGC DAC */
2284 status = read16(state, IQM_AF_STDBY__A, &data);
2285 if (status < 0)
2286 goto error;
2287 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2288 status = write16(state, IQM_AF_STDBY__A, data);
2289 if (status < 0)
2290 goto error;
43dd07f7 2291
be44eb28
MCC		 2292 /* Disable SCU RF AGC loop */
2293 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2294 if (status < 0)
2295 goto error;
2296 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2297 if (state->m_RfAgcPol)
2298 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2299 else
2300 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2301 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2302 if (status < 0)
2303 goto error;
43dd07f7 2304
be44eb28
MCC		 2305 /* SCU c.o.c. to 0, enabling full control range */
2306 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2307 if (status < 0)
2308 goto error;
43dd07f7 2309
be44eb28
MCC		 2310 /* Write value to output pin */
2311 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2312 if (status < 0)
2313 goto error;
2314 break;
43dd07f7 2315
be44eb28
MCC		 2316 case DRXK_AGC_CTRL_OFF:
2317 /* Disable RF AGC DAC */
2318 status = read16(state, IQM_AF_STDBY__A, &data);
2319 if (status < 0)
2320 goto error;
2321 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2322 status = write16(state, IQM_AF_STDBY__A, data);
2323 if (status < 0)
2324 goto error;
43dd07f7 2325
be44eb28
MCC		 2326 /* Disable SCU RF AGC loop */
2327 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2328 if (status < 0)
2329 goto error;
2330 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2331 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2332 if (status < 0)
2333 goto error;
2334 break;
43dd07f7 2335
be44eb28
MCC		 2336 default:
2337 status = -EINVAL;
43dd07f7 2338
be44eb28
MCC		 2339 }
2340error:
2341 if (status < 0)
2342 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2343 return status;
2344}
2345
2346#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2347
ebc7de22
OE		 2348static int SetAgcIf(struct drxk_state *state,
2349 struct SCfgAgc *pAgcCfg, bool isDTV)
43dd07f7
RM		 2350{
2351 u16 data = 0;
2352 int status = 0;
2353 struct SCfgAgc *pRfAgcSettings;
2354
2da67501
MCC		 2355 dprintk(1, "\n");
2356
be44eb28
MCC		 2357 switch (pAgcCfg->ctrlMode) {
2358 case DRXK_AGC_CTRL_AUTO:
43dd07f7 2359
be44eb28
MCC		 2360 /* Enable IF AGC DAC */
2361 status = read16(state, IQM_AF_STDBY__A, &data);
2362 if (status < 0)
2363 goto error;
2364 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2365 status = write16(state, IQM_AF_STDBY__A, data);
2366 if (status < 0)
2367 goto error;
43dd07f7 2368
be44eb28
MCC		 2369 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2370 if (status < 0)
2371 goto error;
43dd07f7 2372
be44eb28
MCC		 2373 /* Enable SCU IF AGC loop */
2374 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
43dd07f7 2375
be44eb28
MCC		 2376 /* Polarity */
2377 if (state->m_IfAgcPol)
2378 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2379 else
2380 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2381 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2382 if (status < 0)
2383 goto error;
43dd07f7 2384
be44eb28
MCC		 2385 /* Set speed (using complementary reduction value) */
2386 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2387 if (status < 0)
2388 goto error;
2389 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2390 data |= (~(pAgcCfg->speed <<
2391 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2392 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
43dd07f7 2393
be44eb28
MCC		 2394 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2395 if (status < 0)
2396 goto error;
43dd07f7 2397
be44eb28
MCC		 2398 if (IsQAM(state))
2399 pRfAgcSettings = &state->m_qamRfAgcCfg;
2400 else
2401 pRfAgcSettings = &state->m_atvRfAgcCfg;
2402 if (pRfAgcSettings == NULL)
2403 return -1;
2404 /* Restore TOP */
2405 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2406 if (status < 0)
2407 goto error;
2408 break;
43dd07f7 2409
be44eb28 2410 case DRXK_AGC_CTRL_USER:
43dd07f7 2411
be44eb28
MCC		 2412 /* Enable IF AGC DAC */
2413 status = read16(state, IQM_AF_STDBY__A, &data);
2414 if (status < 0)
2415 goto error;
2416 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2417 status = write16(state, IQM_AF_STDBY__A, data);
2418 if (status < 0)
2419 goto error;
43dd07f7 2420
be44eb28
MCC		 2421 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2422 if (status < 0)
2423 goto error;
43dd07f7 2424
be44eb28
MCC		 2425 /* Disable SCU IF AGC loop */
2426 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
43dd07f7 2427
be44eb28
MCC		 2428 /* Polarity */
2429 if (state->m_IfAgcPol)
2430 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2431 else
2432 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2433 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2434 if (status < 0)
2435 goto error;
43dd07f7 2436
be44eb28
MCC		 2437 /* Write value to output pin */
2438 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2439 if (status < 0)
2440 goto error;
2441 break;
43dd07f7 2442
be44eb28 2443 case DRXK_AGC_CTRL_OFF:
43dd07f7 2444
be44eb28
MCC		 2445 /* Disable If AGC DAC */
2446 status = read16(state, IQM_AF_STDBY__A, &data);
ea90f011 2447 if (status < 0)
be44eb28
MCC		 2448 goto error;
2449 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2450 status = write16(state, IQM_AF_STDBY__A, data);
2451 if (status < 0)
2452 goto error;
43dd07f7 2453
be44eb28
MCC		 2454 /* Disable SCU IF AGC loop */
2455 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2456 if (status < 0)
2457 goto error;
2458 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2459 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2460 if (status < 0)
2461 goto error;
2462 break;
2463 } /* switch (agcSettingsIf->ctrlMode) */
43dd07f7 2464
be44eb28
MCC		 2465 /* always set the top to support
2466 configurations without if-loop */
2467 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2468error:
2469 if (status < 0)
2470 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2471 return status;
2472}
2473
2474static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2475{
2476 u16 agcDacLvl;
be44eb28
MCC		 2477 int status;
2478 u16 Level = 0;
43dd07f7 2479
2da67501
MCC		 2480 dprintk(1, "\n");
2481
be44eb28
MCC		 2482 status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2483 if (status < 0) {
2484 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2485 return status;
2486 }
2487
43dd07f7
RM		 2488 *pValue = 0;
2489
be44eb28
MCC		 2490 if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2491 Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2492 if (Level < 14000)
2493 *pValue = (14000 - Level) / 4;
2494 else
2495 *pValue = 0;
2496
43dd07f7
RM		 2497 return status;
2498}
2499
ebc7de22
OE		 2500static int GetQAMSignalToNoise(struct drxk_state *state,
2501 s32 *pSignalToNoise)
43dd07f7
RM		 2502{
2503 int status = 0;
be44eb28
MCC		 2504 u16 qamSlErrPower = 0; /* accum. error between
2505 raw and sliced symbols */
2506 u32 qamSlSigPower = 0; /* used for MER, depends of
2507 QAM constellation */
2508 u32 qamSlMer = 0; /* QAM MER */
43dd07f7 2509
2da67501
MCC		 2510 dprintk(1, "\n");
2511
be44eb28 2512 /* MER calculation */
43dd07f7 2513
be44eb28
MCC		 2514 /* get the register value needed for MER */
2515 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2516 if (status < 0) {
2517 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2518 return -EINVAL;
2519 }
2520
2521 switch (state->param.u.qam.modulation) {
2522 case QAM_16:
2523 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2524 break;
2525 case QAM_32:
2526 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2527 break;
2528 case QAM_64:
2529 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2530 break;
2531 case QAM_128:
2532 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2533 break;
2534 default:
2535 case QAM_256:
2536 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2537 break;
2538 }
2539
2540 if (qamSlErrPower > 0) {
2541 qamSlMer = Log10Times100(qamSlSigPower) -
2542 Log10Times100((u32) qamSlErrPower);
2543 }
2544 *pSignalToNoise = qamSlMer;
43dd07f7 2545
43dd07f7
RM		 2546 return status;
2547}
2548
ebc7de22
OE		 2549static int GetDVBTSignalToNoise(struct drxk_state *state,
2550 s32 *pSignalToNoise)
43dd07f7 2551{
be44eb28 2552 int status;
ebc7de22
OE		 2553 u16 regData = 0;
2554 u32 EqRegTdSqrErrI = 0;
2555 u32 EqRegTdSqrErrQ = 0;
2556 u16 EqRegTdSqrErrExp = 0;
2557 u16 EqRegTdTpsPwrOfs = 0;
2558 u16 EqRegTdReqSmbCnt = 0;
2559 u32 tpsCnt = 0;
2560 u32 SqrErrIQ = 0;
2561 u32 a = 0;
2562 u32 b = 0;
2563 u32 c = 0;
2564 u32 iMER = 0;
43dd07f7
RM		 2565 u16 transmissionParams = 0;
2566
2da67501 2567 dprintk(1, "\n");
43dd07f7 2568
be44eb28
MCC		 2569 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2570 if (status < 0)
2571 goto error;
2572 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2573 if (status < 0)
2574 goto error;
2575 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2576 if (status < 0)
2577 goto error;
2578 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData);
2579 if (status < 0)
2580 goto error;
2581 /* Extend SQR_ERR_I operational range */
2582 EqRegTdSqrErrI = (u32) regData;
2583 if ((EqRegTdSqrErrExp > 11) &&
2584 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2585 EqRegTdSqrErrI += 0x00010000UL;
2586 }
2587 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData);
2588 if (status < 0)
2589 goto error;
2590 /* Extend SQR_ERR_Q operational range */
2591 EqRegTdSqrErrQ = (u32) regData;
2592 if ((EqRegTdSqrErrExp > 11) &&
2593 (EqRegTdSqrErrQ < 0x00000FFFUL))
2594 EqRegTdSqrErrQ += 0x00010000UL;
2595
2596 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2597 if (status < 0)
2598 goto error;
2599
2600 /* Check input data for MER */
2601
2602 /* MER calculation (in 0.1 dB) without math.h */
2603 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2604 iMER = 0;
2605 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2606 /* No error at all, this must be the HW reset value
2607 * Apparently no first measurement yet
2608 * Set MER to 0.0 */
2609 iMER = 0;
2610 } else {
2611 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2612 EqRegTdSqrErrExp;
2613 if ((transmissionParams &
2614 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2615 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2616 tpsCnt = 17;
2617 else
2618 tpsCnt = 68;
2619
2620 /* IMER = 100 * log10 (x)
2621 where x = (EqRegTdTpsPwrOfs^2 *
2622 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2623
2624 => IMER = a + b -c
2625 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2626 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2627 c = 100 * log10 (SqrErrIQ)
2628 */
2629
2630 /* log(x) x = 9bits * 9bits->18 bits */
2631 a = Log10Times100(EqRegTdTpsPwrOfs *
2632 EqRegTdTpsPwrOfs);
2633 /* log(x) x = 16bits * 7bits->23 bits */
2634 b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2635 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2636 c = Log10Times100(SqrErrIQ);
2637
2638 iMER = a + b;
2639 /* No negative MER, clip to zero */
2640 if (iMER > c)
2641 iMER -= c;
2642 else
43dd07f7 2643 iMER = 0;
be44eb28
MCC		 2644 }
2645 *pSignalToNoise = iMER;
43dd07f7 2646
be44eb28
MCC		 2647error:
2648 if (status < 0)
2649 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2650 return status;
2651}
2652
2653static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2654{
2da67501
MCC		 2655 dprintk(1, "\n");
2656
43dd07f7 2657 *pSignalToNoise = 0;
ebc7de22 2658 switch (state->m_OperationMode) {
43dd07f7
RM		 2659 case OM_DVBT:
2660 return GetDVBTSignalToNoise(state, pSignalToNoise);
2661 case OM_QAM_ITU_A:
2662 case OM_QAM_ITU_C:
2663 return GetQAMSignalToNoise(state, pSignalToNoise);
2664 default:
2665 break;
2666 }
2667 return 0;
2668}
2669
2670#if 0
2671static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2672{
2673 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2674 int status = 0;
2675
2da67501
MCC		 2676 dprintk(1, "\n");
2677
ebc7de22
OE		 2678 static s32 QE_SN[] = {
2679 51, /* QPSK 1/2 */
2680 69, /* QPSK 2/3 */
2681 79, /* QPSK 3/4 */
2682 89, /* QPSK 5/6 */
2683 97, /* QPSK 7/8 */
2684 108, /* 16-QAM 1/2 */
2685 131, /* 16-QAM 2/3 */
2686 146, /* 16-QAM 3/4 */
2687 156, /* 16-QAM 5/6 */
2688 160, /* 16-QAM 7/8 */
2689 165, /* 64-QAM 1/2 */
2690 187, /* 64-QAM 2/3 */
2691 202, /* 64-QAM 3/4 */
2692 216, /* 64-QAM 5/6 */
2693 225, /* 64-QAM 7/8 */
2694 };
43dd07f7
RM		 2695
2696 *pQuality = 0;
2697
2698 do {
2699 s32 SignalToNoise = 0;
2700 u16 Constellation = 0;
2701 u16 CodeRate = 0;
2702 u32 SignalToNoiseRel;
2703 u32 BERQuality;
2704
ea90f011
MCC		 2705 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2706 if (status < 0)
2707 break;
5e66b878 2708 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
ea90f011
MCC		 2709 if (status < 0)
2710 break;
43dd07f7
RM		 2711 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2712
5e66b878 2713 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
ea90f011
MCC		 2714 if (status < 0)
2715 break;
43dd07f7
RM		 2716 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2717
2718 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2719 CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2720 break;
2721 SignalToNoiseRel = SignalToNoise -
ebc7de22 2722 QE_SN[Constellation * 5 + CodeRate];
43dd07f7
RM		 2723 BERQuality = 100;
2724
ebc7de22
OE		 2725 if (SignalToNoiseRel < -70)
2726 *pQuality = 0;
43dd07f7
RM		 2727 else if (SignalToNoiseRel < 30)
2728 *pQuality = ((SignalToNoiseRel + 70) *
2729 BERQuality) / 100;
2730 else
2731 *pQuality = BERQuality;
ebc7de22 2732 } while (0);
43dd07f7
RM		 2733 return 0;
2734};
2735
ebc7de22 2736static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
43dd07f7
RM		 2737{
2738 int status = 0;
2739 *pQuality = 0;
2740
2da67501
MCC		 2741 dprintk(1, "\n");
2742
43dd07f7
RM		 2743 do {
2744 u32 SignalToNoise = 0;
2745 u32 BERQuality = 100;
2746 u32 SignalToNoiseRel = 0;
2747
ea90f011
MCC		 2748 status = GetQAMSignalToNoise(state, &SignalToNoise);
2749 if (status < 0)
2750 break;
43dd07f7 2751
ebc7de22 2752 switch (state->param.u.qam.modulation) {
43dd07f7
RM		 2753 case QAM_16:
2754 SignalToNoiseRel = SignalToNoise - 200;
2755 break;
2756 case QAM_32:
2757 SignalToNoiseRel = SignalToNoise - 230;
ebc7de22 2758 break; /* Not in NorDig */
43dd07f7
RM		 2759 case QAM_64:
2760 SignalToNoiseRel = SignalToNoise - 260;
2761 break;
2762 case QAM_128:
2763 SignalToNoiseRel = SignalToNoise - 290;
2764 break;
2765 default:
2766 case QAM_256:
2767 SignalToNoiseRel = SignalToNoise - 320;
2768 break;
2769 }
2770
2771 if (SignalToNoiseRel < -70)
2772 *pQuality = 0;
2773 else if (SignalToNoiseRel < 30)
2774 *pQuality = ((SignalToNoiseRel + 70) *
2775 BERQuality) / 100;
2776 else
2777 *pQuality = BERQuality;
ebc7de22 2778 } while (0);
43dd07f7
RM		 2779
2780 return status;
2781}
2782
2783static int GetQuality(struct drxk_state *state, s32 *pQuality)
2784{
2da67501
MCC		 2785 dprintk(1, "\n");
2786
ebc7de22
OE		 2787 switch (state->m_OperationMode) {
2788 case OM_DVBT:
43dd07f7 2789 return GetDVBTQuality(state, pQuality);
ebc7de22 2790 case OM_QAM_ITU_A:
43dd07f7
RM		 2791 return GetDVBCQuality(state, pQuality);
2792 default:
2793 break;
2794 }
2795
2796 return 0;
2797}
2798#endif
2799
2800/* Free data ram in SIO HI */
2801#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2802#define SIO_HI_RA_RAM_USR_END__A 0x420060
2803
2804#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2805#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2806#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2807#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2808
2809#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2810#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2811#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2812
2813static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2814{
be44eb28 2815 int status = -EINVAL;
43dd07f7 2816
2da67501
MCC		 2817 dprintk(1, "\n");
2818
43dd07f7 2819 if (state->m_DrxkState == DRXK_UNINITIALIZED)
be44eb28 2820 goto error;
43dd07f7 2821 if (state->m_DrxkState == DRXK_POWERED_DOWN)
be44eb28 2822 goto error;
43dd07f7 2823
f1fe1b75
MCC		 2824 if (state->no_i2c_bridge)
2825 return 0;
43dd07f7 2826
be44eb28
MCC		 2827 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2828 if (status < 0)
2829 goto error;
2830 if (bEnableBridge) {
2831 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
ea90f011 2832 if (status < 0)
be44eb28
MCC		 2833 goto error;
2834 } else {
2835 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2836 if (status < 0)
2837 goto error;
2838 }
2839
2840 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2841
2842error:
2843 if (status < 0)
2844 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2845 return status;
2846}
2847
ebc7de22
OE		 2848static int SetPreSaw(struct drxk_state *state,
2849 struct SCfgPreSaw *pPreSawCfg)
43dd07f7 2850{
be44eb28 2851 int status = -EINVAL;
43dd07f7 2852
2da67501
MCC		 2853 dprintk(1, "\n");
2854
ebc7de22
OE		 2855 if ((pPreSawCfg == NULL)
2856 || (pPreSawCfg->reference > IQM_AF_PDREF__M))
be44eb28 2857 goto error;
43dd07f7 2858
5e66b878 2859 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
be44eb28
MCC		 2860error:
2861 if (status < 0)
2862 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2863 return status;
2864}
2865
2866static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
ebc7de22 2867 u16 romOffset, u16 nrOfElements, u32 timeOut)
43dd07f7 2868{
ebc7de22
OE		 2869 u16 blStatus = 0;
2870 u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2871 u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2872 int status;
43dd07f7
RM		 2873 unsigned long end;
2874
2da67501
MCC		 2875 dprintk(1, "\n");
2876
43dd07f7 2877 mutex_lock(&state->mutex);
be44eb28
MCC		 2878 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2879 if (status < 0)
2880 goto error;
2881 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2882 if (status < 0)
2883 goto error;
2884 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2885 if (status < 0)
2886 goto error;
2887 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2888 if (status < 0)
2889 goto error;
2890 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2891 if (status < 0)
2892 goto error;
2893 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2894 if (status < 0)
2895 goto error;
2896
2897 end = jiffies + msecs_to_jiffies(timeOut);
43dd07f7 2898 do {
be44eb28 2899 status = read16(state, SIO_BL_STATUS__A, &blStatus);
ea90f011 2900 if (status < 0)
be44eb28
MCC		 2901 goto error;
2902 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2903 if (blStatus == 0x1) {
2904 printk(KERN_ERR "drxk: SIO not ready\n");
2905 status = -EINVAL;
2906 goto error2;
2907 }
2908error:
2909 if (status < 0)
2910 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2911error2:
43dd07f7
RM		 2912 mutex_unlock(&state->mutex);
2913 return status;
2914
2915}
2916
ebc7de22 2917static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
43dd07f7
RM		 2918{
2919 u16 data = 0;
2920 int status;
2921
2da67501
MCC		 2922 dprintk(1, "\n");
2923
be44eb28
MCC		 2924 /* Start measurement */
2925 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2926 if (status < 0)
2927 goto error;
2928 status = write16(state, IQM_AF_START_LOCK__A, 1);
2929 if (status < 0)
2930 goto error;
43dd07f7 2931
be44eb28
MCC		 2932 *count = 0;
2933 status = read16(state, IQM_AF_PHASE0__A, &data);
2934 if (status < 0)
2935 goto error;
2936 if (data == 127)
2937 *count = *count + 1;
2938 status = read16(state, IQM_AF_PHASE1__A, &data);
2939 if (status < 0)
2940 goto error;
2941 if (data == 127)
2942 *count = *count + 1;
2943 status = read16(state, IQM_AF_PHASE2__A, &data);
2944 if (status < 0)
2945 goto error;
2946 if (data == 127)
2947 *count = *count + 1;
2948
2949error:
2950 if (status < 0)
2951 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2952 return status;
2953}
2954
2955static int ADCSynchronization(struct drxk_state *state)
2956{
2957 u16 count = 0;
2958 int status;
2959
2da67501
MCC		 2960 dprintk(1, "\n");
2961
be44eb28
MCC		 2962 status = ADCSyncMeasurement(state, &count);
2963 if (status < 0)
2964 goto error;
43dd07f7 2965
be44eb28
MCC		 2966 if (count == 1) {
2967 /* Try sampling on a diffrent edge */
2968 u16 clkNeg = 0;
43dd07f7 2969
be44eb28
MCC		 2970 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2971 if (status < 0)
2972 goto error;
2973 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2974 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2975 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2976 clkNeg |=
2977 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2978 } else {
2979 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2980 clkNeg |=
2981 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
43dd07f7 2982 }
be44eb28
MCC		 2983 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2984 if (status < 0)
2985 goto error;
2986 status = ADCSyncMeasurement(state, &count);
2987 if (status < 0)
2988 goto error;
2989 }
43dd07f7 2990
be44eb28
MCC		 2991 if (count < 2)
2992 status = -EINVAL;
2993error:
2994 if (status < 0)
2995 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 2996 return status;
2997}
2998
2999static int SetFrequencyShifter(struct drxk_state *state,
3000 u16 intermediateFreqkHz,
ebc7de22 3001 s32 tunerFreqOffset, bool isDTV)
43dd07f7
RM		 3002{
3003 bool selectPosImage = false;
ebc7de22 3004 u32 rfFreqResidual = tunerFreqOffset;
43dd07f7
RM		 3005 u32 fmFrequencyShift = 0;
3006 bool tunerMirror = !state->m_bMirrorFreqSpect;
3007 u32 adcFreq;
3008 bool adcFlip;
3009 int status;
3010 u32 ifFreqActual;
ebc7de22 3011 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
43dd07f7
RM		 3012 u32 frequencyShift;
3013 bool imageToSelect;
3014
2da67501
MCC		 3015 dprintk(1, "\n");
3016
43dd07f7 3017 /*
ebc7de22
OE		 3018 Program frequency shifter
3019 No need to account for mirroring on RF
3020 */
43dd07f7
RM		 3021 if (isDTV) {
3022 if ((state->m_OperationMode == OM_QAM_ITU_A) ||
3023 (state->m_OperationMode == OM_QAM_ITU_C) ||
3024 (state->m_OperationMode == OM_DVBT))
ebc7de22
OE		 3025 selectPosImage = true;
3026 else
3027 selectPosImage = false;
43dd07f7
RM		 3028 }
3029 if (tunerMirror)
3030 /* tuner doesn't mirror */
3031 ifFreqActual = intermediateFreqkHz +
ebc7de22 3032 rfFreqResidual + fmFrequencyShift;
43dd07f7
RM		 3033 else
3034 /* tuner mirrors */
3035 ifFreqActual = intermediateFreqkHz -
ebc7de22 3036 rfFreqResidual - fmFrequencyShift;
43dd07f7
RM		 3037 if (ifFreqActual > samplingFrequency / 2) {
3038 /* adc mirrors */
3039 adcFreq = samplingFrequency - ifFreqActual;
3040 adcFlip = true;
3041 } else {
3042 /* adc doesn't mirror */
3043 adcFreq = ifFreqActual;
3044 adcFlip = false;
3045 }
3046
3047 frequencyShift = adcFreq;
3048 imageToSelect = state->m_rfmirror ^ tunerMirror ^
ebc7de22
OE		 3049 adcFlip ^ selectPosImage;
3050 state->m_IqmFsRateOfs =
3051 Frac28a((frequencyShift), samplingFrequency);
43dd07f7
RM		 3052
3053 if (imageToSelect)
3054 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
3055
3056 /* Program frequency shifter with tuner offset compensation */
3057 /* frequencyShift += tunerFreqOffset; TODO */
5e66b878
MCC		 3058 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3059 state->m_IqmFsRateOfs);
be44eb28
MCC		 3060 if (status < 0)
3061 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3062 return status;
3063}
3064
3065static int InitAGC(struct drxk_state *state, bool isDTV)
3066{
ebc7de22
OE		 3067 u16 ingainTgt = 0;
3068 u16 ingainTgtMin = 0;
3069 u16 ingainTgtMax = 0;
3070 u16 clpCyclen = 0;
3071 u16 clpSumMin = 0;
3072 u16 clpDirTo = 0;
3073 u16 snsSumMin = 0;
3074 u16 snsSumMax = 0;
3075 u16 clpSumMax = 0;
3076 u16 snsDirTo = 0;
3077 u16 kiInnergainMin = 0;
3078 u16 ifIaccuHiTgt = 0;
43dd07f7
RM		 3079 u16 ifIaccuHiTgtMin = 0;
3080 u16 ifIaccuHiTgtMax = 0;
ebc7de22
OE		 3081 u16 data = 0;
3082 u16 fastClpCtrlDelay = 0;
3083 u16 clpCtrlMode = 0;
43dd07f7
RM		 3084 int status = 0;
3085
2da67501
MCC		 3086 dprintk(1, "\n");
3087
be44eb28
MCC		 3088 /* Common settings */
3089 snsSumMax = 1023;
3090 ifIaccuHiTgtMin = 2047;
3091 clpCyclen = 500;
3092 clpSumMax = 1023;
3093
f1b82970
MCC		 3094 /* AGCInit() not available for DVBT; init done in microcode */
3095 if (!IsQAM(state)) {
3096 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode);
3097 return -EINVAL;
be44eb28 3098 }
f1b82970
MCC		 3099
3100 /* FIXME: Analog TV AGC require different settings */
3101
3102 /* Standard specific settings */
3103 clpSumMin = 8;
3104 clpDirTo = (u16) -9;
3105 clpCtrlMode = 0;
3106 snsSumMin = 8;
3107 snsDirTo = (u16) -9;
3108 kiInnergainMin = (u16) -1030;
3109 ifIaccuHiTgtMax = 0x2380;
3110 ifIaccuHiTgt = 0x2380;
3111 ingainTgtMin = 0x0511;
3112 ingainTgt = 0x0511;
3113 ingainTgtMax = 5119;
3114 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay;
3115
be44eb28
MCC		 3116 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3117 if (status < 0)
3118 goto error;
ea90f011 3119
be44eb28
MCC		 3120 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3121 if (status < 0)
3122 goto error;
3123 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3124 if (status < 0)
3125 goto error;
3126 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3127 if (status < 0)
3128 goto error;
3129 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3130 if (status < 0)
3131 goto error;
3132 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3133 if (status < 0)
3134 goto error;
3135 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3136 if (status < 0)
3137 goto error;
3138 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3139 if (status < 0)
3140 goto error;
3141 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3142 if (status < 0)
3143 goto error;
3144 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3145 if (status < 0)
3146 goto error;
3147 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3148 if (status < 0)
3149 goto error;
3150 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3151 if (status < 0)
3152 goto error;
3153 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3154 if (status < 0)
3155 goto error;
ea90f011 3156
be44eb28
MCC		 3157 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3158 if (status < 0)
3159 goto error;
3160 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3161 if (status < 0)
3162 goto error;
3163 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3164 if (status < 0)
3165 goto error;
ea90f011 3166
be44eb28
MCC		 3167 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3168 if (status < 0)
3169 goto error;
3170 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3171 if (status < 0)
3172 goto error;
3173 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3174 if (status < 0)
3175 goto error;
ea90f011 3176
be44eb28
MCC		 3177 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3178 if (status < 0)
3179 goto error;
3180 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3181 if (status < 0)
3182 goto error;
3183 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3184 if (status < 0)
3185 goto error;
3186 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3187 if (status < 0)
3188 goto error;
3189 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3190 if (status < 0)
3191 goto error;
3192 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3193 if (status < 0)
3194 goto error;
3195 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3196 if (status < 0)
3197 goto error;
3198 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3199 if (status < 0)
3200 goto error;
3201 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3202 if (status < 0)
3203 goto error;
3204 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3205 if (status < 0)
3206 goto error;
3207 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3208 if (status < 0)
3209 goto error;
3210 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3211 if (status < 0)
3212 goto error;
3213 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3214 if (status < 0)
3215 goto error;
3216 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3217 if (status < 0)
3218 goto error;
3219 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3220 if (status < 0)
3221 goto error;
3222 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3223 if (status < 0)
3224 goto error;
3225 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3226 if (status < 0)
3227 goto error;
3228 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3229 if (status < 0)
3230 goto error;
3231 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3232 if (status < 0)
3233 goto error;
43dd07f7 3234
be44eb28
MCC		 3235 /* Initialize inner-loop KI gain factors */
3236 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3237 if (status < 0)
3238 goto error;
f1b82970
MCC		 3239
3240 data = 0x0657;
3241 data &= ~SCU_RAM_AGC_KI_RF__M;
3242 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3243 data &= ~SCU_RAM_AGC_KI_IF__M;
3244 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3245
be44eb28
MCC		 3246 status = write16(state, SCU_RAM_AGC_KI__A, data);
3247error:
3248 if (status < 0)
3249 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3250 return status;
3251}
3252
ebc7de22 3253static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
43dd07f7
RM		 3254{
3255 int status;
3256
2da67501 3257 dprintk(1, "\n");
be44eb28
MCC		 3258 if (packetErr == NULL)
3259 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3260 else
3261 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3262 if (status < 0)
3263 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3264 return status;
3265}
3266
3267static int DVBTScCommand(struct drxk_state *state,
3268 u16 cmd, u16 subcmd,
3269 u16 param0, u16 param1, u16 param2,
3270 u16 param3, u16 param4)
3271{
ebc7de22
OE		 3272 u16 curCmd = 0;
3273 u16 errCode = 0;
43dd07f7 3274 u16 retryCnt = 0;
ebc7de22
OE		 3275 u16 scExec = 0;
3276 int status;
43dd07f7 3277
2da67501 3278 dprintk(1, "\n");
5e66b878 3279 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
43dd07f7
RM		 3280 if (scExec != 1) {
3281 /* SC is not running */
be44eb28 3282 status = -EINVAL;
43dd07f7 3283 }
be44eb28
MCC		 3284 if (status < 0)
3285 goto error;
43dd07f7
RM		 3286
3287 /* Wait until sc is ready to receive command */
ebc7de22 3288 retryCnt = 0;
43dd07f7
RM		 3289 do {
3290 msleep(1);
5e66b878 3291 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
43dd07f7
RM		 3292 retryCnt++;
3293 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
be44eb28
MCC		 3294 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3295 goto error;
3296
43dd07f7
RM		 3297 /* Write sub-command */
3298 switch (cmd) {
3299 /* All commands using sub-cmd */
3300 case OFDM_SC_RA_RAM_CMD_PROC_START:
3301 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3302 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
be44eb28
MCC		 3303 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3304 if (status < 0)
3305 goto error;
43dd07f7
RM		 3306 break;
3307 default:
3308 /* Do nothing */
3309 break;
be44eb28 3310 }
43dd07f7
RM		 3311
3312 /* Write needed parameters and the command */
3313 switch (cmd) {
3314 /* All commands using 5 parameters */
3315 /* All commands using 4 parameters */
3316 /* All commands using 3 parameters */
3317 /* All commands using 2 parameters */
3318 case OFDM_SC_RA_RAM_CMD_PROC_START:
3319 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3320 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
be44eb28 3321 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
43dd07f7
RM		 3322 /* All commands using 1 parameters */
3323 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3324 case OFDM_SC_RA_RAM_CMD_USER_IO:
be44eb28 3325 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
43dd07f7
RM		 3326 /* All commands using 0 parameters */
3327 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3328 case OFDM_SC_RA_RAM_CMD_NULL:
3329 /* Write command */
5e66b878 3330 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
43dd07f7
RM		 3331 break;
3332 default:
3333 /* Unknown command */
be44eb28
MCC		 3334 status = -EINVAL;
3335 }
3336 if (status < 0)
3337 goto error;
43dd07f7
RM		 3338
3339 /* Wait until sc is ready processing command */
3340 retryCnt = 0;
ebc7de22 3341 do {
43dd07f7 3342 msleep(1);
5e66b878 3343 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
43dd07f7 3344 retryCnt++;
ebc7de22 3345 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
be44eb28
MCC		 3346 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3347 goto error;
43dd07f7
RM		 3348
3349 /* Check for illegal cmd */
5e66b878 3350 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
ebc7de22 3351 if (errCode == 0xFFFF) {
43dd07f7 3352 /* illegal command */
be44eb28 3353 status = -EINVAL;
43dd07f7 3354 }
be44eb28
MCC		 3355 if (status < 0)
3356 goto error;
43dd07f7
RM		 3357
3358 /* Retreive results parameters from SC */
3359 switch (cmd) {
3360 /* All commands yielding 5 results */
3361 /* All commands yielding 4 results */
3362 /* All commands yielding 3 results */
3363 /* All commands yielding 2 results */
3364 /* All commands yielding 1 result */
3365 case OFDM_SC_RA_RAM_CMD_USER_IO:
3366 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
be44eb28 3367 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
43dd07f7
RM		 3368 /* All commands yielding 0 results */
3369 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3370 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3371 case OFDM_SC_RA_RAM_CMD_PROC_START:
3372 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3373 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3374 case OFDM_SC_RA_RAM_CMD_NULL:
3375 break;
3376 default:
3377 /* Unknown command */
be44eb28 3378 status = -EINVAL;
43dd07f7 3379 break;
ebc7de22 3380 } /* switch (cmd->cmd) */
be44eb28
MCC		 3381error:
3382 if (status < 0)
3383 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3384 return status;
3385}
3386
ebc7de22 3387static int PowerUpDVBT(struct drxk_state *state)
43dd07f7 3388{
ebc7de22 3389 enum DRXPowerMode powerMode = DRX_POWER_UP;
43dd07f7
RM		 3390 int status;
3391
2da67501 3392 dprintk(1, "\n");
be44eb28
MCC		 3393 status = CtrlPowerMode(state, &powerMode);
3394 if (status < 0)
3395 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3396 return status;
3397}
3398
ebc7de22 3399static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
43dd07f7 3400{
ebc7de22
OE		 3401 int status;
3402
2da67501 3403 dprintk(1, "\n");
ebc7de22 3404 if (*enabled == true)
5e66b878 3405 status = write16(state, IQM_CF_BYPASSDET__A, 0);
ebc7de22 3406 else
5e66b878 3407 status = write16(state, IQM_CF_BYPASSDET__A, 1);
be44eb28
MCC		 3408 if (status < 0)
3409 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 3410 return status;
43dd07f7 3411}
ebc7de22
OE		 3412
3413#define DEFAULT_FR_THRES_8K 4000
3414static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
43dd07f7
RM		 3415{
3416
ebc7de22
OE		 3417 int status;
3418
2da67501 3419 dprintk(1, "\n");
ebc7de22
OE		 3420 if (*enabled == true) {
3421 /* write mask to 1 */
5e66b878 3422 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
ebc7de22
OE		 3423 DEFAULT_FR_THRES_8K);
3424 } else {
3425 /* write mask to 0 */
5e66b878 3426 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
ebc7de22 3427 }
be44eb28
MCC		 3428 if (status < 0)
3429 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22
OE		 3430
3431 return status;
43dd07f7
RM		 3432}
3433
ebc7de22
OE		 3434static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3435 struct DRXKCfgDvbtEchoThres_t *echoThres)
43dd07f7 3436{
ebc7de22 3437 u16 data = 0;
43dd07f7 3438 int status;
43dd07f7 3439
2da67501 3440 dprintk(1, "\n");
be44eb28
MCC		 3441 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3442 if (status < 0)
3443 goto error;
3444
3445 switch (echoThres->fftMode) {
3446 case DRX_FFTMODE_2K:
3447 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3448 data |= ((echoThres->threshold <<
3449 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3450 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
320ed23e 3451 break;
be44eb28
MCC		 3452 case DRX_FFTMODE_8K:
3453 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3454 data |= ((echoThres->threshold <<
3455 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3456 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
320ed23e 3457 break;
be44eb28
MCC		 3458 default:
3459 return -EINVAL;
be44eb28 3460 }
ebc7de22 3461
be44eb28
MCC		 3462 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3463error:
3464 if (status < 0)
3465 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 3466 return status;
43dd07f7
RM		 3467}
3468
3469static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
ebc7de22 3470 enum DRXKCfgDvbtSqiSpeed *speed)
43dd07f7 3471{
be44eb28 3472 int status = -EINVAL;
43dd07f7 3473
2da67501
MCC		 3474 dprintk(1, "\n");
3475
43dd07f7
RM		 3476 switch (*speed) {
3477 case DRXK_DVBT_SQI_SPEED_FAST:
3478 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3479 case DRXK_DVBT_SQI_SPEED_SLOW:
3480 break;
3481 default:
be44eb28 3482 goto error;
43dd07f7 3483 }
5e66b878 3484 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
ebc7de22 3485 (u16) *speed);
be44eb28
MCC		 3486error:
3487 if (status < 0)
3488 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3489 return status;
3490}
3491
3492/*============================================================================*/
3493
3494/**
3495* \brief Activate DVBT specific presets
3496* \param demod instance of demodulator.
3497* \return DRXStatus_t.
3498*
3499* Called in DVBTSetStandard
3500*
3501*/
ebc7de22 3502static int DVBTActivatePresets(struct drxk_state *state)
43dd07f7 3503{
ebc7de22 3504 int status;
be44eb28
MCC		 3505 bool setincenable = false;
3506 bool setfrenable = true;
ebc7de22
OE		 3507
3508 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3509 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3510
2da67501 3511 dprintk(1, "\n");
be44eb28
MCC		 3512 status = DVBTCtrlSetIncEnable(state, &setincenable);
3513 if (status < 0)
3514 goto error;
3515 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3516 if (status < 0)
3517 goto error;
3518 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3519 if (status < 0)
3520 goto error;
3521 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3522 if (status < 0)
3523 goto error;
3524 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3525error:
3526 if (status < 0)
3527 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 3528 return status;
43dd07f7 3529}
ebc7de22 3530
43dd07f7
RM		 3531/*============================================================================*/
3532
3533/**
3534* \brief Initialize channelswitch-independent settings for DVBT.
3535* \param demod instance of demodulator.
3536* \return DRXStatus_t.
3537*
3538* For ROM code channel filter taps are loaded from the bootloader. For microcode
3539* the DVB-T taps from the drxk_filters.h are used.
3540*/
ebc7de22
OE		 3541static int SetDVBTStandard(struct drxk_state *state,
3542 enum OperationMode oMode)
43dd07f7 3543{
ebc7de22
OE		 3544 u16 cmdResult = 0;
3545 u16 data = 0;
3546 int status;
43dd07f7 3547
2da67501 3548 dprintk(1, "\n");
43dd07f7 3549
2da67501 3550 PowerUpDVBT(state);
be44eb28
MCC		 3551 /* added antenna switch */
3552 SwitchAntennaToDVBT(state);
3553 /* send OFDM reset command */
3554 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3555 if (status < 0)
3556 goto error;
43dd07f7 3557
be44eb28
MCC		 3558 /* send OFDM setenv command */
3559 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3560 if (status < 0)
3561 goto error;
43dd07f7 3562
be44eb28
MCC		 3563 /* reset datapath for OFDM, processors first */
3564 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3565 if (status < 0)
3566 goto error;
3567 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3568 if (status < 0)
3569 goto error;
3570 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3571 if (status < 0)
3572 goto error;
43dd07f7 3573
be44eb28
MCC		 3574 /* IQM setup */
3575 /* synchronize on ofdstate->m_festart */
3576 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3577 if (status < 0)
3578 goto error;
3579 /* window size for clipping ADC detection */
3580 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3581 if (status < 0)
3582 goto error;
3583 /* window size for for sense pre-SAW detection */
3584 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3585 if (status < 0)
3586 goto error;
3587 /* sense threshold for sense pre-SAW detection */
3588 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3589 if (status < 0)
3590 goto error;
3591 status = SetIqmAf(state, true);
3592 if (status < 0)
3593 goto error;
43dd07f7 3594
be44eb28
MCC		 3595 status = write16(state, IQM_AF_AGC_RF__A, 0);
3596 if (status < 0)
3597 goto error;
43dd07f7 3598
be44eb28
MCC		 3599 /* Impulse noise cruncher setup */
3600 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3601 if (status < 0)
3602 goto error;
3603 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3604 if (status < 0)
3605 goto error;
3606 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3607 if (status < 0)
3608 goto error;
43dd07f7 3609
be44eb28
MCC		 3610 status = write16(state, IQM_RC_STRETCH__A, 16);
3611 if (status < 0)
3612 goto error;
3613 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3614 if (status < 0)
3615 goto error;
3616 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3617 if (status < 0)
3618 goto error;
3619 status = write16(state, IQM_CF_SCALE__A, 1600);
3620 if (status < 0)
3621 goto error;
3622 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3623 if (status < 0)
3624 goto error;
43dd07f7 3625
be44eb28
MCC		 3626 /* virtual clipping threshold for clipping ADC detection */
3627 status = write16(state, IQM_AF_CLP_TH__A, 448);
3628 if (status < 0)
3629 goto error;
3630 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3631 if (status < 0)
3632 goto error;
43dd07f7 3633
be44eb28
MCC		 3634 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3635 if (status < 0)
3636 goto error;
43dd07f7 3637
be44eb28
MCC		 3638 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3639 if (status < 0)
3640 goto error;
3641 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3642 if (status < 0)
3643 goto error;
3644 /* enable power measurement interrupt */
3645 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3646 if (status < 0)
3647 goto error;
3648 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3649 if (status < 0)
3650 goto error;
43dd07f7 3651
be44eb28
MCC		 3652 /* IQM will not be reset from here, sync ADC and update/init AGC */
3653 status = ADCSynchronization(state);
3654 if (status < 0)
3655 goto error;
3656 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3657 if (status < 0)
3658 goto error;
43dd07f7 3659
be44eb28
MCC		 3660 /* Halt SCU to enable safe non-atomic accesses */
3661 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3662 if (status < 0)
3663 goto error;
43dd07f7 3664
be44eb28
MCC		 3665 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3666 if (status < 0)
3667 goto error;
3668 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3669 if (status < 0)
3670 goto error;
43dd07f7 3671
be44eb28
MCC		 3672 /* Set Noise Estimation notch width and enable DC fix */
3673 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3674 if (status < 0)
3675 goto error;
3676 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3677 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3678 if (status < 0)
3679 goto error;
43dd07f7 3680
be44eb28
MCC		 3681 /* Activate SCU to enable SCU commands */
3682 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3683 if (status < 0)
3684 goto error;
43dd07f7 3685
be44eb28
MCC		 3686 if (!state->m_DRXK_A3_ROM_CODE) {
3687 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3688 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3689 if (status < 0)
3690 goto error;
3691 }
43dd07f7 3692
be44eb28 3693 /* OFDM_SC setup */
43dd07f7 3694#ifdef COMPILE_FOR_NONRT
be44eb28
MCC		 3695 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3696 if (status < 0)
3697 goto error;
3698 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3699 if (status < 0)
3700 goto error;
43dd07f7
RM		 3701#endif
3702
be44eb28
MCC		 3703 /* FEC setup */
3704 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3705 if (status < 0)
3706 goto error;
43dd07f7
RM		 3707
3708
3709#ifdef COMPILE_FOR_NONRT
be44eb28
MCC		 3710 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3711 if (status < 0)
3712 goto error;
43dd07f7 3713#else
be44eb28
MCC		 3714 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3715 if (status < 0)
3716 goto error;
43dd07f7 3717#endif
be44eb28
MCC		 3718 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3719 if (status < 0)
3720 goto error;
43dd07f7 3721
be44eb28
MCC		 3722 /* Setup MPEG bus */
3723 status = MPEGTSDtoSetup(state, OM_DVBT);
ebc7de22 3724 if (status < 0)
be44eb28
MCC		 3725 goto error;
3726 /* Set DVBT Presets */
3727 status = DVBTActivatePresets(state);
3728 if (status < 0)
3729 goto error;
43dd07f7 3730
be44eb28
MCC		 3731error:
3732 if (status < 0)
3733 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 3734 return status;
3735}
3736
3737/*============================================================================*/
3738/**
3739* \brief Start dvbt demodulating for channel.
3740* \param demod instance of demodulator.
3741* \return DRXStatus_t.
3742*/
3743static int DVBTStart(struct drxk_state *state)
3744{
ebc7de22
OE		 3745 u16 param1;
3746 int status;
3747 /* DRXKOfdmScCmd_t scCmd; */
3748
2da67501 3749 dprintk(1, "\n");
ebc7de22
OE		 3750 /* Start correct processes to get in lock */
3751 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
be44eb28
MCC		 3752 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3753 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3754 if (status < 0)
3755 goto error;
3756 /* Start FEC OC */
3757 status = MPEGTSStart(state);
3758 if (status < 0)
3759 goto error;
3760 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3761 if (status < 0)
3762 goto error;
3763error:
3764 if (status < 0)
3765 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 3766 return status;
43dd07f7
RM		 3767}
3768
3769
3770/*============================================================================*/
3771
3772/**
3773* \brief Set up dvbt demodulator for channel.
3774* \param demod instance of demodulator.
3775* \return DRXStatus_t.
3776* // original DVBTSetChannel()
3777*/
ebc7de22
OE		 3778static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3779 s32 tunerFreqOffset)
43dd07f7 3780{
ebc7de22
OE		 3781 u16 cmdResult = 0;
3782 u16 transmissionParams = 0;
3783 u16 operationMode = 0;
3784 u32 iqmRcRateOfs = 0;
3785 u32 bandwidth = 0;
3786 u16 param1;
43dd07f7
RM		 3787 int status;
3788
be44eb28 3789 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
43dd07f7 3790
be44eb28
MCC		 3791 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3792 if (status < 0)
3793 goto error;
43dd07f7 3794
be44eb28
MCC		 3795 /* Halt SCU to enable safe non-atomic accesses */
3796 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3797 if (status < 0)
3798 goto error;
43dd07f7 3799
be44eb28
MCC		 3800 /* Stop processors */
3801 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3802 if (status < 0)
3803 goto error;
3804 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3805 if (status < 0)
3806 goto error;
43dd07f7 3807
be44eb28
MCC		 3808 /* Mandatory fix, always stop CP, required to set spl offset back to
3809 hardware default (is set to 0 by ucode during pilot detection */
3810 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3811 if (status < 0)
3812 goto error;
43dd07f7 3813
be44eb28 3814 /*== Write channel settings to device =====================================*/
43dd07f7 3815
be44eb28
MCC		 3816 /* mode */
3817 switch (state->param.u.ofdm.transmission_mode) {
3818 case TRANSMISSION_MODE_AUTO:
3819 default:
3820 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3821 /* fall through , try first guess DRX_FFTMODE_8K */
3822 case TRANSMISSION_MODE_8K:
3823 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
320ed23e 3824 break;
be44eb28
MCC		 3825 case TRANSMISSION_MODE_2K:
3826 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
320ed23e 3827 break;
be44eb28 3828 }
43dd07f7 3829
be44eb28
MCC		 3830 /* guard */
3831 switch (state->param.u.ofdm.guard_interval) {
3832 default:
3833 case GUARD_INTERVAL_AUTO:
3834 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3835 /* fall through , try first guess DRX_GUARD_1DIV4 */
3836 case GUARD_INTERVAL_1_4:
3837 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
320ed23e 3838 break;
be44eb28
MCC		 3839 case GUARD_INTERVAL_1_32:
3840 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
320ed23e 3841 break;
be44eb28
MCC		 3842 case GUARD_INTERVAL_1_16:
3843 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
320ed23e 3844 break;
be44eb28
MCC		 3845 case GUARD_INTERVAL_1_8:
3846 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
320ed23e 3847 break;
be44eb28 3848 }
43dd07f7 3849
be44eb28
MCC		 3850 /* hierarchy */
3851 switch (state->param.u.ofdm.hierarchy_information) {
3852 case HIERARCHY_AUTO:
3853 case HIERARCHY_NONE:
3854 default:
3855 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3856 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3857 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3858 /* break; */
3859 case HIERARCHY_1:
3860 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3861 break;
3862 case HIERARCHY_2:
3863 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3864 break;
3865 case HIERARCHY_4:
3866 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3867 break;
3868 }
3869
3870
3871 /* constellation */
3872 switch (state->param.u.ofdm.constellation) {
3873 case QAM_AUTO:
3874 default:
3875 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3876 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3877 case QAM_64:
3878 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3879 break;
3880 case QPSK:
3881 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3882 break;
3883 case QAM_16:
3884 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3885 break;
3886 }
43dd07f7 3887#if 0
be44eb28
MCC		 3888 /* No hierachical channels support in BDA */
3889 /* Priority (only for hierarchical channels) */
3890 switch (channel->priority) {
3891 case DRX_PRIORITY_LOW:
3892 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3893 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3894 OFDM_EC_SB_PRIOR_LO);
3895 break;
3896 case DRX_PRIORITY_HIGH:
43dd07f7 3897 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
be44eb28
MCC		 3898 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3899 OFDM_EC_SB_PRIOR_HI));
3900 break;
3901 case DRX_PRIORITY_UNKNOWN: /* fall through */
3902 default:
3903 status = -EINVAL;
3904 goto error;
3905 }
3906#else
3907 /* Set Priorty high */
3908 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3909 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3910 if (status < 0)
3911 goto error;
43dd07f7
RM		 3912#endif
3913
be44eb28
MCC		 3914 /* coderate */
3915 switch (state->param.u.ofdm.code_rate_HP) {
3916 case FEC_AUTO:
3917 default:
3918 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3919 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3920 case FEC_2_3:
3921 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3922 break;
3923 case FEC_1_2:
3924 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3925 break;
3926 case FEC_3_4:
3927 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3928 break;
3929 case FEC_5_6:
3930 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3931 break;
3932 case FEC_7_8:
3933 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3934 break;
3935 }
43dd07f7 3936
be44eb28
MCC		 3937 /* SAW filter selection: normaly not necesarry, but if wanted
3938 the application can select a SAW filter via the driver by using UIOs */
3939 /* First determine real bandwidth (Hz) */
3940 /* Also set delay for impulse noise cruncher */
3941 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3942 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3943 functions */
3944 switch (state->param.u.ofdm.bandwidth) {
3945 case BANDWIDTH_AUTO:
3946 case BANDWIDTH_8_MHZ:
3947 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3948 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3949 if (status < 0)
3950 goto error;
3951 /* cochannel protection for PAL 8 MHz */
3952 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3953 if (status < 0)
3954 goto error;
3955 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3956 if (status < 0)
3957 goto error;
3958 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3959 if (status < 0)
3960 goto error;
3961 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3962 if (status < 0)
3963 goto error;
3964 break;
3965 case BANDWIDTH_7_MHZ:
3966 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3967 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3968 if (status < 0)
3969 goto error;
3970 /* cochannel protection for PAL 7 MHz */
3971 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3972 if (status < 0)
3973 goto error;
3974 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3975 if (status < 0)
3976 goto error;
3977 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3978 if (status < 0)
3979 goto error;
3980 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3981 if (status < 0)
3982 goto error;
3983 break;
3984 case BANDWIDTH_6_MHZ:
3985 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3986 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3987 if (status < 0)
3988 goto error;
3989 /* cochannel protection for NTSC 6 MHz */
3990 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3991 if (status < 0)
3992 goto error;
3993 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
3994 if (status < 0)
3995 goto error;
3996 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
3997 if (status < 0)
3998 goto error;
3999 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
4000 if (status < 0)
4001 goto error;
4002 break;
4003 default:
4004 status = -EINVAL;
4005 goto error;
4006 }
43dd07f7 4007
be44eb28
MCC		 4008 if (iqmRcRateOfs == 0) {
4009 /* Now compute IQM_RC_RATE_OFS
4010 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4011 =>
4012 ((SysFreq / BandWidth) * (2^21)) - (2^23)
4013 */
4014 /* (SysFreq / BandWidth) * (2^28) */
4015 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
4016 => assert(MAX(sysClk) < 16*MIN(bandwidth))
4017 => assert(109714272 > 48000000) = true so Frac 28 can be used */
4018 iqmRcRateOfs = Frac28a((u32)
4019 ((state->m_sysClockFreq *
4020 1000) / 3), bandwidth);
4021 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4022 if ((iqmRcRateOfs & 0x7fL) >= 0x40)
4023 iqmRcRateOfs += 0x80L;
4024 iqmRcRateOfs = iqmRcRateOfs >> 7;
4025 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
4026 iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
4027 }
43dd07f7 4028
be44eb28
MCC		 4029 iqmRcRateOfs &=
4030 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4031 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4032 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4033 if (status < 0)
4034 goto error;
43dd07f7 4035
be44eb28 4036 /* Bandwidth setting done */
43dd07f7 4037
ea90f011 4038#if 0
be44eb28
MCC		 4039 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4040 if (status < 0)
4041 goto error;
ea90f011 4042#endif
be44eb28
MCC		 4043 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4044 if (status < 0)
4045 goto error;
43dd07f7 4046
be44eb28 4047 /*== Start SC, write channel settings to SC ===============================*/
43dd07f7 4048
be44eb28
MCC		 4049 /* Activate SCU to enable SCU commands */
4050 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4051 if (status < 0)
4052 goto error;
43dd07f7 4053
be44eb28
MCC		 4054 /* Enable SC after setting all other parameters */
4055 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4056 if (status < 0)
4057 goto error;
4058 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4059 if (status < 0)
4060 goto error;
43dd07f7 4061
43dd07f7 4062
be44eb28
MCC		 4063 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4064 if (status < 0)
4065 goto error;
4066
4067 /* Write SC parameter registers, set all AUTO flags in operation mode */
4068 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4069 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4070 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4071 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4072 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4073 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4074 0, transmissionParams, param1, 0, 0, 0);
4075 if (status < 0)
4076 goto error;
43dd07f7 4077
be44eb28
MCC		 4078 if (!state->m_DRXK_A3_ROM_CODE)
4079 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4080error:
4081 if (status < 0)
4082 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 4083
4084 return status;
4085}
4086
4087
4088/*============================================================================*/
4089
4090/**
4091* \brief Retreive lock status .
4092* \param demod Pointer to demodulator instance.
4093* \param lockStat Pointer to lock status structure.
4094* \return DRXStatus_t.
4095*
4096*/
4097static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4098{
ebc7de22
OE		 4099 int status;
4100 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4101 OFDM_SC_RA_RAM_LOCK_FEC__M);
4102 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4103 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4104
4105 u16 ScRaRamLock = 0;
4106 u16 ScCommExec = 0;
4107
2da67501
MCC		 4108 dprintk(1, "\n");
4109
be44eb28 4110 *pLockStatus = NOT_LOCKED;
ebc7de22
OE		 4111 /* driver 0.9.0 */
4112 /* Check if SC is running */
5e66b878 4113 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
be44eb28
MCC		 4114 if (status < 0)
4115 goto end;
4116 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
4117 goto end;
ebc7de22 4118
5e66b878 4119 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
be44eb28
MCC		 4120 if (status < 0)
4121 goto end;
ebc7de22
OE		 4122
4123 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4124 *pLockStatus = MPEG_LOCK;
4125 else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4126 *pLockStatus = FEC_LOCK;
4127 else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4128 *pLockStatus = DEMOD_LOCK;
4129 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4130 *pLockStatus = NEVER_LOCK;
be44eb28
MCC		 4131end:
4132 if (status < 0)
4133 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22
OE		 4134
4135 return status;
43dd07f7
RM		 4136}
4137
ebc7de22 4138static int PowerUpQAM(struct drxk_state *state)
43dd07f7 4139{
ebc7de22 4140 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
be44eb28 4141 int status;
43dd07f7 4142
2da67501 4143 dprintk(1, "\n");
be44eb28
MCC		 4144 status = CtrlPowerMode(state, &powerMode);
4145 if (status < 0)
4146 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7 4147
ebc7de22 4148 return status;
43dd07f7
RM		 4149}
4150
4151
ebc7de22 4152/** Power Down QAM */
43dd07f7
RM		 4153static int PowerDownQAM(struct drxk_state *state)
4154{
ebc7de22
OE		 4155 u16 data = 0;
4156 u16 cmdResult;
4157 int status = 0;
4158
2da67501 4159 dprintk(1, "\n");
be44eb28
MCC		 4160 status = read16(state, SCU_COMM_EXEC__A, &data);
4161 if (status < 0)
4162 goto error;
4163 if (data == SCU_COMM_EXEC_ACTIVE) {
4164 /*
4165 STOP demodulator
4166 QAM and HW blocks
4167 */
4168 /* stop all comstate->m_exec */
4169 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
ea90f011 4170 if (status < 0)
be44eb28
MCC		 4171 goto error;
4172 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
ea90f011 4173 if (status < 0)
be44eb28
MCC		 4174 goto error;
4175 }
4176 /* powerdown AFE */
4177 status = SetIqmAf(state, false);
4178
4179error:
4180 if (status < 0)
4181 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22
OE		 4182
4183 return status;
43dd07f7 4184}
ebc7de22 4185
43dd07f7
RM		 4186/*============================================================================*/
4187
4188/**
4189* \brief Setup of the QAM Measurement intervals for signal quality
4190* \param demod instance of demod.
4191* \param constellation current constellation.
4192* \return DRXStatus_t.
4193*
4194* NOTE:
4195* Take into account that for certain settings the errorcounters can overflow.
4196* The implementation does not check this.
4197*
4198*/
4199static int SetQAMMeasurement(struct drxk_state *state,
4200 enum EDrxkConstellation constellation,
4201 u32 symbolRate)
4202{
ebc7de22
OE		 4203 u32 fecBitsDesired = 0; /* BER accounting period */
4204 u32 fecRsPeriodTotal = 0; /* Total period */
4205 u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
4206 u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
43dd07f7
RM		 4207 int status = 0;
4208
2da67501 4209 dprintk(1, "\n");
43dd07f7 4210
2da67501 4211 fecRsPrescale = 1;
be44eb28
MCC		 4212 /* fecBitsDesired = symbolRate [kHz] *
4213 FrameLenght [ms] *
4214 (constellation + 1) *
4215 SyncLoss (== 1) *
4216 ViterbiLoss (==1)
4217 */
4218 switch (constellation) {
4219 case DRX_CONSTELLATION_QAM16:
4220 fecBitsDesired = 4 * symbolRate;
4221 break;
4222 case DRX_CONSTELLATION_QAM32:
4223 fecBitsDesired = 5 * symbolRate;
4224 break;
4225 case DRX_CONSTELLATION_QAM64:
4226 fecBitsDesired = 6 * symbolRate;
4227 break;
4228 case DRX_CONSTELLATION_QAM128:
4229 fecBitsDesired = 7 * symbolRate;
4230 break;
4231 case DRX_CONSTELLATION_QAM256:
4232 fecBitsDesired = 8 * symbolRate;
4233 break;
4234 default:
4235 status = -EINVAL;
4236 }
4237 if (status < 0)
4238 goto error;
43dd07f7 4239
be44eb28
MCC		 4240 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4241 fecBitsDesired *= 500; /* meas. period [ms] */
43dd07f7 4242
be44eb28
MCC		 4243 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4244 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4245 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
43dd07f7 4246
be44eb28
MCC		 4247 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4248 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4249 if (fecRsPrescale == 0) {
4250 /* Divide by zero (though impossible) */
4251 status = -EINVAL;
ea90f011 4252 if (status < 0)
be44eb28
MCC		 4253 goto error;
4254 }
4255 fecRsPeriod =
4256 ((u16) fecRsPeriodTotal +
4257 (fecRsPrescale >> 1)) / fecRsPrescale;
43dd07f7 4258
be44eb28
MCC		 4259 /* write corresponding registers */
4260 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
ebc7de22 4261 if (status < 0)
be44eb28
MCC		 4262 goto error;
4263 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4264 if (status < 0)
4265 goto error;
4266 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4267error:
4268 if (status < 0)
4269 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 4270 return status;
4271}
4272
ebc7de22 4273static int SetQAM16(struct drxk_state *state)
43dd07f7 4274{
ebc7de22
OE		 4275 int status = 0;
4276
2da67501 4277 dprintk(1, "\n");
be44eb28
MCC		 4278 /* QAM Equalizer Setup */
4279 /* Equalizer */
4280 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4281 if (status < 0)
4282 goto error;
4283 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4284 if (status < 0)
4285 goto error;
4286 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4287 if (status < 0)
4288 goto error;
4289 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4290 if (status < 0)
4291 goto error;
4292 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4293 if (status < 0)
4294 goto error;
4295 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4296 if (status < 0)
4297 goto error;
4298 /* Decision Feedback Equalizer */
4299 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4300 if (status < 0)
4301 goto error;
4302 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4303 if (status < 0)
4304 goto error;
4305 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4306 if (status < 0)
4307 goto error;
4308 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4309 if (status < 0)
4310 goto error;
4311 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4312 if (status < 0)
4313 goto error;
4314 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4315 if (status < 0)
4316 goto error;
ebc7de22 4317
be44eb28
MCC		 4318 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4319 if (status < 0)
4320 goto error;
4321 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4322 if (status < 0)
4323 goto error;
4324 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4325 if (status < 0)
4326 goto error;
ebc7de22 4327
be44eb28
MCC		 4328 /* QAM Slicer Settings */
4329 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4330 if (status < 0)
4331 goto error;
ebc7de22 4332
be44eb28
MCC		 4333 /* QAM Loop Controller Coeficients */
4334 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4335 if (status < 0)
4336 goto error;
4337 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4338 if (status < 0)
4339 goto error;
4340 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4341 if (status < 0)
4342 goto error;
4343 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4344 if (status < 0)
4345 goto error;
4346 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4347 if (status < 0)
4348 goto error;
4349 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4350 if (status < 0)
4351 goto error;
4352 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4353 if (status < 0)
4354 goto error;
4355 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4356 if (status < 0)
4357 goto error;
ea90f011 4358
be44eb28
MCC		 4359 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4360 if (status < 0)
4361 goto error;
4362 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4363 if (status < 0)
4364 goto error;
4365 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4366 if (status < 0)
4367 goto error;
4368 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4369 if (status < 0)
4370 goto error;
4371 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4372 if (status < 0)
4373 goto error;
4374 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4375 if (status < 0)
4376 goto error;
4377 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4378 if (status < 0)
4379 goto error;
4380 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4381 if (status < 0)
4382 goto error;
4383 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4384 if (status < 0)
4385 goto error;
4386 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4387 if (status < 0)
4388 goto error;
4389 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4390 if (status < 0)
4391 goto error;
4392 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4393 if (status < 0)
4394 goto error;
ebc7de22
OE		 4395
4396
be44eb28 4397 /* QAM State Machine (FSM) Thresholds */
ebc7de22 4398
be44eb28
MCC		 4399 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4400 if (status < 0)
4401 goto error;
4402 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4403 if (status < 0)
4404 goto error;
4405 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4406 if (status < 0)
4407 goto error;
4408 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4409 if (status < 0)
4410 goto error;
4411 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4412 if (status < 0)
4413 goto error;
4414 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4415 if (status < 0)
4416 goto error;
ebc7de22 4417
be44eb28
MCC		 4418 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4419 if (status < 0)
4420 goto error;
4421 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4422 if (status < 0)
4423 goto error;
4424 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4425 if (status < 0)
4426 goto error;
ebc7de22
OE		 4427
4428
be44eb28 4429 /* QAM FSM Tracking Parameters */
ebc7de22 4430
be44eb28
MCC		 4431 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4432 if (status < 0)
4433 goto error;
4434 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4435 if (status < 0)
4436 goto error;
4437 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4438 if (status < 0)
4439 goto error;
4440 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4441 if (status < 0)
4442 goto error;
4443 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4444 if (status < 0)
4445 goto error;
4446 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4447 if (status < 0)
4448 goto error;
4449 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4450 if (status < 0)
4451 goto error;
ebc7de22 4452
be44eb28
MCC		 4453error:
4454 if (status < 0)
4455 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 4456 return status;
43dd07f7
RM		 4457}
4458
4459/*============================================================================*/
4460
4461/**
4462* \brief QAM32 specific setup
4463* \param demod instance of demod.
4464* \return DRXStatus_t.
4465*/
ebc7de22 4466static int SetQAM32(struct drxk_state *state)
43dd07f7 4467{
ebc7de22
OE		 4468 int status = 0;
4469
2da67501 4470 dprintk(1, "\n");
ebc7de22 4471
be44eb28
MCC		 4472 /* QAM Equalizer Setup */
4473 /* Equalizer */
4474 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4475 if (status < 0)
4476 goto error;
4477 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4478 if (status < 0)
4479 goto error;
4480 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4481 if (status < 0)
4482 goto error;
4483 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4484 if (status < 0)
4485 goto error;
4486 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4487 if (status < 0)
4488 goto error;
4489 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4490 if (status < 0)
4491 goto error;
ebc7de22 4492
be44eb28
MCC		 4493 /* Decision Feedback Equalizer */
4494 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4495 if (status < 0)
4496 goto error;
4497 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4498 if (status < 0)
4499 goto error;
4500 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4501 if (status < 0)
4502 goto error;
4503 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4504 if (status < 0)
4505 goto error;
4506 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4507 if (status < 0)
4508 goto error;
4509 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4510 if (status < 0)
4511 goto error;
ebc7de22 4512
be44eb28
MCC		 4513 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4514 if (status < 0)
4515 goto error;
4516 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4517 if (status < 0)
4518 goto error;
4519 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4520 if (status < 0)
4521 goto error;
ebc7de22 4522
be44eb28 4523 /* QAM Slicer Settings */
ebc7de22 4524
be44eb28
MCC		 4525 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4526 if (status < 0)
4527 goto error;
ebc7de22 4528
ebc7de22 4529
be44eb28 4530 /* QAM Loop Controller Coeficients */
ea90f011 4531
be44eb28
MCC		 4532 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4533 if (status < 0)
4534 goto error;
4535 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4536 if (status < 0)
4537 goto error;
4538 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4539 if (status < 0)
4540 goto error;
4541 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4542 if (status < 0)
4543 goto error;
4544 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4545 if (status < 0)
4546 goto error;
4547 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4548 if (status < 0)
4549 goto error;
4550 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4551 if (status < 0)
4552 goto error;
4553 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4554 if (status < 0)
4555 goto error;
ebc7de22 4556
be44eb28
MCC		 4557 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4558 if (status < 0)
4559 goto error;
4560 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4561 if (status < 0)
4562 goto error;
4563 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4564 if (status < 0)
4565 goto error;
4566 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4567 if (status < 0)
4568 goto error;
4569 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4570 if (status < 0)
4571 goto error;
4572 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4573 if (status < 0)
4574 goto error;
4575 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4576 if (status < 0)
4577 goto error;
4578 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4579 if (status < 0)
4580 goto error;
4581 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4582 if (status < 0)
4583 goto error;
4584 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4585 if (status < 0)
4586 goto error;
4587 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4588 if (status < 0)
4589 goto error;
4590 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4591 if (status < 0)
4592 goto error;
ebc7de22 4593
ebc7de22 4594
be44eb28 4595 /* QAM State Machine (FSM) Thresholds */
ebc7de22 4596
be44eb28
MCC		 4597 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4598 if (status < 0)
4599 goto error;
4600 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4601 if (status < 0)
4602 goto error;
4603 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4604 if (status < 0)
4605 goto error;
4606 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4607 if (status < 0)
4608 goto error;
4609 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4610 if (status < 0)
4611 goto error;
4612 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4613 if (status < 0)
4614 goto error;
ebc7de22 4615
be44eb28
MCC		 4616 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4617 if (status < 0)
4618 goto error;
4619 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4620 if (status < 0)
4621 goto error;
4622 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4623 if (status < 0)
4624 goto error;
ebc7de22 4625
ebc7de22 4626
be44eb28 4627 /* QAM FSM Tracking Parameters */
ebc7de22 4628
be44eb28
MCC		 4629 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4630 if (status < 0)
4631 goto error;
4632 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4633 if (status < 0)
4634 goto error;
4635 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4636 if (status < 0)
4637 goto error;
4638 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4639 if (status < 0)
4640 goto error;
4641 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4642 if (status < 0)
4643 goto error;
4644 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4645 if (status < 0)
4646 goto error;
4647 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4648error:
4649 if (status < 0)
4650 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 4651 return status;
43dd07f7
RM		 4652}
4653
4654/*============================================================================*/
4655
4656/**
4657* \brief QAM64 specific setup
4658* \param demod instance of demod.
4659* \return DRXStatus_t.
4660*/
ebc7de22 4661static int SetQAM64(struct drxk_state *state)
43dd07f7 4662{
ebc7de22
OE		 4663 int status = 0;
4664
2da67501 4665 dprintk(1, "\n");
be44eb28
MCC		 4666 /* QAM Equalizer Setup */
4667 /* Equalizer */
4668 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4669 if (status < 0)
4670 goto error;
4671 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4672 if (status < 0)
4673 goto error;
4674 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4675 if (status < 0)
4676 goto error;
4677 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4678 if (status < 0)
4679 goto error;
4680 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4681 if (status < 0)
4682 goto error;
4683 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4684 if (status < 0)
4685 goto error;
ebc7de22 4686
be44eb28
MCC		 4687 /* Decision Feedback Equalizer */
4688 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4689 if (status < 0)
4690 goto error;
4691 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4692 if (status < 0)
4693 goto error;
4694 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4695 if (status < 0)
4696 goto error;
4697 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4698 if (status < 0)
4699 goto error;
4700 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4701 if (status < 0)
4702 goto error;
4703 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4704 if (status < 0)
4705 goto error;
ebc7de22 4706
be44eb28
MCC		 4707 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4708 if (status < 0)
4709 goto error;
4710 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4711 if (status < 0)
4712 goto error;
4713 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4714 if (status < 0)
4715 goto error;
ebc7de22 4716
be44eb28
MCC		 4717 /* QAM Slicer Settings */
4718 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4719 if (status < 0)
4720 goto error;
ebc7de22
OE		 4721
4722
be44eb28 4723 /* QAM Loop Controller Coeficients */
ebc7de22 4724
be44eb28
MCC		 4725 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4726 if (status < 0)
4727 goto error;
4728 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4729 if (status < 0)
4730 goto error;
4731 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4732 if (status < 0)
4733 goto error;
4734 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4735 if (status < 0)
4736 goto error;
4737 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4738 if (status < 0)
4739 goto error;
4740 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4741 if (status < 0)
4742 goto error;
4743 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4744 if (status < 0)
4745 goto error;
4746 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4747 if (status < 0)
4748 goto error;
ea90f011 4749
be44eb28
MCC		 4750 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4751 if (status < 0)
4752 goto error;
4753 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4754 if (status < 0)
4755 goto error;
4756 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4757 if (status < 0)
4758 goto error;
4759 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4760 if (status < 0)
4761 goto error;
4762 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4763 if (status < 0)
4764 goto error;
4765 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4766 if (status < 0)
4767 goto error;
4768 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4769 if (status < 0)
4770 goto error;
4771 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4772 if (status < 0)
4773 goto error;
4774 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4775 if (status < 0)
4776 goto error;
4777 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4778 if (status < 0)
4779 goto error;
4780 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4781 if (status < 0)
4782 goto error;
4783 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4784 if (status < 0)
4785 goto error;
ebc7de22
OE		 4786
4787
be44eb28 4788 /* QAM State Machine (FSM) Thresholds */
ebc7de22 4789
be44eb28
MCC		 4790 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4791 if (status < 0)
4792 goto error;
4793 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4794 if (status < 0)
4795 goto error;
4796 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4797 if (status < 0)
4798 goto error;
4799 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4800 if (status < 0)
4801 goto error;
4802 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4803 if (status < 0)
4804 goto error;
4805 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4806 if (status < 0)
4807 goto error;
ebc7de22 4808
be44eb28
MCC		 4809 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4810 if (status < 0)
4811 goto error;
4812 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4813 if (status < 0)
4814 goto error;
4815 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4816 if (status < 0)
4817 goto error;
ebc7de22
OE		 4818
4819
be44eb28 4820 /* QAM FSM Tracking Parameters */
ebc7de22 4821
be44eb28
MCC		 4822 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4823 if (status < 0)
4824 goto error;
4825 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4826 if (status < 0)
4827 goto error;
4828 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4829 if (status < 0)
4830 goto error;
4831 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4832 if (status < 0)
4833 goto error;
4834 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4835 if (status < 0)
4836 goto error;
4837 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4838 if (status < 0)
4839 goto error;
4840 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4841error:
4842 if (status < 0)
4843 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22
OE		 4844
4845 return status;
43dd07f7
RM		 4846}
4847
4848/*============================================================================*/
4849
4850/**
4851* \brief QAM128 specific setup
4852* \param demod: instance of demod.
4853* \return DRXStatus_t.
4854*/
4855static int SetQAM128(struct drxk_state *state)
4856{
ebc7de22
OE		 4857 int status = 0;
4858
2da67501 4859 dprintk(1, "\n");
be44eb28
MCC		 4860 /* QAM Equalizer Setup */
4861 /* Equalizer */
4862 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4863 if (status < 0)
4864 goto error;
4865 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4866 if (status < 0)
4867 goto error;
4868 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4869 if (status < 0)
4870 goto error;
4871 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4872 if (status < 0)
4873 goto error;
4874 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4875 if (status < 0)
4876 goto error;
4877 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4878 if (status < 0)
4879 goto error;
ebc7de22 4880
be44eb28
MCC		 4881 /* Decision Feedback Equalizer */
4882 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4883 if (status < 0)
4884 goto error;
4885 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4886 if (status < 0)
4887 goto error;
4888 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4889 if (status < 0)
4890 goto error;
4891 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4892 if (status < 0)
4893 goto error;
4894 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4895 if (status < 0)
4896 goto error;
4897 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4898 if (status < 0)
4899 goto error;
ebc7de22 4900
be44eb28
MCC		 4901 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4902 if (status < 0)
4903 goto error;
4904 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4905 if (status < 0)
4906 goto error;
4907 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4908 if (status < 0)
4909 goto error;
ebc7de22 4910
ebc7de22 4911
be44eb28 4912 /* QAM Slicer Settings */
ebc7de22 4913
be44eb28
MCC		 4914 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4915 if (status < 0)
4916 goto error;
ebc7de22 4917
ebc7de22 4918
be44eb28 4919 /* QAM Loop Controller Coeficients */
ea90f011 4920
be44eb28
MCC		 4921 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4922 if (status < 0)
4923 goto error;
4924 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4925 if (status < 0)
4926 goto error;
4927 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4928 if (status < 0)
4929 goto error;
4930 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4931 if (status < 0)
4932 goto error;
4933 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4934 if (status < 0)
4935 goto error;
4936 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4937 if (status < 0)
4938 goto error;
4939 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4940 if (status < 0)
4941 goto error;
4942 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4943 if (status < 0)
4944 goto error;
4945
4946 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4947 if (status < 0)
4948 goto error;
4949 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4950 if (status < 0)
4951 goto error;
4952 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4953 if (status < 0)
4954 goto error;
4955 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4956 if (status < 0)
4957 goto error;
4958 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4959 if (status < 0)
4960 goto error;
4961 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4962 if (status < 0)
4963 goto error;
4964 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4965 if (status < 0)
4966 goto error;
4967 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4968 if (status < 0)
4969 goto error;
4970 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4971 if (status < 0)
4972 goto error;
4973 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4974 if (status < 0)
4975 goto error;
4976 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4977 if (status < 0)
4978 goto error;
4979 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4980 if (status < 0)
4981 goto error;
ebc7de22
OE		 4982
4983
be44eb28 4984 /* QAM State Machine (FSM) Thresholds */
ebc7de22 4985
be44eb28
MCC		 4986 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4987 if (status < 0)
4988 goto error;
4989 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4990 if (status < 0)
4991 goto error;
4992 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4993 if (status < 0)
4994 goto error;
4995 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4996 if (status < 0)
4997 goto error;
4998 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4999 if (status < 0)
5000 goto error;
5001 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5002 if (status < 0)
5003 goto error;
ebc7de22 5004
be44eb28
MCC		 5005 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5006 if (status < 0)
5007 goto error;
5008 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5009 if (status < 0)
5010 goto error;
ebc7de22 5011
be44eb28
MCC		 5012 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5013 if (status < 0)
5014 goto error;
ebc7de22 5015
be44eb28 5016 /* QAM FSM Tracking Parameters */
ebc7de22 5017
be44eb28
MCC		 5018 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5019 if (status < 0)
5020 goto error;
5021 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5022 if (status < 0)
5023 goto error;
5024 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5025 if (status < 0)
5026 goto error;
5027 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5028 if (status < 0)
5029 goto error;
5030 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5031 if (status < 0)
5032 goto error;
5033 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5034 if (status < 0)
5035 goto error;
5036 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5037error:
5038 if (status < 0)
5039 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22
OE		 5040
5041 return status;
43dd07f7
RM		 5042}
5043
5044/*============================================================================*/
5045
5046/**
5047* \brief QAM256 specific setup
5048* \param demod: instance of demod.
5049* \return DRXStatus_t.
5050*/
5051static int SetQAM256(struct drxk_state *state)
5052{
ebc7de22
OE		 5053 int status = 0;
5054
2da67501 5055 dprintk(1, "\n");
be44eb28
MCC		 5056 /* QAM Equalizer Setup */
5057 /* Equalizer */
5058 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5059 if (status < 0)
5060 goto error;
5061 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5062 if (status < 0)
5063 goto error;
5064 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5065 if (status < 0)
5066 goto error;
5067 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5068 if (status < 0)
5069 goto error;
5070 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5071 if (status < 0)
5072 goto error;
5073 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5074 if (status < 0)
5075 goto error;
ebc7de22 5076
be44eb28
MCC		 5077 /* Decision Feedback Equalizer */
5078 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5079 if (status < 0)
5080 goto error;
5081 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5082 if (status < 0)
5083 goto error;
5084 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5085 if (status < 0)
5086 goto error;
5087 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5088 if (status < 0)
5089 goto error;
5090 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5091 if (status < 0)
5092 goto error;
5093 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5094 if (status < 0)
5095 goto error;
ebc7de22 5096
be44eb28
MCC		 5097 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5098 if (status < 0)
5099 goto error;
5100 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5101 if (status < 0)
5102 goto error;
5103 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5104 if (status < 0)
5105 goto error;
ebc7de22 5106
be44eb28 5107 /* QAM Slicer Settings */
ebc7de22 5108
be44eb28
MCC		 5109 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5110 if (status < 0)
5111 goto error;
ebc7de22 5112
ebc7de22 5113
be44eb28 5114 /* QAM Loop Controller Coeficients */
ea90f011 5115
be44eb28
MCC		 5116 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5117 if (status < 0)
5118 goto error;
5119 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5120 if (status < 0)
5121 goto error;
5122 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5123 if (status < 0)
5124 goto error;
5125 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5126 if (status < 0)
5127 goto error;
5128 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5129 if (status < 0)
5130 goto error;
5131 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5132 if (status < 0)
5133 goto error;
5134 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5135 if (status < 0)
5136 goto error;
5137 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5138 if (status < 0)
5139 goto error;
ebc7de22 5140
be44eb28
MCC		 5141 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5142 if (status < 0)
5143 goto error;
5144 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5145 if (status < 0)
5146 goto error;
5147 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5148 if (status < 0)
5149 goto error;
5150 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5151 if (status < 0)
5152 goto error;
5153 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5154 if (status < 0)
5155 goto error;
5156 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5157 if (status < 0)
5158 goto error;
5159 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5160 if (status < 0)
5161 goto error;
5162 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5163 if (status < 0)
5164 goto error;
5165 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5166 if (status < 0)
5167 goto error;
5168 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5169 if (status < 0)
5170 goto error;
5171 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5172 if (status < 0)
5173 goto error;
5174 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5175 if (status < 0)
5176 goto error;
ebc7de22 5177
ebc7de22 5178
be44eb28 5179 /* QAM State Machine (FSM) Thresholds */
ebc7de22 5180
be44eb28
MCC		 5181 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5182 if (status < 0)
5183 goto error;
5184 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5185 if (status < 0)
5186 goto error;
5187 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5188 if (status < 0)
5189 goto error;
5190 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5191 if (status < 0)
5192 goto error;
5193 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5194 if (status < 0)
5195 goto error;
5196 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5197 if (status < 0)
5198 goto error;
ebc7de22 5199
be44eb28
MCC		 5200 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5201 if (status < 0)
5202 goto error;
5203 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5204 if (status < 0)
5205 goto error;
5206 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5207 if (status < 0)
5208 goto error;
ebc7de22 5209
ebc7de22 5210
be44eb28 5211 /* QAM FSM Tracking Parameters */
ebc7de22 5212
be44eb28
MCC		 5213 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5214 if (status < 0)
5215 goto error;
5216 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5217 if (status < 0)
5218 goto error;
5219 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5220 if (status < 0)
5221 goto error;
5222 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5223 if (status < 0)
5224 goto error;
5225 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5226 if (status < 0)
5227 goto error;
5228 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5229 if (status < 0)
5230 goto error;
5231 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5232error:
5233 if (status < 0)
5234 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5235 return status;
43dd07f7
RM		 5236}
5237
5238
5239/*============================================================================*/
5240/**
5241* \brief Reset QAM block.
5242* \param demod: instance of demod.
5243* \param channel: pointer to channel data.
5244* \return DRXStatus_t.
5245*/
5246static int QAMResetQAM(struct drxk_state *state)
5247{
ebc7de22
OE		 5248 int status;
5249 u16 cmdResult;
43dd07f7 5250
2da67501 5251 dprintk(1, "\n");
be44eb28
MCC		 5252 /* Stop QAM comstate->m_exec */
5253 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5254 if (status < 0)
5255 goto error;
43dd07f7 5256
be44eb28
MCC		 5257 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5258error:
5259 if (status < 0)
5260 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5261 return status;
43dd07f7
RM		 5262}
5263
5264/*============================================================================*/
5265
5266/**
5267* \brief Set QAM symbolrate.
5268* \param demod: instance of demod.
5269* \param channel: pointer to channel data.
5270* \return DRXStatus_t.
5271*/
5272static int QAMSetSymbolrate(struct drxk_state *state)
5273{
ebc7de22
OE		 5274 u32 adcFrequency = 0;
5275 u32 symbFreq = 0;
5276 u32 iqmRcRate = 0;
5277 u16 ratesel = 0;
5278 u32 lcSymbRate = 0;
5279 int status;
5280
2da67501 5281 dprintk(1, "\n");
be44eb28
MCC		 5282 /* Select & calculate correct IQM rate */
5283 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5284 ratesel = 0;
5285 /* printk(KERN_DEBUG "drxk: SR %d\n", state->param.u.qam.symbol_rate); */
5286 if (state->param.u.qam.symbol_rate <= 1188750)
5287 ratesel = 3;
5288 else if (state->param.u.qam.symbol_rate <= 2377500)
5289 ratesel = 2;
5290 else if (state->param.u.qam.symbol_rate <= 4755000)
5291 ratesel = 1;
5292 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5293 if (status < 0)
5294 goto error;
ebc7de22 5295
be44eb28
MCC		 5296 /*
5297 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5298 */
5299 symbFreq = state->param.u.qam.symbol_rate * (1 << ratesel);
5300 if (symbFreq == 0) {
5301 /* Divide by zero */
5302 status = -EINVAL;
5303 goto error;
5304 }
5305 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5306 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5307 (1 << 23);
5308 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5309 if (status < 0)
5310 goto error;
5311 state->m_iqmRcRate = iqmRcRate;
5312 /*
5313 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5314 */
5315 symbFreq = state->param.u.qam.symbol_rate;
5316 if (adcFrequency == 0) {
5317 /* Divide by zero */
5318 status = -EINVAL;
5319 goto error;
5320 }
5321 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5322 (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5323 16);
5324 if (lcSymbRate > 511)
5325 lcSymbRate = 511;
5326 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5327
5328error:
5329 if (status < 0)
5330 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5331 return status;
43dd07f7
RM		 5332}
5333
5334/*============================================================================*/
5335
5336/**
5337* \brief Get QAM lock status.
5338* \param demod: instance of demod.
5339* \param channel: pointer to channel data.
5340* \return DRXStatus_t.
5341*/
5342
5343static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5344{
5345 int status;
ebc7de22 5346 u16 Result[2] = { 0, 0 };
43dd07f7 5347
2da67501 5348 dprintk(1, "\n");
be44eb28
MCC		 5349 *pLockStatus = NOT_LOCKED;
5350 status = scu_command(state,
ebc7de22
OE		 5351 SCU_RAM_COMMAND_STANDARD_QAM |
5352 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5353 Result);
5354 if (status < 0)
e0e6ecaf 5355 printk(KERN_ERR "drxk: %s status = %08x\n", __func__, status);
ebc7de22
OE		 5356
5357 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
43dd07f7 5358 /* 0x0000 NOT LOCKED */
ebc7de22 5359 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
43dd07f7
RM		 5360 /* 0x4000 DEMOD LOCKED */
5361 *pLockStatus = DEMOD_LOCK;
ebc7de22 5362 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
43dd07f7
RM		 5363 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5364 *pLockStatus = MPEG_LOCK;
ebc7de22 5365 } else {
43dd07f7
RM		 5366 /* 0xC000 NEVER LOCKED */
5367 /* (system will never be able to lock to the signal) */
5368 /* TODO: check this, intermediate & standard specific lock states are not
5369 taken into account here */
5370 *pLockStatus = NEVER_LOCK;
5371 }
5372 return status;
5373}
5374
5375#define QAM_MIRROR__M 0x03
5376#define QAM_MIRROR_NORMAL 0x00
5377#define QAM_MIRRORED 0x01
5378#define QAM_MIRROR_AUTO_ON 0x02
5379#define QAM_LOCKRANGE__M 0x10
5380#define QAM_LOCKRANGE_NORMAL 0x10
5381
ebc7de22
OE		 5382static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5383 s32 tunerFreqOffset)
43dd07f7 5384{
be44eb28 5385 int status;
ebc7de22
OE		 5386 u16 setParamParameters[4] = { 0, 0, 0, 0 };
5387 u16 cmdResult;
43dd07f7 5388
2da67501 5389 dprintk(1, "\n");
be44eb28 5390 /*
119faf90
MCC		 5391 * STEP 1: reset demodulator
5392 * resets FEC DI and FEC RS
5393 * resets QAM block
5394 * resets SCU variables
5395 */
be44eb28
MCC		 5396 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5397 if (status < 0)
5398 goto error;
5399 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5400 if (status < 0)
5401 goto error;
5402 status = QAMResetQAM(state);
5403 if (status < 0)
5404 goto error;
43dd07f7 5405
be44eb28 5406 /*
119faf90
MCC		 5407 * STEP 2: configure demodulator
5408 * -set params; resets IQM,QAM,FEC HW; initializes some
5409 * SCU variables
5410 */
be44eb28
MCC		 5411 status = QAMSetSymbolrate(state);
5412 if (status < 0)
5413 goto error;
5414
be44eb28
MCC		 5415 /* Set params */
5416 switch (state->param.u.qam.modulation) {
5417 case QAM_256:
5418 state->m_Constellation = DRX_CONSTELLATION_QAM256;
5419 break;
5420 case QAM_AUTO:
5421 case QAM_64:
5422 state->m_Constellation = DRX_CONSTELLATION_QAM64;
5423 break;
5424 case QAM_16:
5425 state->m_Constellation = DRX_CONSTELLATION_QAM16;
5426 break;
5427 case QAM_32:
5428 state->m_Constellation = DRX_CONSTELLATION_QAM32;
5429 break;
5430 case QAM_128:
5431 state->m_Constellation = DRX_CONSTELLATION_QAM128;
5432 break;
5433 default:
5434 status = -EINVAL;
5435 break;
5436 }
5437 if (status < 0)
5438 goto error;
5439 setParamParameters[0] = state->m_Constellation; /* constellation */
5440 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
119faf90
MCC		 5441 if (state->m_OperationMode == OM_QAM_ITU_C)
5442 setParamParameters[2] = QAM_TOP_ANNEX_C;
5443 else
5444 setParamParameters[2] = QAM_TOP_ANNEX_A;
5445 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5446 /* Env parameters */
5447 /* check for LOCKRANGE Extented */
5448 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
43dd07f7 5449
be44eb28 5450 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult);
5eee2bb2
MCC		 5451 if (status < 0) {
5452 /* Fall-back to the simpler call */
5eee2bb2 5453 if (state->m_OperationMode == OM_QAM_ITU_C)
119faf90 5454 setParamParameters[0] = QAM_TOP_ANNEX_C;
5eee2bb2 5455 else
119faf90
MCC		 5456 setParamParameters[0] = QAM_TOP_ANNEX_A;
5457 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 1, setParamParameters, 1, &cmdResult);
5458 if (status < 0)
5459 goto error;
43dd07f7 5460
5eee2bb2
MCC		 5461 setParamParameters[0] = state->m_Constellation; /* constellation */
5462 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5eee2bb2
MCC		 5463 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult);
5464 }
5465 if (status < 0)
5466 goto error;
43dd07f7 5467
119faf90
MCC		 5468 /*
5469 * STEP 3: enable the system in a mode where the ADC provides valid
5470 * signal setup constellation independent registers
5471 */
ea90f011 5472#if 0
be44eb28
MCC		 5473 status = SetFrequency(channel, tunerFreqOffset));
5474 if (status < 0)
5475 goto error;
ea90f011 5476#endif
be44eb28
MCC		 5477 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5478 if (status < 0)
5479 goto error;
43dd07f7 5480
be44eb28
MCC		 5481 /* Setup BER measurement */
5482 status = SetQAMMeasurement(state, state->m_Constellation, state->param.u. qam.symbol_rate);
5483 if (status < 0)
5484 goto error;
ebc7de22 5485
be44eb28
MCC		 5486 /* Reset default values */
5487 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5488 if (status < 0)
5489 goto error;
5490 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5491 if (status < 0)
5492 goto error;
ea90f011 5493
be44eb28
MCC		 5494 /* Reset default LC values */
5495 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5496 if (status < 0)
5497 goto error;
5498 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5499 if (status < 0)
5500 goto error;
5501 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5502 if (status < 0)
5503 goto error;
5504 status = write16(state, QAM_LC_MODE__A, 7);
5505 if (status < 0)
5506 goto error;
ebc7de22 5507
be44eb28
MCC		 5508 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5509 if (status < 0)
5510 goto error;
5511 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5512 if (status < 0)
5513 goto error;
5514 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5515 if (status < 0)
5516 goto error;
5517 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5518 if (status < 0)
5519 goto error;
5520 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5521 if (status < 0)
5522 goto error;
5523 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5524 if (status < 0)
5525 goto error;
5526 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5527 if (status < 0)
5528 goto error;
5529 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5530 if (status < 0)
5531 goto error;
5532 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5533 if (status < 0)
5534 goto error;
5535 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5536 if (status < 0)
5537 goto error;
5538 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5539 if (status < 0)
5540 goto error;
5541 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5542 if (status < 0)
5543 goto error;
5544 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5545 if (status < 0)
5546 goto error;
5547 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5548 if (status < 0)
5549 goto error;
5550 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5551 if (status < 0)
5552 goto error;
ebc7de22 5553
be44eb28
MCC		 5554 /* Mirroring, QAM-block starting point not inverted */
5555 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5556 if (status < 0)
5557 goto error;
ebc7de22 5558
be44eb28
MCC		 5559 /* Halt SCU to enable safe non-atomic accesses */
5560 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5561 if (status < 0)
5562 goto error;
ebc7de22 5563
be44eb28
MCC		 5564 /* STEP 4: constellation specific setup */
5565 switch (state->param.u.qam.modulation) {
5566 case QAM_16:
5567 status = SetQAM16(state);
5568 break;
5569 case QAM_32:
5570 status = SetQAM32(state);
5571 break;
5572 case QAM_AUTO:
5573 case QAM_64:
5574 status = SetQAM64(state);
5575 break;
5576 case QAM_128:
5577 status = SetQAM128(state);
5578 break;
5579 case QAM_256:
5580 status = SetQAM256(state);
5581 break;
5582 default:
5583 status = -EINVAL;
5584 break;
5585 }
5586 if (status < 0)
5587 goto error;
ebc7de22 5588
be44eb28
MCC		 5589 /* Activate SCU to enable SCU commands */
5590 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5591 if (status < 0)
5592 goto error;
ebc7de22 5593
be44eb28
MCC		 5594 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5595 /* extAttr->currentChannel.constellation = channel->constellation; */
5596 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5597 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5598 if (status < 0)
5599 goto error;
ebc7de22 5600
be44eb28
MCC		 5601 /* Start processes */
5602 status = MPEGTSStart(state);
5603 if (status < 0)
5604 goto error;
5605 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5606 if (status < 0)
5607 goto error;
5608 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5609 if (status < 0)
5610 goto error;
5611 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5612 if (status < 0)
5613 goto error;
ebc7de22 5614
be44eb28
MCC		 5615 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5616 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5617 if (status < 0)
5618 goto error;
ebc7de22 5619
be44eb28
MCC		 5620 /* update global DRXK data container */
5621/*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
ebc7de22 5622
be44eb28 5623error:
ebc7de22 5624 if (status < 0)
be44eb28 5625 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5626 return status;
43dd07f7
RM		 5627}
5628
ebc7de22
OE		 5629static int SetQAMStandard(struct drxk_state *state,
5630 enum OperationMode oMode)
43dd07f7 5631{
be44eb28 5632 int status;
43dd07f7
RM		 5633#ifdef DRXK_QAM_TAPS
5634#define DRXK_QAMA_TAPS_SELECT
5635#include "drxk_filters.h"
5636#undef DRXK_QAMA_TAPS_SELECT
43dd07f7
RM		 5637#endif
5638
f1b82970
MCC		 5639 dprintk(1, "\n");
5640
be44eb28
MCC		 5641 /* added antenna switch */
5642 SwitchAntennaToQAM(state);
ebc7de22 5643
be44eb28
MCC		 5644 /* Ensure correct power-up mode */
5645 status = PowerUpQAM(state);
5646 if (status < 0)
5647 goto error;
5648 /* Reset QAM block */
5649 status = QAMResetQAM(state);
5650 if (status < 0)
5651 goto error;
ebc7de22 5652
be44eb28 5653 /* Setup IQM */
ebc7de22 5654
be44eb28
MCC		 5655 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5656 if (status < 0)
5657 goto error;
5658 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5659 if (status < 0)
5660 goto error;
ebc7de22 5661
be44eb28
MCC		 5662 /* Upload IQM Channel Filter settings by
5663 boot loader from ROM table */
5664 switch (oMode) {
5665 case OM_QAM_ITU_A:
5666 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5667 break;
5668 case OM_QAM_ITU_C:
5669 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
ea90f011 5670 if (status < 0)
be44eb28
MCC		 5671 goto error;
5672 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5673 break;
5674 default:
5675 status = -EINVAL;
5676 }
5677 if (status < 0)
5678 goto error;
ea90f011 5679
be44eb28
MCC		 5680 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5681 if (status < 0)
5682 goto error;
5683 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5684 if (status < 0)
5685 goto error;
5686 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5687 if (status < 0)
5688 goto error;
ea90f011 5689
be44eb28
MCC		 5690 status = write16(state, IQM_RC_STRETCH__A, 21);
5691 if (status < 0)
5692 goto error;
5693 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5694 if (status < 0)
5695 goto error;
5696 status = write16(state, IQM_AF_CLP_TH__A, 448);
5697 if (status < 0)
5698 goto error;
5699 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5700 if (status < 0)
5701 goto error;
5702 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5703 if (status < 0)
5704 goto error;
ea90f011 5705
be44eb28
MCC		 5706 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5707 if (status < 0)
5708 goto error;
5709 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5710 if (status < 0)
5711 goto error;
5712 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5713 if (status < 0)
5714 goto error;
5715 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5716 if (status < 0)
5717 goto error;
ebc7de22 5718
be44eb28
MCC		 5719 /* IQM Impulse Noise Processing Unit */
5720 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5721 if (status < 0)
5722 goto error;
5723 status = write16(state, IQM_CF_DATATH__A, 1000);
5724 if (status < 0)
5725 goto error;
5726 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5727 if (status < 0)
5728 goto error;
5729 status = write16(state, IQM_CF_DET_LCT__A, 0);
5730 if (status < 0)
5731 goto error;
5732 status = write16(state, IQM_CF_WND_LEN__A, 1);
5733 if (status < 0)
5734 goto error;
5735 status = write16(state, IQM_CF_PKDTH__A, 1);
5736 if (status < 0)
5737 goto error;
5738 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5739 if (status < 0)
5740 goto error;
ebc7de22 5741
be44eb28
MCC		 5742 /* turn on IQMAF. Must be done before setAgc**() */
5743 status = SetIqmAf(state, true);
5744 if (status < 0)
5745 goto error;
5746 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5747 if (status < 0)
5748 goto error;
ebc7de22 5749
be44eb28
MCC		 5750 /* IQM will not be reset from here, sync ADC and update/init AGC */
5751 status = ADCSynchronization(state);
5752 if (status < 0)
5753 goto error;
ebc7de22 5754
be44eb28
MCC		 5755 /* Set the FSM step period */
5756 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5757 if (status < 0)
5758 goto error;
ebc7de22 5759
be44eb28
MCC		 5760 /* Halt SCU to enable safe non-atomic accesses */
5761 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5762 if (status < 0)
5763 goto error;
ebc7de22 5764
be44eb28
MCC		 5765 /* No more resets of the IQM, current standard correctly set =>
5766 now AGCs can be configured. */
ebc7de22 5767
be44eb28
MCC		 5768 status = InitAGC(state, true);
5769 if (status < 0)
5770 goto error;
5771 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5772 if (status < 0)
5773 goto error;
ebc7de22 5774
be44eb28
MCC		 5775 /* Configure AGC's */
5776 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5777 if (status < 0)
5778 goto error;
5779 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5780 if (status < 0)
5781 goto error;
ebc7de22 5782
be44eb28
MCC		 5783 /* Activate SCU to enable SCU commands */
5784 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5785error:
5786 if (status < 0)
5787 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5788 return status;
43dd07f7
RM		 5789}
5790
5791static int WriteGPIO(struct drxk_state *state)
5792{
ebc7de22
OE		 5793 int status;
5794 u16 value = 0;
5795
2da67501 5796 dprintk(1, "\n");
be44eb28
MCC		 5797 /* stop lock indicator process */
5798 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5799 if (status < 0)
5800 goto error;
ebc7de22 5801
be44eb28
MCC		 5802 /* Write magic word to enable pdr reg write */
5803 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5804 if (status < 0)
5805 goto error;
ebc7de22 5806
be44eb28 5807 if (state->m_hasSAWSW) {
90796aca
MCC		 5808 if (state->UIO_mask & 0x0001) { /* UIO-1 */
5809 /* write to io pad configuration register - output mode */
5810 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5811 if (status < 0)
5812 goto error;
ebc7de22 5813
90796aca
MCC		 5814 /* use corresponding bit in io data output registar */
5815 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5816 if (status < 0)
5817 goto error;
5818 if ((state->m_GPIO & 0x0001) == 0)
5819 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5820 else
5821 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5822 /* write back to io data output register */
5823 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5824 if (status < 0)
5825 goto error;
5826 }
5827 if (state->UIO_mask & 0x0002) { /* UIO-2 */
5828 /* write to io pad configuration register - output mode */
5829 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5830 if (status < 0)
5831 goto error;
be44eb28 5832
90796aca
MCC		 5833 /* use corresponding bit in io data output registar */
5834 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5835 if (status < 0)
5836 goto error;
5837 if ((state->m_GPIO & 0x0002) == 0)
5838 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5839 else
5840 value |= 0x4000; /* write one to 14th bit - 2st UIO */
5841 /* write back to io data output register */
5842 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5843 if (status < 0)
5844 goto error;
5845 }
5846 if (state->UIO_mask & 0x0004) { /* UIO-3 */
5847 /* write to io pad configuration register - output mode */
5848 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5849 if (status < 0)
5850 goto error;
5851
5852 /* use corresponding bit in io data output registar */
5853 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5854 if (status < 0)
5855 goto error;
5856 if ((state->m_GPIO & 0x0004) == 0)
5857 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5858 else
5859 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5860 /* write back to io data output register */
5861 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5862 if (status < 0)
5863 goto error;
5864 }
be44eb28
MCC		 5865 }
5866 /* Write magic word to disable pdr reg write */
5867 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5868error:
5869 if (status < 0)
5870 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5871 return status;
43dd07f7
RM		 5872}
5873
5874static int SwitchAntennaToQAM(struct drxk_state *state)
5875{
147e110b 5876 int status = 0;
90796aca 5877 bool gpio_state;
ebc7de22 5878
2da67501 5879 dprintk(1, "\n");
147e110b 5880
90796aca
MCC		 5881 if (!state->antenna_gpio)
5882 return 0;
5883
5884 gpio_state = state->m_GPIO & state->antenna_gpio;
5885
5886 if (state->antenna_dvbt ^ gpio_state) {
5887 /* Antenna is on DVB-T mode. Switch */
5888 if (state->antenna_dvbt)
5889 state->m_GPIO &= ~state->antenna_gpio;
5890 else
5891 state->m_GPIO |= state->antenna_gpio;
5892 status = WriteGPIO(state);
ebc7de22 5893 }
be44eb28
MCC		 5894 if (status < 0)
5895 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5896 return status;
43dd07f7
RM		 5897}
5898
5899static int SwitchAntennaToDVBT(struct drxk_state *state)
5900{
147e110b 5901 int status = 0;
90796aca 5902 bool gpio_state;
ebc7de22 5903
2da67501 5904 dprintk(1, "\n");
90796aca
MCC		 5905
5906 if (!state->antenna_gpio)
5907 return 0;
5908
5909 gpio_state = state->m_GPIO & state->antenna_gpio;
5910
5911 if (!(state->antenna_dvbt ^ gpio_state)) {
5912 /* Antenna is on DVB-C mode. Switch */
5913 if (state->antenna_dvbt)
5914 state->m_GPIO |= state->antenna_gpio;
5915 else
5916 state->m_GPIO &= ~state->antenna_gpio;
5917 status = WriteGPIO(state);
43dd07f7 5918 }
be44eb28
MCC		 5919 if (status < 0)
5920 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7
RM		 5921 return status;
5922}
5923
5924
5925static int PowerDownDevice(struct drxk_state *state)
5926{
5927 /* Power down to requested mode */
5928 /* Backup some register settings */
5929 /* Set pins with possible pull-ups connected to them in input mode */
5930 /* Analog power down */
5931 /* ADC power down */
5932 /* Power down device */
5933 int status;
2da67501
MCC		 5934
5935 dprintk(1, "\n");
be44eb28
MCC		 5936 if (state->m_bPDownOpenBridge) {
5937 /* Open I2C bridge before power down of DRXK */
5938 status = ConfigureI2CBridge(state, true);
ea90f011 5939 if (status < 0)
be44eb28
MCC		 5940 goto error;
5941 }
5942 /* driver 0.9.0 */
5943 status = DVBTEnableOFDMTokenRing(state, false);
5944 if (status < 0)
5945 goto error;
43dd07f7 5946
be44eb28 5947 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
ebc7de22 5948 if (status < 0)
be44eb28
MCC		 5949 goto error;
5950 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5951 if (status < 0)
5952 goto error;
5953 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5954 status = HI_CfgCommand(state);
5955error:
5956 if (status < 0)
5957 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
ebc7de22 5958
be44eb28 5959 return status;
43dd07f7
RM		 5960}
5961
e4f4f875 5962static int load_microcode(struct drxk_state *state, const char *mc_name)
43dd07f7
RM		 5963{
5964 const struct firmware *fw = NULL;
ebc7de22 5965 int err = 0;
43dd07f7 5966
2da67501
MCC		 5967 dprintk(1, "\n");
5968
43dd07f7
RM		 5969 err = request_firmware(&fw, mc_name, state->i2c->dev.parent);
5970 if (err < 0) {
5971 printk(KERN_ERR
e0e6ecaf 5972 "drxk: Could not load firmware file %s.\n", mc_name);
43dd07f7 5973 printk(KERN_INFO
e0e6ecaf 5974 "drxk: Copy %s to your hotplug directory!\n", mc_name);
43dd07f7
RM		 5975 return err;
5976 }
ebc7de22 5977 err = DownloadMicrocode(state, fw->data, fw->size);
43dd07f7
RM		 5978 release_firmware(fw);
5979 return err;
5980}
5981
5982static int init_drxk(struct drxk_state *state)
5983{
be44eb28 5984 int status = 0;
ebc7de22 5985 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
43dd07f7
RM		 5986 u16 driverVersion;
5987
2da67501 5988 dprintk(1, "\n");
43dd07f7 5989 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
be44eb28
MCC		 5990 status = PowerUpDevice(state);
5991 if (status < 0)
5992 goto error;
5993 status = DRXX_Open(state);
5994 if (status < 0)
5995 goto error;
5996 /* Soft reset of OFDM-, sys- and osc-clockdomain */
5997 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
5998 if (status < 0)
5999 goto error;
6000 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6001 if (status < 0)
6002 goto error;
6003 /* TODO is this needed, if yes how much delay in worst case scenario */
6004 msleep(1);
6005 state->m_DRXK_A3_PATCH_CODE = true;
6006 status = GetDeviceCapabilities(state);
6007 if (status < 0)
6008 goto error;
6009
6010 /* Bridge delay, uses oscilator clock */
6011 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6012 /* SDA brdige delay */
6013 state->m_HICfgBridgeDelay =
6014 (u16) ((state->m_oscClockFreq / 1000) *
6015 HI_I2C_BRIDGE_DELAY) / 1000;
6016 /* Clipping */
6017 if (state->m_HICfgBridgeDelay >
6018 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
ebc7de22 6019 state->m_HICfgBridgeDelay =
be44eb28
MCC		 6020 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6021 }
6022 /* SCL bridge delay, same as SDA for now */
6023 state->m_HICfgBridgeDelay +=
6024 state->m_HICfgBridgeDelay <<
6025 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6026
6027 status = InitHI(state);
6028 if (status < 0)
6029 goto error;
6030 /* disable various processes */
43dd07f7 6031#if NOA1ROM
be44eb28
MCC		 6032 if (!(state->m_DRXK_A1_ROM_CODE)
6033 && !(state->m_DRXK_A2_ROM_CODE))
43dd07f7 6034#endif
be44eb28
MCC		 6035 {
6036 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
ea90f011 6037 if (status < 0)
be44eb28
MCC		 6038 goto error;
6039 }
43dd07f7 6040
be44eb28
MCC		 6041 /* disable MPEG port */
6042 status = MPEGTSDisable(state);
6043 if (status < 0)
6044 goto error;
43dd07f7 6045
be44eb28
MCC		 6046 /* Stop AUD and SCU */
6047 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6048 if (status < 0)
6049 goto error;
6050 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6051 if (status < 0)
6052 goto error;
e4f4f875 6053
be44eb28
MCC		 6054 /* enable token-ring bus through OFDM block for possible ucode upload */
6055 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6056 if (status < 0)
6057 goto error;
43dd07f7 6058
be44eb28
MCC		 6059 /* include boot loader section */
6060 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6061 if (status < 0)
6062 goto error;
6063 status = BLChainCmd(state, 0, 6, 100);
6064 if (status < 0)
6065 goto error;
43dd07f7 6066
be44eb28
MCC		 6067 if (!state->microcode_name)
6068 load_microcode(state, "drxk_a3.mc");
6069 else
6070 load_microcode(state, state->microcode_name);
43dd07f7 6071
be44eb28
MCC		 6072 /* disable token-ring bus through OFDM block for possible ucode upload */
6073 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6074 if (status < 0)
6075 goto error;
ebc7de22 6076
be44eb28
MCC		 6077 /* Run SCU for a little while to initialize microcode version numbers */
6078 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6079 if (status < 0)
6080 goto error;
6081 status = DRXX_Open(state);
6082 if (status < 0)
6083 goto error;
6084 /* added for test */
6085 msleep(30);
43dd07f7 6086
be44eb28
MCC		 6087 powerMode = DRXK_POWER_DOWN_OFDM;
6088 status = CtrlPowerMode(state, &powerMode);
6089 if (status < 0)
6090 goto error;
6091
6092 /* Stamp driver version number in SCU data RAM in BCD code
6093 Done to enable field application engineers to retreive drxdriver version
6094 via I2C from SCU RAM.
6095 Not using SCU command interface for SCU register access since no
6096 microcode may be present.
6097 */
6098 driverVersion =
6099 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6100 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6101 ((DRXK_VERSION_MAJOR % 10) << 4) +
6102 (DRXK_VERSION_MINOR % 10);
6103 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6104 if (status < 0)
6105 goto error;
6106 driverVersion =
6107 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6108 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6109 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6110 (DRXK_VERSION_PATCH % 10);
6111 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6112 if (status < 0)
6113 goto error;
6114
6115 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6116 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6117 DRXK_VERSION_PATCH);
6118
6119 /* Dirty fix of default values for ROM/PATCH microcode
6120 Dirty because this fix makes it impossible to setup suitable values
6121 before calling DRX_Open. This solution requires changes to RF AGC speed
6122 to be done via the CTRL function after calling DRX_Open */
6123
6124 /* m_dvbtRfAgcCfg.speed = 3; */
6125
6126 /* Reset driver debug flags to 0 */
6127 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6128 if (status < 0)
6129 goto error;
6130 /* driver 0.9.0 */
6131 /* Setup FEC OC:
6132 NOTE: No more full FEC resets allowed afterwards!! */
6133 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6134 if (status < 0)
6135 goto error;
6136 /* MPEGTS functions are still the same */
6137 status = MPEGTSDtoInit(state);
6138 if (status < 0)
6139 goto error;
6140 status = MPEGTSStop(state);
6141 if (status < 0)
6142 goto error;
6143 status = MPEGTSConfigurePolarity(state);
6144 if (status < 0)
6145 goto error;
6146 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6147 if (status < 0)
6148 goto error;
6149 /* added: configure GPIO */
6150 status = WriteGPIO(state);
6151 if (status < 0)
6152 goto error;
43dd07f7 6153
be44eb28 6154 state->m_DrxkState = DRXK_STOPPED;
43dd07f7 6155
be44eb28
MCC		 6156 if (state->m_bPowerDown) {
6157 status = PowerDownDevice(state);
ea90f011 6158 if (status < 0)
be44eb28
MCC		 6159 goto error;
6160 state->m_DrxkState = DRXK_POWERED_DOWN;
6161 } else
ebc7de22 6162 state->m_DrxkState = DRXK_STOPPED;
43dd07f7 6163 }
be44eb28
MCC		 6164error:
6165 if (status < 0)
6166 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
43dd07f7 6167
e716adac 6168 return status;
43dd07f7
RM		 6169}
6170
ebc7de22 6171static void drxk_c_release(struct dvb_frontend *fe)
43dd07f7 6172{
ebc7de22
OE		 6173 struct drxk_state *state = fe->demodulator_priv;
6174
2da67501 6175 dprintk(1, "\n");
43dd07f7
RM		 6176 kfree(state);
6177}
6178
ebc7de22 6179static int drxk_c_init(struct dvb_frontend *fe)
43dd07f7 6180{
ebc7de22 6181 struct drxk_state *state = fe->demodulator_priv;
43dd07f7 6182
2da67501 6183 dprintk(1, "\n");
ebc7de22 6184 if (mutex_trylock(&state->ctlock) == 0)
43dd07f7
RM		 6185 return -EBUSY;
6186 SetOperationMode(state, OM_QAM_ITU_A);
6187 return 0;
6188}
6189
ebc7de22 6190static int drxk_c_sleep(struct dvb_frontend *fe)
43dd07f7 6191{
ebc7de22 6192 struct drxk_state *state = fe->demodulator_priv;
43dd07f7 6193
2da67501 6194 dprintk(1, "\n");
43dd07f7
RM		 6195 ShutDown(state);
6196 mutex_unlock(&state->ctlock);
6197 return 0;
6198}
6199
ebc7de22 6200static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
43dd07f7
RM		 6201{
6202 struct drxk_state *state = fe->demodulator_priv;
6203
2da67501 6204 dprintk(1, "%s\n", enable ? "enable" : "disable");
43dd07f7
RM		 6205 return ConfigureI2CBridge(state, enable ? true : false);
6206}
6207
ebc7de22
OE		 6208static int drxk_set_parameters(struct dvb_frontend *fe,
6209 struct dvb_frontend_parameters *p)
43dd07f7
RM		 6210{
6211 struct drxk_state *state = fe->demodulator_priv;
6212 u32 IF;
6213
2da67501 6214 dprintk(1, "\n");
8513e144
MCC		 6215
6216 if (!fe->ops.tuner_ops.get_if_frequency) {
6217 printk(KERN_ERR
6218 "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6219 return -EINVAL;
6220 }
6221
2440f7af
MCC		 6222 if (state->m_OperationMode == OM_QAM_ITU_A ||
6223 state->m_OperationMode == OM_QAM_ITU_C) {
6224 if (fe->dtv_property_cache.rolloff == ROLLOFF_13)
6225 state->m_OperationMode = OM_QAM_ITU_C;
6226 else
6227 state->m_OperationMode = OM_QAM_ITU_A;
6228 }
8513e144 6229
43dd07f7
RM		 6230 if (fe->ops.i2c_gate_ctrl)
6231 fe->ops.i2c_gate_ctrl(fe, 1);
6232 if (fe->ops.tuner_ops.set_params)
6233 fe->ops.tuner_ops.set_params(fe, p);
6234 if (fe->ops.i2c_gate_ctrl)
6235 fe->ops.i2c_gate_ctrl(fe, 0);
ebc7de22 6236 state->param = *p;
8513e144 6237 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
43dd07f7
RM		 6238 Start(state, 0, IF);
6239
e0e6ecaf 6240 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
ebc7de22 6241
43dd07f7
RM		 6242 return 0;
6243}
6244
ebc7de22
OE		 6245static int drxk_c_get_frontend(struct dvb_frontend *fe,
6246 struct dvb_frontend_parameters *p)
43dd07f7 6247{
2da67501 6248 dprintk(1, "\n");
43dd07f7
RM		 6249 return 0;
6250}
6251
6252static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6253{
6254 struct drxk_state *state = fe->demodulator_priv;
6255 u32 stat;
6256
2da67501 6257 dprintk(1, "\n");
ebc7de22 6258 *status = 0;
43dd07f7 6259 GetLockStatus(state, &stat, 0);
ebc7de22
OE		 6260 if (stat == MPEG_LOCK)
6261 *status |= 0x1f;
6262 if (stat == FEC_LOCK)
6263 *status |= 0x0f;
6264 if (stat == DEMOD_LOCK)
6265 *status |= 0x07;
43dd07f7
RM		 6266 return 0;
6267}
6268
6269static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber)
6270{
2da67501
MCC		 6271 dprintk(1, "\n");
6272
ebc7de22 6273 *ber = 0;
43dd07f7
RM		 6274 return 0;
6275}
6276
ebc7de22
OE		 6277static int drxk_read_signal_strength(struct dvb_frontend *fe,
6278 u16 *strength)
43dd07f7
RM		 6279{
6280 struct drxk_state *state = fe->demodulator_priv;
be44eb28 6281 u32 val = 0;
43dd07f7 6282
2da67501 6283 dprintk(1, "\n");
43dd07f7 6284 ReadIFAgc(state, &val);
ebc7de22 6285 *strength = val & 0xffff;
43dd07f7
RM		 6286 return 0;
6287}
6288
6289static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6290{
6291 struct drxk_state *state = fe->demodulator_priv;
6292 s32 snr2;
6293
2da67501 6294 dprintk(1, "\n");
43dd07f7 6295 GetSignalToNoise(state, &snr2);
ebc7de22 6296 *snr = snr2 & 0xffff;
43dd07f7
RM		 6297 return 0;
6298}
6299
6300static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6301{
6302 struct drxk_state *state = fe->demodulator_priv;
6303 u16 err;
6304
2da67501 6305 dprintk(1, "\n");
43dd07f7
RM		 6306 DVBTQAMGetAccPktErr(state, &err);
6307 *ucblocks = (u32) err;
6308 return 0;
6309}
6310
ebc7de22
OE		 6311static int drxk_c_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6312 *sets)
43dd07f7 6313{
2da67501 6314 dprintk(1, "\n");
ebc7de22
OE		 6315 sets->min_delay_ms = 3000;
6316 sets->max_drift = 0;
6317 sets->step_size = 0;
43dd07f7
RM		 6318 return 0;
6319}
6320
ebc7de22 6321static void drxk_t_release(struct dvb_frontend *fe)
43dd07f7 6322{
c4c3a3d3
MCC		 6323 /*
6324 * There's nothing to release here, as the state struct
6325 * is already freed by drxk_c_release.
6326 */
43dd07f7
RM		 6327}
6328
ebc7de22 6329static int drxk_t_init(struct dvb_frontend *fe)
43dd07f7 6330{
ebc7de22 6331 struct drxk_state *state = fe->demodulator_priv;
2da67501
MCC		 6332
6333 dprintk(1, "\n");
ebc7de22 6334 if (mutex_trylock(&state->ctlock) == 0)
43dd07f7 6335 return -EBUSY;
43dd07f7 6336 SetOperationMode(state, OM_DVBT);
43dd07f7
RM		 6337 return 0;
6338}
6339
ebc7de22 6340static int drxk_t_sleep(struct dvb_frontend *fe)
43dd07f7 6341{
ebc7de22 6342 struct drxk_state *state = fe->demodulator_priv;
2da67501
MCC		 6343
6344 dprintk(1, "\n");
43dd07f7
RM		 6345 mutex_unlock(&state->ctlock);
6346 return 0;
6347}
6348
ebc7de22
OE		 6349static int drxk_t_get_frontend(struct dvb_frontend *fe,
6350 struct dvb_frontend_parameters *p)
43dd07f7 6351{
2da67501
MCC		 6352 dprintk(1, "\n");
6353
43dd07f7
RM		 6354 return 0;
6355}
6356
6357static struct dvb_frontend_ops drxk_c_ops = {
6358 .info = {
ebc7de22
OE		 6359 .name = "DRXK DVB-C",
6360 .type = FE_QAM,
6361 .frequency_stepsize = 62500,
6362 .frequency_min = 47000000,
6363 .frequency_max = 862000000,
6364 .symbol_rate_min = 870000,
6365 .symbol_rate_max = 11700000,
6366 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6367 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
43dd07f7
RM		 6368 .release = drxk_c_release,
6369 .init = drxk_c_init,
6370 .sleep = drxk_c_sleep,
6371 .i2c_gate_ctrl = drxk_gate_ctrl,
6372
6373 .set_frontend = drxk_set_parameters,
6374 .get_frontend = drxk_c_get_frontend,
6375 .get_tune_settings = drxk_c_get_tune_settings,
6376
6377 .read_status = drxk_read_status,
6378 .read_ber = drxk_read_ber,
6379 .read_signal_strength = drxk_read_signal_strength,
6380 .read_snr = drxk_read_snr,
6381 .read_ucblocks = drxk_read_ucblocks,
6382};
6383
6384static struct dvb_frontend_ops drxk_t_ops = {
6385 .info = {
ebc7de22
OE		 6386 .name = "DRXK DVB-T",
6387 .type = FE_OFDM,
6388 .frequency_min = 47125000,
6389 .frequency_max = 865000000,
6390 .frequency_stepsize = 166667,
6391 .frequency_tolerance = 0,
6392 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
6393 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
6394 FE_CAN_FEC_AUTO |
6395 FE_CAN_QAM_16 | FE_CAN_QAM_64 |
6396 FE_CAN_QAM_AUTO |
6397 FE_CAN_TRANSMISSION_MODE_AUTO |
6398 FE_CAN_GUARD_INTERVAL_AUTO |
6399 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
43dd07f7
RM		 6400 .release = drxk_t_release,
6401 .init = drxk_t_init,
6402 .sleep = drxk_t_sleep,
6403 .i2c_gate_ctrl = drxk_gate_ctrl,
6404
6405 .set_frontend = drxk_set_parameters,
6406 .get_frontend = drxk_t_get_frontend,
6407
6408 .read_status = drxk_read_status,
6409 .read_ber = drxk_read_ber,
6410 .read_signal_strength = drxk_read_signal_strength,
6411 .read_snr = drxk_read_snr,
6412 .read_ucblocks = drxk_read_ucblocks,
6413};
6414
0fc55e81
MCC		 6415struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6416 struct i2c_adapter *i2c,
43dd07f7
RM		 6417 struct dvb_frontend **fe_t)
6418{
6419 struct drxk_state *state = NULL;
0fc55e81 6420 u8 adr = config->adr;
43dd07f7 6421
2da67501 6422 dprintk(1, "\n");
ebc7de22 6423 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
43dd07f7
RM		 6424 if (!state)
6425 return NULL;
6426
ebc7de22
OE		 6427 state->i2c = i2c;
6428 state->demod_address = adr;
e076c92e 6429 state->single_master = config->single_master;
e4f4f875 6430 state->microcode_name = config->microcode_name;
f1fe1b75 6431 state->no_i2c_bridge = config->no_i2c_bridge;
90796aca
MCC		 6432 state->antenna_gpio = config->antenna_gpio;
6433 state->antenna_dvbt = config->antenna_dvbt;
82e7dbbd 6434 state->m_ChunkSize = config->chunk_size;
90796aca
MCC		 6435
6436 /* NOTE: as more UIO bits will be used, add them to the mask */
6437 state->UIO_mask = config->antenna_gpio;
6438
6439 /* Default gpio to DVB-C */
6440 if (!state->antenna_dvbt && state->antenna_gpio)
6441 state->m_GPIO |= state->antenna_gpio;
6442 else
6443 state->m_GPIO &= ~state->antenna_gpio;
43dd07f7
RM		 6444
6445 mutex_init(&state->mutex);
6446 mutex_init(&state->ctlock);
6447
ebc7de22
OE		 6448 memcpy(&state->c_frontend.ops, &drxk_c_ops,
6449 sizeof(struct dvb_frontend_ops));
6450 memcpy(&state->t_frontend.ops, &drxk_t_ops,
6451 sizeof(struct dvb_frontend_ops));
6452 state->c_frontend.demodulator_priv = state;
6453 state->t_frontend.demodulator_priv = state;
43dd07f7
RM		 6454
6455 init_state(state);
ebc7de22 6456 if (init_drxk(state) < 0)
43dd07f7
RM		 6457 goto error;
6458 *fe_t = &state->t_frontend;
cf694b14 6459
43dd07f7
RM		 6460 return &state->c_frontend;
6461
6462error:
ebc7de22 6463 printk(KERN_ERR "drxk: not found\n");
43dd07f7
RM		 6464 kfree(state);
6465 return NULL;
6466}
ebc7de22 6467EXPORT_SYMBOL(drxk_attach);
43dd07f7
RM		 6468
6469MODULE_DESCRIPTION("DRX-K driver");
6470MODULE_AUTHOR("Ralph Metzler");
6471MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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