[media] dvb_frontend: Fix inversion breakage due to DVBv5 conversion
[deliverable/linux.git] / drivers / media / dvb / frontends / lgdt330x.c
CommitLineData
d8667cbb 1/*
1963c907 2 * Support for LGDT3302 and LGDT3303 - VSB/QAM
d8667cbb
MM
3 *
4 * Copyright (C) 2005 Wilson Michaels <wilsonmichaels@earthlink.net>
5 *
d8667cbb
MM
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 */
21
22/*
23 * NOTES ABOUT THIS DRIVER
24 *
1963c907
MK
25 * This Linux driver supports:
26 * DViCO FusionHDTV 3 Gold-Q
27 * DViCO FusionHDTV 3 Gold-T
28 * DViCO FusionHDTV 5 Gold
3cff00d9 29 * DViCO FusionHDTV 5 Lite
d8e6acf2 30 * DViCO FusionHDTV 5 USB Gold
c0b11b91 31 * Air2PC/AirStar 2 ATSC 3rd generation (HD5000)
20fe4f65 32 * pcHDTV HD5500
d8667cbb 33 *
d8667cbb
MM
34 */
35
d8667cbb
MM
36#include <linux/kernel.h>
37#include <linux/module.h>
d8667cbb
MM
38#include <linux/init.h>
39#include <linux/delay.h>
4e57b681
TS
40#include <linux/string.h>
41#include <linux/slab.h>
d8667cbb
MM
42#include <asm/byteorder.h>
43
44#include "dvb_frontend.h"
19be685a 45#include "dvb_math.h"
6ddcc919
MK
46#include "lgdt330x_priv.h"
47#include "lgdt330x.h"
d8667cbb 48
19be685a
TP
49/* Use Equalizer Mean Squared Error instead of Phaser Tracker MSE */
50/* #define USE_EQMSE */
51
ff699e6b 52static int debug;
d8667cbb 53module_param(debug, int, 0644);
6ddcc919 54MODULE_PARM_DESC(debug,"Turn on/off lgdt330x frontend debugging (default:off).");
d8667cbb
MM
55#define dprintk(args...) \
56do { \
6ddcc919 57if (debug) printk(KERN_DEBUG "lgdt330x: " args); \
d8667cbb
MM
58} while (0)
59
6ddcc919 60struct lgdt330x_state
d8667cbb
MM
61{
62 struct i2c_adapter* i2c;
d8667cbb
MM
63
64 /* Configuration settings */
6ddcc919 65 const struct lgdt330x_config* config;
d8667cbb
MM
66
67 struct dvb_frontend frontend;
68
69 /* Demodulator private data */
70 fe_modulation_t current_modulation;
19be685a 71 u32 snr; /* Result of last SNR calculation */
d8667cbb
MM
72
73 /* Tuner private data */
74 u32 current_frequency;
75};
76
1963c907 77static int i2c_write_demod_bytes (struct lgdt330x_state* state,
dc9ca2af
MK
78 u8 *buf, /* data bytes to send */
79 int len /* number of bytes to send */ )
d8667cbb 80{
b6aef071 81 struct i2c_msg msg =
1963c907
MK
82 { .addr = state->config->demod_address,
83 .flags = 0,
84 .buf = buf,
85 .len = 2 };
b6aef071 86 int i;
1963c907 87 int err;
d8667cbb 88
1963c907 89 for (i=0; i<len-1; i+=2){
d8667cbb 90 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
271ddbf7 91 printk(KERN_WARNING "lgdt330x: %s error (addr %02x <- %02x, err = %i)\n", __func__, msg.buf[0], msg.buf[1], err);
58ba006b
MK
92 if (err < 0)
93 return err;
94 else
95 return -EREMOTEIO;
d8667cbb 96 }
1963c907 97 msg.buf += 2;
d8667cbb
MM
98 }
99 return 0;
100}
101
102/*
103 * This routine writes the register (reg) to the demod bus
104 * then reads the data returned for (len) bytes.
105 */
106
1963c907 107static u8 i2c_read_demod_bytes (struct lgdt330x_state* state,
d8667cbb
MM
108 enum I2C_REG reg, u8* buf, int len)
109{
110 u8 wr [] = { reg };
111 struct i2c_msg msg [] = {
112 { .addr = state->config->demod_address,
113 .flags = 0, .buf = wr, .len = 1 },
114 { .addr = state->config->demod_address,
115 .flags = I2C_M_RD, .buf = buf, .len = len },
116 };
117 int ret;
118 ret = i2c_transfer(state->i2c, msg, 2);
119 if (ret != 2) {
271ddbf7 120 printk(KERN_WARNING "lgdt330x: %s: addr 0x%02x select 0x%02x error (ret == %i)\n", __func__, state->config->demod_address, reg, ret);
d8667cbb
MM
121 } else {
122 ret = 0;
123 }
124 return ret;
125}
126
127/* Software reset */
1963c907 128static int lgdt3302_SwReset(struct lgdt330x_state* state)
d8667cbb
MM
129{
130 u8 ret;
131 u8 reset[] = {
132 IRQ_MASK,
133 0x00 /* bit 6 is active low software reset
134 * bits 5-0 are 1 to mask interrupts */
135 };
136
1963c907 137 ret = i2c_write_demod_bytes(state,
dc9ca2af 138 reset, sizeof(reset));
d8667cbb 139 if (ret == 0) {
1963c907
MK
140
141 /* force reset high (inactive) and unmask interrupts */
142 reset[1] = 0x7f;
143 ret = i2c_write_demod_bytes(state,
dc9ca2af 144 reset, sizeof(reset));
d8667cbb 145 }
d8667cbb
MM
146 return ret;
147}
148
1963c907
MK
149static int lgdt3303_SwReset(struct lgdt330x_state* state)
150{
151 u8 ret;
152 u8 reset[] = {
153 0x02,
154 0x00 /* bit 0 is active low software reset */
155 };
156
157 ret = i2c_write_demod_bytes(state,
dc9ca2af 158 reset, sizeof(reset));
1963c907
MK
159 if (ret == 0) {
160
161 /* force reset high (inactive) */
162 reset[1] = 0x01;
163 ret = i2c_write_demod_bytes(state,
dc9ca2af 164 reset, sizeof(reset));
1963c907
MK
165 }
166 return ret;
167}
168
169static int lgdt330x_SwReset(struct lgdt330x_state* state)
170{
171 switch (state->config->demod_chip) {
172 case LGDT3302:
173 return lgdt3302_SwReset(state);
174 case LGDT3303:
175 return lgdt3303_SwReset(state);
176 default:
177 return -ENODEV;
178 }
179}
180
6ddcc919 181static int lgdt330x_init(struct dvb_frontend* fe)
d8667cbb
MM
182{
183 /* Hardware reset is done using gpio[0] of cx23880x chip.
184 * I'd like to do it here, but don't know how to find chip address.
185 * cx88-cards.c arranges for the reset bit to be inactive (high).
186 * Maybe there needs to be a callable function in cx88-core or
187 * the caller of this function needs to do it. */
188
1963c907
MK
189 /*
190 * Array of byte pairs <address, value>
191 * to initialize each different chip
192 */
193 static u8 lgdt3302_init_data[] = {
194 /* Use 50MHz parameter values from spec sheet since xtal is 50 */
195 /* Change the value of NCOCTFV[25:0] of carrier
196 recovery center frequency register */
197 VSB_CARRIER_FREQ0, 0x00,
198 VSB_CARRIER_FREQ1, 0x87,
199 VSB_CARRIER_FREQ2, 0x8e,
200 VSB_CARRIER_FREQ3, 0x01,
201 /* Change the TPCLK pin polarity
202 data is valid on falling clock */
203 DEMUX_CONTROL, 0xfb,
204 /* Change the value of IFBW[11:0] of
205 AGC IF/RF loop filter bandwidth register */
206 AGC_RF_BANDWIDTH0, 0x40,
207 AGC_RF_BANDWIDTH1, 0x93,
208 AGC_RF_BANDWIDTH2, 0x00,
209 /* Change the value of bit 6, 'nINAGCBY' and
210 'NSSEL[1:0] of ACG function control register 2 */
211 AGC_FUNC_CTRL2, 0xc6,
212 /* Change the value of bit 6 'RFFIX'
213 of AGC function control register 3 */
214 AGC_FUNC_CTRL3, 0x40,
215 /* Set the value of 'INLVTHD' register 0x2a/0x2c
216 to 0x7fe */
217 AGC_DELAY0, 0x07,
218 AGC_DELAY2, 0xfe,
219 /* Change the value of IAGCBW[15:8]
9aaeded7 220 of inner AGC loop filter bandwidth */
1963c907
MK
221 AGC_LOOP_BANDWIDTH0, 0x08,
222 AGC_LOOP_BANDWIDTH1, 0x9a
223 };
224
225 static u8 lgdt3303_init_data[] = {
226 0x4c, 0x14
227 };
228
c0f4c0ad 229 static u8 flip_1_lgdt3303_init_data[] = {
c0b11b91
MK
230 0x4c, 0x14,
231 0x87, 0xf3
232 };
233
c0f4c0ad
MK
234 static u8 flip_2_lgdt3303_init_data[] = {
235 0x4c, 0x14,
236 0x87, 0xda
237 };
238
1963c907
MK
239 struct lgdt330x_state* state = fe->demodulator_priv;
240 char *chip_name;
241 int err;
242
243 switch (state->config->demod_chip) {
244 case LGDT3302:
245 chip_name = "LGDT3302";
246 err = i2c_write_demod_bytes(state, lgdt3302_init_data,
dc9ca2af
MK
247 sizeof(lgdt3302_init_data));
248 break;
1963c907
MK
249 case LGDT3303:
250 chip_name = "LGDT3303";
c0f4c0ad
MK
251 switch (state->config->clock_polarity_flip) {
252 case 2:
253 err = i2c_write_demod_bytes(state,
254 flip_2_lgdt3303_init_data,
255 sizeof(flip_2_lgdt3303_init_data));
256 break;
257 case 1:
258 err = i2c_write_demod_bytes(state,
259 flip_1_lgdt3303_init_data,
260 sizeof(flip_1_lgdt3303_init_data));
261 break;
262 case 0:
263 default:
c0b11b91
MK
264 err = i2c_write_demod_bytes(state, lgdt3303_init_data,
265 sizeof(lgdt3303_init_data));
266 }
dc9ca2af 267 break;
1963c907
MK
268 default:
269 chip_name = "undefined";
270 printk (KERN_WARNING "Only LGDT3302 and LGDT3303 are supported chips.\n");
271 err = -ENODEV;
272 }
271ddbf7 273 dprintk("%s entered as %s\n", __func__, chip_name);
1963c907
MK
274 if (err < 0)
275 return err;
276 return lgdt330x_SwReset(state);
d8667cbb
MM
277}
278
6ddcc919 279static int lgdt330x_read_ber(struct dvb_frontend* fe, u32* ber)
d8667cbb 280{
1963c907 281 *ber = 0; /* Not supplied by the demod chips */
d8667cbb
MM
282 return 0;
283}
284
6ddcc919 285static int lgdt330x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
d8667cbb 286{
1963c907
MK
287 struct lgdt330x_state* state = fe->demodulator_priv;
288 int err;
d8667cbb
MM
289 u8 buf[2];
290
26110dac
MK
291 *ucblocks = 0;
292
1963c907
MK
293 switch (state->config->demod_chip) {
294 case LGDT3302:
295 err = i2c_read_demod_bytes(state, LGDT3302_PACKET_ERR_COUNTER1,
dc9ca2af
MK
296 buf, sizeof(buf));
297 break;
1963c907
MK
298 case LGDT3303:
299 err = i2c_read_demod_bytes(state, LGDT3303_PACKET_ERR_COUNTER1,
dc9ca2af
MK
300 buf, sizeof(buf));
301 break;
1963c907
MK
302 default:
303 printk(KERN_WARNING
dc9ca2af 304 "Only LGDT3302 and LGDT3303 are supported chips.\n");
1963c907
MK
305 err = -ENODEV;
306 }
26110dac
MK
307 if (err < 0)
308 return err;
d8667cbb
MM
309
310 *ucblocks = (buf[0] << 8) | buf[1];
311 return 0;
312}
313
ca7072dd 314static int lgdt330x_set_parameters(struct dvb_frontend *fe)
d8667cbb 315{
ca7072dd 316 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1963c907
MK
317 /*
318 * Array of byte pairs <address, value>
319 * to initialize 8VSB for lgdt3303 chip 50 MHz IF
320 */
321 static u8 lgdt3303_8vsb_44_data[] = {
322 0x04, 0x00,
323 0x0d, 0x40,
0b6389ff
MK
324 0x0e, 0x87,
325 0x0f, 0x8e,
326 0x10, 0x01,
327 0x47, 0x8b };
1963c907
MK
328
329 /*
330 * Array of byte pairs <address, value>
331 * to initialize QAM for lgdt3303 chip
332 */
333 static u8 lgdt3303_qam_data[] = {
334 0x04, 0x00,
335 0x0d, 0x00,
336 0x0e, 0x00,
337 0x0f, 0x00,
338 0x10, 0x00,
339 0x51, 0x63,
340 0x47, 0x66,
341 0x48, 0x66,
342 0x4d, 0x1a,
343 0x49, 0x08,
344 0x4a, 0x9b };
345
346 struct lgdt330x_state* state = fe->demodulator_priv;
d8667cbb 347
d8667cbb 348 static u8 top_ctrl_cfg[] = { TOP_CONTROL, 0x03 };
d8667cbb 349
54828d19 350 int err = 0;
d8667cbb 351 /* Change only if we are actually changing the modulation */
ca7072dd
MCC
352 if (state->current_modulation != p->modulation) {
353 switch (p->modulation) {
d8667cbb 354 case VSB_8:
271ddbf7 355 dprintk("%s: VSB_8 MODE\n", __func__);
d8667cbb 356
1963c907
MK
357 /* Select VSB mode */
358 top_ctrl_cfg[1] = 0x03;
0ccef6db
MK
359
360 /* Select ANT connector if supported by card */
361 if (state->config->pll_rf_set)
362 state->config->pll_rf_set(fe, 1);
1963c907
MK
363
364 if (state->config->demod_chip == LGDT3303) {
365 err = i2c_write_demod_bytes(state, lgdt3303_8vsb_44_data,
dc9ca2af 366 sizeof(lgdt3303_8vsb_44_data));
1963c907 367 }
d8667cbb
MM
368 break;
369
370 case QAM_64:
271ddbf7 371 dprintk("%s: QAM_64 MODE\n", __func__);
d8667cbb 372
1963c907
MK
373 /* Select QAM_64 mode */
374 top_ctrl_cfg[1] = 0x00;
0ccef6db
MK
375
376 /* Select CABLE connector if supported by card */
377 if (state->config->pll_rf_set)
378 state->config->pll_rf_set(fe, 0);
1963c907
MK
379
380 if (state->config->demod_chip == LGDT3303) {
381 err = i2c_write_demod_bytes(state, lgdt3303_qam_data,
382 sizeof(lgdt3303_qam_data));
383 }
d8667cbb
MM
384 break;
385
386 case QAM_256:
271ddbf7 387 dprintk("%s: QAM_256 MODE\n", __func__);
d8667cbb 388
1963c907
MK
389 /* Select QAM_256 mode */
390 top_ctrl_cfg[1] = 0x01;
0ccef6db
MK
391
392 /* Select CABLE connector if supported by card */
393 if (state->config->pll_rf_set)
394 state->config->pll_rf_set(fe, 0);
1963c907
MK
395
396 if (state->config->demod_chip == LGDT3303) {
397 err = i2c_write_demod_bytes(state, lgdt3303_qam_data,
398 sizeof(lgdt3303_qam_data));
399 }
d8667cbb
MM
400 break;
401 default:
ca7072dd 402 printk(KERN_WARNING "lgdt330x: %s: Modulation type(%d) UNSUPPORTED\n", __func__, p->modulation);
d8667cbb
MM
403 return -1;
404 }
54828d19
MK
405 if (err < 0)
406 printk(KERN_WARNING "lgdt330x: %s: error blasting "
407 "bytes to lgdt3303 for modulation type(%d)\n",
ca7072dd 408 __func__, p->modulation);
54828d19 409
1963c907
MK
410 /*
411 * select serial or parallel MPEG harware interface
412 * Serial: 0x04 for LGDT3302 or 0x40 for LGDT3303
413 * Parallel: 0x00
414 */
415 top_ctrl_cfg[1] |= state->config->serial_mpeg;
d8667cbb
MM
416
417 /* Select the requested mode */
1963c907 418 i2c_write_demod_bytes(state, top_ctrl_cfg,
dc9ca2af
MK
419 sizeof(top_ctrl_cfg));
420 if (state->config->set_ts_params)
421 state->config->set_ts_params(fe, 0);
ca7072dd 422 state->current_modulation = p->modulation;
d8667cbb 423 }
d8667cbb 424
dc9ca2af 425 /* Tune to the specified frequency */
dea74869 426 if (fe->ops.tuner_ops.set_params) {
14d24d14 427 fe->ops.tuner_ops.set_params(fe);
dea74869 428 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
02269f37 429 }
dc9ca2af
MK
430
431 /* Keep track of the new frequency */
4302c15e
MCC
432 /* FIXME this is the wrong way to do this... */
433 /* The tuner is shared with the video4linux analog API */
ca7072dd 434 state->current_frequency = p->frequency;
dc9ca2af 435
6ddcc919 436 lgdt330x_SwReset(state);
d8667cbb
MM
437 return 0;
438}
439
ca7072dd
MCC
440static int lgdt330x_get_frontend(struct dvb_frontend *fe,
441 struct dtv_frontend_properties *p)
d8667cbb 442{
6ddcc919 443 struct lgdt330x_state *state = fe->demodulator_priv;
ca7072dd 444 p->frequency = state->current_frequency;
d8667cbb
MM
445 return 0;
446}
447
1963c907 448static int lgdt3302_read_status(struct dvb_frontend* fe, fe_status_t* status)
d8667cbb 449{
1963c907 450 struct lgdt330x_state* state = fe->demodulator_priv;
d8667cbb
MM
451 u8 buf[3];
452
453 *status = 0; /* Reset status result */
454
08d80525 455 /* AGC status register */
1963c907 456 i2c_read_demod_bytes(state, AGC_STATUS, buf, 1);
271ddbf7 457 dprintk("%s: AGC_STATUS = 0x%02x\n", __func__, buf[0]);
08d80525
MK
458 if ((buf[0] & 0x0c) == 0x8){
459 /* Test signal does not exist flag */
460 /* as well as the AGC lock flag. */
461 *status |= FE_HAS_SIGNAL;
08d80525
MK
462 }
463
1963c907
MK
464 /*
465 * You must set the Mask bits to 1 in the IRQ_MASK in order
466 * to see that status bit in the IRQ_STATUS register.
467 * This is done in SwReset();
468 */
d8667cbb 469 /* signal status */
1963c907 470 i2c_read_demod_bytes(state, TOP_CONTROL, buf, sizeof(buf));
271ddbf7 471 dprintk("%s: TOP_CONTROL = 0x%02x, IRO_MASK = 0x%02x, IRQ_STATUS = 0x%02x\n", __func__, buf[0], buf[1], buf[2]);
08d80525 472
d8667cbb
MM
473
474 /* sync status */
475 if ((buf[2] & 0x03) == 0x01) {
476 *status |= FE_HAS_SYNC;
477 }
478
479 /* FEC error status */
480 if ((buf[2] & 0x0c) == 0x08) {
481 *status |= FE_HAS_LOCK;
482 *status |= FE_HAS_VITERBI;
483 }
484
d8667cbb 485 /* Carrier Recovery Lock Status Register */
1963c907 486 i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1);
271ddbf7 487 dprintk("%s: CARRIER_LOCK = 0x%02x\n", __func__, buf[0]);
d8667cbb
MM
488 switch (state->current_modulation) {
489 case QAM_256:
490 case QAM_64:
af901ca1 491 /* Need to understand why there are 3 lock levels here */
d8667cbb
MM
492 if ((buf[0] & 0x07) == 0x07)
493 *status |= FE_HAS_CARRIER;
d8667cbb 494 break;
d8667cbb
MM
495 case VSB_8:
496 if ((buf[0] & 0x80) == 0x80)
497 *status |= FE_HAS_CARRIER;
d8667cbb 498 break;
d8667cbb 499 default:
271ddbf7 500 printk(KERN_WARNING "lgdt330x: %s: Modulation set to unsupported value\n", __func__);
d8667cbb 501 }
d8667cbb
MM
502
503 return 0;
504}
505
1963c907
MK
506static int lgdt3303_read_status(struct dvb_frontend* fe, fe_status_t* status)
507{
508 struct lgdt330x_state* state = fe->demodulator_priv;
509 int err;
510 u8 buf[3];
511
512 *status = 0; /* Reset status result */
513
514 /* lgdt3303 AGC status register */
515 err = i2c_read_demod_bytes(state, 0x58, buf, 1);
516 if (err < 0)
517 return err;
518
271ddbf7 519 dprintk("%s: AGC_STATUS = 0x%02x\n", __func__, buf[0]);
1963c907
MK
520 if ((buf[0] & 0x21) == 0x01){
521 /* Test input signal does not exist flag */
522 /* as well as the AGC lock flag. */
523 *status |= FE_HAS_SIGNAL;
1963c907
MK
524 }
525
526 /* Carrier Recovery Lock Status Register */
527 i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1);
271ddbf7 528 dprintk("%s: CARRIER_LOCK = 0x%02x\n", __func__, buf[0]);
1963c907
MK
529 switch (state->current_modulation) {
530 case QAM_256:
531 case QAM_64:
af901ca1 532 /* Need to understand why there are 3 lock levels here */
1963c907
MK
533 if ((buf[0] & 0x07) == 0x07)
534 *status |= FE_HAS_CARRIER;
535 else
536 break;
537 i2c_read_demod_bytes(state, 0x8a, buf, 1);
538 if ((buf[0] & 0x04) == 0x04)
539 *status |= FE_HAS_SYNC;
540 if ((buf[0] & 0x01) == 0x01)
541 *status |= FE_HAS_LOCK;
542 if ((buf[0] & 0x08) == 0x08)
543 *status |= FE_HAS_VITERBI;
544 break;
545 case VSB_8:
546 if ((buf[0] & 0x80) == 0x80)
547 *status |= FE_HAS_CARRIER;
548 else
549 break;
550 i2c_read_demod_bytes(state, 0x38, buf, 1);
551 if ((buf[0] & 0x02) == 0x00)
552 *status |= FE_HAS_SYNC;
553 if ((buf[0] & 0x01) == 0x01) {
554 *status |= FE_HAS_LOCK;
555 *status |= FE_HAS_VITERBI;
556 }
557 break;
558 default:
271ddbf7 559 printk(KERN_WARNING "lgdt330x: %s: Modulation set to unsupported value\n", __func__);
1963c907
MK
560 }
561 return 0;
562}
563
19be685a
TP
564/* Calculate SNR estimation (scaled by 2^24)
565
566 8-VSB SNR equations from LGDT3302 and LGDT3303 datasheets, QAM
567 equations from LGDT3303 datasheet. VSB is the same between the '02
568 and '03, so maybe QAM is too? Perhaps someone with a newer datasheet
569 that has QAM information could verify?
570
571 For 8-VSB: (two ways, take your pick)
572 LGDT3302:
573 SNR_EQ = 10 * log10(25 * 24^2 / EQ_MSE)
574 LGDT3303:
575 SNR_EQ = 10 * log10(25 * 32^2 / EQ_MSE)
576 LGDT3302 & LGDT3303:
577 SNR_PT = 10 * log10(25 * 32^2 / PT_MSE) (we use this one)
578 For 64-QAM:
579 SNR = 10 * log10( 688128 / MSEQAM)
580 For 256-QAM:
581 SNR = 10 * log10( 696320 / MSEQAM)
582
583 We re-write the snr equation as:
584 SNR * 2^24 = 10*(c - intlog10(MSE))
585 Where for 256-QAM, c = log10(696320) * 2^24, and so on. */
586
587static u32 calculate_snr(u32 mse, u32 c)
d8667cbb 588{
19be685a
TP
589 if (mse == 0) /* No signal */
590 return 0;
591
592 mse = intlog10(mse);
593 if (mse > c) {
594 /* Negative SNR, which is possible, but realisticly the
595 demod will lose lock before the signal gets this bad. The
596 API only allows for unsigned values, so just return 0 */
597 return 0;
598 }
599 return 10*(c - mse);
d8667cbb
MM
600}
601
1963c907 602static int lgdt3302_read_snr(struct dvb_frontend* fe, u16* snr)
d8667cbb 603{
6ddcc919 604 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
19be685a
TP
605 u8 buf[5]; /* read data buffer */
606 u32 noise; /* noise value */
607 u32 c; /* per-modulation SNR calculation constant */
d8667cbb 608
19be685a
TP
609 switch(state->current_modulation) {
610 case VSB_8:
611 i2c_read_demod_bytes(state, LGDT3302_EQPH_ERR0, buf, 5);
612#ifdef USE_EQMSE
613 /* Use Equalizer Mean-Square Error Register */
614 /* SNR for ranges from -15.61 to +41.58 */
d8667cbb 615 noise = ((buf[0] & 7) << 16) | (buf[1] << 8) | buf[2];
19be685a 616 c = 69765745; /* log10(25*24^2)*2^24 */
d8667cbb 617#else
19be685a
TP
618 /* Use Phase Tracker Mean-Square Error Register */
619 /* SNR for ranges from -13.11 to +44.08 */
d8667cbb 620 noise = ((buf[0] & 7<<3) << 13) | (buf[3] << 8) | buf[4];
19be685a
TP
621 c = 73957994; /* log10(25*32^2)*2^24 */
622#endif
623 break;
624 case QAM_64:
625 case QAM_256:
626 i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2);
1963c907 627 noise = ((buf[0] & 3) << 8) | buf[1];
19be685a
TP
628 c = state->current_modulation == QAM_64 ? 97939837 : 98026066;
629 /* log10(688128)*2^24 and log10(696320)*2^24 */
630 break;
631 default:
632 printk(KERN_ERR "lgdt330x: %s: Modulation set to unsupported value\n",
271ddbf7 633 __func__);
19be685a 634 return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */
d8667cbb
MM
635 }
636
19be685a
TP
637 state->snr = calculate_snr(noise, c);
638 *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */
d8667cbb 639
271ddbf7 640 dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __func__, noise,
19be685a 641 state->snr >> 24, (((state->snr>>8) & 0xffff) * 100) >> 16);
d8667cbb
MM
642
643 return 0;
644}
645
1963c907
MK
646static int lgdt3303_read_snr(struct dvb_frontend* fe, u16* snr)
647{
1963c907 648 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
19be685a
TP
649 u8 buf[5]; /* read data buffer */
650 u32 noise; /* noise value */
651 u32 c; /* per-modulation SNR calculation constant */
1963c907 652
19be685a
TP
653 switch(state->current_modulation) {
654 case VSB_8:
655 i2c_read_demod_bytes(state, LGDT3303_EQPH_ERR0, buf, 5);
656#ifdef USE_EQMSE
657 /* Use Equalizer Mean-Square Error Register */
658 /* SNR for ranges from -16.12 to +44.08 */
659 noise = ((buf[0] & 0x78) << 13) | (buf[1] << 8) | buf[2];
660 c = 73957994; /* log10(25*32^2)*2^24 */
661#else
662 /* Use Phase Tracker Mean-Square Error Register */
663 /* SNR for ranges from -13.11 to +44.08 */
1963c907 664 noise = ((buf[0] & 7) << 16) | (buf[3] << 8) | buf[4];
19be685a
TP
665 c = 73957994; /* log10(25*32^2)*2^24 */
666#endif
667 break;
668 case QAM_64:
669 case QAM_256:
670 i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2);
1963c907 671 noise = (buf[0] << 8) | buf[1];
19be685a
TP
672 c = state->current_modulation == QAM_64 ? 97939837 : 98026066;
673 /* log10(688128)*2^24 and log10(696320)*2^24 */
674 break;
675 default:
676 printk(KERN_ERR "lgdt330x: %s: Modulation set to unsupported value\n",
271ddbf7 677 __func__);
19be685a 678 return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */
1963c907
MK
679 }
680
19be685a
TP
681 state->snr = calculate_snr(noise, c);
682 *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */
683
271ddbf7 684 dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __func__, noise,
19be685a
TP
685 state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
686
687 return 0;
688}
689
690static int lgdt330x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
691{
692 /* Calculate Strength from SNR up to 35dB */
693 /* Even though the SNR can go higher than 35dB, there is some comfort */
694 /* factor in having a range of strong signals that can show at 100% */
695 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
696 u16 snr;
697 int ret;
1963c907 698
19be685a
TP
699 ret = fe->ops.read_snr(fe, &snr);
700 if (ret != 0)
701 return ret;
702 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
703 /* scale the range 0 - 35*2^24 into 0 - 65535 */
704 if (state->snr >= 8960 * 0x10000)
705 *strength = 0xffff;
706 else
707 *strength = state->snr / 8960;
1963c907
MK
708
709 return 0;
710}
711
6ddcc919 712static int lgdt330x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
d8667cbb
MM
713{
714 /* I have no idea about this - it may not be needed */
715 fe_tune_settings->min_delay_ms = 500;
716 fe_tune_settings->step_size = 0;
717 fe_tune_settings->max_drift = 0;
718 return 0;
719}
720
6ddcc919 721static void lgdt330x_release(struct dvb_frontend* fe)
d8667cbb 722{
6ddcc919 723 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
d8667cbb
MM
724 kfree(state);
725}
726
1963c907
MK
727static struct dvb_frontend_ops lgdt3302_ops;
728static struct dvb_frontend_ops lgdt3303_ops;
d8667cbb 729
6ddcc919 730struct dvb_frontend* lgdt330x_attach(const struct lgdt330x_config* config,
d8667cbb
MM
731 struct i2c_adapter* i2c)
732{
6ddcc919 733 struct lgdt330x_state* state = NULL;
d8667cbb
MM
734 u8 buf[1];
735
736 /* Allocate memory for the internal state */
7408187d 737 state = kzalloc(sizeof(struct lgdt330x_state), GFP_KERNEL);
d8667cbb
MM
738 if (state == NULL)
739 goto error;
d8667cbb
MM
740
741 /* Setup the state */
742 state->config = config;
743 state->i2c = i2c;
dea74869
PB
744
745 /* Create dvb_frontend */
1963c907
MK
746 switch (config->demod_chip) {
747 case LGDT3302:
dea74869 748 memcpy(&state->frontend.ops, &lgdt3302_ops, sizeof(struct dvb_frontend_ops));
1963c907
MK
749 break;
750 case LGDT3303:
dea74869 751 memcpy(&state->frontend.ops, &lgdt3303_ops, sizeof(struct dvb_frontend_ops));
1963c907
MK
752 break;
753 default:
754 goto error;
755 }
dea74869 756 state->frontend.demodulator_priv = state;
1963c907 757
d8667cbb 758 /* Verify communication with demod chip */
1963c907 759 if (i2c_read_demod_bytes(state, 2, buf, 1))
d8667cbb
MM
760 goto error;
761
762 state->current_frequency = -1;
763 state->current_modulation = -1;
764
d8667cbb
MM
765 return &state->frontend;
766
767error:
2ea75330 768 kfree(state);
271ddbf7 769 dprintk("%s: ERROR\n",__func__);
d8667cbb
MM
770 return NULL;
771}
772
1963c907 773static struct dvb_frontend_ops lgdt3302_ops = {
ca7072dd 774 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1963c907 775 .info = {
e179d8b0 776 .name= "LG Electronics LGDT3302 VSB/QAM Frontend",
1963c907
MK
777 .type = FE_ATSC,
778 .frequency_min= 54000000,
779 .frequency_max= 858000000,
780 .frequency_stepsize= 62500,
66944e99
MK
781 .symbol_rate_min = 5056941, /* QAM 64 */
782 .symbol_rate_max = 10762000, /* VSB 8 */
1963c907
MK
783 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
784 },
785 .init = lgdt330x_init,
ca7072dd
MCC
786 .set_frontend = lgdt330x_set_parameters,
787 .get_frontend = lgdt330x_get_frontend,
1963c907
MK
788 .get_tune_settings = lgdt330x_get_tune_settings,
789 .read_status = lgdt3302_read_status,
790 .read_ber = lgdt330x_read_ber,
791 .read_signal_strength = lgdt330x_read_signal_strength,
792 .read_snr = lgdt3302_read_snr,
793 .read_ucblocks = lgdt330x_read_ucblocks,
794 .release = lgdt330x_release,
795};
796
797static struct dvb_frontend_ops lgdt3303_ops = {
ca7072dd 798 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
d8667cbb 799 .info = {
1963c907 800 .name= "LG Electronics LGDT3303 VSB/QAM Frontend",
d8667cbb
MM
801 .type = FE_ATSC,
802 .frequency_min= 54000000,
803 .frequency_max= 858000000,
804 .frequency_stepsize= 62500,
66944e99
MK
805 .symbol_rate_min = 5056941, /* QAM 64 */
806 .symbol_rate_max = 10762000, /* VSB 8 */
d8667cbb
MM
807 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
808 },
6ddcc919 809 .init = lgdt330x_init,
ca7072dd
MCC
810 .set_frontend = lgdt330x_set_parameters,
811 .get_frontend = lgdt330x_get_frontend,
6ddcc919 812 .get_tune_settings = lgdt330x_get_tune_settings,
1963c907 813 .read_status = lgdt3303_read_status,
6ddcc919
MK
814 .read_ber = lgdt330x_read_ber,
815 .read_signal_strength = lgdt330x_read_signal_strength,
1963c907 816 .read_snr = lgdt3303_read_snr,
6ddcc919
MK
817 .read_ucblocks = lgdt330x_read_ucblocks,
818 .release = lgdt330x_release,
d8667cbb
MM
819};
820
1963c907 821MODULE_DESCRIPTION("LGDT330X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver");
d8667cbb
MM
822MODULE_AUTHOR("Wilson Michaels");
823MODULE_LICENSE("GPL");
824
6ddcc919 825EXPORT_SYMBOL(lgdt330x_attach);
d8667cbb
MM
826
827/*
828 * Local variables:
829 * c-basic-offset: 8
d8667cbb
MM
830 * End:
831 */
This page took 0.67894 seconds and 5 git commands to generate.