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V4L/DVB (13716): [Mantis] Bug: incorrect byte swap
[deliverable/linux.git] / drivers / media / dvb / frontends / mb86a16.c
CommitLineData
41e840b1
MA		 1/*
2 Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
3
4 Copyright (C) 2005, 2006 Manu Abraham (abraham.manu@gmail.com)
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19*/
20
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25
26#include "dvb_frontend.h"
27#include "mb86a16.h"
28#include "mb86a16_priv.h"
29
30unsigned int verbose = 5;
31module_param(verbose, int, 0644);
32
33#define ABS(x) ((x) < 0 ? (-x) : (x))
34
35struct mb86a16_state {
36 struct i2c_adapter *i2c_adap;
37 const struct mb86a16_config *config;
38 struct dvb_frontend frontend;
39 u8 signal;
40
41 // tuning parameters
42 int frequency;
43 int srate;
44
45 // Internal stuff
46 int master_clk;
47 int deci;
48 int csel;
49 int rsel;
50};
51
52#define MB86A16_ERROR 0
53#define MB86A16_NOTICE 1
54#define MB86A16_INFO 2
55#define MB86A16_DEBUG 3
56
57#define dprintk(x, y, z, format, arg...) do { \
58 if (z) { \
59 if ((x > MB86A16_ERROR) && (x > y)) \
60 printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \
61 else if ((x > MB86A16_NOTICE) && (x > y)) \
62 printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \
63 else if ((x > MB86A16_INFO) && (x > y)) \
64 printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \
65 else if ((x > MB86A16_DEBUG) && (x > y)) \
66 printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \
67 } else { \
68 if (x > y) \
69 printk(format, ##arg); \
70 } \
71} while (0)
72
73#define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
74#define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
75
76static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val)
77{
78 int ret;
79 u8 buf[] = { reg, val };
80
81 struct i2c_msg msg = {
82 .addr = state->config->demod_address,
83 .flags = 0,
84 .buf = buf,
85 .len = 2
86 };
87
88 dprintk(verbose, MB86A16_DEBUG, 1,
89 "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]",
90 state->config->demod_address, buf[0], buf[1]);
91
92 ret = i2c_transfer(state->i2c_adap, &msg, 1);
93
94 return (ret != 1) ? -EREMOTEIO : 0;
95}
96
97static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val)
98{
99 int ret;
100 u8 b0[] = { reg };
101 u8 b1[] = { 0 };
102
103 struct i2c_msg msg[] = {
104 {
105 .addr = state->config->demod_address,
106 .flags = 0,
107 .buf = b0,
108 .len = 1
109 },{
110 .addr = state->config->demod_address,
111 .flags = I2C_M_RD,
112 .buf = b1,
113 .len = 1
114 }
115 };
116 ret = i2c_transfer(state->i2c_adap, msg, 2);
117 if (ret != 2) {
118 dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=0x%i)",
119 reg, ret);
120
121 return -EREMOTEIO;
122 }
123 *val = b1[0];
124
125 return ret;
126}
127
128static int CNTM_set(struct mb86a16_state *state,
129 unsigned char timint1,
130 unsigned char timint2,
131 unsigned char cnext)
132{
133 unsigned char val;
134
135 val = (timint1 << 4) | (timint2 << 2) | cnext;
136 if (mb86a16_write(state, MB86A16_CNTMR, val) < 0)
137 goto err;
138
139 return 0;
140
141err:
142 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
143 return -EREMOTEIO;
144}
145
146static int smrt_set(struct mb86a16_state *state, int rate)
147{
148 int tmp ;
149 int m ;
150 unsigned char STOFS0, STOFS1;
151
152 m = 1 << state->deci;
153 tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk;
154
155 STOFS0 = tmp & 0x0ff;
156 STOFS1 = (tmp & 0xf00) >> 8;
157
158 if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) |
159 (state->csel << 1) |
160 state->rsel) < 0)
161 goto err;
162 if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0)
163 goto err;
164 if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0)
165 goto err;
166
167 return 0;
168err:
169 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
170 return -1;
171}
172
173static int srst(struct mb86a16_state *state)
174{
175 if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0)
176 goto err;
177
178 return 0;
179err:
180 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
181 return -EREMOTEIO;
182
183}
184
185static int afcex_data_set(struct mb86a16_state *state,
186 unsigned char AFCEX_L,
187 unsigned char AFCEX_H)
188{
189 if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0)
190 goto err;
191 if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0)
192 goto err;
193
194 return 0;
195err:
196 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
197
198 return -1;
199}
200
201static int afcofs_data_set(struct mb86a16_state *state,
202 unsigned char AFCEX_L,
203 unsigned char AFCEX_H)
204{
205 if (mb86a16_write(state, 0x58, AFCEX_L) < 0)
206 goto err;
207 if (mb86a16_write(state, 0x59, AFCEX_H) < 0)
208 goto err;
209
210 return 0;
211err:
212 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
213 return -EREMOTEIO;
214}
215
216static int stlp_set(struct mb86a16_state *state,
217 unsigned char STRAS,
218 unsigned char STRBS)
219{
220 if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0)
221 goto err;
222
223 return 0;
224err:
225 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
226 return -EREMOTEIO;
227}
228
229static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA)
230{
231 if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0)
232 goto err;
233 if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0)
234 goto err;
235
236 return 0;
237err:
238 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
239 return -EREMOTEIO;
240}
241
242static int initial_set(struct mb86a16_state *state)
243{
244 if (stlp_set(state, 5, 7))
245 goto err;
a890cce5
MA		 246
247 udelay(100);
41e840b1
MA		 248 if (afcex_data_set(state, 0, 0))
249 goto err;
a890cce5
MA		 250
251 udelay(100);
41e840b1
MA		 252 if (afcofs_data_set(state, 0, 0))
253 goto err;
254
a890cce5 255 udelay(100);
41e840b1
MA		 256 if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0)
257 goto err;
258 if (mb86a16_write(state, 0x2f, 0x21) < 0)
259 goto err;
260 if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0)
261 goto err;
262 if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0)
263 goto err;
264 if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0)
265 goto err;
266 if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0)
267 goto err;
268 if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0)
269 goto err;
270 if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0)
271 goto err;
272 if (mb86a16_write(state, 0x54, 0xff) < 0)
273 goto err;
274 if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0)
275 goto err;
276
277 return 0;
278
279err:
280 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
281 return -EREMOTEIO;
282}
283
284static int S01T_set(struct mb86a16_state *state,
285 unsigned char s1t,
286 unsigned s0t)
287{
288 if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0)
289 goto err;
290
291 return 0;
292err:
293 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
294 return -EREMOTEIO;
295}
296
297
298static int EN_set(struct mb86a16_state *state,
299 int cren,
300 int afcen)
301{
302 unsigned char val;
303
304 val = 0x7a | (cren << 7) | (afcen << 2);
305 if (mb86a16_write(state, 0x49, val) < 0)
306 goto err;
307
308 return 0;
309err:
310 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
311 return -EREMOTEIO;
312}
313
314static int AFCEXEN_set(struct mb86a16_state *state,
315 int afcexen,
316 int smrt)
317{
318 unsigned char AFCA ;
319
320 if (smrt > 18875)
321 AFCA = 4;
322 else if (smrt > 9375)
323 AFCA = 3;
324 else if (smrt > 2250)
325 AFCA = 2;
326 else
327 AFCA = 1;
328
329 if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0)
330 goto err;
331
332 return 0;
333
334err:
335 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
336 return -EREMOTEIO;
337}
338
339static int DAGC_data_set(struct mb86a16_state *state,
340 unsigned char DAGCA,
341 unsigned char DAGCW)
342{
343 if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0)
344 goto err;
345
346 return 0;
347
348err:
349 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
350 return -EREMOTEIO;
351}
352
353static void smrt_info_get(struct mb86a16_state *state, int rate)
354{
355 if (rate >= 37501) {
356 state->deci = 0; state->csel = 0; state->rsel = 0;
357 } else if (rate >= 30001) {
358 state->deci = 0; state->csel = 0; state->rsel = 1;
359 } else if (rate >= 26251) {
360 state->deci = 0; state->csel = 1; state->rsel = 0;
361 } else if (rate >= 22501) {
362 state->deci = 0; state->csel = 1; state->rsel = 1;
363 } else if (rate >= 18751) {
364 state->deci = 1; state->csel = 0; state->rsel = 0;
365 } else if (rate >= 15001) {
366 state->deci = 1; state->csel = 0; state->rsel = 1;
367 } else if (rate >= 13126) {
368 state->deci = 1; state->csel = 1; state->rsel = 0;
369 } else if (rate >= 11251) {
370 state->deci = 1; state->csel = 1; state->rsel = 1;
371 } else if (rate >= 9376) {
372 state->deci = 2; state->csel = 0; state->rsel = 0;
373 } else if (rate >= 7501) {
374 state->deci = 2; state->csel = 0; state->rsel = 1;
375 } else if (rate >= 6563) {
376 state->deci = 2; state->csel = 1; state->rsel = 0;
377 } else if (rate >= 5626) {
378 state->deci = 2; state->csel = 1; state->rsel = 1;
379 } else if (rate >= 4688) {
380 state->deci = 3; state->csel = 0; state->rsel = 0;
381 } else if (rate >= 3751) {
382 state->deci = 3; state->csel = 0; state->rsel = 1;
383 } else if (rate >= 3282) {
384 state->deci = 3; state->csel = 1; state->rsel = 0;
385 } else if (rate >= 2814) {
386 state->deci = 3; state->csel = 1; state->rsel = 1;
387 } else if (rate >= 2344) {
388 state->deci = 4; state->csel = 0; state->rsel = 0;
389 } else if (rate >= 1876) {
390 state->deci = 4; state->csel = 0; state->rsel = 1;
391 } else if (rate >= 1641) {
392 state->deci = 4; state->csel = 1; state->rsel = 0;
393 } else if (rate >= 1407) {
394 state->deci = 4; state->csel = 1; state->rsel = 1;
395 } else if (rate >= 1172) {
396 state->deci = 5; state->csel = 0; state->rsel = 0;
397 } else if (rate >= 939) {
398 state->deci = 5; state->csel = 0; state->rsel = 1;
399 } else if (rate >= 821) {
400 state->deci = 5; state->csel = 1; state->rsel = 0;
401 } else {
402 state->deci = 5; state->csel = 1; state->rsel = 1;
403 }
404
405 if (state->csel == 0)
406 state->master_clk = 92000;
407 else
408 state->master_clk = 61333;
409
410}
411
412static int signal_det(struct mb86a16_state *state,
413 int smrt,
414 unsigned char *SIG)
415{
416
417 int ret ;
418 int smrtd ;
419 int wait_sym ;
e15c7ccd
MA		 420
421 u32 wait_t;
41e840b1
MA		 422 unsigned char S[3] ;
423 int i ;
424
425 if (*SIG > 45) {
426 if (CNTM_set(state, 2, 1, 2) < 0) {
427 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
428 return -1;
429 }
430 wait_sym = 40000;
431 } else {
432 if (CNTM_set(state, 3, 1, 2) < 0) {
433 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
434 return -1;
435 }
436 wait_sym = 80000;
437 }
438 for (i = 0; i < 3; i++) {
439 if (i == 0 )
440 smrtd = smrt * 98 / 100;
441 else if (i == 1)
442 smrtd = smrt;
443 else
444 smrtd = smrt * 102 / 100;
445 smrt_info_get(state, smrtd);
446 smrt_set(state, smrtd);
447 srst(state);
448 wait_t = (wait_sym + 99 * smrtd / 100) / smrtd;
449 if (wait_t == 0)
450 wait_t = 1;
451 msleep_interruptible(10);
452 if (mb86a16_read(state, 0x37, &(S[i])) != 2) {
453 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
454 return -EREMOTEIO;
455 }
456 }
457 if ((S[1] > S[0] * 112 / 100) &&
458 (S[1] > S[2] * 112 / 100)) {
459
460 ret = 1;
461 } else {
462 ret = 0;
463 }
464 *SIG = S[1];
465
466 if (CNTM_set(state, 0, 1, 2) < 0) {
467 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
468 return -1;
469 }
470
471 return ret;
472}
473
474static int rf_val_set(struct mb86a16_state *state,
475 int f,
476 int smrt,
477 unsigned char R)
478{
479 unsigned char C, F, B;
480 int M;
481 unsigned char rf_val[5];
482 int ack = -1;
483
484 if (smrt > 37750 )
485 C = 1;
486 else if (smrt > 18875)
487 C = 2;
488 else if (smrt > 5500 )
489 C = 3;
490 else
491 C = 4;
492
493 if (smrt > 30500)
494 F = 3;
495 else if (smrt > 9375)
496 F = 1;
497 else if (smrt > 4625)
498 F = 0;
499 else
500 F = 2;
501
502 if (f < 1060)
503 B = 0;
504 else if (f < 1175)
505 B = 1;
506 else if (f < 1305)
507 B = 2;
508 else if (f < 1435)
509 B = 3;
510 else if (f < 1570)
511 B = 4;
512 else if (f < 1715)
513 B = 5;
514 else if (f < 1845)
515 B = 6;
516 else if (f < 1980)
517 B = 7;
518 else if (f < 2080)
519 B = 8;
520 else
521 B = 9;
522
523 M = f * (1 << R) / 2;
524
525 rf_val[0] = 0x01 | (C << 3) | (F << 1);
526 rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
527 rf_val[2] = (M & 0x00ff0) >> 4;
528 rf_val[3] = ((M & 0x0000f) << 4) | B;
529
530 // Frequency Set
531 if (mb86a16_write(state, 0x21, rf_val[0]) < 0)
532 ack = 0;
533 if (mb86a16_write(state, 0x22, rf_val[1]) < 0)
534 ack = 0;
535 if (mb86a16_write(state, 0x23, rf_val[2]) < 0)
536 ack = 0;
537 if (mb86a16_write(state, 0x24, rf_val[3]) < 0)
538 ack = 0;
539 if (mb86a16_write(state, 0x25, 0x01) < 0)
540 ack = 0;
541 if (ack == 0) {
542 dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error");
543 return -EREMOTEIO;
544 }
545
546 return 0;
547}
548
549static int afcerr_chk(struct mb86a16_state *state)
550{
551 unsigned char AFCM_L, AFCM_H ;
552 int AFCM ;
553 int afcm, afcerr ;
554
555 if (mb86a16_read(state, 0x0e, &AFCM_L) != 2)
556 goto err;
557 if (mb86a16_read(state, 0x0f, &AFCM_H) != 2)
558 goto err;
559
560 AFCM = (AFCM_H << 8) + AFCM_L;
561
562 if (AFCM > 2048)
563 afcm = AFCM - 4096;
564 else
565 afcm = AFCM;
566 afcerr = afcm * state->master_clk / 8192;
567
568 return afcerr;
569
570err:
571 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
572 return -EREMOTEIO;
573}
574
575static int dagcm_val_get(struct mb86a16_state *state)
576{
577 int DAGCM;
578 unsigned char DAGCM_H, DAGCM_L;
579
580 if (mb86a16_read(state, 0x45, &DAGCM_L) != 2)
581 goto err;
582 if (mb86a16_read(state, 0x46, &DAGCM_H) != 2)
583 goto err;
584
585 DAGCM = (DAGCM_H << 8) + DAGCM_L;
586
587 return DAGCM;
588
589err:
590 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
591 return -EREMOTEIO;
592}
593
594static int mb86a16_read_status(struct dvb_frontend *fe, fe_status_t *status)
595{
596 struct mb86a16_state *state = fe->demodulator_priv;
597
1fa1f107 598 *status = 0;
41e840b1
MA		 599 if (state->signal & 0x02)
600 *status |= FE_HAS_VITERBI;
601 if (state->signal & 0x01)
602 *status |= FE_HAS_SYNC;
603 if (state->signal & 0x03)
604 *status |= FE_HAS_LOCK;
605
606 return 0;
607}
608
609static int sync_chk(struct mb86a16_state *state,
610 unsigned char *VIRM)
611{
612 unsigned char val;
613 int sync;
614
615 if (mb86a16_read(state, 0x0d, &val) != 2)
616 goto err;
617
618 dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val);
619 sync = val & 0x01;
620 *VIRM = (val & 0x1c) >> 2;
621
622 return sync;
623err:
624 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
625 return -EREMOTEIO;
626
627}
628
629static int freqerr_chk(struct mb86a16_state *state,
630 int fTP,
631 int smrt,
632 int unit)
633{
634 unsigned char CRM, AFCML, AFCMH;
635 unsigned char temp1, temp2, temp3;
636 int crm, afcm, AFCM;
637 int crrerr, afcerr; // [kHz]
638 int frqerr; // [MHz]
639 int afcen, afcexen = 0;
640 int R, M, fOSC, fOSC_OFS;
641
642 if (mb86a16_read(state, 0x43, &CRM) != 2)
643 goto err;
644
645 if (CRM > 127)
646 crm = CRM - 256;
647 else
648 crm = CRM;
649
650 crrerr = smrt * crm / 256;
651 if (mb86a16_read(state, 0x49, &temp1) != 2)
652 goto err;
653
654 afcen = (temp1 & 0x04) >> 2;
655 if (afcen == 0) {
656 if (mb86a16_read(state, 0x2a, &temp1) != 2)
657 goto err;
658 afcexen = (temp1 & 0x20) >> 5;
659 }
660
661 if (afcen == 1) {
662 if (mb86a16_read(state, 0x0e, &AFCML) != 2)
663 goto err;
664 if (mb86a16_read(state, 0x0f, &AFCMH) != 2)
665 goto err;
666 } else if (afcexen == 1) {
667 if (mb86a16_read(state, 0x2b, &AFCML) != 2)
668 goto err;
669 if (mb86a16_read(state, 0x2c, &AFCMH) != 2)
670 goto err;
671 }
672 if ((afcen == 1) || (afcexen == 1)) {
673 smrt_info_get(state, smrt);
674 AFCM = ((AFCMH & 0x01) << 8) + AFCML;
675 if (AFCM > 255)
676 afcm = AFCM - 512;
677 else
678 afcm = AFCM;
679
680 afcerr = afcm * state->master_clk / 8192;
681 } else
682 afcerr = 0;
683
684 if (mb86a16_read(state, 0x22, &temp1) != 2)
685 goto err;
686 if (mb86a16_read(state, 0x23, &temp2) != 2)
687 goto err;
688 if (mb86a16_read(state, 0x24, &temp3) != 2)
689 goto err;
690
691 R = (temp1 & 0xe0) >> 5;
692 M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
693 if (R == 0)
694 fOSC = 2 * M;
695 else
696 fOSC = M;
697
698 fOSC_OFS = fOSC - fTP;
699
700 if (unit == 0) { //[MHz]
701 if (crrerr + afcerr + fOSC_OFS * 1000 >= 0)
702 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000;
703 else
704 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000;
705 } else { //[kHz]
706 frqerr = crrerr + afcerr + fOSC_OFS * 1000;
707 }
708
709 return frqerr;
710err:
711 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
712 return -EREMOTEIO;
713}
714
715static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt)
716{
717 unsigned char R;
718
719 if (smrt > 9375)
720 R = 0;
721 else
722 R = 1;
723
724 return R;
725}
726
727static void swp_info_get(struct mb86a16_state *state,
728 int fOSC_start,
729 int smrt,
730 int v, int R,
731 int swp_ofs,
732 int *fOSC,
733 int *afcex_freq,
734 unsigned char *AFCEX_L,
735 unsigned char *AFCEX_H)
736{
737 int AFCEX ;
738 int crnt_swp_freq ;
739
740 crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
741
742 if (R == 0 )
743 *fOSC = (crnt_swp_freq + 1000) / 2000 * 2;
744 else
745 *fOSC = (crnt_swp_freq + 500) / 1000;
746
747 if (*fOSC >= crnt_swp_freq)
748 *afcex_freq = *fOSC *1000 - crnt_swp_freq;
749 else
750 *afcex_freq = crnt_swp_freq - *fOSC * 1000;
751
752 AFCEX = *afcex_freq * 8192 / state->master_clk;
753 *AFCEX_L = AFCEX & 0x00ff;
754 *AFCEX_H = (AFCEX & 0x0f00) >> 8;
755}
756
757
758static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin,
759 int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1)
760{
761 int swp_freq ;
762
763 if ((i % 2 == 1) && (v <= vmax)) {
764 // positive v (case 1)
765 if ((v - 1 == vmin) &&
766 (*(V + 30 + v) >= 0) &&
767 (*(V + 30 + v - 1) >= 0) &&
768 (*(V + 30 + v - 1) > *(V + 30 + v)) &&
769 (*(V + 30 + v - 1) > SIGMIN)) {
770
771 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
772 *SIG1 = *(V + 30 + v - 1);
773 } else if ((v == vmax) &&
774 (*(V + 30 + v) >= 0) &&
775 (*(V + 30 + v - 1) >= 0) &&
776 (*(V + 30 + v) > *(V + 30 + v - 1)) &&
777 (*(V + 30 + v) > SIGMIN)) {
778 // (case 2)
779 swp_freq = fOSC * 1000 + afcex_freq;
780 *SIG1 = *(V + 30 + v);
781 } else if ((*(V + 30 + v) > 0) &&
782 (*(V + 30 + v - 1) > 0) &&
783 (*(V + 30 + v - 2) > 0) &&
784 (*(V + 30 + v - 3) > 0) &&
785 (*(V + 30 + v - 1) > *(V + 30 + v)) &&
786 (*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
787 ((*(V + 30 + v - 1) > SIGMIN) ||
788 (*(V + 30 + v - 2) > SIGMIN))) {
789 // (case 3)
790 if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
791 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
792 *SIG1 = *(V + 30 + v - 1);
793 } else {
794 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2;
795 *SIG1 = *(V + 30 + v - 2);
796 }
797 } else if ((v == vmax) &&
798 (*(V + 30 + v) >= 0) &&
799 (*(V + 30 + v - 1) >= 0) &&
800 (*(V + 30 + v - 2) >= 0) &&
801 (*(V + 30 + v) > *(V + 30 + v - 2)) &&
802 (*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
803 ((*(V + 30 + v) > SIGMIN) ||
804 (*(V + 30 + v - 1) > SIGMIN))) {
805 // (case 4)
806 if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
807 swp_freq = fOSC * 1000 + afcex_freq;
808 *SIG1 = *(V + 30 + v);
809 } else {
810 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
811 *SIG1 = *(V + 30 + v - 1);
812 }
813 } else {
814 swp_freq = -1 ;
815 }
816 } else if ((i % 2 == 0) && (v >= vmin)) {
817 // Negative v (case 1)
818 if ((*(V + 30 + v) > 0) &&
819 (*(V + 30 + v + 1) > 0) &&
820 (*(V + 30 + v + 2) > 0) &&
821 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
822 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
823 (*(V + 30 + v + 1) > SIGMIN)) {
824
825 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
826 *SIG1 = *(V + 30 + v + 1);
827 } else if ((v + 1 == vmax) &&
828 (*(V + 30 + v) >= 0) &&
829 (*(V + 30 + v + 1) >= 0) &&
830 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
831 (*(V + 30 + v + 1) > SIGMIN)) {
832 // (case 2)
833 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
834 *SIG1 = *(V + 30 + v);
835 } else if ((v == vmin) &&
836 (*(V + 30 + v) > 0) &&
837 (*(V + 30 + v + 1) > 0) &&
838 (*(V + 30 + v + 2) > 0) &&
839 (*(V + 30 + v) > *(V + 30 + v + 1)) &&
840 (*(V + 30 + v) > *(V + 30 + v + 2)) &&
841 (*(V + 30 + v) > SIGMIN)) {
842 // (case 3)
843 swp_freq = fOSC * 1000 + afcex_freq;
844 *SIG1 = *(V + 30 + v);
845 } else if ((*(V + 30 + v) >= 0) &&
846 (*(V + 30 + v + 1) >= 0) &&
847 (*(V + 30 + v + 2) >= 0) &&
848 (*(V +30 + v + 3) >= 0) &&
849 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
850 (*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
851 ((*(V + 30 + v + 1) > SIGMIN) ||
852 (*(V + 30 + v + 2) > SIGMIN))) {
853 // (case 4)
854 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
855 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
856 *SIG1 = *(V + 30 + v + 1);
857 } else {
858 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
859 *SIG1 = *(V + 30 + v + 2);
860 }
861 } else if ((*(V + 30 + v) >= 0) &&
862 (*(V + 30 + v + 1) >= 0) &&
863 (*(V + 30 + v + 2) >= 0) &&
864 (*(V + 30 + v + 3) >= 0) &&
865 (*(V + 30 + v) > *(V + 30 + v + 2)) &&
866 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
867 (*(V + 30 + v) > *(V + 30 + v + 3)) &&
868 (*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
869 ((*(V + 30 + v) > SIGMIN) ||
870 (*(V + 30 + v + 1) > SIGMIN))) {
871 // (case 5)
872 if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
873 swp_freq = fOSC * 1000 + afcex_freq;
874 *SIG1 = *(V + 30 + v);
875 } else {
876 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
877 *SIG1 = *(V + 30 + v + 1);
878 }
879 } else if ((v + 2 == vmin) &&
880 (*(V + 30 + v) >= 0) &&
881 (*(V + 30 + v + 1) >= 0) &&
882 (*(V + 30 + v + 2) >= 0) &&
883 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
884 (*(V + 30 + v + 2) > *(V + 30 + v)) &&
885 ((*(V + 30 + v + 1) > SIGMIN) ||
886 (*(V + 30 + v + 2) > SIGMIN))) {
887 // (case 6)
888 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
889 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
890 *SIG1 = *(V + 30 + v + 1);
891 } else {
892 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
893 *SIG1 = *(V + 30 + v + 2);
894 }
895 } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
896 swp_freq = fOSC * 1000;
897 *SIG1 = *(V + 30 + v);
898 } else swp_freq = -1;
899 } else swp_freq = -1;
900
901 return swp_freq;
902}
903
904static void swp_info_get2(struct mb86a16_state *state,
905 int smrt,
906 int R,
907 int swp_freq,
908 int *afcex_freq,
909 int *fOSC,
910 unsigned char *AFCEX_L,
911 unsigned char *AFCEX_H)
912{
913 int AFCEX ;
914
915 if (R == 0)
916 *fOSC = (swp_freq + 1000) / 2000 * 2;
917 else
918 *fOSC = (swp_freq + 500) / 1000;
919
920 if (*fOSC >= swp_freq)
921 *afcex_freq = *fOSC * 1000 - swp_freq;
922 else
923 *afcex_freq = swp_freq - *fOSC * 1000;
924
925 AFCEX = *afcex_freq * 8192 / state->master_clk;
926 *AFCEX_L = AFCEX & 0x00ff;
927 *AFCEX_H = (AFCEX & 0x0f00) >> 8;
928}
929
930static void afcex_info_get(struct mb86a16_state *state,
931 int afcex_freq,
932 unsigned char *AFCEX_L,
933 unsigned char *AFCEX_H)
934{
935 int AFCEX ;
936
937 AFCEX = afcex_freq * 8192 / state->master_clk;
938 *AFCEX_L = AFCEX & 0x00ff;
939 *AFCEX_H = (AFCEX & 0x0f00) >> 8;
940}
941
942static int SEQ_set(struct mb86a16_state *state, unsigned char loop)
943{
944 // SLOCK0 = 0
945 if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) {
946 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
947 return -EREMOTEIO;
948 }
949
950 return 0;
951}
952
953static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV)
954{
955 // Viterbi Rate, IQ Settings
956 if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) {
957 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
958 return -EREMOTEIO;
959 }
960
961 return 0;
962}
963
964static int FEC_srst(struct mb86a16_state *state)
965{
966 if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) {
967 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
968 return -EREMOTEIO;
969 }
970
971 return 0;
972}
973
974static int S2T_set(struct mb86a16_state *state, unsigned char S2T)
975{
976 if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) {
977 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
978 return -EREMOTEIO;
979 }
980
981 return 0;
982}
983
984static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T)
985{
986 if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) {
987 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
988 return -EREMOTEIO;
989 }
990
991 return 0;
992}
993
994
995static int mb86a16_set_fe(struct mb86a16_state *state)
996{
997 u8 agcval, cnmval;
998
999 int i, j;
1000 int fOSC = 0;
1001 int fOSC_start = 0;
1002 int wait_t;
1003 int fcp;
1004 int swp_ofs;
1005 int V[60];
1006 u8 SIG1MIN;
1007
1008 unsigned char CREN, AFCEN, AFCEXEN;
1009 unsigned char SIG1;
1010 unsigned char TIMINT1, TIMINT2, TIMEXT;
1011 unsigned char S0T, S1T;
1012 unsigned char S2T;
1013// unsigned char S2T, S3T;
1014 unsigned char S4T, S5T;
1015 unsigned char AFCEX_L, AFCEX_H;
1016 unsigned char R;
1017 unsigned char VIRM;
1018 unsigned char ETH, VIA;
1019 unsigned char junk;
1020
1021 int loop;
1022 int ftemp;
1023 int v, vmax, vmin;
1024 int vmax_his, vmin_his;
1025 int swp_freq, prev_swp_freq[20];
1026 int prev_freq_num;
1027 int signal_dupl;
1028 int afcex_freq;
1029 int signal;
1030 int afcerr;
1031 int temp_freq, delta_freq;
1032 int dagcm[4];
1033 int smrt_d;
1034// int freq_err;
1035 int n;
1036 int ret = -1;
1037 int sync;
1038
1039 dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate);
1040
b05c90de 1041 fcp = 3000;
41e840b1
MA		 1042 swp_ofs = state->srate / 4;
1043
1044 for (i = 0; i < 60; i++)
1045 V[i] = -1;
1046
1047 for (i = 0; i < 20; i++)
1048 prev_swp_freq[i] = 0;
1049
1050 SIG1MIN = 25;
1051
1052 for (n = 0; ((n < 3) && (ret == -1)); n++) {
1053 SEQ_set(state, 0);
1054 iq_vt_set(state, 0);
1055
1056 CREN = 0;
1057 AFCEN = 0;
1058 AFCEXEN = 1;
1059 TIMINT1 = 0;
1060 TIMINT2 = 1;
1061 TIMEXT = 2;
1062 S1T = 0;
1063 S0T = 0;
1064
1065 if (initial_set(state) < 0) {
1066 dprintk(verbose, MB86A16_ERROR, 1, "initial set failed");
1067 return -1;
1068 }
1069 if (DAGC_data_set(state, 3, 2) < 0) {
1070 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
1071 return -1;
1072 }
1073 if (EN_set(state, CREN, AFCEN) < 0) {
1074 dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
1075 return -1; // (0, 0)
1076 }
1077 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
1078 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1079 return -1; // (1, smrt) = (1, symbolrate)
1080 }
1081 if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) {
1082 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error");
1083 return -1; // (0, 1, 2)
1084 }
1085 if (S01T_set(state, S1T, S0T) < 0) {
1086 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
1087 return -1; // (0, 0)
1088 }
1089 smrt_info_get(state, state->srate);
1090 if (smrt_set(state, state->srate) < 0) {
1091 dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error");
1092 return -1;
1093 }
1094
1095 R = vco_dev_get(state, state->srate);
1096 if (R == 1)
1097 fOSC_start = state->frequency;
1098
1099 else if (R == 0) {
1100 if (state->frequency % 2 == 0) {
1101 fOSC_start = state->frequency;
1102 } else {
1103 fOSC_start = state->frequency + 1;
1104 if (fOSC_start > 2150)
1105 fOSC_start = state->frequency - 1;
1106 }
1107 }
1108 loop = 1;
1109 ftemp = fOSC_start * 1000;
1110 vmax = 0 ;
1111 while (loop == 1) {
1112 ftemp = ftemp + swp_ofs;
1113 vmax++;
1114
1115 // Upper bound
1116 if (ftemp > 2150000) {
1117 loop = 0;
1118 vmax--;
1119 }
1120 else if ((ftemp == 2150000) || (ftemp - state->frequency * 1000 >= fcp + state->srate / 4))
1121 loop = 0;
1122 }
1123
1124 loop = 1;
1125 ftemp = fOSC_start * 1000;
1126 vmin = 0 ;
1127 while (loop == 1) {
1128 ftemp = ftemp - swp_ofs;
1129 vmin--;
1130
1131 // Lower bound
1132 if (ftemp < 950000) {
1133 loop = 0;
1134 vmin++;
1135 }
1136 else if ((ftemp == 950000) || (state->frequency * 1000 - ftemp >= fcp + state->srate / 4))
1137 loop = 0;
1138 }
1139
1140 wait_t = (8000 + state->srate / 2) / state->srate;
1141 if (wait_t == 0)
1142 wait_t = 1;
1143
1144 i = 0;
1145 j = 0;
1146 prev_freq_num = 0;
1147 loop = 1;
1148 signal = 0;
1149 vmax_his = 0;
1150 vmin_his = 0;
1151 v = 0;
1152
1153 while (loop == 1) {
1154 swp_info_get(state, fOSC_start, state->srate,
1155 v, R, swp_ofs, &fOSC,
1156 &afcex_freq, &AFCEX_L, &AFCEX_H);
1157
a890cce5 1158 udelay(100);
41e840b1
MA		 1159 if (rf_val_set(state, fOSC, state->srate, R) < 0) {
1160 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1161 return -1;
1162 }
a890cce5 1163 udelay(100);
41e840b1
MA		 1164 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1165 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1166 return -1;
1167 }
1168 if (srst(state) < 0) {
1169 dprintk(verbose, MB86A16_ERROR, 1, "srst error");
1170 return -1;
1171 }
1172 msleep_interruptible(wait_t);
1173
1174 if (mb86a16_read(state, 0x37, &SIG1) != 2) {
1175 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1176 return -1;
1177 }
1178 V[30 + v] = SIG1 ;
1179 swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
1180 SIG1MIN, fOSC, afcex_freq,
1181 swp_ofs, &SIG1); //changed
1182
1183 signal_dupl = 0;
1184 for (j = 0; j < prev_freq_num; j++) {
1185 if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) {
1186 signal_dupl = 1;
1187 dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j);
1188 }
1189 }
1190 if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) {
1191 dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate);
1192 prev_swp_freq[prev_freq_num] = swp_freq;
1193 prev_freq_num++;
1194 swp_info_get2(state, state->srate, R, swp_freq,
1195 &afcex_freq, &fOSC,
1196 &AFCEX_L, &AFCEX_H);
1197
1198 if (rf_val_set(state, fOSC, state->srate, R) < 0) {
1199 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1200 return -1;
1201 }
1202 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1203 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1204 return -1;
1205 }
1206 signal = signal_det(state, state->srate, &SIG1);
1207 if (signal == 1) {
1208 dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****");
1209 loop = 0;
1210 } else {
1211 dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again...");
1212 smrt_info_get(state, state->srate);
1213 if (smrt_set(state, state->srate) < 0) {
1214 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1215 return -1;
1216 }
1217 }
1218 }
1219 if (v > vmax)
1220 vmax_his = 1 ;
1221 if (v < vmin)
1222 vmin_his = 1 ;
1223 i++;
1224
1225 if ((i % 2 == 1) && (vmax_his == 1))
1226 i++;
1227 if ((i % 2 == 0) && (vmin_his == 1))
1228 i++;
1229
1230 if (i % 2 == 1)
1231 v = (i + 1) / 2;
1232 else
1233 v = -i / 2;
1234
1235 if ((vmax_his == 1) && (vmin_his == 1))
1236 loop = 0 ;
1237 }
1238
1239 if (signal == 1) {
1240 dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check");
1241 S1T = 7 ;
1242 S0T = 1 ;
1243 CREN = 0 ;
1244 AFCEN = 1 ;
1245 AFCEXEN = 0 ;
1246
1247 if (S01T_set(state, S1T, S0T) < 0) {
1248 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
1249 return -1;
1250 }
1251 smrt_info_get(state, state->srate);
1252 if (smrt_set(state, state->srate) < 0) {
1253 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1254 return -1;
1255 }
1256 if (EN_set(state, CREN, AFCEN) < 0) {
1257 dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
1258 return -1;
1259 }
1260 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
1261 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1262 return -1;
1263 }
1264 afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H);
1265 if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1266 dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error");
1267 return -1;
1268 }
1269 if (srst(state) < 0) {
1270 dprintk(verbose, MB86A16_ERROR, 1, "srst error");
1271 return -1;
1272 }
1273 // delay 4~200
1274 wait_t = 200000 / state->master_clk + 200000 / state->srate;
1275 msleep(wait_t);
1276 afcerr = afcerr_chk(state);
1277 if (afcerr == -1)
1278 return -1;
1279
1280 swp_freq = fOSC * 1000 + afcerr ;
1281 AFCEXEN = 1 ;
1282 if (state->srate >= 1500)
1283 smrt_d = state->srate / 3;
1284 else
1285 smrt_d = state->srate / 2;
1286 smrt_info_get(state, smrt_d);
1287 if (smrt_set(state, smrt_d) < 0) {
1288 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1289 return -1;
1290 }
1291 if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) {
1292 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1293 return -1;
1294 }
1295 R = vco_dev_get(state, smrt_d);
1296 if (DAGC_data_set(state, 2, 0) < 0) {
1297 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
1298 return -1;
1299 }
1300 for (i = 0; i < 3; i++) {
1301 temp_freq = swp_freq + (i - 1) * state->srate / 8;
1302 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1303 if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
1304 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1305 return -1;
1306 }
1307 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1308 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1309 return -1;
1310 }
1311 wait_t = 200000 / state->master_clk + 40000 / smrt_d;
1312 msleep(wait_t);
1313 dagcm[i] = dagcm_val_get(state);
1314 }
1315 if ((dagcm[0] > dagcm[1]) &&
1316 (dagcm[0] > dagcm[2]) &&
1317 (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) {
1318
1319 temp_freq = swp_freq - 2 * state->srate / 8;
1320 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1321 if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
1322 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1323 return -1;
1324 }
1325 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1326 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
1327 return -1;
1328 }
1329 wait_t = 200000 / state->master_clk + 40000 / smrt_d;
1330 msleep(wait_t);
1331 dagcm[3] = dagcm_val_get(state);
1332 if (dagcm[3] > dagcm[1])
1333 delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300;
1334 else
1335 delta_freq = 0;
1336 } else if ((dagcm[2] > dagcm[1]) &&
1337 (dagcm[2] > dagcm[0]) &&
1338 (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) {
1339
1340 temp_freq = swp_freq + 2 * state->srate / 8;
1341 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1342 if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
1343 dprintk(verbose, MB86A16_ERROR, 1, "rf val set");
1344 return -1;
1345 }
1346 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1347 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
1348 return -1;
1349 }
1350 wait_t = 200000 / state->master_clk + 40000 / smrt_d;
1351 msleep(wait_t);
1352 dagcm[3] = dagcm_val_get(state);
1353 if (dagcm[3] > dagcm[1])
1354 delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300;
1355 else
1356 delta_freq = 0 ;
1357
1358 } else {
1359 delta_freq = 0 ;
1360 }
1361 dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq);
1362 swp_freq += delta_freq;
1363 dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq);
1364 if (ABS(state->frequency * 1000 - swp_freq) > 3800) {
1365 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !");
1366 } else {
1367
1368 S1T = 0;
1369 S0T = 3;
1370 CREN = 1;
1371 AFCEN = 0;
1372 AFCEXEN = 1;
1373
1374 if (S01T_set(state, S1T, S0T) < 0) {
1375 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
1376 return -1;
1377 }
1378 if (DAGC_data_set(state, 0, 0) < 0) {
1379 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
1380 return -1;
1381 }
1382 R = vco_dev_get(state, state->srate);
1383 smrt_info_get(state, state->srate);
1384 if (smrt_set(state, state->srate) < 0) {
1385 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1386 return -1;
1387 }
1388 if (EN_set(state, CREN, AFCEN) < 0) {
1389 dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
1390 return -1;
1391 }
1392 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
1393 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1394 return -1;
1395 }
1396 swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1397 if (rf_val_set(state, fOSC, state->srate, R) < 0) {
1398 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1399 return -1;
1400 }
1401 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1402 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1403 return -1;
1404 }
1405 if (srst(state) < 0) {
1406 dprintk(verbose, MB86A16_ERROR, 1, "srst error");
1407 return -1;
1408 }
1409 wait_t = 7 + (10000 + state->srate / 2) / state->srate;
1410 if (wait_t == 0)
1411 wait_t = 1;
1412 msleep_interruptible(wait_t);
1413 if (mb86a16_read(state, 0x37, &SIG1) != 2) {
1414 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1415 return -EREMOTEIO;
1416 }
1417
1418 if (SIG1 > 110) {
1419 S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6;
1420 wait_t = 7 + (917504 + state->srate / 2) / state->srate;
1421 } else if (SIG1 > 105) {
1422 S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1423 wait_t = 7 + (1048576 + state->srate / 2) / state->srate;
1424 } else if (SIG1 > 85) {
1425 S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1426 wait_t = 7 + (1310720 + state->srate / 2) / state->srate;
1427 } else if (SIG1 > 65) {
1428 S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1429 wait_t = 7 + (1572864 + state->srate / 2) / state->srate;
1430 } else {
1431 S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1432 wait_t = 7 + (2097152 + state->srate / 2) / state->srate;
1433 }
e15c7ccd 1434 wait_t *= 2; /* FOS */
41e840b1
MA		 1435 S2T_set(state, S2T);
1436 S45T_set(state, S4T, S5T);
1437 Vi_set(state, ETH, VIA);
1438 srst(state);
1439 msleep_interruptible(wait_t);
1440 sync = sync_chk(state, &VIRM);
1441 dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync);
1442 if (mb86a16_read(state, 0x0d, &state->signal) != 2) {
1443 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1444 return -EREMOTEIO;
1445 }
1446 if (VIRM) {
1447 if (VIRM == 4) { // 5/6
1448 if (SIG1 > 110)
1449 wait_t = ( 786432 + state->srate / 2) / state->srate;
1450 else
1451 wait_t = (1572864 + state->srate / 2) / state->srate;
1452 if (state->srate < 5000)
1453 // FIXME ! , should be a long wait !
1454 msleep_interruptible(wait_t);
1455 else
1456 msleep_interruptible(wait_t);
1457
1458 if (sync_chk(state, &junk) == 0) {
1459 iq_vt_set(state, 1);
1460 FEC_srst(state);
1461 }
1462 if (SIG1 > 110)
1463 wait_t = ( 786432 + state->srate / 2) / state->srate;
1464 else
1465 wait_t = (1572864 + state->srate / 2) / state->srate;
1466
1467 msleep_interruptible(wait_t);
1468 SEQ_set(state, 1);
1469 } else { // 1/2, 2/3, 3/4, 7/8
1470 if (SIG1 > 110)
1471 wait_t = ( 786432 + state->srate / 2) / state->srate;
1472 else
1473 wait_t = (1572864 + state->srate / 2) / state->srate;
1474
1475 msleep_interruptible(wait_t);
1476 SEQ_set(state, 1);
1477 }
1478 } else {
776c3ebe 1479 dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC");
41e840b1
MA		 1480 SEQ_set(state, 1);
1481 }
1482 }
1483 } else {
1484 dprintk (verbose, MB86A16_INFO, 1, "NO -- SIGNAL");
1485 }
1486
1487 sync = sync_chk(state, &junk);
1488 if (sync) {
1489 dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******");
1490 freqerr_chk(state, state->frequency, state->srate, 1);
071e3060 1491 break;
41e840b1
MA		 1492 }
1493 }
1494
1495 mb86a16_read(state, 0x15, &agcval);
1496 mb86a16_read(state, 0x26, &cnmval);
1497 dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval);
1498
1499 return ret;
1500}
1501
1502static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe,
1503 struct dvb_diseqc_master_cmd *cmd)
1504{
1505 struct mb86a16_state *state = fe->demodulator_priv;
1506 int i;
1507 u8 regs;
1508
1509 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
1510 goto err;
1511 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
1512 goto err;
1513 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
1514 goto err;
1515
1516 regs = 0x18;
1517
1518 if (cmd->msg_len > 5 || cmd->msg_len < 4)
1519 return -EINVAL;
1520
1521 for (i = 0; i < cmd->msg_len; i++) {
1522 if (mb86a16_write(state, regs, cmd->msg[i]) < 0)
1523 goto err;
1524
1525 regs++;
1526 }
1527 i += 0x90;
1528
1529 msleep_interruptible(10);
1530
1531 if (mb86a16_write(state, MB86A16_DCC1, i) < 0)
1532 goto err;
1533 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1534 goto err;
1535
1536 return 0;
1537
1538err:
1539 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1540 return -EREMOTEIO;
1541}
1542
1543static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
1544{
1545 struct mb86a16_state *state = fe->demodulator_priv;
1546
1547 switch (burst) {
1548 case SEC_MINI_A:
1549 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
1550 MB86A16_DCC1_TBEN |
1551 MB86A16_DCC1_TBO) < 0)
1552 goto err;
1553 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1554 goto err;
1555 break;
1556 case SEC_MINI_B:
1557 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
1558 MB86A16_DCC1_TBEN) < 0)
1559 goto err;
1560 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1561 goto err;
1562 break;
1563 }
1564
1565 return 0;
1566err:
1567 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1568 return -EREMOTEIO;
1569}
1570
1571static int mb86a16_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
1572{
1573 struct mb86a16_state *state = fe->demodulator_priv;
1574
1575 switch (tone) {
1576 case SEC_TONE_ON:
1577 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0)
1578 goto err;
1579 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
1580 MB86A16_DCC1_CTOE) < 0)
1581
1582 goto err;
1583 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1584 goto err;
1585 break;
1586 case SEC_TONE_OFF:
1587 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
1588 goto err;
1589 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
1590 goto err;
1591 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
1592 goto err;
1593 break;
1594 default:
1595 return -EINVAL;
1596 }
1597 return 0;
1598
1599err:
1600 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1601 return -EREMOTEIO;
1602}
1603
1604#define MB86A16_FE_ALGO 1
1605
1606static int mb86a16_frontend_algo(struct dvb_frontend *fe)
1607{
1608 return MB86A16_FE_ALGO;
1609}
1610
1611static int mb86a16_set_frontend(struct dvb_frontend *fe,
1612 struct dvb_frontend_parameters *p,
1613 unsigned int mode_flags,
1614 int *delay,
1615 fe_status_t *status)
1616{
1617 int ret = 0;
1618 struct mb86a16_state *state = fe->demodulator_priv;
1619
1620 if (p != NULL) {
1621 state->frequency = p->frequency / 1000;
1622 state->srate = p->u.qpsk.symbol_rate / 1000;
1623 ret = mb86a16_set_fe(state);
1624 }
1625 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
1626 mb86a16_read_status(fe, status);
1627
1628 *delay = HZ/3000;
1629
1630 return ret;
1631}
1632
1633static void mb86a16_release(struct dvb_frontend *fe)
1634{
1635 struct mb86a16_state *state = fe->demodulator_priv;
1636 kfree(state);
1637}
1638
1639static int mb86a16_init(struct dvb_frontend *fe)
1640{
1641 return 0;
1642}
1643
1644static int mb86a16_sleep(struct dvb_frontend *fe)
1645{
1646 return 0;
1647}
1648
1649static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber)
1650{
1651 return 0;
1652}
1653
1654static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
1655{
1656 *strength = 0;
1657
1658 return 0;
1659}
1660
1661struct cnr {
1662 u8 cn_reg;
1663 u8 cn_val;
1664};
1665
1666static const struct cnr cnr_tab[] = {
1667 { 35, 2 },
1668 { 40, 3 },
1669 { 50, 4 },
1670 { 60, 5 },
1671 { 70, 6 },
1672 { 80, 7 },
1673 { 92, 8 },
1674 { 103, 9 },
1675 { 115, 10 },
1676 { 138, 12 },
1677 { 162, 15 },
1678 { 180, 18 },
1679 { 185, 19 },
1680 { 189, 20 },
1681 { 195, 22 },
1682 { 199, 24 },
1683 { 201, 25 },
1684 { 202, 26 },
1685 { 203, 27 },
1686 { 205, 28 },
1687 { 208, 30 }
1688};
1689
1690static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr)
1691{
1692 struct mb86a16_state *state = fe->demodulator_priv;
1693 int i = 0;
1694 int low_tide = 2, high_tide = 30, q_level;
1695 u8 cn;
1696
1fa1f107 1697 *snr = 0;
41e840b1
MA		 1698 if (mb86a16_read(state, 0x26, &cn) != 2) {
1699 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1700 return -EREMOTEIO;
1701 }
1702
1703 for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) {
1704 if (cn < cnr_tab[i].cn_reg) {
1705 *snr = cnr_tab[i].cn_val;
1706 break;
1707 }
1708 }
1709 q_level = (*snr * 100) / (high_tide - low_tide);
1710 dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level);
1711
1712 return 0;
1713}
1714
1715static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1716{
1717 return 0;
1718}
1719
1720static struct dvb_frontend_ops mb86a16_ops = {
1721 .info = {
1722 .name = "Fujitsu MB86A16 DVB-S",
1723 .type = FE_QPSK,
1724 .frequency_min = 950000,
1725 .frequency_max = 2150000,
1726 .frequency_stepsize = 125,
1727 .frequency_tolerance = 0,
1728 .symbol_rate_min = 1000000,
1729 .symbol_rate_max = 45000000,
1730 .symbol_rate_tolerance = 500,
1731 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1732 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
1733 FE_CAN_FEC_7_8 | FE_CAN_QPSK |
1734 FE_CAN_FEC_AUTO
1735 },
1736 .release = mb86a16_release,
1737 .tune = mb86a16_set_frontend,
1738 .read_status = mb86a16_read_status,
1739 .get_frontend_algo = mb86a16_frontend_algo,
1740 .init = mb86a16_init,
1741 .sleep = mb86a16_sleep,
1742 .read_status = mb86a16_read_status,
1743
1744 .read_ber = mb86a16_read_ber,
1745 .read_signal_strength = mb86a16_read_signal_strength,
1746 .read_snr = mb86a16_read_snr,
1747 .read_ucblocks = mb86a16_read_ucblocks,
1748
1749 .diseqc_send_master_cmd = mb86a16_send_diseqc_msg,
1750 .diseqc_send_burst = mb86a16_send_diseqc_burst,
1751 .set_tone = mb86a16_set_tone,
1752};
1753
1754struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
1755 struct i2c_adapter *i2c_adap)
1756{
1757 u8 dev_id = 0;
1758 struct mb86a16_state *state = NULL;
1759
1760 state = kmalloc(sizeof (struct mb86a16_state), GFP_KERNEL);
1761 if (state == NULL)
1762 goto error;
1763
1764 state->config = config;
1765 state->i2c_adap = i2c_adap;
1766
1767 mb86a16_read(state, 0x7f, &dev_id);
1768 if (dev_id != 0xfe)
1769 goto error;
1770
1771 memcpy(&state->frontend.ops, &mb86a16_ops, sizeof (struct dvb_frontend_ops));
1772 state->frontend.demodulator_priv = state;
1773 state->frontend.ops.set_voltage = state->config->set_voltage;
1774
1775 return &state->frontend;
1776error:
1777 kfree(state);
1778 return NULL;
1779}
1780EXPORT_SYMBOL(mb86a16_attach);
1781MODULE_LICENSE("GPL");
1782MODULE_AUTHOR("Manu Abraham");
Linux kernel - Deliverables
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