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V4L/DVB (13699): [Mantis, MB86A16] Initial checkin: Mantis, MB86A16
[deliverable/linux.git] / drivers / media / dvb / frontends / mb86a16.c
CommitLineData
41e840b1
MA		 1/*
2 Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
3
4 Copyright (C) 2005, 2006 Manu Abraham (abraham.manu@gmail.com)
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19*/
20
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25
26#include "dvb_frontend.h"
27#include "mb86a16.h"
28#include "mb86a16_priv.h"
29
30unsigned int verbose = 5;
31module_param(verbose, int, 0644);
32
33#define ABS(x) ((x) < 0 ? (-x) : (x))
34
35struct mb86a16_state {
36 struct i2c_adapter *i2c_adap;
37 const struct mb86a16_config *config;
38 struct dvb_frontend frontend;
39 u8 signal;
40
41 // tuning parameters
42 int frequency;
43 int srate;
44
45 // Internal stuff
46 int master_clk;
47 int deci;
48 int csel;
49 int rsel;
50};
51
52#define MB86A16_ERROR 0
53#define MB86A16_NOTICE 1
54#define MB86A16_INFO 2
55#define MB86A16_DEBUG 3
56
57#define dprintk(x, y, z, format, arg...) do { \
58 if (z) { \
59 if ((x > MB86A16_ERROR) && (x > y)) \
60 printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \
61 else if ((x > MB86A16_NOTICE) && (x > y)) \
62 printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \
63 else if ((x > MB86A16_INFO) && (x > y)) \
64 printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \
65 else if ((x > MB86A16_DEBUG) && (x > y)) \
66 printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \
67 } else { \
68 if (x > y) \
69 printk(format, ##arg); \
70 } \
71} while (0)
72
73#define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
74#define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
75
76static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val)
77{
78 int ret;
79 u8 buf[] = { reg, val };
80
81 struct i2c_msg msg = {
82 .addr = state->config->demod_address,
83 .flags = 0,
84 .buf = buf,
85 .len = 2
86 };
87
88 dprintk(verbose, MB86A16_DEBUG, 1,
89 "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]",
90 state->config->demod_address, buf[0], buf[1]);
91
92 ret = i2c_transfer(state->i2c_adap, &msg, 1);
93
94 return (ret != 1) ? -EREMOTEIO : 0;
95}
96
97static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val)
98{
99 int ret;
100 u8 b0[] = { reg };
101 u8 b1[] = { 0 };
102
103 struct i2c_msg msg[] = {
104 {
105 .addr = state->config->demod_address,
106 .flags = 0,
107 .buf = b0,
108 .len = 1
109 },{
110 .addr = state->config->demod_address,
111 .flags = I2C_M_RD,
112 .buf = b1,
113 .len = 1
114 }
115 };
116 ret = i2c_transfer(state->i2c_adap, msg, 2);
117 if (ret != 2) {
118 dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=0x%i)",
119 reg, ret);
120
121 return -EREMOTEIO;
122 }
123 *val = b1[0];
124
125 return ret;
126}
127
128static int CNTM_set(struct mb86a16_state *state,
129 unsigned char timint1,
130 unsigned char timint2,
131 unsigned char cnext)
132{
133 unsigned char val;
134
135 val = (timint1 << 4) | (timint2 << 2) | cnext;
136 if (mb86a16_write(state, MB86A16_CNTMR, val) < 0)
137 goto err;
138
139 return 0;
140
141err:
142 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
143 return -EREMOTEIO;
144}
145
146static int smrt_set(struct mb86a16_state *state, int rate)
147{
148 int tmp ;
149 int m ;
150 unsigned char STOFS0, STOFS1;
151
152 m = 1 << state->deci;
153 tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk;
154
155 STOFS0 = tmp & 0x0ff;
156 STOFS1 = (tmp & 0xf00) >> 8;
157
158 if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) |
159 (state->csel << 1) |
160 state->rsel) < 0)
161 goto err;
162 if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0)
163 goto err;
164 if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0)
165 goto err;
166
167 return 0;
168err:
169 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
170 return -1;
171}
172
173static int srst(struct mb86a16_state *state)
174{
175 if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0)
176 goto err;
177
178 return 0;
179err:
180 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
181 return -EREMOTEIO;
182
183}
184
185static int afcex_data_set(struct mb86a16_state *state,
186 unsigned char AFCEX_L,
187 unsigned char AFCEX_H)
188{
189 if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0)
190 goto err;
191 if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0)
192 goto err;
193
194 return 0;
195err:
196 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
197
198 return -1;
199}
200
201static int afcofs_data_set(struct mb86a16_state *state,
202 unsigned char AFCEX_L,
203 unsigned char AFCEX_H)
204{
205 if (mb86a16_write(state, 0x58, AFCEX_L) < 0)
206 goto err;
207 if (mb86a16_write(state, 0x59, AFCEX_H) < 0)
208 goto err;
209
210 return 0;
211err:
212 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
213 return -EREMOTEIO;
214}
215
216static int stlp_set(struct mb86a16_state *state,
217 unsigned char STRAS,
218 unsigned char STRBS)
219{
220 if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0)
221 goto err;
222
223 return 0;
224err:
225 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
226 return -EREMOTEIO;
227}
228
229static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA)
230{
231 if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0)
232 goto err;
233 if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0)
234 goto err;
235
236 return 0;
237err:
238 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
239 return -EREMOTEIO;
240}
241
242static int initial_set(struct mb86a16_state *state)
243{
244 if (stlp_set(state, 5, 7))
245 goto err;
246 if (afcex_data_set(state, 0, 0))
247 goto err;
248 if (afcofs_data_set(state, 0, 0))
249 goto err;
250
251 if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0)
252 goto err;
253 if (mb86a16_write(state, 0x2f, 0x21) < 0)
254 goto err;
255 if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0)
256 goto err;
257 if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0)
258 goto err;
259 if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0)
260 goto err;
261 if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0)
262 goto err;
263 if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0)
264 goto err;
265 if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0)
266 goto err;
267 if (mb86a16_write(state, 0x54, 0xff) < 0)
268 goto err;
269 if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0)
270 goto err;
271
272 return 0;
273
274err:
275 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
276 return -EREMOTEIO;
277}
278
279static int S01T_set(struct mb86a16_state *state,
280 unsigned char s1t,
281 unsigned s0t)
282{
283 if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0)
284 goto err;
285
286 return 0;
287err:
288 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
289 return -EREMOTEIO;
290}
291
292
293static int EN_set(struct mb86a16_state *state,
294 int cren,
295 int afcen)
296{
297 unsigned char val;
298
299 val = 0x7a | (cren << 7) | (afcen << 2);
300 if (mb86a16_write(state, 0x49, val) < 0)
301 goto err;
302
303 return 0;
304err:
305 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
306 return -EREMOTEIO;
307}
308
309static int AFCEXEN_set(struct mb86a16_state *state,
310 int afcexen,
311 int smrt)
312{
313 unsigned char AFCA ;
314
315 if (smrt > 18875)
316 AFCA = 4;
317 else if (smrt > 9375)
318 AFCA = 3;
319 else if (smrt > 2250)
320 AFCA = 2;
321 else
322 AFCA = 1;
323
324 if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0)
325 goto err;
326
327 return 0;
328
329err:
330 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
331 return -EREMOTEIO;
332}
333
334static int DAGC_data_set(struct mb86a16_state *state,
335 unsigned char DAGCA,
336 unsigned char DAGCW)
337{
338 if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0)
339 goto err;
340
341 return 0;
342
343err:
344 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
345 return -EREMOTEIO;
346}
347
348static void smrt_info_get(struct mb86a16_state *state, int rate)
349{
350 if (rate >= 37501) {
351 state->deci = 0; state->csel = 0; state->rsel = 0;
352 } else if (rate >= 30001) {
353 state->deci = 0; state->csel = 0; state->rsel = 1;
354 } else if (rate >= 26251) {
355 state->deci = 0; state->csel = 1; state->rsel = 0;
356 } else if (rate >= 22501) {
357 state->deci = 0; state->csel = 1; state->rsel = 1;
358 } else if (rate >= 18751) {
359 state->deci = 1; state->csel = 0; state->rsel = 0;
360 } else if (rate >= 15001) {
361 state->deci = 1; state->csel = 0; state->rsel = 1;
362 } else if (rate >= 13126) {
363 state->deci = 1; state->csel = 1; state->rsel = 0;
364 } else if (rate >= 11251) {
365 state->deci = 1; state->csel = 1; state->rsel = 1;
366 } else if (rate >= 9376) {
367 state->deci = 2; state->csel = 0; state->rsel = 0;
368 } else if (rate >= 7501) {
369 state->deci = 2; state->csel = 0; state->rsel = 1;
370 } else if (rate >= 6563) {
371 state->deci = 2; state->csel = 1; state->rsel = 0;
372 } else if (rate >= 5626) {
373 state->deci = 2; state->csel = 1; state->rsel = 1;
374 } else if (rate >= 4688) {
375 state->deci = 3; state->csel = 0; state->rsel = 0;
376 } else if (rate >= 3751) {
377 state->deci = 3; state->csel = 0; state->rsel = 1;
378 } else if (rate >= 3282) {
379 state->deci = 3; state->csel = 1; state->rsel = 0;
380 } else if (rate >= 2814) {
381 state->deci = 3; state->csel = 1; state->rsel = 1;
382 } else if (rate >= 2344) {
383 state->deci = 4; state->csel = 0; state->rsel = 0;
384 } else if (rate >= 1876) {
385 state->deci = 4; state->csel = 0; state->rsel = 1;
386 } else if (rate >= 1641) {
387 state->deci = 4; state->csel = 1; state->rsel = 0;
388 } else if (rate >= 1407) {
389 state->deci = 4; state->csel = 1; state->rsel = 1;
390 } else if (rate >= 1172) {
391 state->deci = 5; state->csel = 0; state->rsel = 0;
392 } else if (rate >= 939) {
393 state->deci = 5; state->csel = 0; state->rsel = 1;
394 } else if (rate >= 821) {
395 state->deci = 5; state->csel = 1; state->rsel = 0;
396 } else {
397 state->deci = 5; state->csel = 1; state->rsel = 1;
398 }
399
400 if (state->csel == 0)
401 state->master_clk = 92000;
402 else
403 state->master_clk = 61333;
404
405}
406
407static int signal_det(struct mb86a16_state *state,
408 int smrt,
409 unsigned char *SIG)
410{
411
412 int ret ;
413 int smrtd ;
414 int wait_sym ;
415 int wait_t ;
416 unsigned char S[3] ;
417 int i ;
418
419 if (*SIG > 45) {
420 if (CNTM_set(state, 2, 1, 2) < 0) {
421 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
422 return -1;
423 }
424 wait_sym = 40000;
425 } else {
426 if (CNTM_set(state, 3, 1, 2) < 0) {
427 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
428 return -1;
429 }
430 wait_sym = 80000;
431 }
432 for (i = 0; i < 3; i++) {
433 if (i == 0 )
434 smrtd = smrt * 98 / 100;
435 else if (i == 1)
436 smrtd = smrt;
437 else
438 smrtd = smrt * 102 / 100;
439 smrt_info_get(state, smrtd);
440 smrt_set(state, smrtd);
441 srst(state);
442 wait_t = (wait_sym + 99 * smrtd / 100) / smrtd;
443 if (wait_t == 0)
444 wait_t = 1;
445 msleep_interruptible(10);
446 if (mb86a16_read(state, 0x37, &(S[i])) != 2) {
447 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
448 return -EREMOTEIO;
449 }
450 }
451 if ((S[1] > S[0] * 112 / 100) &&
452 (S[1] > S[2] * 112 / 100)) {
453
454 ret = 1;
455 } else {
456 ret = 0;
457 }
458 *SIG = S[1];
459
460 if (CNTM_set(state, 0, 1, 2) < 0) {
461 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
462 return -1;
463 }
464
465 return ret;
466}
467
468static int rf_val_set(struct mb86a16_state *state,
469 int f,
470 int smrt,
471 unsigned char R)
472{
473 unsigned char C, F, B;
474 int M;
475 unsigned char rf_val[5];
476 int ack = -1;
477
478 if (smrt > 37750 )
479 C = 1;
480 else if (smrt > 18875)
481 C = 2;
482 else if (smrt > 5500 )
483 C = 3;
484 else
485 C = 4;
486
487 if (smrt > 30500)
488 F = 3;
489 else if (smrt > 9375)
490 F = 1;
491 else if (smrt > 4625)
492 F = 0;
493 else
494 F = 2;
495
496 if (f < 1060)
497 B = 0;
498 else if (f < 1175)
499 B = 1;
500 else if (f < 1305)
501 B = 2;
502 else if (f < 1435)
503 B = 3;
504 else if (f < 1570)
505 B = 4;
506 else if (f < 1715)
507 B = 5;
508 else if (f < 1845)
509 B = 6;
510 else if (f < 1980)
511 B = 7;
512 else if (f < 2080)
513 B = 8;
514 else
515 B = 9;
516
517 M = f * (1 << R) / 2;
518
519 rf_val[0] = 0x01 | (C << 3) | (F << 1);
520 rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
521 rf_val[2] = (M & 0x00ff0) >> 4;
522 rf_val[3] = ((M & 0x0000f) << 4) | B;
523
524 // Frequency Set
525 if (mb86a16_write(state, 0x21, rf_val[0]) < 0)
526 ack = 0;
527 if (mb86a16_write(state, 0x22, rf_val[1]) < 0)
528 ack = 0;
529 if (mb86a16_write(state, 0x23, rf_val[2]) < 0)
530 ack = 0;
531 if (mb86a16_write(state, 0x24, rf_val[3]) < 0)
532 ack = 0;
533 if (mb86a16_write(state, 0x25, 0x01) < 0)
534 ack = 0;
535 if (ack == 0) {
536 dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error");
537 return -EREMOTEIO;
538 }
539
540 return 0;
541}
542
543static int afcerr_chk(struct mb86a16_state *state)
544{
545 unsigned char AFCM_L, AFCM_H ;
546 int AFCM ;
547 int afcm, afcerr ;
548
549 if (mb86a16_read(state, 0x0e, &AFCM_L) != 2)
550 goto err;
551 if (mb86a16_read(state, 0x0f, &AFCM_H) != 2)
552 goto err;
553
554 AFCM = (AFCM_H << 8) + AFCM_L;
555
556 if (AFCM > 2048)
557 afcm = AFCM - 4096;
558 else
559 afcm = AFCM;
560 afcerr = afcm * state->master_clk / 8192;
561
562 return afcerr;
563
564err:
565 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
566 return -EREMOTEIO;
567}
568
569static int dagcm_val_get(struct mb86a16_state *state)
570{
571 int DAGCM;
572 unsigned char DAGCM_H, DAGCM_L;
573
574 if (mb86a16_read(state, 0x45, &DAGCM_L) != 2)
575 goto err;
576 if (mb86a16_read(state, 0x46, &DAGCM_H) != 2)
577 goto err;
578
579 DAGCM = (DAGCM_H << 8) + DAGCM_L;
580
581 return DAGCM;
582
583err:
584 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
585 return -EREMOTEIO;
586}
587
588static int mb86a16_read_status(struct dvb_frontend *fe, fe_status_t *status)
589{
590 struct mb86a16_state *state = fe->demodulator_priv;
591
592 if (state->signal & 0x02)
593 *status |= FE_HAS_VITERBI;
594 if (state->signal & 0x01)
595 *status |= FE_HAS_SYNC;
596 if (state->signal & 0x03)
597 *status |= FE_HAS_LOCK;
598
599 return 0;
600}
601
602static int sync_chk(struct mb86a16_state *state,
603 unsigned char *VIRM)
604{
605 unsigned char val;
606 int sync;
607
608 if (mb86a16_read(state, 0x0d, &val) != 2)
609 goto err;
610
611 dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val);
612 sync = val & 0x01;
613 *VIRM = (val & 0x1c) >> 2;
614
615 return sync;
616err:
617 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
618 return -EREMOTEIO;
619
620}
621
622static int freqerr_chk(struct mb86a16_state *state,
623 int fTP,
624 int smrt,
625 int unit)
626{
627 unsigned char CRM, AFCML, AFCMH;
628 unsigned char temp1, temp2, temp3;
629 int crm, afcm, AFCM;
630 int crrerr, afcerr; // [kHz]
631 int frqerr; // [MHz]
632 int afcen, afcexen = 0;
633 int R, M, fOSC, fOSC_OFS;
634
635 if (mb86a16_read(state, 0x43, &CRM) != 2)
636 goto err;
637
638 if (CRM > 127)
639 crm = CRM - 256;
640 else
641 crm = CRM;
642
643 crrerr = smrt * crm / 256;
644 if (mb86a16_read(state, 0x49, &temp1) != 2)
645 goto err;
646
647 afcen = (temp1 & 0x04) >> 2;
648 if (afcen == 0) {
649 if (mb86a16_read(state, 0x2a, &temp1) != 2)
650 goto err;
651 afcexen = (temp1 & 0x20) >> 5;
652 }
653
654 if (afcen == 1) {
655 if (mb86a16_read(state, 0x0e, &AFCML) != 2)
656 goto err;
657 if (mb86a16_read(state, 0x0f, &AFCMH) != 2)
658 goto err;
659 } else if (afcexen == 1) {
660 if (mb86a16_read(state, 0x2b, &AFCML) != 2)
661 goto err;
662 if (mb86a16_read(state, 0x2c, &AFCMH) != 2)
663 goto err;
664 }
665 if ((afcen == 1) || (afcexen == 1)) {
666 smrt_info_get(state, smrt);
667 AFCM = ((AFCMH & 0x01) << 8) + AFCML;
668 if (AFCM > 255)
669 afcm = AFCM - 512;
670 else
671 afcm = AFCM;
672
673 afcerr = afcm * state->master_clk / 8192;
674 } else
675 afcerr = 0;
676
677 if (mb86a16_read(state, 0x22, &temp1) != 2)
678 goto err;
679 if (mb86a16_read(state, 0x23, &temp2) != 2)
680 goto err;
681 if (mb86a16_read(state, 0x24, &temp3) != 2)
682 goto err;
683
684 R = (temp1 & 0xe0) >> 5;
685 M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
686 if (R == 0)
687 fOSC = 2 * M;
688 else
689 fOSC = M;
690
691 fOSC_OFS = fOSC - fTP;
692
693 if (unit == 0) { //[MHz]
694 if (crrerr + afcerr + fOSC_OFS * 1000 >= 0)
695 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000;
696 else
697 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000;
698 } else { //[kHz]
699 frqerr = crrerr + afcerr + fOSC_OFS * 1000;
700 }
701
702 return frqerr;
703err:
704 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
705 return -EREMOTEIO;
706}
707
708static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt)
709{
710 unsigned char R;
711
712 if (smrt > 9375)
713 R = 0;
714 else
715 R = 1;
716
717 return R;
718}
719
720static void swp_info_get(struct mb86a16_state *state,
721 int fOSC_start,
722 int smrt,
723 int v, int R,
724 int swp_ofs,
725 int *fOSC,
726 int *afcex_freq,
727 unsigned char *AFCEX_L,
728 unsigned char *AFCEX_H)
729{
730 int AFCEX ;
731 int crnt_swp_freq ;
732
733 crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
734
735 if (R == 0 )
736 *fOSC = (crnt_swp_freq + 1000) / 2000 * 2;
737 else
738 *fOSC = (crnt_swp_freq + 500) / 1000;
739
740 if (*fOSC >= crnt_swp_freq)
741 *afcex_freq = *fOSC *1000 - crnt_swp_freq;
742 else
743 *afcex_freq = crnt_swp_freq - *fOSC * 1000;
744
745 AFCEX = *afcex_freq * 8192 / state->master_clk;
746 *AFCEX_L = AFCEX & 0x00ff;
747 *AFCEX_H = (AFCEX & 0x0f00) >> 8;
748}
749
750
751static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin,
752 int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1)
753{
754 int swp_freq ;
755
756 if ((i % 2 == 1) && (v <= vmax)) {
757 // positive v (case 1)
758 if ((v - 1 == vmin) &&
759 (*(V + 30 + v) >= 0) &&
760 (*(V + 30 + v - 1) >= 0) &&
761 (*(V + 30 + v - 1) > *(V + 30 + v)) &&
762 (*(V + 30 + v - 1) > SIGMIN)) {
763
764 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
765 *SIG1 = *(V + 30 + v - 1);
766 } else if ((v == vmax) &&
767 (*(V + 30 + v) >= 0) &&
768 (*(V + 30 + v - 1) >= 0) &&
769 (*(V + 30 + v) > *(V + 30 + v - 1)) &&
770 (*(V + 30 + v) > SIGMIN)) {
771 // (case 2)
772 swp_freq = fOSC * 1000 + afcex_freq;
773 *SIG1 = *(V + 30 + v);
774 } else if ((*(V + 30 + v) > 0) &&
775 (*(V + 30 + v - 1) > 0) &&
776 (*(V + 30 + v - 2) > 0) &&
777 (*(V + 30 + v - 3) > 0) &&
778 (*(V + 30 + v - 1) > *(V + 30 + v)) &&
779 (*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
780 ((*(V + 30 + v - 1) > SIGMIN) ||
781 (*(V + 30 + v - 2) > SIGMIN))) {
782 // (case 3)
783 if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
784 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
785 *SIG1 = *(V + 30 + v - 1);
786 } else {
787 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2;
788 *SIG1 = *(V + 30 + v - 2);
789 }
790 } else if ((v == vmax) &&
791 (*(V + 30 + v) >= 0) &&
792 (*(V + 30 + v - 1) >= 0) &&
793 (*(V + 30 + v - 2) >= 0) &&
794 (*(V + 30 + v) > *(V + 30 + v - 2)) &&
795 (*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
796 ((*(V + 30 + v) > SIGMIN) ||
797 (*(V + 30 + v - 1) > SIGMIN))) {
798 // (case 4)
799 if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
800 swp_freq = fOSC * 1000 + afcex_freq;
801 *SIG1 = *(V + 30 + v);
802 } else {
803 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
804 *SIG1 = *(V + 30 + v - 1);
805 }
806 } else {
807 swp_freq = -1 ;
808 }
809 } else if ((i % 2 == 0) && (v >= vmin)) {
810 // Negative v (case 1)
811 if ((*(V + 30 + v) > 0) &&
812 (*(V + 30 + v + 1) > 0) &&
813 (*(V + 30 + v + 2) > 0) &&
814 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
815 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
816 (*(V + 30 + v + 1) > SIGMIN)) {
817
818 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
819 *SIG1 = *(V + 30 + v + 1);
820 } else if ((v + 1 == vmax) &&
821 (*(V + 30 + v) >= 0) &&
822 (*(V + 30 + v + 1) >= 0) &&
823 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
824 (*(V + 30 + v + 1) > SIGMIN)) {
825 // (case 2)
826 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
827 *SIG1 = *(V + 30 + v);
828 } else if ((v == vmin) &&
829 (*(V + 30 + v) > 0) &&
830 (*(V + 30 + v + 1) > 0) &&
831 (*(V + 30 + v + 2) > 0) &&
832 (*(V + 30 + v) > *(V + 30 + v + 1)) &&
833 (*(V + 30 + v) > *(V + 30 + v + 2)) &&
834 (*(V + 30 + v) > SIGMIN)) {
835 // (case 3)
836 swp_freq = fOSC * 1000 + afcex_freq;
837 *SIG1 = *(V + 30 + v);
838 } else if ((*(V + 30 + v) >= 0) &&
839 (*(V + 30 + v + 1) >= 0) &&
840 (*(V + 30 + v + 2) >= 0) &&
841 (*(V +30 + v + 3) >= 0) &&
842 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
843 (*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
844 ((*(V + 30 + v + 1) > SIGMIN) ||
845 (*(V + 30 + v + 2) > SIGMIN))) {
846 // (case 4)
847 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
848 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
849 *SIG1 = *(V + 30 + v + 1);
850 } else {
851 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
852 *SIG1 = *(V + 30 + v + 2);
853 }
854 } else if ((*(V + 30 + v) >= 0) &&
855 (*(V + 30 + v + 1) >= 0) &&
856 (*(V + 30 + v + 2) >= 0) &&
857 (*(V + 30 + v + 3) >= 0) &&
858 (*(V + 30 + v) > *(V + 30 + v + 2)) &&
859 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
860 (*(V + 30 + v) > *(V + 30 + v + 3)) &&
861 (*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
862 ((*(V + 30 + v) > SIGMIN) ||
863 (*(V + 30 + v + 1) > SIGMIN))) {
864 // (case 5)
865 if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
866 swp_freq = fOSC * 1000 + afcex_freq;
867 *SIG1 = *(V + 30 + v);
868 } else {
869 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
870 *SIG1 = *(V + 30 + v + 1);
871 }
872 } else if ((v + 2 == vmin) &&
873 (*(V + 30 + v) >= 0) &&
874 (*(V + 30 + v + 1) >= 0) &&
875 (*(V + 30 + v + 2) >= 0) &&
876 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
877 (*(V + 30 + v + 2) > *(V + 30 + v)) &&
878 ((*(V + 30 + v + 1) > SIGMIN) ||
879 (*(V + 30 + v + 2) > SIGMIN))) {
880 // (case 6)
881 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
882 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
883 *SIG1 = *(V + 30 + v + 1);
884 } else {
885 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
886 *SIG1 = *(V + 30 + v + 2);
887 }
888 } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
889 swp_freq = fOSC * 1000;
890 *SIG1 = *(V + 30 + v);
891 } else swp_freq = -1;
892 } else swp_freq = -1;
893
894 return swp_freq;
895}
896
897static void swp_info_get2(struct mb86a16_state *state,
898 int smrt,
899 int R,
900 int swp_freq,
901 int *afcex_freq,
902 int *fOSC,
903 unsigned char *AFCEX_L,
904 unsigned char *AFCEX_H)
905{
906 int AFCEX ;
907
908 if (R == 0)
909 *fOSC = (swp_freq + 1000) / 2000 * 2;
910 else
911 *fOSC = (swp_freq + 500) / 1000;
912
913 if (*fOSC >= swp_freq)
914 *afcex_freq = *fOSC * 1000 - swp_freq;
915 else
916 *afcex_freq = swp_freq - *fOSC * 1000;
917
918 AFCEX = *afcex_freq * 8192 / state->master_clk;
919 *AFCEX_L = AFCEX & 0x00ff;
920 *AFCEX_H = (AFCEX & 0x0f00) >> 8;
921}
922
923static void afcex_info_get(struct mb86a16_state *state,
924 int afcex_freq,
925 unsigned char *AFCEX_L,
926 unsigned char *AFCEX_H)
927{
928 int AFCEX ;
929
930 AFCEX = afcex_freq * 8192 / state->master_clk;
931 *AFCEX_L = AFCEX & 0x00ff;
932 *AFCEX_H = (AFCEX & 0x0f00) >> 8;
933}
934
935static int SEQ_set(struct mb86a16_state *state, unsigned char loop)
936{
937 // SLOCK0 = 0
938 if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) {
939 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
940 return -EREMOTEIO;
941 }
942
943 return 0;
944}
945
946static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV)
947{
948 // Viterbi Rate, IQ Settings
949 if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) {
950 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
951 return -EREMOTEIO;
952 }
953
954 return 0;
955}
956
957static int FEC_srst(struct mb86a16_state *state)
958{
959 if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) {
960 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
961 return -EREMOTEIO;
962 }
963
964 return 0;
965}
966
967static int S2T_set(struct mb86a16_state *state, unsigned char S2T)
968{
969 if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) {
970 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
971 return -EREMOTEIO;
972 }
973
974 return 0;
975}
976
977static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T)
978{
979 if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) {
980 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
981 return -EREMOTEIO;
982 }
983
984 return 0;
985}
986
987
988static int mb86a16_set_fe(struct mb86a16_state *state)
989{
990 u8 agcval, cnmval;
991
992 int i, j;
993 int fOSC = 0;
994 int fOSC_start = 0;
995 int wait_t;
996 int fcp;
997 int swp_ofs;
998 int V[60];
999 u8 SIG1MIN;
1000
1001 unsigned char CREN, AFCEN, AFCEXEN;
1002 unsigned char SIG1;
1003 unsigned char TIMINT1, TIMINT2, TIMEXT;
1004 unsigned char S0T, S1T;
1005 unsigned char S2T;
1006// unsigned char S2T, S3T;
1007 unsigned char S4T, S5T;
1008 unsigned char AFCEX_L, AFCEX_H;
1009 unsigned char R;
1010 unsigned char VIRM;
1011 unsigned char ETH, VIA;
1012 unsigned char junk;
1013
1014 int loop;
1015 int ftemp;
1016 int v, vmax, vmin;
1017 int vmax_his, vmin_his;
1018 int swp_freq, prev_swp_freq[20];
1019 int prev_freq_num;
1020 int signal_dupl;
1021 int afcex_freq;
1022 int signal;
1023 int afcerr;
1024 int temp_freq, delta_freq;
1025 int dagcm[4];
1026 int smrt_d;
1027// int freq_err;
1028 int n;
1029 int ret = -1;
1030 int sync;
1031
1032 dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate);
1033
1034 fcp = 5000; // (carrier recovery [kHz])
1035// fcp = 3000;
1036 swp_ofs = state->srate / 4;
1037
1038 for (i = 0; i < 60; i++)
1039 V[i] = -1;
1040
1041 for (i = 0; i < 20; i++)
1042 prev_swp_freq[i] = 0;
1043
1044 SIG1MIN = 25;
1045
1046 for (n = 0; ((n < 3) && (ret == -1)); n++) {
1047 SEQ_set(state, 0);
1048 iq_vt_set(state, 0);
1049
1050 CREN = 0;
1051 AFCEN = 0;
1052 AFCEXEN = 1;
1053 TIMINT1 = 0;
1054 TIMINT2 = 1;
1055 TIMEXT = 2;
1056 S1T = 0;
1057 S0T = 0;
1058
1059 if (initial_set(state) < 0) {
1060 dprintk(verbose, MB86A16_ERROR, 1, "initial set failed");
1061 return -1;
1062 }
1063 if (DAGC_data_set(state, 3, 2) < 0) {
1064 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
1065 return -1;
1066 }
1067 if (EN_set(state, CREN, AFCEN) < 0) {
1068 dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
1069 return -1; // (0, 0)
1070 }
1071 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
1072 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1073 return -1; // (1, smrt) = (1, symbolrate)
1074 }
1075 if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) {
1076 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error");
1077 return -1; // (0, 1, 2)
1078 }
1079 if (S01T_set(state, S1T, S0T) < 0) {
1080 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
1081 return -1; // (0, 0)
1082 }
1083 smrt_info_get(state, state->srate);
1084 if (smrt_set(state, state->srate) < 0) {
1085 dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error");
1086 return -1;
1087 }
1088
1089 R = vco_dev_get(state, state->srate);
1090 if (R == 1)
1091 fOSC_start = state->frequency;
1092
1093 else if (R == 0) {
1094 if (state->frequency % 2 == 0) {
1095 fOSC_start = state->frequency;
1096 } else {
1097 fOSC_start = state->frequency + 1;
1098 if (fOSC_start > 2150)
1099 fOSC_start = state->frequency - 1;
1100 }
1101 }
1102 loop = 1;
1103 ftemp = fOSC_start * 1000;
1104 vmax = 0 ;
1105 while (loop == 1) {
1106 ftemp = ftemp + swp_ofs;
1107 vmax++;
1108
1109 // Upper bound
1110 if (ftemp > 2150000) {
1111 loop = 0;
1112 vmax--;
1113 }
1114 else if ((ftemp == 2150000) || (ftemp - state->frequency * 1000 >= fcp + state->srate / 4))
1115 loop = 0;
1116 }
1117
1118 loop = 1;
1119 ftemp = fOSC_start * 1000;
1120 vmin = 0 ;
1121 while (loop == 1) {
1122 ftemp = ftemp - swp_ofs;
1123 vmin--;
1124
1125 // Lower bound
1126 if (ftemp < 950000) {
1127 loop = 0;
1128 vmin++;
1129 }
1130 else if ((ftemp == 950000) || (state->frequency * 1000 - ftemp >= fcp + state->srate / 4))
1131 loop = 0;
1132 }
1133
1134 wait_t = (8000 + state->srate / 2) / state->srate;
1135 if (wait_t == 0)
1136 wait_t = 1;
1137
1138 i = 0;
1139 j = 0;
1140 prev_freq_num = 0;
1141 loop = 1;
1142 signal = 0;
1143 vmax_his = 0;
1144 vmin_his = 0;
1145 v = 0;
1146
1147 while (loop == 1) {
1148 swp_info_get(state, fOSC_start, state->srate,
1149 v, R, swp_ofs, &fOSC,
1150 &afcex_freq, &AFCEX_L, &AFCEX_H);
1151
1152 if (rf_val_set(state, fOSC, state->srate, R) < 0) {
1153 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1154 return -1;
1155 }
1156
1157 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1158 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1159 return -1;
1160 }
1161 if (srst(state) < 0) {
1162 dprintk(verbose, MB86A16_ERROR, 1, "srst error");
1163 return -1;
1164 }
1165 msleep_interruptible(wait_t);
1166
1167 if (mb86a16_read(state, 0x37, &SIG1) != 2) {
1168 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1169 return -1;
1170 }
1171 V[30 + v] = SIG1 ;
1172 swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
1173 SIG1MIN, fOSC, afcex_freq,
1174 swp_ofs, &SIG1); //changed
1175
1176 signal_dupl = 0;
1177 for (j = 0; j < prev_freq_num; j++) {
1178 if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) {
1179 signal_dupl = 1;
1180 dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j);
1181 }
1182 }
1183 if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) {
1184 dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate);
1185 prev_swp_freq[prev_freq_num] = swp_freq;
1186 prev_freq_num++;
1187 swp_info_get2(state, state->srate, R, swp_freq,
1188 &afcex_freq, &fOSC,
1189 &AFCEX_L, &AFCEX_H);
1190
1191 if (rf_val_set(state, fOSC, state->srate, R) < 0) {
1192 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1193 return -1;
1194 }
1195 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1196 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1197 return -1;
1198 }
1199 signal = signal_det(state, state->srate, &SIG1);
1200 if (signal == 1) {
1201 dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****");
1202 loop = 0;
1203 } else {
1204 dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again...");
1205 smrt_info_get(state, state->srate);
1206 if (smrt_set(state, state->srate) < 0) {
1207 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1208 return -1;
1209 }
1210 }
1211 }
1212 if (v > vmax)
1213 vmax_his = 1 ;
1214 if (v < vmin)
1215 vmin_his = 1 ;
1216 i++;
1217
1218 if ((i % 2 == 1) && (vmax_his == 1))
1219 i++;
1220 if ((i % 2 == 0) && (vmin_his == 1))
1221 i++;
1222
1223 if (i % 2 == 1)
1224 v = (i + 1) / 2;
1225 else
1226 v = -i / 2;
1227
1228 if ((vmax_his == 1) && (vmin_his == 1))
1229 loop = 0 ;
1230 }
1231
1232 if (signal == 1) {
1233 dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check");
1234 S1T = 7 ;
1235 S0T = 1 ;
1236 CREN = 0 ;
1237 AFCEN = 1 ;
1238 AFCEXEN = 0 ;
1239
1240 if (S01T_set(state, S1T, S0T) < 0) {
1241 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
1242 return -1;
1243 }
1244 smrt_info_get(state, state->srate);
1245 if (smrt_set(state, state->srate) < 0) {
1246 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1247 return -1;
1248 }
1249 if (EN_set(state, CREN, AFCEN) < 0) {
1250 dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
1251 return -1;
1252 }
1253 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
1254 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1255 return -1;
1256 }
1257 afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H);
1258 if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1259 dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error");
1260 return -1;
1261 }
1262 if (srst(state) < 0) {
1263 dprintk(verbose, MB86A16_ERROR, 1, "srst error");
1264 return -1;
1265 }
1266 // delay 4~200
1267 wait_t = 200000 / state->master_clk + 200000 / state->srate;
1268 msleep(wait_t);
1269 afcerr = afcerr_chk(state);
1270 if (afcerr == -1)
1271 return -1;
1272
1273 swp_freq = fOSC * 1000 + afcerr ;
1274 AFCEXEN = 1 ;
1275 if (state->srate >= 1500)
1276 smrt_d = state->srate / 3;
1277 else
1278 smrt_d = state->srate / 2;
1279 smrt_info_get(state, smrt_d);
1280 if (smrt_set(state, smrt_d) < 0) {
1281 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1282 return -1;
1283 }
1284 if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) {
1285 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1286 return -1;
1287 }
1288 R = vco_dev_get(state, smrt_d);
1289 if (DAGC_data_set(state, 2, 0) < 0) {
1290 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
1291 return -1;
1292 }
1293 for (i = 0; i < 3; i++) {
1294 temp_freq = swp_freq + (i - 1) * state->srate / 8;
1295 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1296 if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
1297 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1298 return -1;
1299 }
1300 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1301 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1302 return -1;
1303 }
1304 wait_t = 200000 / state->master_clk + 40000 / smrt_d;
1305 msleep(wait_t);
1306 dagcm[i] = dagcm_val_get(state);
1307 }
1308 if ((dagcm[0] > dagcm[1]) &&
1309 (dagcm[0] > dagcm[2]) &&
1310 (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) {
1311
1312 temp_freq = swp_freq - 2 * state->srate / 8;
1313 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1314 if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
1315 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1316 return -1;
1317 }
1318 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1319 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
1320 return -1;
1321 }
1322 wait_t = 200000 / state->master_clk + 40000 / smrt_d;
1323 msleep(wait_t);
1324 dagcm[3] = dagcm_val_get(state);
1325 if (dagcm[3] > dagcm[1])
1326 delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300;
1327 else
1328 delta_freq = 0;
1329 } else if ((dagcm[2] > dagcm[1]) &&
1330 (dagcm[2] > dagcm[0]) &&
1331 (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) {
1332
1333 temp_freq = swp_freq + 2 * state->srate / 8;
1334 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1335 if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
1336 dprintk(verbose, MB86A16_ERROR, 1, "rf val set");
1337 return -1;
1338 }
1339 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1340 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
1341 return -1;
1342 }
1343 wait_t = 200000 / state->master_clk + 40000 / smrt_d;
1344 msleep(wait_t);
1345 dagcm[3] = dagcm_val_get(state);
1346 if (dagcm[3] > dagcm[1])
1347 delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300;
1348 else
1349 delta_freq = 0 ;
1350
1351 } else {
1352 delta_freq = 0 ;
1353 }
1354 dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq);
1355 swp_freq += delta_freq;
1356 dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq);
1357 if (ABS(state->frequency * 1000 - swp_freq) > 3800) {
1358 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !");
1359 } else {
1360
1361 S1T = 0;
1362 S0T = 3;
1363 CREN = 1;
1364 AFCEN = 0;
1365 AFCEXEN = 1;
1366
1367 if (S01T_set(state, S1T, S0T) < 0) {
1368 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
1369 return -1;
1370 }
1371 if (DAGC_data_set(state, 0, 0) < 0) {
1372 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
1373 return -1;
1374 }
1375 R = vco_dev_get(state, state->srate);
1376 smrt_info_get(state, state->srate);
1377 if (smrt_set(state, state->srate) < 0) {
1378 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1379 return -1;
1380 }
1381 if (EN_set(state, CREN, AFCEN) < 0) {
1382 dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
1383 return -1;
1384 }
1385 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
1386 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1387 return -1;
1388 }
1389 swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1390 if (rf_val_set(state, fOSC, state->srate, R) < 0) {
1391 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1392 return -1;
1393 }
1394 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1395 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1396 return -1;
1397 }
1398 if (srst(state) < 0) {
1399 dprintk(verbose, MB86A16_ERROR, 1, "srst error");
1400 return -1;
1401 }
1402 wait_t = 7 + (10000 + state->srate / 2) / state->srate;
1403 if (wait_t == 0)
1404 wait_t = 1;
1405 msleep_interruptible(wait_t);
1406 if (mb86a16_read(state, 0x37, &SIG1) != 2) {
1407 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1408 return -EREMOTEIO;
1409 }
1410
1411 if (SIG1 > 110) {
1412 S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6;
1413 wait_t = 7 + (917504 + state->srate / 2) / state->srate;
1414 } else if (SIG1 > 105) {
1415 S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1416 wait_t = 7 + (1048576 + state->srate / 2) / state->srate;
1417 } else if (SIG1 > 85) {
1418 S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1419 wait_t = 7 + (1310720 + state->srate / 2) / state->srate;
1420 } else if (SIG1 > 65) {
1421 S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1422 wait_t = 7 + (1572864 + state->srate / 2) / state->srate;
1423 } else {
1424 S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1425 wait_t = 7 + (2097152 + state->srate / 2) / state->srate;
1426 }
1427 S2T_set(state, S2T);
1428 S45T_set(state, S4T, S5T);
1429 Vi_set(state, ETH, VIA);
1430 srst(state);
1431 msleep_interruptible(wait_t);
1432 sync = sync_chk(state, &VIRM);
1433 dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync);
1434 if (mb86a16_read(state, 0x0d, &state->signal) != 2) {
1435 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1436 return -EREMOTEIO;
1437 }
1438 if (VIRM) {
1439 if (VIRM == 4) { // 5/6
1440 if (SIG1 > 110)
1441 wait_t = ( 786432 + state->srate / 2) / state->srate;
1442 else
1443 wait_t = (1572864 + state->srate / 2) / state->srate;
1444 if (state->srate < 5000)
1445 // FIXME ! , should be a long wait !
1446 msleep_interruptible(wait_t);
1447 else
1448 msleep_interruptible(wait_t);
1449
1450 if (sync_chk(state, &junk) == 0) {
1451 iq_vt_set(state, 1);
1452 FEC_srst(state);
1453 }
1454 if (SIG1 > 110)
1455 wait_t = ( 786432 + state->srate / 2) / state->srate;
1456 else
1457 wait_t = (1572864 + state->srate / 2) / state->srate;
1458
1459 msleep_interruptible(wait_t);
1460 SEQ_set(state, 1);
1461 } else { // 1/2, 2/3, 3/4, 7/8
1462 if (SIG1 > 110)
1463 wait_t = ( 786432 + state->srate / 2) / state->srate;
1464 else
1465 wait_t = (1572864 + state->srate / 2) / state->srate;
1466
1467 msleep_interruptible(wait_t);
1468 SEQ_set(state, 1);
1469 }
1470 } else {
1471 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL");
1472 SEQ_set(state, 1);
1473 }
1474 }
1475 } else {
1476 dprintk (verbose, MB86A16_INFO, 1, "NO -- SIGNAL");
1477 }
1478
1479 sync = sync_chk(state, &junk);
1480 if (sync) {
1481 dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******");
1482 freqerr_chk(state, state->frequency, state->srate, 1);
1483 }
1484 }
1485
1486 mb86a16_read(state, 0x15, &agcval);
1487 mb86a16_read(state, 0x26, &cnmval);
1488 dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval);
1489
1490 return ret;
1491}
1492
1493static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe,
1494 struct dvb_diseqc_master_cmd *cmd)
1495{
1496 struct mb86a16_state *state = fe->demodulator_priv;
1497 int i;
1498 u8 regs;
1499
1500 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
1501 goto err;
1502 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
1503 goto err;
1504 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
1505 goto err;
1506
1507 regs = 0x18;
1508
1509 if (cmd->msg_len > 5 || cmd->msg_len < 4)
1510 return -EINVAL;
1511
1512 for (i = 0; i < cmd->msg_len; i++) {
1513 if (mb86a16_write(state, regs, cmd->msg[i]) < 0)
1514 goto err;
1515
1516 regs++;
1517 }
1518 i += 0x90;
1519
1520 msleep_interruptible(10);
1521
1522 if (mb86a16_write(state, MB86A16_DCC1, i) < 0)
1523 goto err;
1524 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1525 goto err;
1526
1527 return 0;
1528
1529err:
1530 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1531 return -EREMOTEIO;
1532}
1533
1534static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
1535{
1536 struct mb86a16_state *state = fe->demodulator_priv;
1537
1538 switch (burst) {
1539 case SEC_MINI_A:
1540 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
1541 MB86A16_DCC1_TBEN |
1542 MB86A16_DCC1_TBO) < 0)
1543 goto err;
1544 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1545 goto err;
1546 break;
1547 case SEC_MINI_B:
1548 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
1549 MB86A16_DCC1_TBEN) < 0)
1550 goto err;
1551 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1552 goto err;
1553 break;
1554 }
1555
1556 return 0;
1557err:
1558 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1559 return -EREMOTEIO;
1560}
1561
1562static int mb86a16_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
1563{
1564 struct mb86a16_state *state = fe->demodulator_priv;
1565
1566 switch (tone) {
1567 case SEC_TONE_ON:
1568 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0)
1569 goto err;
1570 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
1571 MB86A16_DCC1_CTOE) < 0)
1572
1573 goto err;
1574 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1575 goto err;
1576 break;
1577 case SEC_TONE_OFF:
1578 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
1579 goto err;
1580 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
1581 goto err;
1582 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
1583 goto err;
1584 break;
1585 default:
1586 return -EINVAL;
1587 }
1588 return 0;
1589
1590err:
1591 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1592 return -EREMOTEIO;
1593}
1594
1595#define MB86A16_FE_ALGO 1
1596
1597static int mb86a16_frontend_algo(struct dvb_frontend *fe)
1598{
1599 return MB86A16_FE_ALGO;
1600}
1601
1602static int mb86a16_set_frontend(struct dvb_frontend *fe,
1603 struct dvb_frontend_parameters *p,
1604 unsigned int mode_flags,
1605 int *delay,
1606 fe_status_t *status)
1607{
1608 int ret = 0;
1609 struct mb86a16_state *state = fe->demodulator_priv;
1610
1611 if (p != NULL) {
1612 state->frequency = p->frequency / 1000;
1613 state->srate = p->u.qpsk.symbol_rate / 1000;
1614 ret = mb86a16_set_fe(state);
1615 }
1616 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
1617 mb86a16_read_status(fe, status);
1618
1619 *delay = HZ/3000;
1620
1621 return ret;
1622}
1623
1624static void mb86a16_release(struct dvb_frontend *fe)
1625{
1626 struct mb86a16_state *state = fe->demodulator_priv;
1627 kfree(state);
1628}
1629
1630static int mb86a16_init(struct dvb_frontend *fe)
1631{
1632 return 0;
1633}
1634
1635static int mb86a16_sleep(struct dvb_frontend *fe)
1636{
1637 return 0;
1638}
1639
1640static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber)
1641{
1642 return 0;
1643}
1644
1645static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
1646{
1647 *strength = 0;
1648
1649 return 0;
1650}
1651
1652struct cnr {
1653 u8 cn_reg;
1654 u8 cn_val;
1655};
1656
1657static const struct cnr cnr_tab[] = {
1658 { 35, 2 },
1659 { 40, 3 },
1660 { 50, 4 },
1661 { 60, 5 },
1662 { 70, 6 },
1663 { 80, 7 },
1664 { 92, 8 },
1665 { 103, 9 },
1666 { 115, 10 },
1667 { 138, 12 },
1668 { 162, 15 },
1669 { 180, 18 },
1670 { 185, 19 },
1671 { 189, 20 },
1672 { 195, 22 },
1673 { 199, 24 },
1674 { 201, 25 },
1675 { 202, 26 },
1676 { 203, 27 },
1677 { 205, 28 },
1678 { 208, 30 }
1679};
1680
1681static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr)
1682{
1683 struct mb86a16_state *state = fe->demodulator_priv;
1684 int i = 0;
1685 int low_tide = 2, high_tide = 30, q_level;
1686 u8 cn;
1687
1688 if (mb86a16_read(state, 0x26, &cn) != 2) {
1689 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1690 return -EREMOTEIO;
1691 }
1692
1693 for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) {
1694 if (cn < cnr_tab[i].cn_reg) {
1695 *snr = cnr_tab[i].cn_val;
1696 break;
1697 }
1698 }
1699 q_level = (*snr * 100) / (high_tide - low_tide);
1700 dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level);
1701
1702 return 0;
1703}
1704
1705static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1706{
1707 return 0;
1708}
1709
1710static struct dvb_frontend_ops mb86a16_ops = {
1711 .info = {
1712 .name = "Fujitsu MB86A16 DVB-S",
1713 .type = FE_QPSK,
1714 .frequency_min = 950000,
1715 .frequency_max = 2150000,
1716 .frequency_stepsize = 125,
1717 .frequency_tolerance = 0,
1718 .symbol_rate_min = 1000000,
1719 .symbol_rate_max = 45000000,
1720 .symbol_rate_tolerance = 500,
1721 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1722 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
1723 FE_CAN_FEC_7_8 | FE_CAN_QPSK |
1724 FE_CAN_FEC_AUTO
1725 },
1726 .release = mb86a16_release,
1727 .tune = mb86a16_set_frontend,
1728 .read_status = mb86a16_read_status,
1729 .get_frontend_algo = mb86a16_frontend_algo,
1730 .init = mb86a16_init,
1731 .sleep = mb86a16_sleep,
1732 .read_status = mb86a16_read_status,
1733
1734 .read_ber = mb86a16_read_ber,
1735 .read_signal_strength = mb86a16_read_signal_strength,
1736 .read_snr = mb86a16_read_snr,
1737 .read_ucblocks = mb86a16_read_ucblocks,
1738
1739 .diseqc_send_master_cmd = mb86a16_send_diseqc_msg,
1740 .diseqc_send_burst = mb86a16_send_diseqc_burst,
1741 .set_tone = mb86a16_set_tone,
1742};
1743
1744struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
1745 struct i2c_adapter *i2c_adap)
1746{
1747 u8 dev_id = 0;
1748 struct mb86a16_state *state = NULL;
1749
1750 state = kmalloc(sizeof (struct mb86a16_state), GFP_KERNEL);
1751 if (state == NULL)
1752 goto error;
1753
1754 state->config = config;
1755 state->i2c_adap = i2c_adap;
1756
1757 mb86a16_read(state, 0x7f, &dev_id);
1758 if (dev_id != 0xfe)
1759 goto error;
1760
1761 memcpy(&state->frontend.ops, &mb86a16_ops, sizeof (struct dvb_frontend_ops));
1762 state->frontend.demodulator_priv = state;
1763 state->frontend.ops.set_voltage = state->config->set_voltage;
1764
1765 return &state->frontend;
1766error:
1767 kfree(state);
1768 return NULL;
1769}
1770EXPORT_SYMBOL(mb86a16_attach);
1771MODULE_LICENSE("GPL");
1772MODULE_AUTHOR("Manu Abraham");
Linux kernel - Deliverables
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