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V4L/DVB (13334): stv6110: add configurable gain
[deliverable/linux.git] / drivers / media / dvb / frontends / stv0900_core.c
CommitLineData
99277b38
IL		 1/*
2 * stv0900_core.c
3 *
4 * Driver for ST STV0900 satellite demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2009 NetUP Inc.
8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/string.h>
29#include <linux/slab.h>
30#include <linux/i2c.h>
31
32#include "stv0900.h"
33#include "stv0900_reg.h"
34#include "stv0900_priv.h"
35#include "stv0900_init.h"
36
8171c205 37int stvdebug = 1;
5a771cb1 38module_param_named(debug, stvdebug, int, 0644);
99277b38
IL		 39
40/* internal params node */
41struct stv0900_inode {
42 /* pointer for internal params, one for each pair of demods */
43 struct stv0900_internal *internal;
44 struct stv0900_inode *next_inode;
45};
46
47/* first internal params */
48static struct stv0900_inode *stv0900_first_inode;
49
50/* find chip by i2c adapter and i2c address */
51static struct stv0900_inode *find_inode(struct i2c_adapter *i2c_adap,
52 u8 i2c_addr)
53{
54 struct stv0900_inode *temp_chip = stv0900_first_inode;
55
56 if (temp_chip != NULL) {
57 /*
58 Search of the last stv0900 chip or
59 find it by i2c adapter and i2c address */
60 while ((temp_chip != NULL) &&
61 ((temp_chip->internal->i2c_adap != i2c_adap) ||
78175bf2 62 (temp_chip->internal->i2c_addr != i2c_addr)))
99277b38
IL		 63
64 temp_chip = temp_chip->next_inode;
78175bf2 65
99277b38
IL		 66 }
67
68 return temp_chip;
69}
70
71/* deallocating chip */
72static void remove_inode(struct stv0900_internal *internal)
73{
74 struct stv0900_inode *prev_node = stv0900_first_inode;
75 struct stv0900_inode *del_node = find_inode(internal->i2c_adap,
76 internal->i2c_addr);
77
78 if (del_node != NULL) {
79 if (del_node == stv0900_first_inode) {
80 stv0900_first_inode = del_node->next_inode;
81 } else {
82 while (prev_node->next_inode != del_node)
83 prev_node = prev_node->next_inode;
84
85 if (del_node->next_inode == NULL)
86 prev_node->next_inode = NULL;
87 else
88 prev_node->next_inode =
89 prev_node->next_inode->next_inode;
90 }
91
92 kfree(del_node);
93 }
94}
95
96/* allocating new chip */
97static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
98{
99 struct stv0900_inode *new_node = stv0900_first_inode;
100
101 if (new_node == NULL) {
102 new_node = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
103 stv0900_first_inode = new_node;
104 } else {
105 while (new_node->next_inode != NULL)
106 new_node = new_node->next_inode;
107
108 new_node->next_inode = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
109 if (new_node->next_inode != NULL)
110 new_node = new_node->next_inode;
111 else
112 new_node = NULL;
113 }
114
115 if (new_node != NULL) {
116 new_node->internal = internal;
117 new_node->next_inode = NULL;
118 }
119
120 return new_node;
121}
122
123s32 ge2comp(s32 a, s32 width)
124{
125 if (width == 32)
126 return a;
127 else
128 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
129}
130
131void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr,
132 u8 reg_data)
133{
134 u8 data[3];
135 int ret;
136 struct i2c_msg i2cmsg = {
137 .addr = i_params->i2c_addr,
138 .flags = 0,
139 .len = 3,
140 .buf = data,
141 };
142
143 data[0] = MSB(reg_addr);
144 data[1] = LSB(reg_addr);
145 data[2] = reg_data;
146
147 ret = i2c_transfer(i_params->i2c_adap, &i2cmsg, 1);
148 if (ret != 1)
8171c205 149 dprintk("%s: i2c error %d\n", __func__, ret);
99277b38
IL		 150}
151
68191ede 152u8 stv0900_read_reg(struct stv0900_internal *i_params, u16 reg)
99277b38 153{
99277b38 154 int ret;
68191ede
AO		 155 u8 b0[] = { MSB(reg), LSB(reg) };
156 u8 buf = 0;
157 struct i2c_msg msg[] = {
158 {
159 .addr = i_params->i2c_addr,
160 .flags = 0,
161 .buf = b0,
162 .len = 2,
163 }, {
164 .addr = i_params->i2c_addr,
165 .flags = I2C_M_RD,
166 .buf = &buf,
167 .len = 1,
168 },
99277b38
IL		 169 };
170
68191ede
AO		 171 ret = i2c_transfer(i_params->i2c_adap, msg, 2);
172 if (ret != 2)
8171c205 173 dprintk("%s: i2c error %d, reg[0x%02x]\n",
68191ede 174 __func__, ret, reg);
99277b38 175
68191ede 176 return buf;
99277b38
IL		 177}
178
179void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
180{
181 u8 position = 0, i = 0;
182
183 (*mask) = label & 0xff;
184
185 while ((position == 0) && (i < 8)) {
186 position = ((*mask) >> i) & 0x01;
187 i++;
188 }
189
190 (*pos) = (i - 1);
191}
192
193void stv0900_write_bits(struct stv0900_internal *i_params, u32 label, u8 val)
194{
195 u8 reg, mask, pos;
196
197 reg = stv0900_read_reg(i_params, (label >> 16) & 0xffff);
198 extract_mask_pos(label, &mask, &pos);
199
200 val = mask & (val << pos);
201
202 reg = (reg & (~mask)) | val;
203 stv0900_write_reg(i_params, (label >> 16) & 0xffff, reg);
204
205}
206
207u8 stv0900_get_bits(struct stv0900_internal *i_params, u32 label)
208{
209 u8 val = 0xff;
210 u8 mask, pos;
211
212 extract_mask_pos(label, &mask, &pos);
213
214 val = stv0900_read_reg(i_params, label >> 16);
215 val = (val & mask) >> pos;
216
217 return val;
218}
219
220enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *i_params)
221{
222 s32 i;
223 enum fe_stv0900_error error;
224
225 if (i_params != NULL) {
226 i_params->chip_id = stv0900_read_reg(i_params, R0900_MID);
227 if (i_params->errs == STV0900_NO_ERROR) {
228 /*Startup sequence*/
229 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5c);
230 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5c);
231 stv0900_write_reg(i_params, R0900_P1_TNRCFG, 0x6c);
232 stv0900_write_reg(i_params, R0900_P2_TNRCFG, 0x6f);
fc7e4a3e
AO		 233 stv0900_write_reg(i_params, R0900_P1_I2CRPT, 0x20);
234 stv0900_write_reg(i_params, R0900_P2_I2CRPT, 0x20);
99277b38
IL		 235 stv0900_write_reg(i_params, R0900_NCOARSE, 0x13);
236 msleep(3);
237 stv0900_write_reg(i_params, R0900_I2CCFG, 0x08);
238
239 switch (i_params->clkmode) {
240 case 0:
241 case 2:
242 stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20
243 | i_params->clkmode);
244 break;
245 default:
246 /* preserve SELOSCI bit */
247 i = 0x02 & stv0900_read_reg(i_params, R0900_SYNTCTRL);
248 stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20 | i);
249 break;
250 }
251
252 msleep(3);
e9d4a6d5 253 for (i = 0; i < 182; i++)
99277b38
IL		 254 stv0900_write_reg(i_params, STV0900_InitVal[i][0], STV0900_InitVal[i][1]);
255
256 if (stv0900_read_reg(i_params, R0900_MID) >= 0x20) {
257 stv0900_write_reg(i_params, R0900_TSGENERAL, 0x0c);
258 for (i = 0; i < 32; i++)
259 stv0900_write_reg(i_params, STV0900_Cut20_AddOnVal[i][0], STV0900_Cut20_AddOnVal[i][1]);
260 }
261
262 stv0900_write_reg(i_params, R0900_P1_FSPYCFG, 0x6c);
263 stv0900_write_reg(i_params, R0900_P2_FSPYCFG, 0x6c);
264 stv0900_write_reg(i_params, R0900_TSTRES0, 0x80);
265 stv0900_write_reg(i_params, R0900_TSTRES0, 0x00);
266 }
267 error = i_params->errs;
268 } else
269 error = STV0900_INVALID_HANDLE;
270
271 return error;
272
273}
274
275u32 stv0900_get_mclk_freq(struct stv0900_internal *i_params, u32 ext_clk)
276{
277 u32 mclk = 90000000, div = 0, ad_div = 0;
278
279 div = stv0900_get_bits(i_params, F0900_M_DIV);
280 ad_div = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
281
282 mclk = (div + 1) * ext_clk / ad_div;
283
8171c205 284 dprintk("%s: Calculated Mclk = %d\n", __func__, mclk);
99277b38
IL		 285
286 return mclk;
287}
288
289enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *i_params, u32 mclk)
290{
291 enum fe_stv0900_error error = STV0900_NO_ERROR;
292 u32 m_div, clk_sel;
293
8171c205 294 dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
99277b38
IL		 295 i_params->quartz);
296
297 if (i_params == NULL)
298 error = STV0900_INVALID_HANDLE;
299 else {
300 if (i_params->errs)
301 error = STV0900_I2C_ERROR;
302 else {
303 clk_sel = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
304 m_div = ((clk_sel * mclk) / i_params->quartz) - 1;
305 stv0900_write_bits(i_params, F0900_M_DIV, m_div);
306 i_params->mclk = stv0900_get_mclk_freq(i_params,
307 i_params->quartz);
308
309 /*Set the DiseqC frequency to 22KHz */
310 /*
311 Formula:
312 DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
313 DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
314 */
315 m_div = i_params->mclk / 704000;
316 stv0900_write_reg(i_params, R0900_P1_F22TX, m_div);
317 stv0900_write_reg(i_params, R0900_P1_F22RX, m_div);
318
319 stv0900_write_reg(i_params, R0900_P2_F22TX, m_div);
320 stv0900_write_reg(i_params, R0900_P2_F22RX, m_div);
321
322 if ((i_params->errs))
323 error = STV0900_I2C_ERROR;
324 }
325 }
326
327 return error;
328}
329
330u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr,
331 enum fe_stv0900_demod_num demod)
332{
333 u32 lsb, msb, hsb, err_val;
334 s32 err1field_hsb, err1field_msb, err1field_lsb;
335 s32 err2field_hsb, err2field_msb, err2field_lsb;
336
337 dmd_reg(err1field_hsb, F0900_P1_ERR_CNT12, F0900_P2_ERR_CNT12);
338 dmd_reg(err1field_msb, F0900_P1_ERR_CNT11, F0900_P2_ERR_CNT11);
339 dmd_reg(err1field_lsb, F0900_P1_ERR_CNT10, F0900_P2_ERR_CNT10);
340
341 dmd_reg(err2field_hsb, F0900_P1_ERR_CNT22, F0900_P2_ERR_CNT22);
342 dmd_reg(err2field_msb, F0900_P1_ERR_CNT21, F0900_P2_ERR_CNT21);
343 dmd_reg(err2field_lsb, F0900_P1_ERR_CNT20, F0900_P2_ERR_CNT20);
344
345 switch (cntr) {
346 case 0:
347 default:
348 hsb = stv0900_get_bits(i_params, err1field_hsb);
349 msb = stv0900_get_bits(i_params, err1field_msb);
350 lsb = stv0900_get_bits(i_params, err1field_lsb);
351 break;
352 case 1:
353 hsb = stv0900_get_bits(i_params, err2field_hsb);
354 msb = stv0900_get_bits(i_params, err2field_msb);
355 lsb = stv0900_get_bits(i_params, err2field_lsb);
356 break;
357 }
358
359 err_val = (hsb << 16) + (msb << 8) + (lsb);
360
361 return err_val;
362}
363
364static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
365{
366 struct stv0900_state *state = fe->demodulator_priv;
367 struct stv0900_internal *i_params = state->internal;
368 enum fe_stv0900_demod_num demod = state->demod;
369
370 u32 fi2c;
371
372 dmd_reg(fi2c, F0900_P1_I2CT_ON, F0900_P2_I2CT_ON);
fc7e4a3e
AO		 373
374 stv0900_write_bits(i_params, fi2c, enable);
99277b38
IL		 375
376 return 0;
377}
378
379static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
380 enum fe_stv0900_clock_type path1_ts,
381 enum fe_stv0900_clock_type path2_ts)
382{
383
8171c205 384 dprintk("%s\n", __func__);
99277b38
IL		 385
386 if (i_params->chip_id >= 0x20) {
387 switch (path1_ts) {
388 case STV0900_PARALLEL_PUNCT_CLOCK:
389 case STV0900_DVBCI_CLOCK:
390 switch (path2_ts) {
391 case STV0900_SERIAL_PUNCT_CLOCK:
392 case STV0900_SERIAL_CONT_CLOCK:
393 default:
394 stv0900_write_reg(i_params, R0900_TSGENERAL,
395 0x00);
396 break;
397 case STV0900_PARALLEL_PUNCT_CLOCK:
398 case STV0900_DVBCI_CLOCK:
399 stv0900_write_reg(i_params, R0900_TSGENERAL,
400 0x06);
401 stv0900_write_bits(i_params,
402 F0900_P1_TSFIFO_MANSPEED, 3);
403 stv0900_write_bits(i_params,
404 F0900_P2_TSFIFO_MANSPEED, 0);
405 stv0900_write_reg(i_params,
406 R0900_P1_TSSPEED, 0x14);
407 stv0900_write_reg(i_params,
408 R0900_P2_TSSPEED, 0x28);
409 break;
410 }
411 break;
412 case STV0900_SERIAL_PUNCT_CLOCK:
413 case STV0900_SERIAL_CONT_CLOCK:
414 default:
415 switch (path2_ts) {
416 case STV0900_SERIAL_PUNCT_CLOCK:
417 case STV0900_SERIAL_CONT_CLOCK:
418 default:
419 stv0900_write_reg(i_params,
420 R0900_TSGENERAL, 0x0C);
421 break;
422 case STV0900_PARALLEL_PUNCT_CLOCK:
423 case STV0900_DVBCI_CLOCK:
424 stv0900_write_reg(i_params,
425 R0900_TSGENERAL, 0x0A);
8171c205 426 dprintk("%s: 0x0a\n", __func__);
99277b38
IL		 427 break;
428 }
429 break;
430 }
431 } else {
432 switch (path1_ts) {
433 case STV0900_PARALLEL_PUNCT_CLOCK:
434 case STV0900_DVBCI_CLOCK:
435 switch (path2_ts) {
436 case STV0900_SERIAL_PUNCT_CLOCK:
437 case STV0900_SERIAL_CONT_CLOCK:
438 default:
439 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
440 0x10);
441 break;
442 case STV0900_PARALLEL_PUNCT_CLOCK:
443 case STV0900_DVBCI_CLOCK:
444 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
445 0x16);
446 stv0900_write_bits(i_params,
447 F0900_P1_TSFIFO_MANSPEED, 3);
448 stv0900_write_bits(i_params,
449 F0900_P2_TSFIFO_MANSPEED, 0);
450 stv0900_write_reg(i_params, R0900_P1_TSSPEED,
451 0x14);
452 stv0900_write_reg(i_params, R0900_P2_TSSPEED,
453 0x28);
454 break;
455 }
456
457 break;
458 case STV0900_SERIAL_PUNCT_CLOCK:
459 case STV0900_SERIAL_CONT_CLOCK:
460 default:
461 switch (path2_ts) {
462 case STV0900_SERIAL_PUNCT_CLOCK:
463 case STV0900_SERIAL_CONT_CLOCK:
464 default:
465 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
466 0x14);
467 break;
468 case STV0900_PARALLEL_PUNCT_CLOCK:
469 case STV0900_DVBCI_CLOCK:
470 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
471 0x12);
8171c205 472 dprintk("%s: 0x12\n", __func__);
99277b38
IL		 473 break;
474 }
475
476 break;
477 }
478 }
479
480 switch (path1_ts) {
481 case STV0900_PARALLEL_PUNCT_CLOCK:
482 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
483 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
484 break;
485 case STV0900_DVBCI_CLOCK:
486 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
487 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
488 break;
489 case STV0900_SERIAL_PUNCT_CLOCK:
490 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
491 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
492 break;
493 case STV0900_SERIAL_CONT_CLOCK:
494 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
495 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
496 break;
497 default:
498 break;
499 }
500
501 switch (path2_ts) {
502 case STV0900_PARALLEL_PUNCT_CLOCK:
503 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
504 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
505 break;
506 case STV0900_DVBCI_CLOCK:
507 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
508 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
509 break;
510 case STV0900_SERIAL_PUNCT_CLOCK:
511 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
512 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
513 break;
514 case STV0900_SERIAL_CONT_CLOCK:
515 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
516 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
517 break;
518 default:
519 break;
520 }
521
522 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1);
523 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 0);
524 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1);
525 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 0);
526}
527
528void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
529 u32 bandwidth)
530{
531 struct dvb_frontend_ops *frontend_ops = NULL;
532 struct dvb_tuner_ops *tuner_ops = NULL;
533
534 if (&fe->ops)
535 frontend_ops = &fe->ops;
536
537 if (&frontend_ops->tuner_ops)
538 tuner_ops = &frontend_ops->tuner_ops;
539
540 if (tuner_ops->set_frequency) {
541 if ((tuner_ops->set_frequency(fe, frequency)) < 0)
542 dprintk("%s: Invalid parameter\n", __func__);
543 else
544 dprintk("%s: Frequency=%d\n", __func__, frequency);
545
546 }
547
548 if (tuner_ops->set_bandwidth) {
549 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
550 dprintk("%s: Invalid parameter\n", __func__);
551 else
552 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
553
554 }
555}
556
557void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
558{
559 struct dvb_frontend_ops *frontend_ops = NULL;
560 struct dvb_tuner_ops *tuner_ops = NULL;
561
562 if (&fe->ops)
563 frontend_ops = &fe->ops;
564
565 if (&frontend_ops->tuner_ops)
566 tuner_ops = &frontend_ops->tuner_ops;
567
568 if (tuner_ops->set_bandwidth) {
569 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
570 dprintk("%s: Invalid parameter\n", __func__);
571 else
572 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
573
574 }
575}
576
577static s32 stv0900_get_rf_level(struct stv0900_internal *i_params,
578 const struct stv0900_table *lookup,
579 enum fe_stv0900_demod_num demod)
580{
581 s32 agc_gain = 0,
582 imin,
583 imax,
584 i,
585 rf_lvl = 0;
586
8171c205 587 dprintk("%s\n", __func__);
99277b38
IL		 588
589 if ((lookup != NULL) && lookup->size) {
590 switch (demod) {
591 case STV0900_DEMOD_1:
592 default:
593 agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE1),
594 stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE0));
595 break;
596 case STV0900_DEMOD_2:
597 agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE1),
598 stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE0));
599 break;
600 }
601
602 imin = 0;
603 imax = lookup->size - 1;
604 if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[imax].regval)) {
605 while ((imax - imin) > 1) {
606 i = (imax + imin) >> 1;
607
608 if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[i].regval))
609 imax = i;
610 else
611 imin = i;
612 }
613
614 rf_lvl = (((s32)agc_gain - lookup->table[imin].regval)
615 * (lookup->table[imax].realval - lookup->table[imin].realval)
616 / (lookup->table[imax].regval - lookup->table[imin].regval))
617 + lookup->table[imin].realval;
618 } else if (agc_gain > lookup->table[0].regval)
619 rf_lvl = 5;
620 else if (agc_gain < lookup->table[lookup->size-1].regval)
621 rf_lvl = -100;
622
623 }
624
8171c205 625 dprintk("%s: RFLevel = %d\n", __func__, rf_lvl);
99277b38
IL		 626
627 return rf_lvl;
628}
629
630static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
631{
632 struct stv0900_state *state = fe->demodulator_priv;
633 struct stv0900_internal *internal = state->internal;
634 s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf,
635 state->demod);
636
637 *strength = (rflevel + 100) * (16383 / 105);
638
639 return 0;
640}
641
642
643static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
644 const struct stv0900_table *lookup)
645{
646 struct stv0900_state *state = fe->demodulator_priv;
647 struct stv0900_internal *i_params = state->internal;
648 enum fe_stv0900_demod_num demod = state->demod;
649
650 s32 c_n = -100,
651 regval, imin, imax,
652 i,
653 lock_flag_field,
654 noise_field1,
655 noise_field0;
656
8171c205 657 dprintk("%s\n", __func__);
99277b38 658
11a84143
IL		 659 dmd_reg(lock_flag_field, F0900_P1_LOCK_DEFINITIF,
660 F0900_P2_LOCK_DEFINITIF);
99277b38 661 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
11a84143
IL		 662 dmd_reg(noise_field1, F0900_P1_NOSPLHT_NORMED1,
663 F0900_P2_NOSPLHT_NORMED1);
664 dmd_reg(noise_field0, F0900_P1_NOSPLHT_NORMED0,
665 F0900_P2_NOSPLHT_NORMED0);
99277b38 666 } else {
11a84143
IL		 667 dmd_reg(noise_field1, F0900_P1_NOSDATAT_NORMED1,
668 F0900_P2_NOSDATAT_NORMED1);
669 dmd_reg(noise_field0, F0900_P1_NOSDATAT_NORMED0,
5765348c 670 F0900_P2_NOSDATAT_NORMED0);
99277b38
IL		 671 }
672
673 if (stv0900_get_bits(i_params, lock_flag_field)) {
674 if ((lookup != NULL) && lookup->size) {
675 regval = 0;
676 msleep(5);
677 for (i = 0; i < 16; i++) {
11a84143
IL		 678 regval += MAKEWORD(stv0900_get_bits(i_params,
679 noise_field1),
680 stv0900_get_bits(i_params,
681 noise_field0));
99277b38
IL		 682 msleep(1);
683 }
684
685 regval /= 16;
686 imin = 0;
687 imax = lookup->size - 1;
11a84143
IL		 688 if (INRANGE(lookup->table[imin].regval,
689 regval,
690 lookup->table[imax].regval)) {
99277b38
IL		 691 while ((imax - imin) > 1) {
692 i = (imax + imin) >> 1;
11a84143
IL		 693 if (INRANGE(lookup->table[imin].regval,
694 regval,
695 lookup->table[i].regval))
99277b38
IL		 696 imax = i;
697 else
698 imin = i;
699 }
700
701 c_n = ((regval - lookup->table[imin].regval)
11a84143
IL		 702 * (lookup->table[imax].realval
703 - lookup->table[imin].realval)
704 / (lookup->table[imax].regval
705 - lookup->table[imin].regval))
99277b38
IL		 706 + lookup->table[imin].realval;
707 } else if (regval < lookup->table[imin].regval)
708 c_n = 1000;
709 }
710 }
711
712 return c_n;
713}
714
ee1ebcfe
AO		 715static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
716{
717 struct stv0900_state *state = fe->demodulator_priv;
718 struct stv0900_internal *i_params = state->internal;
719 enum fe_stv0900_demod_num demod = state->demod;
720 u8 err_val1, err_val0;
721 s32 err_field1, err_field0;
722 u32 header_err_val = 0;
723
724 *ucblocks = 0x0;
725 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
726 /* DVB-S2 delineator errors count */
727
728 /* retreiving number for errnous headers */
729 dmd_reg(err_field0, R0900_P1_BBFCRCKO0,
730 R0900_P2_BBFCRCKO0);
731 dmd_reg(err_field1, R0900_P1_BBFCRCKO1,
732 R0900_P2_BBFCRCKO1);
733
734 err_val1 = stv0900_read_reg(i_params, err_field1);
735 err_val0 = stv0900_read_reg(i_params, err_field0);
736 header_err_val = (err_val1<<8) | err_val0;
737
738 /* retreiving number for errnous packets */
739 dmd_reg(err_field0, R0900_P1_UPCRCKO0,
740 R0900_P2_UPCRCKO0);
741 dmd_reg(err_field1, R0900_P1_UPCRCKO1,
742 R0900_P2_UPCRCKO1);
743
744 err_val1 = stv0900_read_reg(i_params, err_field1);
745 err_val0 = stv0900_read_reg(i_params, err_field0);
746 *ucblocks = (err_val1<<8) | err_val0;
747 *ucblocks += header_err_val;
748 }
749
750 return 0;
751}
752
99277b38
IL		 753static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
754{
11a84143
IL		 755 *snr = stv0900_carr_get_quality(fe,
756 (const struct stv0900_table *)&stv0900_s2_cn);
757 *snr += 30;
758 *snr *= (16383 / 1030);
99277b38
IL		 759
760 return 0;
761}
762
763static u32 stv0900_get_ber(struct stv0900_internal *i_params,
764 enum fe_stv0900_demod_num demod)
765{
766 u32 ber = 10000000, i;
767 s32 dmd_state_reg;
768 s32 demod_state;
769 s32 vstatus_reg;
770 s32 prvit_field;
771 s32 pdel_status_reg;
772 s32 pdel_lock_field;
773
774 dmd_reg(dmd_state_reg, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
775 dmd_reg(vstatus_reg, R0900_P1_VSTATUSVIT, R0900_P2_VSTATUSVIT);
776 dmd_reg(prvit_field, F0900_P1_PRFVIT, F0900_P2_PRFVIT);
777 dmd_reg(pdel_status_reg, R0900_P1_PDELSTATUS1, R0900_P2_PDELSTATUS1);
778 dmd_reg(pdel_lock_field, F0900_P1_PKTDELIN_LOCK,
779 F0900_P2_PKTDELIN_LOCK);
780
781 demod_state = stv0900_get_bits(i_params, dmd_state_reg);
782
783 switch (demod_state) {
784 case STV0900_SEARCH:
785 case STV0900_PLH_DETECTED:
786 default:
787 ber = 10000000;
788 break;
789 case STV0900_DVBS_FOUND:
790 ber = 0;
791 for (i = 0; i < 5; i++) {
792 msleep(5);
793 ber += stv0900_get_err_count(i_params, 0, demod);
794 }
795
796 ber /= 5;
797 if (stv0900_get_bits(i_params, prvit_field)) {
798 ber *= 9766;
799 ber = ber >> 13;
800 }
801
802 break;
803 case STV0900_DVBS2_FOUND:
804 ber = 0;
805 for (i = 0; i < 5; i++) {
806 msleep(5);
807 ber += stv0900_get_err_count(i_params, 0, demod);
808 }
809
810 ber /= 5;
811 if (stv0900_get_bits(i_params, pdel_lock_field)) {
812 ber *= 9766;
813 ber = ber >> 13;
814 }
815
816 break;
817 }
818
819 return ber;
820}
821
822static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
823{
824 struct stv0900_state *state = fe->demodulator_priv;
825 struct stv0900_internal *internal = state->internal;
826
827 *ber = stv0900_get_ber(internal, state->demod);
828
829 return 0;
830}
831
832int stv0900_get_demod_lock(struct stv0900_internal *i_params,
833 enum fe_stv0900_demod_num demod, s32 time_out)
834{
835 s32 timer = 0,
836 lock = 0,
837 header_field,
838 lock_field;
839
840 enum fe_stv0900_search_state dmd_state;
841
842 dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
843 dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
844 while ((timer < time_out) && (lock == 0)) {
845 dmd_state = stv0900_get_bits(i_params, header_field);
846 dprintk("Demod State = %d\n", dmd_state);
847 switch (dmd_state) {
848 case STV0900_SEARCH:
849 case STV0900_PLH_DETECTED:
850 default:
851 lock = 0;
852 break;
853 case STV0900_DVBS2_FOUND:
854 case STV0900_DVBS_FOUND:
855 lock = stv0900_get_bits(i_params, lock_field);
856 break;
857 }
858
859 if (lock == 0)
860 msleep(10);
861
862 timer += 10;
863 }
864
865 if (lock)
866 dprintk("DEMOD LOCK OK\n");
867 else
868 dprintk("DEMOD LOCK FAIL\n");
869
870 return lock;
871}
872
873void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params,
874 enum fe_stv0900_demod_num demod)
875{
876 s32 regflist,
877 i;
878
8171c205 879 dprintk("%s\n", __func__);
99277b38
IL		 880
881 dmd_reg(regflist, R0900_P1_MODCODLST0, R0900_P2_MODCODLST0);
882
883 for (i = 0; i < 16; i++)
884 stv0900_write_reg(i_params, regflist + i, 0xff);
885}
886
887void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
888 enum fe_stv0900_demod_num demod)
889{
890 u32 matype,
891 mod_code,
892 fmod,
893 reg_index,
894 field_index;
895
8171c205 896 dprintk("%s\n", __func__);
99277b38
IL		 897
898 if (i_params->chip_id <= 0x11) {
899 msleep(5);
900
901 switch (demod) {
902 case STV0900_DEMOD_1:
903 default:
904 mod_code = stv0900_read_reg(i_params,
905 R0900_P1_PLHMODCOD);
906 matype = mod_code & 0x3;
907 mod_code = (mod_code & 0x7f) >> 2;
908
909 reg_index = R0900_P1_MODCODLSTF - mod_code / 2;
910 field_index = mod_code % 2;
911 break;
912 case STV0900_DEMOD_2:
913 mod_code = stv0900_read_reg(i_params,
914 R0900_P2_PLHMODCOD);
915 matype = mod_code & 0x3;
916 mod_code = (mod_code & 0x7f) >> 2;
917
918 reg_index = R0900_P2_MODCODLSTF - mod_code / 2;
919 field_index = mod_code % 2;
920 break;
921 }
922
923
924 switch (matype) {
925 case 0:
926 default:
927 fmod = 14;
928 break;
929 case 1:
930 fmod = 13;
931 break;
932 case 2:
933 fmod = 11;
934 break;
935 case 3:
936 fmod = 7;
937 break;
938 }
939
940 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
941 && (matype <= 1)) {
942 if (field_index == 0)
943 stv0900_write_reg(i_params, reg_index,
944 0xf0 | fmod);
945 else
946 stv0900_write_reg(i_params, reg_index,
947 (fmod << 4) | 0xf);
948 }
949 } else if (i_params->chip_id >= 0x12) {
950 switch (demod) {
951 case STV0900_DEMOD_1:
952 default:
953 for (reg_index = 0; reg_index < 7; reg_index++)
954 stv0900_write_reg(i_params, R0900_P1_MODCODLST0 + reg_index, 0xff);
955
956 stv0900_write_reg(i_params, R0900_P1_MODCODLSTE, 0xff);
957 stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0xcf);
958 for (reg_index = 0; reg_index < 8; reg_index++)
959 stv0900_write_reg(i_params, R0900_P1_MODCODLST7 + reg_index, 0xcc);
960
961 break;
962 case STV0900_DEMOD_2:
963 for (reg_index = 0; reg_index < 7; reg_index++)
964 stv0900_write_reg(i_params, R0900_P2_MODCODLST0 + reg_index, 0xff);
965
966 stv0900_write_reg(i_params, R0900_P2_MODCODLSTE, 0xff);
967 stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0xcf);
968 for (reg_index = 0; reg_index < 8; reg_index++)
969 stv0900_write_reg(i_params, R0900_P2_MODCODLST7 + reg_index, 0xcc);
970
971 break;
972 }
973
974 }
975}
976
977void stv0900_activate_s2_modcode_single(struct stv0900_internal *i_params,
978 enum fe_stv0900_demod_num demod)
979{
980 u32 reg_index;
981
8171c205 982 dprintk("%s\n", __func__);
99277b38
IL		 983
984 switch (demod) {
985 case STV0900_DEMOD_1:
986 default:
987 stv0900_write_reg(i_params, R0900_P1_MODCODLST0, 0xff);
988 stv0900_write_reg(i_params, R0900_P1_MODCODLST1, 0xf0);
989 stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0x0f);
990 for (reg_index = 0; reg_index < 13; reg_index++)
991 stv0900_write_reg(i_params,
992 R0900_P1_MODCODLST2 + reg_index, 0);
993
994 break;
995 case STV0900_DEMOD_2:
996 stv0900_write_reg(i_params, R0900_P2_MODCODLST0, 0xff);
997 stv0900_write_reg(i_params, R0900_P2_MODCODLST1, 0xf0);
998 stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0x0f);
999 for (reg_index = 0; reg_index < 13; reg_index++)
1000 stv0900_write_reg(i_params,
1001 R0900_P2_MODCODLST2 + reg_index, 0);
1002
1003 break;
1004 }
1005}
1006
1007static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
1008{
1009 return DVBFE_ALGO_CUSTOM;
1010}
1011
1012static int stb0900_set_property(struct dvb_frontend *fe,
1013 struct dtv_property *tvp)
1014{
8171c205 1015 dprintk("%s(..)\n", __func__);
99277b38
IL		 1016
1017 return 0;
1018}
1019
1020static int stb0900_get_property(struct dvb_frontend *fe,
1021 struct dtv_property *tvp)
1022{
8171c205 1023 dprintk("%s(..)\n", __func__);
99277b38
IL		 1024
1025 return 0;
1026}
1027
1028void stv0900_start_search(struct stv0900_internal *i_params,
1029 enum fe_stv0900_demod_num demod)
1030{
1031
1032 switch (demod) {
1033 case STV0900_DEMOD_1:
1034 default:
1035 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1f);
1036
1037 if (i_params->chip_id == 0x10)
1038 stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xaa);
1039
1040 if (i_params->chip_id < 0x20)
1041 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55);
1042
1043 if (i_params->dmd1_symbol_rate <= 5000000) {
1044 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0x44);
1045 stv0900_write_reg(i_params, R0900_P1_CFRUP1, 0x0f);
1046 stv0900_write_reg(i_params, R0900_P1_CFRUP0, 0xff);
1047 stv0900_write_reg(i_params, R0900_P1_CFRLOW1, 0xf0);
1048 stv0900_write_reg(i_params, R0900_P1_CFRLOW0, 0x00);
1049 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
1050 } else {
1051 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xc4);
1052 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44);
1053 }
1054
1055 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
1056 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
1057
1058 if (i_params->chip_id >= 0x20) {
1059 stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
1060 stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
1061
1062 if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) {
1063 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
1064 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
1065 }
1066 }
1067
1068 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00);
1069 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xe0);
1070 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xc0);
1071 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0);
1072 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
1073 stv0900_write_bits(i_params, F0900_P1_S1S2_SEQUENTIAL, 0);
1074 stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
1075 if (i_params->chip_id >= 0x20) {
1076 if (i_params->dmd1_symbol_rate < 2000000) {
1077 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x39);
1078 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x40);
1079 }
1080
1081 if (i_params->dmd1_symbol_rate < 10000000) {
1082 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4c);
1083 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
1084 } else {
1085 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4b);
1086 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
1087 }
1088
1089 } else {
1090 if (i_params->dmd1_symbol_rate < 10000000)
1091 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xef);
1092 else
1093 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
1094 }
1095
1096 switch (i_params->dmd1_srch_algo) {
1097 case STV0900_WARM_START:
1098 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
1099 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1100 break;
1101 case STV0900_COLD_START:
1102 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
1103 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
1104 break;
1105 default:
1106 break;
1107 }
1108
1109 break;
1110 case STV0900_DEMOD_2:
1111 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1f);
1112 if (i_params->chip_id == 0x10)
1113 stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xaa);
1114
1115 if (i_params->chip_id < 0x20)
1116 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
1117
1118 if (i_params->dmd2_symbol_rate <= 5000000) {
1119 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0x44);
1120 stv0900_write_reg(i_params, R0900_P2_CFRUP1, 0x0f);
1121 stv0900_write_reg(i_params, R0900_P2_CFRUP0, 0xff);
1122 stv0900_write_reg(i_params, R0900_P2_CFRLOW1, 0xf0);
1123 stv0900_write_reg(i_params, R0900_P2_CFRLOW0, 0x00);
1124 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68);
1125 } else {
1126 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xc4);
1127 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
1128 }
1129
1130 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0);
1131 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0);
1132
1133 if (i_params->chip_id >= 0x20) {
1134 stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41);
1135 stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
1136 if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) {
1137 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
1138 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
1139 }
1140 }
1141
1142 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00);
1143 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xe0);
1144 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xc0);
1145 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0);
1146 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
1147 stv0900_write_bits(i_params, F0900_P2_S1S2_SEQUENTIAL, 0);
1148 stv0900_write_reg(i_params, R0900_P2_RTC, 0x88);
1149 if (i_params->chip_id >= 0x20) {
1150 if (i_params->dmd2_symbol_rate < 2000000) {
1151 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x39);
1152 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x40);
1153 }
1154
1155 if (i_params->dmd2_symbol_rate < 10000000) {
1156 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4c);
1157 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
1158 } else {
1159 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4b);
1160 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
1161 }
1162
1163 } else {
1164 if (i_params->dmd2_symbol_rate < 10000000)
1165 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xef);
1166 else
1167 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
1168 }
1169
1170 switch (i_params->dmd2_srch_algo) {
1171 case STV0900_WARM_START:
1172 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
1173 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1174 break;
1175 case STV0900_COLD_START:
1176 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
1177 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
1178 break;
1179 default:
1180 break;
1181 }
1182
1183 break;
1184 }
1185}
1186
1187u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
1188 s32 pilot, u8 chip_id)
1189{
1190 u8 aclc_value = 0x29;
1191 s32 i;
1192 const struct stv0900_car_loop_optim *car_loop_s2;
1193
8171c205 1194 dprintk("%s\n", __func__);
99277b38
IL		 1195
1196 if (chip_id <= 0x12)
1197 car_loop_s2 = FE_STV0900_S2CarLoop;
1198 else if (chip_id == 0x20)
1199 car_loop_s2 = FE_STV0900_S2CarLoopCut20;
1200 else
1201 car_loop_s2 = FE_STV0900_S2CarLoop;
1202
1203 if (modcode < STV0900_QPSK_12) {
1204 i = 0;
1205 while ((i < 3) && (modcode != FE_STV0900_S2LowQPCarLoopCut20[i].modcode))
1206 i++;
1207
1208 if (i >= 3)
1209 i = 2;
1210 } else {
1211 i = 0;
1212 while ((i < 14) && (modcode != car_loop_s2[i].modcode))
1213 i++;
1214
1215 if (i >= 14) {
1216 i = 0;
1217 while ((i < 11) && (modcode != FE_STV0900_S2APSKCarLoopCut20[i].modcode))
1218 i++;
1219
1220 if (i >= 11)
1221 i = 10;
1222 }
1223 }
1224
1225 if (modcode <= STV0900_QPSK_25) {
1226 if (pilot) {
1227 if (srate <= 3000000)
1228 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_2;
1229 else if (srate <= 7000000)
1230 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_5;
1231 else if (srate <= 15000000)
1232 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_10;
1233 else if (srate <= 25000000)
1234 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_20;
1235 else
1236 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_30;
1237 } else {
1238 if (srate <= 3000000)
1239 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_2;
1240 else if (srate <= 7000000)
1241 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_5;
1242 else if (srate <= 15000000)
1243 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_10;
1244 else if (srate <= 25000000)
1245 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_20;
1246 else
1247 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_30;
1248 }
1249
1250 } else if (modcode <= STV0900_8PSK_910) {
1251 if (pilot) {
1252 if (srate <= 3000000)
1253 aclc_value = car_loop_s2[i].car_loop_pilots_on_2;
1254 else if (srate <= 7000000)
1255 aclc_value = car_loop_s2[i].car_loop_pilots_on_5;
1256 else if (srate <= 15000000)
1257 aclc_value = car_loop_s2[i].car_loop_pilots_on_10;
1258 else if (srate <= 25000000)
1259 aclc_value = car_loop_s2[i].car_loop_pilots_on_20;
1260 else
1261 aclc_value = car_loop_s2[i].car_loop_pilots_on_30;
1262 } else {
1263 if (srate <= 3000000)
1264 aclc_value = car_loop_s2[i].car_loop_pilots_off_2;
1265 else if (srate <= 7000000)
1266 aclc_value = car_loop_s2[i].car_loop_pilots_off_5;
1267 else if (srate <= 15000000)
1268 aclc_value = car_loop_s2[i].car_loop_pilots_off_10;
1269 else if (srate <= 25000000)
1270 aclc_value = car_loop_s2[i].car_loop_pilots_off_20;
1271 else
1272 aclc_value = car_loop_s2[i].car_loop_pilots_off_30;
1273 }
1274
1275 } else {
1276 if (srate <= 3000000)
1277 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_2;
1278 else if (srate <= 7000000)
1279 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_5;
1280 else if (srate <= 15000000)
1281 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_10;
1282 else if (srate <= 25000000)
1283 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_20;
1284 else
1285 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_30;
1286 }
1287
1288 return aclc_value;
1289}
1290
1291u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modulation, u8 chip_id)
1292{
1293 s32 mod_index = 0;
1294
1295 u8 aclc_value = 0x0b;
1296
8171c205 1297 dprintk("%s\n", __func__);
99277b38
IL		 1298
1299 switch (modulation) {
1300 case STV0900_QPSK:
1301 default:
1302 mod_index = 0;
1303 break;
1304 case STV0900_8PSK:
1305 mod_index = 1;
1306 break;
1307 case STV0900_16APSK:
1308 mod_index = 2;
1309 break;
1310 case STV0900_32APSK:
1311 mod_index = 3;
1312 break;
1313 }
1314
1315 switch (chip_id) {
1316 case 0x20:
1317 if (srate <= 3000000)
1318 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_2;
1319 else if (srate <= 7000000)
1320 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_5;
1321 else if (srate <= 15000000)
1322 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_10;
1323 else if (srate <= 25000000)
1324 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_20;
1325 else
1326 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_30;
1327
1328 break;
1329 case 0x12:
1330 default:
1331 if (srate <= 3000000)
1332 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_2;
1333 else if (srate <= 7000000)
1334 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_5;
1335 else if (srate <= 15000000)
1336 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_10;
1337 else if (srate <= 25000000)
1338 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_20;
1339 else
1340 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_30;
1341
1342 break;
1343 }
1344
1345 return aclc_value;
1346}
1347
1348static enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *i_params,
1349 enum fe_stv0900_demod_mode LDPC_Mode,
1350 enum fe_stv0900_demod_num demod)
1351{
1352 enum fe_stv0900_error error = STV0900_NO_ERROR;
1353
8171c205 1354 dprintk("%s\n", __func__);
99277b38
IL		 1355
1356 switch (LDPC_Mode) {
1357 case STV0900_DUAL:
1358 default:
1359 if ((i_params->demod_mode != STV0900_DUAL)
1360 || (stv0900_get_bits(i_params, F0900_DDEMOD) != 1)) {
1361 stv0900_write_reg(i_params, R0900_GENCFG, 0x1d);
1362
1363 i_params->demod_mode = STV0900_DUAL;
1364
1365 stv0900_write_bits(i_params, F0900_FRESFEC, 1);
1366 stv0900_write_bits(i_params, F0900_FRESFEC, 0);
1367 }
1368
1369 break;
1370 case STV0900_SINGLE:
1371 if (demod == STV0900_DEMOD_2)
1372 stv0900_write_reg(i_params, R0900_GENCFG, 0x06);
1373 else
1374 stv0900_write_reg(i_params, R0900_GENCFG, 0x04);
1375
1376 i_params->demod_mode = STV0900_SINGLE;
1377
1378 stv0900_write_bits(i_params, F0900_FRESFEC, 1);
1379 stv0900_write_bits(i_params, F0900_FRESFEC, 0);
1380 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1);
1381 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0);
1382 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1);
1383 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0);
1384 break;
1385 }
1386
1387 return error;
1388}
1389
1390static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
1391 struct stv0900_init_params *p_init)
1392{
1393 struct stv0900_state *state = fe->demodulator_priv;
1394 enum fe_stv0900_error error = STV0900_NO_ERROR;
1395 enum fe_stv0900_error demodError = STV0900_NO_ERROR;
f867c3f4 1396 int selosci, i;
99277b38
IL		 1397
1398 struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
1399 state->config->demod_address);
1400
8171c205 1401 dprintk("%s\n", __func__);
99277b38
IL		 1402
1403 if (temp_int != NULL) {
1404 state->internal = temp_int->internal;
1405 (state->internal->dmds_used)++;
8171c205 1406 dprintk("%s: Find Internal Structure!\n", __func__);
99277b38
IL		 1407 return STV0900_NO_ERROR;
1408 } else {
1409 state->internal = kmalloc(sizeof(struct stv0900_internal), GFP_KERNEL);
1410 temp_int = append_internal(state->internal);
1411 state->internal->dmds_used = 1;
1412 state->internal->i2c_adap = state->i2c_adap;
1413 state->internal->i2c_addr = state->config->demod_address;
1414 state->internal->clkmode = state->config->clkmode;
1415 state->internal->errs = STV0900_NO_ERROR;
8171c205 1416 dprintk("%s: Create New Internal Structure!\n", __func__);
99277b38
IL		 1417 }
1418
1419 if (state->internal != NULL) {
1420 demodError = stv0900_initialize(state->internal);
1421 if (demodError == STV0900_NO_ERROR) {
1422 error = STV0900_NO_ERROR;
1423 } else {
1424 if (demodError == STV0900_INVALID_HANDLE)
1425 error = STV0900_INVALID_HANDLE;
1426 else
1427 error = STV0900_I2C_ERROR;
1428 }
1429
1430 if (state->internal != NULL) {
1431 if (error == STV0900_NO_ERROR) {
1432 state->internal->demod_mode = p_init->demod_mode;
1433
1434 stv0900_st_dvbs2_single(state->internal, state->internal->demod_mode, STV0900_DEMOD_1);
1435
1436 state->internal->chip_id = stv0900_read_reg(state->internal, R0900_MID);
1437 state->internal->rolloff = p_init->rolloff;
1438 state->internal->quartz = p_init->dmd_ref_clk;
1439
1440 stv0900_write_bits(state->internal, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
1441 stv0900_write_bits(state->internal, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
1442
f867c3f4
IL		 1443 state->internal->ts_config = p_init->ts_config;
1444 if (state->internal->ts_config == NULL)
1445 stv0900_set_ts_parallel_serial(state->internal,
1446 p_init->path1_ts_clock,
1447 p_init->path2_ts_clock);
1448 else {
1449 for (i = 0; state->internal->ts_config[i].addr != 0xffff; i++)
1450 stv0900_write_reg(state->internal,
1451 state->internal->ts_config[i].addr,
1452 state->internal->ts_config[i].val);
1453
1454 stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 1);
1455 stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 0);
1456 stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 1);
1457 stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 0);
1458 }
1459
99277b38
IL		 1460 stv0900_write_bits(state->internal, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
1461 switch (p_init->tuner1_adc) {
1462 case 1:
1463 stv0900_write_reg(state->internal, R0900_TSTTNR1, 0x26);
1464 break;
1465 default:
1466 break;
1467 }
1468
1469 stv0900_write_bits(state->internal, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
1470 switch (p_init->tuner2_adc) {
1471 case 1:
1472 stv0900_write_reg(state->internal, R0900_TSTTNR3, 0x26);
1473 break;
1474 default:
1475 break;
1476 }
1477
1478 stv0900_write_bits(state->internal, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inversion);
1479 stv0900_write_bits(state->internal, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inversion);
1480 stv0900_set_mclk(state->internal, 135000000);
1481 msleep(3);
1482
1483 switch (state->internal->clkmode) {
1484 case 0:
1485 case 2:
1486 stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | state->internal->clkmode);
1487 break;
1488 default:
1489 selosci = 0x02 & stv0900_read_reg(state->internal, R0900_SYNTCTRL);
1490 stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | selosci);
1491 break;
1492 }
1493 msleep(3);
1494
1495 state->internal->mclk = stv0900_get_mclk_freq(state->internal, state->internal->quartz);
1496 if (state->internal->errs)
1497 error = STV0900_I2C_ERROR;
1498 }
1499 } else {
1500 error = STV0900_INVALID_HANDLE;
1501 }
1502 }
1503
1504 return error;
1505}
1506
1507static int stv0900_status(struct stv0900_internal *i_params,
1508 enum fe_stv0900_demod_num demod)
1509{
1510 enum fe_stv0900_search_state demod_state;
1511 s32 mode_field, delin_field, lock_field, fifo_field, lockedvit_field;
1512 int locked = FALSE;
1513
1514 dmd_reg(mode_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
1515 dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
1516 dmd_reg(delin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
1517 dmd_reg(fifo_field, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
1518 dmd_reg(lockedvit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
1519
1520 demod_state = stv0900_get_bits(i_params, mode_field);
1521 switch (demod_state) {
1522 case STV0900_SEARCH:
1523 case STV0900_PLH_DETECTED:
1524 default:
1525 locked = FALSE;
1526 break;
1527 case STV0900_DVBS2_FOUND:
1528 locked = stv0900_get_bits(i_params, lock_field) &&
1529 stv0900_get_bits(i_params, delin_field) &&
1530 stv0900_get_bits(i_params, fifo_field);
1531 break;
1532 case STV0900_DVBS_FOUND:
1533 locked = stv0900_get_bits(i_params, lock_field) &&
1534 stv0900_get_bits(i_params, lockedvit_field) &&
1535 stv0900_get_bits(i_params, fifo_field);
1536 break;
1537 }
1538
1539 return locked;
1540}
1541
1542static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
1543 struct dvb_frontend_parameters *params)
1544{
1545 struct stv0900_state *state = fe->demodulator_priv;
1546 struct stv0900_internal *i_params = state->internal;
1547 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1548
1549 struct stv0900_search_params p_search;
1550 struct stv0900_signal_info p_result;
1551
1552 enum fe_stv0900_error error = STV0900_NO_ERROR;
1553
8171c205 1554 dprintk("%s: ", __func__);
99277b38
IL		 1555
1556 p_result.locked = FALSE;
1557 p_search.path = state->demod;
1558 p_search.frequency = c->frequency;
1559 p_search.symbol_rate = c->symbol_rate;
1560 p_search.search_range = 10000000;
1561 p_search.fec = STV0900_FEC_UNKNOWN;
1562 p_search.standard = STV0900_AUTO_SEARCH;
1563 p_search.iq_inversion = STV0900_IQ_AUTO;
1564 p_search.search_algo = STV0900_BLIND_SEARCH;
1565
1566 if ((INRANGE(100000, p_search.symbol_rate, 70000000)) &&
1567 (INRANGE(100000, p_search.search_range, 50000000))) {
1568 switch (p_search.path) {
1569 case STV0900_DEMOD_1:
1570 default:
1571 i_params->dmd1_srch_standard = p_search.standard;
1572 i_params->dmd1_symbol_rate = p_search.symbol_rate;
1573 i_params->dmd1_srch_range = p_search.search_range;
1574 i_params->tuner1_freq = p_search.frequency;
1575 i_params->dmd1_srch_algo = p_search.search_algo;
1576 i_params->dmd1_srch_iq_inv = p_search.iq_inversion;
1577 i_params->dmd1_fec = p_search.fec;
1578 break;
1579
1580 case STV0900_DEMOD_2:
1581 i_params->dmd2_srch_stndrd = p_search.standard;
1582 i_params->dmd2_symbol_rate = p_search.symbol_rate;
1583 i_params->dmd2_srch_range = p_search.search_range;
1584 i_params->tuner2_freq = p_search.frequency;
1585 i_params->dmd2_srch_algo = p_search.search_algo;
1586 i_params->dmd2_srch_iq_inv = p_search.iq_inversion;
1587 i_params->dmd2_fec = p_search.fec;
1588 break;
1589 }
1590
1591 if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
1592 (i_params->errs == STV0900_NO_ERROR)) {
1593 switch (p_search.path) {
1594 case STV0900_DEMOD_1:
1595 default:
1596 p_result.locked = i_params->dmd1_rslts.locked;
1597 p_result.standard = i_params->dmd1_rslts.standard;
1598 p_result.frequency = i_params->dmd1_rslts.frequency;
1599 p_result.symbol_rate = i_params->dmd1_rslts.symbol_rate;
1600 p_result.fec = i_params->dmd1_rslts.fec;
1601 p_result.modcode = i_params->dmd1_rslts.modcode;
1602 p_result.pilot = i_params->dmd1_rslts.pilot;
1603 p_result.frame_length = i_params->dmd1_rslts.frame_length;
1604 p_result.spectrum = i_params->dmd1_rslts.spectrum;
1605 p_result.rolloff = i_params->dmd1_rslts.rolloff;
1606 p_result.modulation = i_params->dmd1_rslts.modulation;
1607 break;
1608 case STV0900_DEMOD_2:
1609 p_result.locked = i_params->dmd2_rslts.locked;
1610 p_result.standard = i_params->dmd2_rslts.standard;
1611 p_result.frequency = i_params->dmd2_rslts.frequency;
1612 p_result.symbol_rate = i_params->dmd2_rslts.symbol_rate;
1613 p_result.fec = i_params->dmd2_rslts.fec;
1614 p_result.modcode = i_params->dmd2_rslts.modcode;
1615 p_result.pilot = i_params->dmd2_rslts.pilot;
1616 p_result.frame_length = i_params->dmd2_rslts.frame_length;
1617 p_result.spectrum = i_params->dmd2_rslts.spectrum;
1618 p_result.rolloff = i_params->dmd2_rslts.rolloff;
1619 p_result.modulation = i_params->dmd2_rslts.modulation;
1620 break;
1621 }
1622
1623 } else {
1624 p_result.locked = FALSE;
1625 switch (p_search.path) {
1626 case STV0900_DEMOD_1:
1627 switch (i_params->dmd1_err) {
1628 case STV0900_I2C_ERROR:
1629 error = STV0900_I2C_ERROR;
1630 break;
1631 case STV0900_NO_ERROR:
1632 default:
1633 error = STV0900_SEARCH_FAILED;
1634 break;
1635 }
1636 break;
1637 case STV0900_DEMOD_2:
1638 switch (i_params->dmd2_err) {
1639 case STV0900_I2C_ERROR:
1640 error = STV0900_I2C_ERROR;
1641 break;
1642 case STV0900_NO_ERROR:
1643 default:
1644 error = STV0900_SEARCH_FAILED;
1645 break;
1646 }
1647 break;
1648 }
1649 }
1650
1651 } else
1652 error = STV0900_BAD_PARAMETER;
1653
1654 if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
8171c205 1655 dprintk("Search Success\n");
99277b38
IL		 1656 return DVBFE_ALGO_SEARCH_SUCCESS;
1657 } else {
8171c205 1658 dprintk("Search Fail\n");
99277b38
IL		 1659 return DVBFE_ALGO_SEARCH_FAILED;
1660 }
1661
1662 return DVBFE_ALGO_SEARCH_ERROR;
1663}
1664
1665static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
1666{
1667 struct stv0900_state *state = fe->demodulator_priv;
1668
78175bf2 1669 dprintk("%s: ", __func__);
99277b38
IL		 1670
1671 if ((stv0900_status(state->internal, state->demod)) == TRUE) {
1672 dprintk("DEMOD LOCK OK\n");
1673 *status = FE_HAS_CARRIER
1674 | FE_HAS_VITERBI
1675 | FE_HAS_SYNC
1676 | FE_HAS_LOCK;
1677 } else
1678 dprintk("DEMOD LOCK FAIL\n");
1679
1680 return 0;
1681}
1682
1683static int stv0900_track(struct dvb_frontend *fe,
1684 struct dvb_frontend_parameters *p)
1685{
1686 return 0;
1687}
1688
1689static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
1690{
1691
1692 struct stv0900_state *state = fe->demodulator_priv;
1693 struct stv0900_internal *i_params = state->internal;
1694 enum fe_stv0900_demod_num demod = state->demod;
1695 s32 rst_field;
1696
1697 dmd_reg(rst_field, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE);
1698
1699 if (stop_ts == TRUE)
1700 stv0900_write_bits(i_params, rst_field, 1);
1701 else
1702 stv0900_write_bits(i_params, rst_field, 0);
1703
1704 return 0;
1705}
1706
1707static int stv0900_diseqc_init(struct dvb_frontend *fe)
1708{
1709 struct stv0900_state *state = fe->demodulator_priv;
1710 struct stv0900_internal *i_params = state->internal;
1711 enum fe_stv0900_demod_num demod = state->demod;
1712 s32 mode_field, reset_field;
1713
1714 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1715 dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
1716
1717 stv0900_write_bits(i_params, mode_field, state->config->diseqc_mode);
1718 stv0900_write_bits(i_params, reset_field, 1);
1719 stv0900_write_bits(i_params, reset_field, 0);
1720
1721 return 0;
1722}
1723
1724static int stv0900_init(struct dvb_frontend *fe)
1725{
8171c205 1726 dprintk("%s\n", __func__);
99277b38
IL		 1727
1728 stv0900_stop_ts(fe, 1);
1729 stv0900_diseqc_init(fe);
1730
1731 return 0;
1732}
1733
1734static int stv0900_diseqc_send(struct stv0900_internal *i_params , u8 *Data,
1735 u32 NbData, enum fe_stv0900_demod_num demod)
1736{
1737 s32 i = 0;
1738
1739 switch (demod) {
1740 case STV0900_DEMOD_1:
1741 default:
1742 stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 1);
1743 while (i < NbData) {
1744 while (stv0900_get_bits(i_params, F0900_P1_FIFO_FULL))
1745 ;/* checkpatch complains */
1746 stv0900_write_reg(i_params, R0900_P1_DISTXDATA, Data[i]);
1747 i++;
1748 }
1749
1750 stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 0);
1751 i = 0;
1752 while ((stv0900_get_bits(i_params, F0900_P1_TX_IDLE) != 1) && (i < 10)) {
1753 msleep(10);
1754 i++;
1755 }
1756
1757 break;
1758 case STV0900_DEMOD_2:
1759 stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 1);
1760
1761 while (i < NbData) {
1762 while (stv0900_get_bits(i_params, F0900_P2_FIFO_FULL))
1763 ;/* checkpatch complains */
1764 stv0900_write_reg(i_params, R0900_P2_DISTXDATA, Data[i]);
1765 i++;
1766 }
1767
1768 stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 0);
1769 i = 0;
1770 while ((stv0900_get_bits(i_params, F0900_P2_TX_IDLE) != 1) && (i < 10)) {
1771 msleep(10);
1772 i++;
1773 }
1774
1775 break;
1776 }
1777
1778 return 0;
1779}
1780
1781static int stv0900_send_master_cmd(struct dvb_frontend *fe,
1782 struct dvb_diseqc_master_cmd *cmd)
1783{
1784 struct stv0900_state *state = fe->demodulator_priv;
1785
1786 return stv0900_diseqc_send(state->internal,
1787 cmd->msg,
1788 cmd->msg_len,
1789 state->demod);
1790}
1791
1792static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
1793{
1794 struct stv0900_state *state = fe->demodulator_priv;
1795 struct stv0900_internal *i_params = state->internal;
1796 enum fe_stv0900_demod_num demod = state->demod;
1797 s32 mode_field;
1798 u32 diseqc_fifo;
1799
1800 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1801 dmd_reg(diseqc_fifo, R0900_P1_DISTXDATA, R0900_P2_DISTXDATA);
1802
1803 switch (burst) {
1804 case SEC_MINI_A:
1805 stv0900_write_bits(i_params, mode_field, 3);/* Unmodulated */
1806 stv0900_write_reg(i_params, diseqc_fifo, 0x00);
1807 break;
1808 case SEC_MINI_B:
1809 stv0900_write_bits(i_params, mode_field, 2);/* Modulated */
1810 stv0900_write_reg(i_params, diseqc_fifo, 0xff);
1811 break;
1812 }
1813
1814 return 0;
1815}
1816
1817static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
1818 struct dvb_diseqc_slave_reply *reply)
1819{
1820 struct stv0900_state *state = fe->demodulator_priv;
1821 struct stv0900_internal *i_params = state->internal;
1822 s32 i = 0;
1823
1824 switch (state->demod) {
1825 case STV0900_DEMOD_1:
1826 default:
1827 reply->msg_len = 0;
1828
1829 while ((stv0900_get_bits(i_params, F0900_P1_RX_END) != 1) && (i < 10)) {
1830 msleep(10);
1831 i++;
1832 }
1833
1834 if (stv0900_get_bits(i_params, F0900_P1_RX_END)) {
1835 reply->msg_len = stv0900_get_bits(i_params, F0900_P1_FIFO_BYTENBR);
1836
1837 for (i = 0; i < reply->msg_len; i++)
1838 reply->msg[i] = stv0900_read_reg(i_params, R0900_P1_DISRXDATA);
1839 }
1840 break;
1841 case STV0900_DEMOD_2:
1842 reply->msg_len = 0;
1843
1844 while ((stv0900_get_bits(i_params, F0900_P2_RX_END) != 1) && (i < 10)) {
1845 msleep(10);
1846 i++;
1847 }
1848
1849 if (stv0900_get_bits(i_params, F0900_P2_RX_END)) {
1850 reply->msg_len = stv0900_get_bits(i_params, F0900_P2_FIFO_BYTENBR);
1851
1852 for (i = 0; i < reply->msg_len; i++)
1853 reply->msg[i] = stv0900_read_reg(i_params, R0900_P2_DISRXDATA);
1854 }
1855 break;
1856 }
1857
1858 return 0;
1859}
1860
1861static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
1862{
1863 struct stv0900_state *state = fe->demodulator_priv;
1864 struct stv0900_internal *i_params = state->internal;
1865 enum fe_stv0900_demod_num demod = state->demod;
1866 s32 mode_field, reset_field;
1867
8171c205 1868 dprintk("%s: %s\n", __func__, ((tone == 0) ? "Off" : "On"));
99277b38
IL		 1869
1870 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1871 dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
1872
1873 if (tone) {
1874 /*Set the DiseqC mode to 22Khz continues tone*/
1875 stv0900_write_bits(i_params, mode_field, 0);
1876 stv0900_write_bits(i_params, reset_field, 1);
1877 /*release DiseqC reset to enable the 22KHz tone*/
1878 stv0900_write_bits(i_params, reset_field, 0);
1879 } else {
1880 stv0900_write_bits(i_params, mode_field, 0);
1881 /*maintain the DiseqC reset to disable the 22KHz tone*/
1882 stv0900_write_bits(i_params, reset_field, 1);
1883 }
1884
1885 return 0;
1886}
1887
1888static void stv0900_release(struct dvb_frontend *fe)
1889{
1890 struct stv0900_state *state = fe->demodulator_priv;
1891
8171c205 1892 dprintk("%s\n", __func__);
99277b38
IL		 1893
1894 if ((--(state->internal->dmds_used)) <= 0) {
1895
8171c205 1896 dprintk("%s: Actually removing\n", __func__);
99277b38
IL		 1897
1898 remove_inode(state->internal);
1899 kfree(state->internal);
1900 }
1901
1902 kfree(state);
1903}
1904
1905static struct dvb_frontend_ops stv0900_ops = {
1906
1907 .info = {
1908 .name = "STV0900 frontend",
1909 .type = FE_QPSK,
1910 .frequency_min = 950000,
1911 .frequency_max = 2150000,
1912 .frequency_stepsize = 125,
1913 .frequency_tolerance = 0,
1914 .symbol_rate_min = 1000000,
1915 .symbol_rate_max = 45000000,
1916 .symbol_rate_tolerance = 500,
1917 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1918 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
1919 FE_CAN_FEC_7_8 | FE_CAN_QPSK |
1920 FE_CAN_2G_MODULATION |
1921 FE_CAN_FEC_AUTO
1922 },
1923 .release = stv0900_release,
1924 .init = stv0900_init,
1925 .get_frontend_algo = stv0900_frontend_algo,
1926 .i2c_gate_ctrl = stv0900_i2c_gate_ctrl,
1927 .diseqc_send_master_cmd = stv0900_send_master_cmd,
1928 .diseqc_send_burst = stv0900_send_burst,
1929 .diseqc_recv_slave_reply = stv0900_recv_slave_reply,
1930 .set_tone = stv0900_set_tone,
1931 .set_property = stb0900_set_property,
1932 .get_property = stb0900_get_property,
1933 .search = stv0900_search,
1934 .track = stv0900_track,
1935 .read_status = stv0900_read_status,
1936 .read_ber = stv0900_read_ber,
1937 .read_signal_strength = stv0900_read_signal_strength,
1938 .read_snr = stv0900_read_snr,
ee1ebcfe 1939 .read_ucblocks = stv0900_read_ucblocks,
99277b38
IL		 1940};
1941
1942struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
1943 struct i2c_adapter *i2c,
1944 int demod)
1945{
1946 struct stv0900_state *state = NULL;
1947 struct stv0900_init_params init_params;
1948 enum fe_stv0900_error err_stv0900;
1949
1950 state = kzalloc(sizeof(struct stv0900_state), GFP_KERNEL);
1951 if (state == NULL)
1952 goto error;
1953
1954 state->demod = demod;
1955 state->config = config;
1956 state->i2c_adap = i2c;
1957
1958 memcpy(&state->frontend.ops, &stv0900_ops,
1959 sizeof(struct dvb_frontend_ops));
1960 state->frontend.demodulator_priv = state;
1961
1962 switch (demod) {
1963 case 0:
1964 case 1:
1965 init_params.dmd_ref_clk = config->xtal;
1966 init_params.demod_mode = STV0900_DUAL;
1967 init_params.rolloff = STV0900_35;
1968 init_params.path1_ts_clock = config->path1_mode;
1969 init_params.tun1_maddress = config->tun1_maddress;
1970 init_params.tun1_iq_inversion = STV0900_IQ_NORMAL;
1971 init_params.tuner1_adc = config->tun1_adc;
1972 init_params.path2_ts_clock = config->path2_mode;
f867c3f4 1973 init_params.ts_config = config->ts_config_regs;
99277b38
IL		 1974 init_params.tun2_maddress = config->tun2_maddress;
1975 init_params.tuner2_adc = config->tun2_adc;
1976 init_params.tun2_iq_inversion = STV0900_IQ_SWAPPED;
1977
1978 err_stv0900 = stv0900_init_internal(&state->frontend,
1979 &init_params);
1980
1981 if (err_stv0900)
1982 goto error;
1983
99277b38
IL		 1984 break;
1985 default:
1986 goto error;
1987 break;
1988 }
1989
1990 dprintk("%s: Attaching STV0900 demodulator(%d) \n", __func__, demod);
1991 return &state->frontend;
1992
1993error:
1994 dprintk("%s: Failed to attach STV0900 demodulator(%d) \n",
1995 __func__, demod);
1996 kfree(state);
1997 return NULL;
1998}
1999EXPORT_SYMBOL(stv0900_attach);
2000
2001MODULE_PARM_DESC(debug, "Set debug");
2002
2003MODULE_AUTHOR("Igor M. Liplianin");
2004MODULE_DESCRIPTION("ST STV0900 frontend");
2005MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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