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V4L/DVB (11700): tda10048: Added option to block i2c gate control from other drivers.
[deliverable/linux.git] / drivers / media / dvb / frontends / tda10048.c
CommitLineData
7bbb1ce4
ST		 1/*
2 NXP TDA10048HN DVB OFDM demodulator driver
3
6d897616 4 Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
7bbb1ce4
ST		 5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
20*/
21
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/string.h>
26#include <linux/slab.h>
27#include <linux/delay.h>
d1141538 28#include <asm/div64.h>
7bbb1ce4 29#include "dvb_frontend.h"
d5b3d9ff 30#include "dvb_math.h"
7bbb1ce4
ST		 31#include "tda10048.h"
32
33#define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw"
34#define TDA10048_DEFAULT_FIRMWARE_SIZE 24878
35
36/* Register name definitions */
37#define TDA10048_IDENTITY 0x00
38#define TDA10048_VERSION 0x01
39#define TDA10048_DSP_CODE_CPT 0x0C
40#define TDA10048_DSP_CODE_IN 0x0E
41#define TDA10048_IN_CONF1 0x10
42#define TDA10048_IN_CONF2 0x11
43#define TDA10048_IN_CONF3 0x12
44#define TDA10048_OUT_CONF1 0x14
45#define TDA10048_OUT_CONF2 0x15
46#define TDA10048_OUT_CONF3 0x16
47#define TDA10048_AUTO 0x18
48#define TDA10048_SYNC_STATUS 0x1A
49#define TDA10048_CONF_C4_1 0x1E
50#define TDA10048_CONF_C4_2 0x1F
51#define TDA10048_CODE_IN_RAM 0x20
52#define TDA10048_CHANNEL_INFO_1_R 0x22
53#define TDA10048_CHANNEL_INFO_2_R 0x23
54#define TDA10048_CHANNEL_INFO1 0x24
55#define TDA10048_CHANNEL_INFO2 0x25
56#define TDA10048_TIME_ERROR_R 0x26
57#define TDA10048_TIME_ERROR 0x27
58#define TDA10048_FREQ_ERROR_LSB_R 0x28
59#define TDA10048_FREQ_ERROR_MSB_R 0x29
60#define TDA10048_FREQ_ERROR_LSB 0x2A
61#define TDA10048_FREQ_ERROR_MSB 0x2B
62#define TDA10048_IT_SEL 0x30
63#define TDA10048_IT_STAT 0x32
64#define TDA10048_DSP_AD_LSB 0x3C
65#define TDA10048_DSP_AD_MSB 0x3D
66#define TDA10048_DSP_REF_LSB 0x3E
67#define TDA10048_DSP_REF_MSB 0x3F
68#define TDA10048_CONF_TRISTATE1 0x44
69#define TDA10048_CONF_TRISTATE2 0x45
70#define TDA10048_CONF_POLARITY 0x46
71#define TDA10048_GPIO_SP_DS0 0x48
72#define TDA10048_GPIO_SP_DS1 0x49
73#define TDA10048_GPIO_SP_DS2 0x4A
74#define TDA10048_GPIO_SP_DS3 0x4B
75#define TDA10048_GPIO_OUT_SEL 0x4C
76#define TDA10048_GPIO_SELECT 0x4D
77#define TDA10048_IC_MODE 0x4E
78#define TDA10048_CONF_XO 0x50
79#define TDA10048_CONF_PLL1 0x51
80#define TDA10048_CONF_PLL2 0x52
81#define TDA10048_CONF_PLL3 0x53
82#define TDA10048_CONF_ADC 0x54
83#define TDA10048_CONF_ADC_2 0x55
84#define TDA10048_CONF_C1_1 0x60
85#define TDA10048_CONF_C1_3 0x62
86#define TDA10048_AGC_CONF 0x70
87#define TDA10048_AGC_THRESHOLD_LSB 0x72
88#define TDA10048_AGC_THRESHOLD_MSB 0x73
89#define TDA10048_AGC_RENORM 0x74
90#define TDA10048_AGC_GAINS 0x76
91#define TDA10048_AGC_TUN_MIN 0x78
92#define TDA10048_AGC_TUN_MAX 0x79
93#define TDA10048_AGC_IF_MIN 0x7A
94#define TDA10048_AGC_IF_MAX 0x7B
95#define TDA10048_AGC_TUN_LEVEL 0x7E
96#define TDA10048_AGC_IF_LEVEL 0x7F
97#define TDA10048_DIG_AGC_LEVEL 0x81
98#define TDA10048_FREQ_PHY2_LSB 0x86
99#define TDA10048_FREQ_PHY2_MSB 0x87
100#define TDA10048_TIME_INVWREF_LSB 0x88
101#define TDA10048_TIME_INVWREF_MSB 0x89
102#define TDA10048_TIME_WREF_LSB 0x8A
103#define TDA10048_TIME_WREF_MID1 0x8B
104#define TDA10048_TIME_WREF_MID2 0x8C
105#define TDA10048_TIME_WREF_MSB 0x8D
106#define TDA10048_NP_OUT 0xA2
107#define TDA10048_CELL_ID_LSB 0xA4
108#define TDA10048_CELL_ID_MSB 0xA5
109#define TDA10048_EXTTPS_ODD 0xAA
110#define TDA10048_EXTTPS_EVEN 0xAB
111#define TDA10048_TPS_LENGTH 0xAC
112#define TDA10048_FREE_REG_1 0xB2
113#define TDA10048_FREE_REG_2 0xB3
114#define TDA10048_CONF_C3_1 0xC0
115#define TDA10048_CYBER_CTRL 0xC2
116#define TDA10048_CBER_NMAX_LSB 0xC4
117#define TDA10048_CBER_NMAX_MSB 0xC5
118#define TDA10048_CBER_LSB 0xC6
119#define TDA10048_CBER_MSB 0xC7
120#define TDA10048_VBER_LSB 0xC8
121#define TDA10048_VBER_MID 0xC9
122#define TDA10048_VBER_MSB 0xCA
123#define TDA10048_CYBER_LUT 0xCC
124#define TDA10048_UNCOR_CTRL 0xCD
125#define TDA10048_UNCOR_CPT_LSB 0xCE
126#define TDA10048_UNCOR_CPT_MSB 0xCF
127#define TDA10048_SOFT_IT_C3 0xD6
128#define TDA10048_CONF_TS2 0xE0
129#define TDA10048_CONF_TS1 0xE1
130
131static unsigned int debug;
132
133#define dprintk(level, fmt, arg...)\
134 do { if (debug >= level)\
135 printk(KERN_DEBUG "tda10048: " fmt, ## arg);\
136 } while (0)
137
138struct tda10048_state {
139
140 struct i2c_adapter *i2c;
141
142 /* configuration settings */
143 const struct tda10048_config *config;
144 struct dvb_frontend frontend;
145
146 int fwloaded;
d1141538
ST		 147
148 u32 freq_if_hz;
149 u32 xtal_hz;
150 u32 pll_mfactor;
151 u32 pll_nfactor;
152 u32 pll_pfactor;
153 u32 sample_freq;
154
155 enum fe_bandwidth bandwidth;
7bbb1ce4
ST		 156};
157
158static struct init_tab {
159 u8 reg;
160 u16 data;
161} init_tab[] = {
162 { TDA10048_CONF_PLL1, 0x08 },
163 { TDA10048_CONF_ADC_2, 0x00 },
164 { TDA10048_CONF_C4_1, 0x00 },
165 { TDA10048_CONF_PLL1, 0x0f },
166 { TDA10048_CONF_PLL2, 0x0a },
167 { TDA10048_CONF_PLL3, 0x43 },
168 { TDA10048_FREQ_PHY2_LSB, 0x02 },
169 { TDA10048_FREQ_PHY2_MSB, 0x0a },
170 { TDA10048_TIME_WREF_LSB, 0xbd },
171 { TDA10048_TIME_WREF_MID1, 0xe4 },
172 { TDA10048_TIME_WREF_MID2, 0xa8 },
173 { TDA10048_TIME_WREF_MSB, 0x02 },
174 { TDA10048_TIME_INVWREF_LSB, 0x04 },
175 { TDA10048_TIME_INVWREF_MSB, 0x06 },
176 { TDA10048_CONF_C4_1, 0x00 },
177 { TDA10048_CONF_C1_1, 0xa8 },
178 { TDA10048_AGC_CONF, 0x16 },
179 { TDA10048_CONF_C1_3, 0x0b },
180 { TDA10048_AGC_TUN_MIN, 0x00 },
181 { TDA10048_AGC_TUN_MAX, 0xff },
182 { TDA10048_AGC_IF_MIN, 0x00 },
183 { TDA10048_AGC_IF_MAX, 0xff },
184 { TDA10048_AGC_THRESHOLD_MSB, 0x00 },
185 { TDA10048_AGC_THRESHOLD_LSB, 0x70 },
186 { TDA10048_CYBER_CTRL, 0x38 },
187 { TDA10048_AGC_GAINS, 0x12 },
188 { TDA10048_CONF_XO, 0x00 },
189 { TDA10048_CONF_TS1, 0x07 },
190 { TDA10048_IC_MODE, 0x00 },
191 { TDA10048_CONF_TS2, 0xc0 },
192 { TDA10048_CONF_TRISTATE1, 0x21 },
193 { TDA10048_CONF_TRISTATE2, 0x00 },
194 { TDA10048_CONF_POLARITY, 0x00 },
195 { TDA10048_CONF_C4_2, 0x04 },
196 { TDA10048_CONF_ADC, 0x60 },
197 { TDA10048_CONF_ADC_2, 0x10 },
198 { TDA10048_CONF_ADC, 0x60 },
199 { TDA10048_CONF_ADC_2, 0x00 },
200 { TDA10048_CONF_C1_1, 0xa8 },
201 { TDA10048_UNCOR_CTRL, 0x00 },
202 { TDA10048_CONF_C4_2, 0x04 },
203};
204
205static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data)
206{
207 int ret;
5c2a164a 208 u8 buf[] = { reg, data };
7bbb1ce4
ST		 209 struct i2c_msg msg = {
210 .addr = state->config->demod_address,
211 .flags = 0, .buf = buf, .len = 2 };
212
213 dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data);
214
215 ret = i2c_transfer(state->i2c, &msg, 1);
216
217 if (ret != 1)
218 printk("%s: writereg error (ret == %i)\n", __func__, ret);
219
220 return (ret != 1) ? -1 : 0;
221}
222
223static u8 tda10048_readreg(struct tda10048_state *state, u8 reg)
224{
225 int ret;
5c2a164a
ST		 226 u8 b0[] = { reg };
227 u8 b1[] = { 0 };
228 struct i2c_msg msg[] = {
7bbb1ce4
ST		 229 { .addr = state->config->demod_address,
230 .flags = 0, .buf = b0, .len = 1 },
231 { .addr = state->config->demod_address,
232 .flags = I2C_M_RD, .buf = b1, .len = 1 } };
233
234 dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg);
235
236 ret = i2c_transfer(state->i2c, msg, 2);
237
238 if (ret != 2)
239 printk(KERN_ERR "%s: readreg error (ret == %i)\n",
240 __func__, ret);
241
242 return b1[0];
243}
244
245static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg,
bc179153 246 const u8 *data, u16 len)
7bbb1ce4
ST		 247{
248 int ret = -EREMOTEIO;
249 struct i2c_msg msg;
250 u8 *buf;
251
252 dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len);
253
254 buf = kmalloc(len + 1, GFP_KERNEL);
255 if (buf == NULL) {
256 ret = -ENOMEM;
257 goto error;
258 }
259
260 *buf = reg;
261 memcpy(buf + 1, data, len);
262
263 msg.addr = state->config->demod_address;
264 msg.flags = 0;
265 msg.buf = buf;
266 msg.len = len + 1;
267
268 dprintk(2, "%s(): write len = %d\n",
269 __func__, msg.len);
270
271 ret = i2c_transfer(state->i2c, &msg, 1);
272 if (ret != 1) {
273 printk(KERN_ERR "%s(): writereg error err %i\n",
274 __func__, ret);
275 ret = -EREMOTEIO;
276 }
277
278error:
279 kfree(buf);
280
281 return ret;
282}
283
d1141538
ST		 284static int tda10048_set_phy2(struct dvb_frontend *fe, u32 sample_freq_hz,
285 u32 if_hz)
286{
287 struct tda10048_state *state = fe->demodulator_priv;
288 u64 t;
289
290 dprintk(1, "%s()\n", __func__);
291
292 if (sample_freq_hz == 0)
293 return -EINVAL;
294
295 if (if_hz < (sample_freq_hz / 2)) {
296 /* PHY2 = (if2/fs) * 2^15 */
297 t = if_hz;
298 t *= 10;
299 t *= 32768;
300 do_div(t, sample_freq_hz);
301 t += 5;
302 do_div(t, 10);
303 } else {
304 /* PHY2 = ((IF1-fs)/fs) * 2^15 */
305 t = sample_freq_hz - if_hz;
306 t *= 10;
307 t *= 32768;
308 do_div(t, sample_freq_hz);
309 t += 5;
310 do_div(t, 10);
311 t = ~t + 1;
312 }
313
314 tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t);
315 tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8));
316
317 return 0;
318}
319
320static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz,
321 u32 bw)
322{
323 struct tda10048_state *state = fe->demodulator_priv;
324 u64 t, z;
325 u32 b = 8000000;
326
327 dprintk(1, "%s()\n", __func__);
328
329 if (sample_freq_hz == 0)
330 return -EINVAL;
331
332 if (bw == BANDWIDTH_6_MHZ)
333 b = 6000000;
334 else
335 if (bw == BANDWIDTH_7_MHZ)
336 b = 7000000;
337
338 /* WREF = (B / (7 * fs)) * 2^31 */
339 t = b * 10;
340 /* avoid warning: this decimal constant is unsigned only in ISO C90 */
341 /* t *= 2147483648 on 32bit platforms */
342 t *= (2048 * 1024);
343 t *= 1024;
344 z = 7 * sample_freq_hz;
345 do_div(t, z);
346 t += 5;
347 do_div(t, 10);
348
349 tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t);
350 tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8));
351 tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16));
352 tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24));
353
354 return 0;
355}
356
357static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz,
358 u32 bw)
359{
360 struct tda10048_state *state = fe->demodulator_priv;
361 u64 t;
362 u32 b = 8000000;
363
364 dprintk(1, "%s()\n", __func__);
365
366 if (sample_freq_hz == 0)
367 return -EINVAL;
368
369 if (bw == BANDWIDTH_6_MHZ)
370 b = 6000000;
371 else
372 if (bw == BANDWIDTH_7_MHZ)
373 b = 7000000;
374
375 /* INVWREF = ((7 * fs) / B) * 2^5 */
376 t = sample_freq_hz;
377 t *= 7;
378 t *= 32;
379 t *= 10;
380 do_div(t, b);
381 t += 5;
382 do_div(t, 10);
383
384 tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t);
385 tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8));
386
387 return 0;
388}
389
390static int tda10048_set_bandwidth(struct dvb_frontend *fe,
391 enum fe_bandwidth bw)
392{
393 struct tda10048_state *state = fe->demodulator_priv;
394 dprintk(1, "%s(bw=%d)\n", __func__, bw);
395
396 /* Bandwidth setting may need to be adjusted */
397 switch (bw) {
398 case BANDWIDTH_6_MHZ:
399 case BANDWIDTH_7_MHZ:
400 case BANDWIDTH_8_MHZ:
401 tda10048_set_wref(fe, state->sample_freq, bw);
402 tda10048_set_invwref(fe, state->sample_freq, bw);
403 break;
404 default:
405 printk(KERN_ERR "%s() invalid bandwidth\n", __func__);
406 return -EINVAL;
407 }
408
409 state->bandwidth = bw;
410
411 return 0;
412}
413
414static int tda10048_set_pll(struct dvb_frontend *fe)
415{
416 struct tda10048_state *state = fe->demodulator_priv;
417 int ret = 0;
418
419 dprintk(1, "%s()\n", __func__);
420
421 if ((state->config->clk_freq_khz == TDA10048_CLK_4000) &&
422 (state->config->if_freq_khz == TDA10048_IF_36130)) {
423 state->freq_if_hz = TDA10048_IF_36130 * 1000;
424 state->xtal_hz = TDA10048_CLK_4000 * 1000;
425 state->pll_mfactor = 10;
426 state->pll_nfactor = 0;
427 state->pll_pfactor = 0;
428 } else
429 if ((state->config->clk_freq_khz == TDA10048_CLK_16000) &&
430 (state->config->if_freq_khz == TDA10048_IF_4300)) {
431 state->freq_if_hz = TDA10048_IF_4300 * 1000;
432 state->xtal_hz = TDA10048_CLK_16000 * 1000;
433 state->pll_mfactor = 10;
434 state->pll_nfactor = 3;
435 state->pll_pfactor = 0;
436 } else
437 if ((state->config->clk_freq_khz == TDA10048_CLK_16000) &&
438 (state->config->if_freq_khz == TDA10048_IF_4000)) {
439 state->freq_if_hz = TDA10048_IF_4000 * 1000;
440 state->xtal_hz = TDA10048_CLK_16000 * 1000;
441 state->pll_mfactor = 10;
442 state->pll_nfactor = 3;
443 state->pll_pfactor = 0;
444 } else
445 if ((state->config->clk_freq_khz == TDA10048_CLK_16000) &&
446 (state->config->if_freq_khz == TDA10048_IF_36130)) {
447 state->freq_if_hz = TDA10048_IF_36130 * 1000;
448 state->xtal_hz = TDA10048_CLK_16000 * 1000;
449 state->pll_mfactor = 10;
450 state->pll_nfactor = 3;
451 state->pll_pfactor = 0;
452 } else {
453 printk(KERN_ERR "%s() Incorrect attach settings\n", __func__);
454 ret = -EINVAL;
455 }
456
457 dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz);
458 dprintk(1, "- xtal_hz = %d\n", state->xtal_hz);
459 dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor);
460 dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor);
461 dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor);
462
463 /* Calculate the sample frequency */
464 state->sample_freq = state->xtal_hz * (state->pll_mfactor + 45);
465 state->sample_freq /= (state->pll_nfactor + 1);
466 state->sample_freq /= (state->pll_pfactor + 4);
467 dprintk(1, "- sample_freq = %d\n", state->sample_freq);
468
469 tda10048_set_phy2(fe, state->sample_freq,
470 state->config->if_freq_khz * 1000);
471 tda10048_set_wref(fe, state->sample_freq, state->bandwidth);
472 tda10048_set_invwref(fe, state->sample_freq, state->bandwidth);
473
474 return ret;
475}
476
7bbb1ce4
ST		 477static int tda10048_firmware_upload(struct dvb_frontend *fe)
478{
479 struct tda10048_state *state = fe->demodulator_priv;
480 const struct firmware *fw;
481 int ret;
482 int pos = 0;
483 int cnt;
484 u8 wlen = state->config->fwbulkwritelen;
485
486 if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50))
487 wlen = TDA10048_BULKWRITE_200;
488
489 /* request the firmware, this will block and timeout */
490 printk(KERN_INFO "%s: waiting for firmware upload (%s)...\n",
491 __func__,
492 TDA10048_DEFAULT_FIRMWARE);
493
494 ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE,
e9785250 495 state->i2c->dev.parent);
7bbb1ce4
ST		 496 if (ret) {
497 printk(KERN_ERR "%s: Upload failed. (file not found?)\n",
498 __func__);
499 return -EIO;
500 } else {
501 printk(KERN_INFO "%s: firmware read %Zu bytes.\n",
502 __func__,
503 fw->size);
504 ret = 0;
505 }
506
507 if (fw->size != TDA10048_DEFAULT_FIRMWARE_SIZE) {
508 printk(KERN_ERR "%s: firmware incorrect size\n", __func__);
877b5f4e 509 ret = -EIO;
7bbb1ce4
ST		 510 } else {
511 printk(KERN_INFO "%s: firmware uploading\n", __func__);
512
513 /* Soft reset */
514 tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
515 tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
516 & 0xfe);
517 tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
518 tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
519 | 0x01);
520
521 /* Put the demod into host download mode */
522 tda10048_writereg(state, TDA10048_CONF_C4_1,
523 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9);
524
525 /* Boot the DSP */
526 tda10048_writereg(state, TDA10048_CONF_C4_1,
527 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08);
528
529 /* Prepare for download */
530 tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0);
531
532 /* Download the firmware payload */
533 while (pos < fw->size) {
534
535 if ((fw->size - pos) > wlen)
536 cnt = wlen;
537 else
538 cnt = fw->size - pos;
539
540 tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN,
541 &fw->data[pos], cnt);
542
543 pos += cnt;
544 }
545
546 ret = -EIO;
547 /* Wait up to 250ms for the DSP to boot */
548 for (cnt = 0; cnt < 250 ; cnt += 10) {
549
550 msleep(10);
551
552 if (tda10048_readreg(state, TDA10048_SYNC_STATUS)
553 & 0x40) {
554 ret = 0;
555 break;
556 }
557 }
558 }
559
560 release_firmware(fw);
561
562 if (ret == 0) {
563 printk(KERN_INFO "%s: firmware uploaded\n", __func__);
564 state->fwloaded = 1;
565 } else
566 printk(KERN_ERR "%s: firmware upload failed\n", __func__);
567
568 return ret;
569}
570
571static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion)
572{
573 struct tda10048_state *state = fe->demodulator_priv;
574
575 dprintk(1, "%s(%d)\n", __func__, inversion);
576
577 if (inversion == TDA10048_INVERSION_ON)
578 tda10048_writereg(state, TDA10048_CONF_C1_1,
579 tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20);
580 else
581 tda10048_writereg(state, TDA10048_CONF_C1_1,
582 tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf);
583
584 return 0;
585}
586
587/* Retrieve the demod settings */
588static int tda10048_get_tps(struct tda10048_state *state,
589 struct dvb_ofdm_parameters *p)
590{
591 u8 val;
592
593 /* Make sure the TPS regs are valid */
594 if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01))
595 return -EAGAIN;
596
597 val = tda10048_readreg(state, TDA10048_OUT_CONF2);
598 switch ((val & 0x60) >> 5) {
5c2a164a
ST		 599 case 0:
600 p->constellation = QPSK;
601 break;
602 case 1:
603 p->constellation = QAM_16;
604 break;
605 case 2:
606 p->constellation = QAM_64;
607 break;
7bbb1ce4
ST		 608 }
609 switch ((val & 0x18) >> 3) {
5c2a164a
ST		 610 case 0:
611 p->hierarchy_information = HIERARCHY_NONE;
612 break;
613 case 1:
614 p->hierarchy_information = HIERARCHY_1;
615 break;
616 case 2:
617 p->hierarchy_information = HIERARCHY_2;
618 break;
619 case 3:
620 p->hierarchy_information = HIERARCHY_4;
621 break;
7bbb1ce4
ST		 622 }
623 switch (val & 0x07) {
5c2a164a
ST		 624 case 0:
625 p->code_rate_HP = FEC_1_2;
626 break;
627 case 1:
628 p->code_rate_HP = FEC_2_3;
629 break;
630 case 2:
631 p->code_rate_HP = FEC_3_4;
632 break;
633 case 3:
634 p->code_rate_HP = FEC_5_6;
635 break;
636 case 4:
637 p->code_rate_HP = FEC_7_8;
638 break;
7bbb1ce4
ST		 639 }
640
641 val = tda10048_readreg(state, TDA10048_OUT_CONF3);
642 switch (val & 0x07) {
5c2a164a
ST		 643 case 0:
644 p->code_rate_LP = FEC_1_2;
645 break;
646 case 1:
647 p->code_rate_LP = FEC_2_3;
648 break;
649 case 2:
650 p->code_rate_LP = FEC_3_4;
651 break;
652 case 3:
653 p->code_rate_LP = FEC_5_6;
654 break;
655 case 4:
656 p->code_rate_LP = FEC_7_8;
657 break;
7bbb1ce4
ST		 658 }
659
660 val = tda10048_readreg(state, TDA10048_OUT_CONF1);
661 switch ((val & 0x0c) >> 2) {
5c2a164a
ST		 662 case 0:
663 p->guard_interval = GUARD_INTERVAL_1_32;
664 break;
665 case 1:
666 p->guard_interval = GUARD_INTERVAL_1_16;
667 break;
668 case 2:
669 p->guard_interval = GUARD_INTERVAL_1_8;
670 break;
671 case 3:
672 p->guard_interval = GUARD_INTERVAL_1_4;
673 break;
7bbb1ce4
ST		 674 }
675 switch (val & 0x02) {
5c2a164a
ST		 676 case 0:
677 p->transmission_mode = TRANSMISSION_MODE_2K;
678 break;
679 case 1:
680 p->transmission_mode = TRANSMISSION_MODE_8K;
681 break;
7bbb1ce4
ST		 682 }
683
684 return 0;
685}
686
687static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
688{
689 struct tda10048_state *state = fe->demodulator_priv;
690 dprintk(1, "%s(%d)\n", __func__, enable);
691
8153c3b7
ST		 692 if (state->config->disable_gate_access)
693 return 0;
694
7bbb1ce4
ST		 695 if (enable)
696 return tda10048_writereg(state, TDA10048_CONF_C4_1,
697 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02);
698 else
699 return tda10048_writereg(state, TDA10048_CONF_C4_1,
700 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd);
701}
702
703static int tda10048_output_mode(struct dvb_frontend *fe, int serial)
704{
705 struct tda10048_state *state = fe->demodulator_priv;
706 dprintk(1, "%s(%d)\n", __func__, serial);
707
708 /* Ensure pins are out of tri-state */
709 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21);
710 tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00);
711
712 if (serial) {
713 tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20);
714 tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0);
715 } else {
716 tda10048_writereg(state, TDA10048_IC_MODE, 0x00);
717 tda10048_writereg(state, TDA10048_CONF_TS2, 0x01);
718 }
719
720 return 0;
721}
722
723/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
724/* TODO: Support manual tuning with specific params */
725static int tda10048_set_frontend(struct dvb_frontend *fe,
726 struct dvb_frontend_parameters *p)
727{
728 struct tda10048_state *state = fe->demodulator_priv;
729
730 dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency);
731
d1141538
ST		 732 if (p->u.ofdm.bandwidth != state->bandwidth)
733 tda10048_set_bandwidth(fe, p->u.ofdm.bandwidth);
734
7bbb1ce4
ST		 735 if (fe->ops.tuner_ops.set_params) {
736
737 if (fe->ops.i2c_gate_ctrl)
738 fe->ops.i2c_gate_ctrl(fe, 1);
739
740 fe->ops.tuner_ops.set_params(fe, p);
741
742 if (fe->ops.i2c_gate_ctrl)
743 fe->ops.i2c_gate_ctrl(fe, 0);
744 }
745
746 /* Enable demod TPS auto detection and begin acquisition */
747 tda10048_writereg(state, TDA10048_AUTO, 0x57);
748
749 return 0;
750}
751
752/* Establish sane defaults and load firmware. */
753static int tda10048_init(struct dvb_frontend *fe)
754{
755 struct tda10048_state *state = fe->demodulator_priv;
756 int ret = 0, i;
757
758 dprintk(1, "%s()\n", __func__);
759
760 /* Apply register defaults */
761 for (i = 0; i < ARRAY_SIZE(init_tab); i++)
762 tda10048_writereg(state, init_tab[i].reg, init_tab[i].data);
763
764 if (state->fwloaded == 0)
765 ret = tda10048_firmware_upload(fe);
766
767 /* Set either serial or parallel */
768 tda10048_output_mode(fe, state->config->output_mode);
769
d1141538 770 /* Set inversion */
7bbb1ce4
ST		 771 tda10048_set_inversion(fe, state->config->inversion);
772
d1141538
ST		 773 /* Establish default PLL values */
774 tda10048_set_pll(fe);
775
776 /* Establish default bandwidth */
777 tda10048_set_bandwidth(fe, BANDWIDTH_8_MHZ);
778
7bbb1ce4
ST		 779 /* Ensure we leave the gate closed */
780 tda10048_i2c_gate_ctrl(fe, 0);
781
782 return ret;
783}
784
785static int tda10048_read_status(struct dvb_frontend *fe, fe_status_t *status)
786{
787 struct tda10048_state *state = fe->demodulator_priv;
788 u8 reg;
789
790 *status = 0;
791
792 reg = tda10048_readreg(state, TDA10048_SYNC_STATUS);
793
794 dprintk(1, "%s() status =0x%02x\n", __func__, reg);
795
796 if (reg & 0x02)
797 *status |= FE_HAS_CARRIER;
798
799 if (reg & 0x04)
800 *status |= FE_HAS_SIGNAL;
801
802 if (reg & 0x08) {
803 *status |= FE_HAS_LOCK;
804 *status |= FE_HAS_VITERBI;
805 *status |= FE_HAS_SYNC;
806 }
807
808 return 0;
809}
810
811static int tda10048_read_ber(struct dvb_frontend *fe, u32 *ber)
812{
813 struct tda10048_state *state = fe->demodulator_priv;
814
815 dprintk(1, "%s()\n", __func__);
816
817 /* TODO: A reset may be required here */
818 *ber = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 |
819 tda10048_readreg(state, TDA10048_CBER_LSB);
820
821 return 0;
822}
823
824static int tda10048_read_signal_strength(struct dvb_frontend *fe,
825 u16 *signal_strength)
826{
827 struct tda10048_state *state = fe->demodulator_priv;
d5b3d9ff 828 u8 v;
7bbb1ce4
ST		 829
830 dprintk(1, "%s()\n", __func__);
831
d5b3d9ff
ST		 832 *signal_strength = 65535;
833
7bbb1ce4 834 v = tda10048_readreg(state, TDA10048_NP_OUT);
d5b3d9ff
ST		 835 if (v > 0)
836 *signal_strength -= (v << 8) | v;
7bbb1ce4
ST		 837
838 return 0;
839}
840
d5b3d9ff
ST		 841/* SNR lookup table */
842static struct snr_tab {
843 u8 val;
844 u8 data;
845} snr_tab[] = {
846 { 0, 0 },
847 { 1, 246 },
848 { 2, 215 },
849 { 3, 198 },
850 { 4, 185 },
851 { 5, 176 },
852 { 6, 168 },
853 { 7, 161 },
854 { 8, 155 },
855 { 9, 150 },
856 { 10, 146 },
857 { 11, 141 },
858 { 12, 138 },
859 { 13, 134 },
860 { 14, 131 },
861 { 15, 128 },
862 { 16, 125 },
863 { 17, 122 },
864 { 18, 120 },
865 { 19, 118 },
866 { 20, 115 },
867 { 21, 113 },
868 { 22, 111 },
869 { 23, 109 },
870 { 24, 107 },
871 { 25, 106 },
872 { 26, 104 },
873 { 27, 102 },
874 { 28, 101 },
875 { 29, 99 },
876 { 30, 98 },
877 { 31, 96 },
878 { 32, 95 },
879 { 33, 94 },
880 { 34, 92 },
881 { 35, 91 },
882 { 36, 90 },
883 { 37, 89 },
884 { 38, 88 },
885 { 39, 86 },
886 { 40, 85 },
887 { 41, 84 },
888 { 42, 83 },
889 { 43, 82 },
890 { 44, 81 },
891 { 45, 80 },
892 { 46, 79 },
893 { 47, 78 },
894 { 48, 77 },
895 { 49, 76 },
896 { 50, 76 },
897 { 51, 75 },
898 { 52, 74 },
899 { 53, 73 },
900 { 54, 72 },
901 { 56, 71 },
902 { 57, 70 },
903 { 58, 69 },
904 { 60, 68 },
905 { 61, 67 },
906 { 63, 66 },
907 { 64, 65 },
908 { 66, 64 },
909 { 67, 63 },
910 { 68, 62 },
911 { 69, 62 },
912 { 70, 61 },
913 { 72, 60 },
914 { 74, 59 },
915 { 75, 58 },
916 { 77, 57 },
917 { 79, 56 },
918 { 81, 55 },
919 { 83, 54 },
920 { 85, 53 },
921 { 87, 52 },
922 { 89, 51 },
923 { 91, 50 },
924 { 93, 49 },
925 { 95, 48 },
926 { 97, 47 },
927 { 100, 46 },
928 { 102, 45 },
929 { 104, 44 },
930 { 107, 43 },
931 { 109, 42 },
932 { 112, 41 },
933 { 114, 40 },
934 { 117, 39 },
935 { 120, 38 },
936 { 123, 37 },
937 { 125, 36 },
938 { 128, 35 },
939 { 131, 34 },
940 { 134, 33 },
941 { 138, 32 },
942 { 141, 31 },
943 { 144, 30 },
944 { 147, 29 },
945 { 151, 28 },
946 { 154, 27 },
947 { 158, 26 },
948 { 162, 25 },
949 { 165, 24 },
950 { 169, 23 },
951 { 173, 22 },
952 { 177, 21 },
953 { 181, 20 },
954 { 186, 19 },
955 { 190, 18 },
956 { 194, 17 },
957 { 199, 16 },
958 { 204, 15 },
959 { 208, 14 },
960 { 213, 13 },
961 { 218, 12 },
962 { 223, 11 },
963 { 229, 10 },
964 { 234, 9 },
965 { 239, 8 },
966 { 245, 7 },
967 { 251, 6 },
968 { 255, 5 },
969};
970
7bbb1ce4
ST		 971static int tda10048_read_snr(struct dvb_frontend *fe, u16 *snr)
972{
973 struct tda10048_state *state = fe->demodulator_priv;
d5b3d9ff
ST		 974 u8 v;
975 int i, ret = -EINVAL;
7bbb1ce4
ST		 976
977 dprintk(1, "%s()\n", __func__);
978
d5b3d9ff
ST		 979 v = tda10048_readreg(state, TDA10048_NP_OUT);
980 for (i = 0; i < ARRAY_SIZE(snr_tab); i++) {
981 if (v <= snr_tab[i].val) {
982 *snr = snr_tab[i].data;
983 ret = 0;
984 break;
985 }
986 }
7bbb1ce4 987
d5b3d9ff 988 return ret;
7bbb1ce4
ST		 989}
990
991static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
992{
993 struct tda10048_state *state = fe->demodulator_priv;
994
995 dprintk(1, "%s()\n", __func__);
996
997 *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 |
998 tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB);
999
1000 return 0;
1001}
1002
1003static int tda10048_get_frontend(struct dvb_frontend *fe,
1004 struct dvb_frontend_parameters *p)
1005{
1006 struct tda10048_state *state = fe->demodulator_priv;
1007
1008 dprintk(1, "%s()\n", __func__);
1009
1010 p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1)
1011 & 0x20 ? INVERSION_ON : INVERSION_OFF;
1012
1013 return tda10048_get_tps(state, &p->u.ofdm);
1014}
1015
1016static int tda10048_get_tune_settings(struct dvb_frontend *fe,
1017 struct dvb_frontend_tune_settings *tune)
1018{
1019 tune->min_delay_ms = 1000;
1020 return 0;
1021}
1022
1023static void tda10048_release(struct dvb_frontend *fe)
1024{
1025 struct tda10048_state *state = fe->demodulator_priv;
1026 dprintk(1, "%s()\n", __func__);
1027 kfree(state);
1028}
1029
1030static struct dvb_frontend_ops tda10048_ops;
1031
1032struct dvb_frontend *tda10048_attach(const struct tda10048_config *config,
1033 struct i2c_adapter *i2c)
1034{
1035 struct tda10048_state *state = NULL;
1036
1037 dprintk(1, "%s()\n", __func__);
1038
1039 /* allocate memory for the internal state */
1040 state = kmalloc(sizeof(struct tda10048_state), GFP_KERNEL);
1041 if (state == NULL)
1042 goto error;
1043
1044 /* setup the state */
1045 state->config = config;
1046 state->i2c = i2c;
1047 state->fwloaded = 0;
d1141538 1048 state->bandwidth = BANDWIDTH_8_MHZ;
7bbb1ce4
ST		 1049
1050 /* check if the demod is present */
1051 if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048)
1052 goto error;
1053
1054 /* create dvb_frontend */
1055 memcpy(&state->frontend.ops, &tda10048_ops,
1056 sizeof(struct dvb_frontend_ops));
1057 state->frontend.demodulator_priv = state;
1058
d1141538
ST		 1059 /* Set the xtal and freq defaults */
1060 if (tda10048_set_pll(&state->frontend) != 0)
1061 goto error;
1062
7bbb1ce4
ST		 1063 /* Leave the gate closed */
1064 tda10048_i2c_gate_ctrl(&state->frontend, 0);
1065
1066 return &state->frontend;
1067
1068error:
1069 kfree(state);
1070 return NULL;
1071}
1072EXPORT_SYMBOL(tda10048_attach);
1073
1074static struct dvb_frontend_ops tda10048_ops = {
1075
1076 .info = {
1077 .name = "NXP TDA10048HN DVB-T",
1078 .type = FE_OFDM,
1079 .frequency_min = 177000000,
1080 .frequency_max = 858000000,
1081 .frequency_stepsize = 166666,
1082 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1083 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1084 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1085 FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
1086 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
1087 },
1088
1089 .release = tda10048_release,
1090 .init = tda10048_init,
1091 .i2c_gate_ctrl = tda10048_i2c_gate_ctrl,
1092 .set_frontend = tda10048_set_frontend,
1093 .get_frontend = tda10048_get_frontend,
1094 .get_tune_settings = tda10048_get_tune_settings,
1095 .read_status = tda10048_read_status,
1096 .read_ber = tda10048_read_ber,
1097 .read_signal_strength = tda10048_read_signal_strength,
1098 .read_snr = tda10048_read_snr,
1099 .read_ucblocks = tda10048_read_ucblocks,
1100};
1101
1102module_param(debug, int, 0644);
1103MODULE_PARM_DESC(debug, "Enable verbose debug messages");
1104
1105MODULE_DESCRIPTION("NXP TDA10048HN DVB-T Demodulator driver");
1106MODULE_AUTHOR("Steven Toth");
1107MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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