Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | Driver for Philips tda1004xh OFDM Demodulator | |
3 | ||
4 | (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ||
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | ||
21 | */ | |
22 | /* | |
23 | * This driver needs external firmware. Please use the commands | |
24 | * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045", | |
25 | * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to | |
26 | * download/extract them, and then copy them to /usr/lib/hotplug/firmware. | |
27 | */ | |
28 | #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw" | |
29 | #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw" | |
30 | ||
31 | #include <linux/init.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/moduleparam.h> | |
34 | #include <linux/device.h> | |
4e57b681 TS |
35 | #include <linux/jiffies.h> |
36 | #include <linux/string.h> | |
37 | #include <linux/slab.h> | |
38 | ||
1da177e4 LT |
39 | #include "dvb_frontend.h" |
40 | #include "tda1004x.h" | |
41 | ||
7f5e02db JS |
42 | enum tda1004x_demod { |
43 | TDA1004X_DEMOD_TDA10045, | |
44 | TDA1004X_DEMOD_TDA10046, | |
45 | }; | |
1da177e4 LT |
46 | |
47 | struct tda1004x_state { | |
48 | struct i2c_adapter* i2c; | |
49 | struct dvb_frontend_ops ops; | |
50 | const struct tda1004x_config* config; | |
51 | struct dvb_frontend frontend; | |
52 | ||
53 | /* private demod data */ | |
7f5e02db JS |
54 | u8 initialised; |
55 | enum tda1004x_demod demod_type; | |
1da177e4 LT |
56 | }; |
57 | ||
1da177e4 LT |
58 | static int debug; |
59 | #define dprintk(args...) \ | |
60 | do { \ | |
61 | if (debug) printk(KERN_DEBUG "tda1004x: " args); \ | |
62 | } while (0) | |
63 | ||
64 | #define TDA1004X_CHIPID 0x00 | |
65 | #define TDA1004X_AUTO 0x01 | |
66 | #define TDA1004X_IN_CONF1 0x02 | |
67 | #define TDA1004X_IN_CONF2 0x03 | |
68 | #define TDA1004X_OUT_CONF1 0x04 | |
69 | #define TDA1004X_OUT_CONF2 0x05 | |
70 | #define TDA1004X_STATUS_CD 0x06 | |
71 | #define TDA1004X_CONFC4 0x07 | |
72 | #define TDA1004X_DSSPARE2 0x0C | |
73 | #define TDA10045H_CODE_IN 0x0D | |
74 | #define TDA10045H_FWPAGE 0x0E | |
75 | #define TDA1004X_SCAN_CPT 0x10 | |
76 | #define TDA1004X_DSP_CMD 0x11 | |
77 | #define TDA1004X_DSP_ARG 0x12 | |
78 | #define TDA1004X_DSP_DATA1 0x13 | |
79 | #define TDA1004X_DSP_DATA2 0x14 | |
80 | #define TDA1004X_CONFADC1 0x15 | |
81 | #define TDA1004X_CONFC1 0x16 | |
82 | #define TDA10045H_S_AGC 0x1a | |
83 | #define TDA10046H_AGC_TUN_LEVEL 0x1a | |
84 | #define TDA1004X_SNR 0x1c | |
85 | #define TDA1004X_CONF_TS1 0x1e | |
86 | #define TDA1004X_CONF_TS2 0x1f | |
87 | #define TDA1004X_CBER_RESET 0x20 | |
88 | #define TDA1004X_CBER_MSB 0x21 | |
89 | #define TDA1004X_CBER_LSB 0x22 | |
90 | #define TDA1004X_CVBER_LUT 0x23 | |
91 | #define TDA1004X_VBER_MSB 0x24 | |
92 | #define TDA1004X_VBER_MID 0x25 | |
93 | #define TDA1004X_VBER_LSB 0x26 | |
94 | #define TDA1004X_UNCOR 0x27 | |
95 | ||
96 | #define TDA10045H_CONFPLL_P 0x2D | |
97 | #define TDA10045H_CONFPLL_M_MSB 0x2E | |
98 | #define TDA10045H_CONFPLL_M_LSB 0x2F | |
99 | #define TDA10045H_CONFPLL_N 0x30 | |
100 | ||
101 | #define TDA10046H_CONFPLL1 0x2D | |
102 | #define TDA10046H_CONFPLL2 0x2F | |
103 | #define TDA10046H_CONFPLL3 0x30 | |
104 | #define TDA10046H_TIME_WREF1 0x31 | |
105 | #define TDA10046H_TIME_WREF2 0x32 | |
106 | #define TDA10046H_TIME_WREF3 0x33 | |
107 | #define TDA10046H_TIME_WREF4 0x34 | |
108 | #define TDA10046H_TIME_WREF5 0x35 | |
109 | ||
110 | #define TDA10045H_UNSURW_MSB 0x31 | |
111 | #define TDA10045H_UNSURW_LSB 0x32 | |
112 | #define TDA10045H_WREF_MSB 0x33 | |
113 | #define TDA10045H_WREF_MID 0x34 | |
114 | #define TDA10045H_WREF_LSB 0x35 | |
115 | #define TDA10045H_MUXOUT 0x36 | |
116 | #define TDA1004X_CONFADC2 0x37 | |
117 | ||
118 | #define TDA10045H_IOFFSET 0x38 | |
119 | ||
120 | #define TDA10046H_CONF_TRISTATE1 0x3B | |
121 | #define TDA10046H_CONF_TRISTATE2 0x3C | |
122 | #define TDA10046H_CONF_POLARITY 0x3D | |
123 | #define TDA10046H_FREQ_OFFSET 0x3E | |
124 | #define TDA10046H_GPIO_OUT_SEL 0x41 | |
125 | #define TDA10046H_GPIO_SELECT 0x42 | |
126 | #define TDA10046H_AGC_CONF 0x43 | |
f03cbea3 HH |
127 | #define TDA10046H_AGC_THR 0x44 |
128 | #define TDA10046H_AGC_RENORM 0x45 | |
1da177e4 LT |
129 | #define TDA10046H_AGC_GAINS 0x46 |
130 | #define TDA10046H_AGC_TUN_MIN 0x47 | |
131 | #define TDA10046H_AGC_TUN_MAX 0x48 | |
132 | #define TDA10046H_AGC_IF_MIN 0x49 | |
133 | #define TDA10046H_AGC_IF_MAX 0x4A | |
134 | ||
135 | #define TDA10046H_FREQ_PHY2_MSB 0x4D | |
136 | #define TDA10046H_FREQ_PHY2_LSB 0x4E | |
137 | ||
138 | #define TDA10046H_CVBER_CTRL 0x4F | |
139 | #define TDA10046H_AGC_IF_LEVEL 0x52 | |
140 | #define TDA10046H_CODE_CPT 0x57 | |
141 | #define TDA10046H_CODE_IN 0x58 | |
142 | ||
143 | ||
144 | static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data) | |
145 | { | |
146 | int ret; | |
147 | u8 buf[] = { reg, data }; | |
7f5e02db | 148 | struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 }; |
1da177e4 LT |
149 | |
150 | dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data); | |
151 | ||
152 | msg.addr = state->config->demod_address; | |
153 | ret = i2c_transfer(state->i2c, &msg, 1); | |
154 | ||
155 | if (ret != 1) | |
156 | dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n", | |
157 | __FUNCTION__, reg, data, ret); | |
158 | ||
159 | dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__, | |
160 | reg, data, ret); | |
161 | return (ret != 1) ? -1 : 0; | |
162 | } | |
163 | ||
164 | static int tda1004x_read_byte(struct tda1004x_state *state, int reg) | |
165 | { | |
166 | int ret; | |
167 | u8 b0[] = { reg }; | |
168 | u8 b1[] = { 0 }; | |
7f5e02db JS |
169 | struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 }, |
170 | { .flags = I2C_M_RD, .buf = b1, .len = 1 }}; | |
1da177e4 LT |
171 | |
172 | dprintk("%s: reg=0x%x\n", __FUNCTION__, reg); | |
173 | ||
174 | msg[0].addr = state->config->demod_address; | |
175 | msg[1].addr = state->config->demod_address; | |
176 | ret = i2c_transfer(state->i2c, msg, 2); | |
177 | ||
178 | if (ret != 2) { | |
179 | dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg, | |
180 | ret); | |
181 | return -1; | |
182 | } | |
183 | ||
184 | dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__, | |
185 | reg, b1[0], ret); | |
186 | return b1[0]; | |
187 | } | |
188 | ||
189 | static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data) | |
190 | { | |
191 | int val; | |
192 | dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg, | |
193 | mask, data); | |
194 | ||
195 | // read a byte and check | |
196 | val = tda1004x_read_byte(state, reg); | |
197 | if (val < 0) | |
198 | return val; | |
199 | ||
200 | // mask if off | |
201 | val = val & ~mask; | |
202 | val |= data & 0xff; | |
203 | ||
204 | // write it out again | |
205 | return tda1004x_write_byteI(state, reg, val); | |
206 | } | |
207 | ||
208 | static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len) | |
209 | { | |
210 | int i; | |
211 | int result; | |
212 | ||
213 | dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len); | |
214 | ||
215 | result = 0; | |
216 | for (i = 0; i < len; i++) { | |
217 | result = tda1004x_write_byteI(state, reg + i, buf[i]); | |
218 | if (result != 0) | |
219 | break; | |
220 | } | |
221 | ||
222 | return result; | |
223 | } | |
224 | ||
225 | static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state) | |
226 | { | |
227 | int result; | |
228 | dprintk("%s\n", __FUNCTION__); | |
229 | ||
230 | result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2); | |
231 | msleep(1); | |
232 | return result; | |
233 | } | |
234 | ||
235 | static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state) | |
236 | { | |
237 | dprintk("%s\n", __FUNCTION__); | |
238 | ||
239 | return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0); | |
240 | } | |
241 | ||
242 | static int tda10045h_set_bandwidth(struct tda1004x_state *state, | |
243 | fe_bandwidth_t bandwidth) | |
244 | { | |
245 | static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f }; | |
246 | static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb }; | |
247 | static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 }; | |
248 | ||
249 | switch (bandwidth) { | |
250 | case BANDWIDTH_6_MHZ: | |
251 | tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz)); | |
252 | break; | |
253 | ||
254 | case BANDWIDTH_7_MHZ: | |
255 | tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz)); | |
256 | break; | |
257 | ||
258 | case BANDWIDTH_8_MHZ: | |
259 | tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz)); | |
260 | break; | |
261 | ||
262 | default: | |
263 | return -EINVAL; | |
264 | } | |
265 | ||
266 | tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0); | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | static int tda10046h_set_bandwidth(struct tda1004x_state *state, | |
272 | fe_bandwidth_t bandwidth) | |
273 | { | |
274 | static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e }; | |
275 | static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 }; | |
276 | static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd }; | |
277 | ||
278 | switch (bandwidth) { | |
279 | case BANDWIDTH_6_MHZ: | |
280 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz)); | |
f03cbea3 HH |
281 | if (state->config->if_freq == TDA10046_FREQ_045) { |
282 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x09); | |
283 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x4f); | |
284 | } | |
1da177e4 LT |
285 | break; |
286 | ||
287 | case BANDWIDTH_7_MHZ: | |
288 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz)); | |
f03cbea3 HH |
289 | if (state->config->if_freq == TDA10046_FREQ_045) { |
290 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a); | |
291 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x79); | |
292 | } | |
1da177e4 LT |
293 | break; |
294 | ||
295 | case BANDWIDTH_8_MHZ: | |
296 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz)); | |
f03cbea3 HH |
297 | if (state->config->if_freq == TDA10046_FREQ_045) { |
298 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0b); | |
299 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xa3); | |
300 | } | |
1da177e4 LT |
301 | break; |
302 | ||
303 | default: | |
304 | return -EINVAL; | |
305 | } | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
310 | static int tda1004x_do_upload(struct tda1004x_state *state, | |
311 | unsigned char *mem, unsigned int len, | |
312 | u8 dspCodeCounterReg, u8 dspCodeInReg) | |
313 | { | |
314 | u8 buf[65]; | |
7f5e02db | 315 | struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 }; |
1da177e4 LT |
316 | int tx_size; |
317 | int pos = 0; | |
318 | ||
319 | /* clear code counter */ | |
320 | tda1004x_write_byteI(state, dspCodeCounterReg, 0); | |
321 | fw_msg.addr = state->config->demod_address; | |
322 | ||
323 | buf[0] = dspCodeInReg; | |
324 | while (pos != len) { | |
1da177e4 LT |
325 | // work out how much to send this time |
326 | tx_size = len - pos; | |
7f5e02db | 327 | if (tx_size > 0x10) |
1da177e4 | 328 | tx_size = 0x10; |
1da177e4 LT |
329 | |
330 | // send the chunk | |
331 | memcpy(buf + 1, mem + pos, tx_size); | |
332 | fw_msg.len = tx_size + 1; | |
333 | if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) { | |
ecb60deb | 334 | printk(KERN_ERR "tda1004x: Error during firmware upload\n"); |
1da177e4 LT |
335 | return -EIO; |
336 | } | |
337 | pos += tx_size; | |
338 | ||
339 | dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos); | |
340 | } | |
ecb60deb HH |
341 | // give the DSP a chance to settle 03/10/05 Hac |
342 | msleep(100); | |
7f5e02db | 343 | |
1da177e4 LT |
344 | return 0; |
345 | } | |
346 | ||
ecb60deb | 347 | static int tda1004x_check_upload_ok(struct tda1004x_state *state) |
1da177e4 LT |
348 | { |
349 | u8 data1, data2; | |
ecb60deb HH |
350 | unsigned long timeout; |
351 | ||
352 | if (state->demod_type == TDA1004X_DEMOD_TDA10046) { | |
353 | timeout = jiffies + 2 * HZ; | |
354 | while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) { | |
355 | if (time_after(jiffies, timeout)) { | |
356 | printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n"); | |
357 | break; | |
358 | } | |
359 | msleep(1); | |
360 | } | |
361 | } else | |
362 | msleep(100); | |
1da177e4 LT |
363 | |
364 | // check upload was OK | |
365 | tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP | |
366 | tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67); | |
367 | ||
368 | data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1); | |
369 | data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2); | |
3faadbb0 | 370 | if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) { |
ecb60deb | 371 | printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2); |
1da177e4 | 372 | return -EIO; |
ecb60deb HH |
373 | } |
374 | printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2); | |
1da177e4 LT |
375 | return 0; |
376 | } | |
377 | ||
378 | static int tda10045_fwupload(struct dvb_frontend* fe) | |
379 | { | |
380 | struct tda1004x_state* state = fe->demodulator_priv; | |
381 | int ret; | |
382 | const struct firmware *fw; | |
383 | ||
1da177e4 | 384 | /* don't re-upload unless necessary */ |
ecb60deb | 385 | if (tda1004x_check_upload_ok(state) == 0) |
7f5e02db | 386 | return 0; |
1da177e4 LT |
387 | |
388 | /* request the firmware, this will block until someone uploads it */ | |
ecb60deb | 389 | printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE); |
1da177e4 LT |
390 | ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); |
391 | if (ret) { | |
ecb60deb | 392 | printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n"); |
1da177e4 LT |
393 | return ret; |
394 | } | |
395 | ||
396 | /* reset chip */ | |
397 | tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); | |
398 | tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); | |
399 | tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); | |
400 | msleep(10); | |
401 | ||
402 | /* set parameters */ | |
403 | tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ); | |
404 | ||
405 | ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN); | |
0c744b01 | 406 | release_firmware(fw); |
1da177e4 LT |
407 | if (ret) |
408 | return ret; | |
ecb60deb | 409 | printk(KERN_INFO "tda1004x: firmware upload complete\n"); |
1da177e4 LT |
410 | |
411 | /* wait for DSP to initialise */ | |
412 | /* DSPREADY doesn't seem to work on the TDA10045H */ | |
413 | msleep(100); | |
414 | ||
ecb60deb | 415 | return tda1004x_check_upload_ok(state); |
1da177e4 LT |
416 | } |
417 | ||
ecb60deb | 418 | static void tda10046_init_plls(struct dvb_frontend* fe) |
71e34201 | 419 | { |
ecb60deb | 420 | struct tda1004x_state* state = fe->demodulator_priv; |
71e34201 | 421 | |
ecb60deb HH |
422 | tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0); |
423 | tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10 | |
424 | if (state->config->xtal_freq == TDA10046_XTAL_4M ) { | |
425 | dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__); | |
426 | tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0 | |
427 | } else { | |
428 | dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__); | |
429 | tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3 | |
430 | } | |
431 | tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99); | |
432 | switch (state->config->if_freq) { | |
433 | case TDA10046_FREQ_3617: | |
434 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); | |
435 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c); | |
436 | break; | |
437 | case TDA10046_FREQ_3613: | |
438 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); | |
439 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x13); | |
440 | break; | |
f03cbea3 HH |
441 | case TDA10046_FREQ_045: |
442 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0b); | |
443 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xa3); | |
444 | break; | |
445 | case TDA10046_FREQ_052: | |
446 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); | |
447 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x06); | |
448 | break; | |
ecb60deb HH |
449 | } |
450 | tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz | |
71e34201 JS |
451 | } |
452 | ||
1da177e4 LT |
453 | static int tda10046_fwupload(struct dvb_frontend* fe) |
454 | { | |
455 | struct tda1004x_state* state = fe->demodulator_priv; | |
1da177e4 LT |
456 | int ret; |
457 | const struct firmware *fw; | |
458 | ||
459 | /* reset + wake up chip */ | |
ecb60deb | 460 | tda1004x_write_byteI(state, TDA1004X_CONFC4, 0); |
1da177e4 | 461 | tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0); |
ecb60deb HH |
462 | /* let the clocks recover from sleep */ |
463 | msleep(5); | |
1da177e4 LT |
464 | |
465 | /* don't re-upload unless necessary */ | |
ecb60deb | 466 | if (tda1004x_check_upload_ok(state) == 0) |
7f5e02db | 467 | return 0; |
1da177e4 | 468 | |
1da177e4 | 469 | /* set parameters */ |
ecb60deb HH |
470 | tda10046_init_plls(fe); |
471 | ||
472 | if (state->config->request_firmware != NULL) { | |
473 | /* request the firmware, this will block until someone uploads it */ | |
474 | printk(KERN_INFO "tda1004x: waiting for firmware upload...\n"); | |
475 | ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE); | |
476 | if (ret) { | |
477 | printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n"); | |
478 | return ret; | |
1da177e4 | 479 | } |
ecb60deb HH |
480 | tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST |
481 | ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN); | |
0c744b01 | 482 | release_firmware(fw); |
ecb60deb HH |
483 | if (ret) |
484 | return ret; | |
485 | } else { | |
486 | /* boot from firmware eeprom */ | |
487 | /* Hac Note: we might need to do some GPIO Magic here */ | |
488 | printk(KERN_INFO "tda1004x: booting from eeprom\n"); | |
489 | tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4); | |
490 | msleep(300); | |
1da177e4 | 491 | } |
ecb60deb | 492 | return tda1004x_check_upload_ok(state); |
1da177e4 LT |
493 | } |
494 | ||
495 | static int tda1004x_encode_fec(int fec) | |
496 | { | |
497 | // convert known FEC values | |
498 | switch (fec) { | |
499 | case FEC_1_2: | |
500 | return 0; | |
501 | case FEC_2_3: | |
502 | return 1; | |
503 | case FEC_3_4: | |
504 | return 2; | |
505 | case FEC_5_6: | |
506 | return 3; | |
507 | case FEC_7_8: | |
508 | return 4; | |
509 | } | |
510 | ||
511 | // unsupported | |
512 | return -EINVAL; | |
513 | } | |
514 | ||
515 | static int tda1004x_decode_fec(int tdafec) | |
516 | { | |
517 | // convert known FEC values | |
518 | switch (tdafec) { | |
519 | case 0: | |
520 | return FEC_1_2; | |
521 | case 1: | |
522 | return FEC_2_3; | |
523 | case 2: | |
524 | return FEC_3_4; | |
525 | case 3: | |
526 | return FEC_5_6; | |
527 | case 4: | |
528 | return FEC_7_8; | |
529 | } | |
530 | ||
531 | // unsupported | |
532 | return -1; | |
533 | } | |
534 | ||
535 | int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data) | |
536 | { | |
537 | struct tda1004x_state* state = fe->demodulator_priv; | |
538 | ||
539 | return tda1004x_write_byteI(state, reg, data); | |
540 | } | |
541 | ||
542 | static int tda10045_init(struct dvb_frontend* fe) | |
543 | { | |
544 | struct tda1004x_state* state = fe->demodulator_priv; | |
545 | ||
546 | dprintk("%s\n", __FUNCTION__); | |
547 | ||
7f5e02db JS |
548 | if (state->initialised) |
549 | return 0; | |
1da177e4 LT |
550 | |
551 | if (tda10045_fwupload(fe)) { | |
552 | printk("tda1004x: firmware upload failed\n"); | |
553 | return -EIO; | |
554 | } | |
555 | ||
556 | tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC | |
557 | ||
558 | // Init the PLL | |
559 | if (state->config->pll_init) { | |
560 | tda1004x_enable_tuner_i2c(state); | |
561 | state->config->pll_init(fe); | |
562 | tda1004x_disable_tuner_i2c(state); | |
563 | } | |
564 | ||
565 | // tda setup | |
566 | tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer | |
567 | tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream | |
568 | tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal | |
569 | tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer | |
570 | tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset | |
571 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset | |
572 | tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface | |
573 | tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface | |
574 | tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits | |
575 | tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity | |
576 | tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e); | |
577 | ||
578 | tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk); | |
579 | ||
580 | state->initialised = 1; | |
581 | return 0; | |
582 | } | |
583 | ||
584 | static int tda10046_init(struct dvb_frontend* fe) | |
585 | { | |
586 | struct tda1004x_state* state = fe->demodulator_priv; | |
587 | dprintk("%s\n", __FUNCTION__); | |
588 | ||
7f5e02db JS |
589 | if (state->initialised) |
590 | return 0; | |
1da177e4 LT |
591 | |
592 | if (tda10046_fwupload(fe)) { | |
593 | printk("tda1004x: firmware upload failed\n"); | |
ecb60deb | 594 | return -EIO; |
1da177e4 LT |
595 | } |
596 | ||
ecb60deb | 597 | // Init the tuner PLL |
1da177e4 LT |
598 | if (state->config->pll_init) { |
599 | tda1004x_enable_tuner_i2c(state); | |
600 | state->config->pll_init(fe); | |
601 | tda1004x_disable_tuner_i2c(state); | |
602 | } | |
603 | ||
604 | // tda setup | |
605 | tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer | |
ecb60deb HH |
606 | tda1004x_write_byteI(state, TDA1004X_AUTO, 7); // select HP stream |
607 | tda1004x_write_byteI(state, TDA1004X_CONFC1, 8); // disable pulse killer | |
608 | ||
609 | tda10046_init_plls(fe); | |
610 | switch (state->config->agc_config) { | |
611 | case TDA10046_AGC_DEFAULT: | |
612 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup | |
613 | tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities | |
614 | break; | |
615 | case TDA10046_AGC_IFO_AUTO_NEG: | |
616 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup | |
617 | tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities | |
618 | break; | |
f03cbea3 HH |
619 | case TDA10046_AGC_IFO_AUTO_POS: |
620 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup | |
621 | tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x00); // set AGC polarities | |
622 | break; | |
623 | case TDA10046_AGC_TDA827X: | |
624 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup | |
625 | tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold | |
626 | tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x0E); // Gain Renormalize | |
627 | tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities | |
628 | break; | |
ecb60deb HH |
629 | } |
630 | tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on | |
1da177e4 LT |
631 | tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // } |
632 | tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values | |
633 | tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // } | |
634 | tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // } | |
1da177e4 | 635 | tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1 |
ecb60deb | 636 | tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits |
1da177e4 | 637 | tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config |
ecb60deb HH |
638 | tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config |
639 | tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7); | |
640 | ||
1da177e4 LT |
641 | tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup |
642 | tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config | |
ecb60deb | 643 | tda1004x_write_byteI(state, TDA10046H_GPIO_SELECT, 8); // GPIO select |
1da177e4 LT |
644 | |
645 | state->initialised = 1; | |
646 | return 0; | |
647 | } | |
648 | ||
649 | static int tda1004x_set_fe(struct dvb_frontend* fe, | |
650 | struct dvb_frontend_parameters *fe_params) | |
651 | { | |
652 | struct tda1004x_state* state = fe->demodulator_priv; | |
653 | int tmp; | |
654 | int inversion; | |
655 | ||
656 | dprintk("%s\n", __FUNCTION__); | |
657 | ||
658 | if (state->demod_type == TDA1004X_DEMOD_TDA10046) { | |
659 | // setup auto offset | |
660 | tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); | |
661 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0); | |
662 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0); | |
663 | ||
664 | // disable agc_conf[2] | |
665 | tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0); | |
666 | } | |
667 | ||
668 | // set frequency | |
669 | tda1004x_enable_tuner_i2c(state); | |
670 | state->config->pll_set(fe, fe_params); | |
671 | tda1004x_disable_tuner_i2c(state); | |
672 | ||
1da177e4 LT |
673 | // Hardcoded to use auto as much as possible on the TDA10045 as it |
674 | // is very unreliable if AUTO mode is _not_ used. | |
675 | if (state->demod_type == TDA1004X_DEMOD_TDA10045) { | |
676 | fe_params->u.ofdm.code_rate_HP = FEC_AUTO; | |
677 | fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO; | |
678 | fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO; | |
679 | } | |
680 | ||
681 | // Set standard params.. or put them to auto | |
682 | if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) || | |
683 | (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) || | |
684 | (fe_params->u.ofdm.constellation == QAM_AUTO) || | |
685 | (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) { | |
686 | tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto | |
687 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits | |
688 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits | |
689 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits | |
690 | } else { | |
691 | tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto | |
692 | ||
693 | // set HP FEC | |
694 | tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP); | |
7f5e02db JS |
695 | if (tmp < 0) |
696 | return tmp; | |
1da177e4 LT |
697 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp); |
698 | ||
699 | // set LP FEC | |
700 | tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP); | |
7f5e02db JS |
701 | if (tmp < 0) |
702 | return tmp; | |
1da177e4 LT |
703 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3); |
704 | ||
705 | // set constellation | |
706 | switch (fe_params->u.ofdm.constellation) { | |
707 | case QPSK: | |
708 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0); | |
709 | break; | |
710 | ||
711 | case QAM_16: | |
712 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1); | |
713 | break; | |
714 | ||
715 | case QAM_64: | |
716 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2); | |
717 | break; | |
718 | ||
719 | default: | |
720 | return -EINVAL; | |
721 | } | |
722 | ||
723 | // set hierarchy | |
724 | switch (fe_params->u.ofdm.hierarchy_information) { | |
725 | case HIERARCHY_NONE: | |
726 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5); | |
727 | break; | |
728 | ||
729 | case HIERARCHY_1: | |
730 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5); | |
731 | break; | |
732 | ||
733 | case HIERARCHY_2: | |
734 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5); | |
735 | break; | |
736 | ||
737 | case HIERARCHY_4: | |
738 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5); | |
739 | break; | |
740 | ||
741 | default: | |
742 | return -EINVAL; | |
743 | } | |
744 | } | |
745 | ||
746 | // set bandwidth | |
7f5e02db | 747 | switch (state->demod_type) { |
1da177e4 LT |
748 | case TDA1004X_DEMOD_TDA10045: |
749 | tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth); | |
750 | break; | |
751 | ||
752 | case TDA1004X_DEMOD_TDA10046: | |
753 | tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth); | |
754 | break; | |
755 | } | |
756 | ||
757 | // set inversion | |
758 | inversion = fe_params->inversion; | |
7f5e02db JS |
759 | if (state->config->invert) |
760 | inversion = inversion ? INVERSION_OFF : INVERSION_ON; | |
1da177e4 LT |
761 | switch (inversion) { |
762 | case INVERSION_OFF: | |
763 | tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0); | |
764 | break; | |
765 | ||
766 | case INVERSION_ON: | |
767 | tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20); | |
768 | break; | |
769 | ||
770 | default: | |
771 | return -EINVAL; | |
772 | } | |
773 | ||
774 | // set guard interval | |
775 | switch (fe_params->u.ofdm.guard_interval) { | |
776 | case GUARD_INTERVAL_1_32: | |
777 | tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); | |
778 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); | |
779 | break; | |
780 | ||
781 | case GUARD_INTERVAL_1_16: | |
782 | tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); | |
783 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2); | |
784 | break; | |
785 | ||
786 | case GUARD_INTERVAL_1_8: | |
787 | tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); | |
788 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2); | |
789 | break; | |
790 | ||
791 | case GUARD_INTERVAL_1_4: | |
792 | tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); | |
793 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2); | |
794 | break; | |
795 | ||
796 | case GUARD_INTERVAL_AUTO: | |
797 | tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2); | |
798 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); | |
799 | break; | |
800 | ||
801 | default: | |
802 | return -EINVAL; | |
803 | } | |
804 | ||
805 | // set transmission mode | |
806 | switch (fe_params->u.ofdm.transmission_mode) { | |
807 | case TRANSMISSION_MODE_2K: | |
808 | tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); | |
809 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4); | |
810 | break; | |
811 | ||
812 | case TRANSMISSION_MODE_8K: | |
813 | tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); | |
814 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4); | |
815 | break; | |
816 | ||
817 | case TRANSMISSION_MODE_AUTO: | |
818 | tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4); | |
819 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0); | |
820 | break; | |
821 | ||
822 | default: | |
823 | return -EINVAL; | |
824 | } | |
825 | ||
826 | // start the lock | |
7f5e02db | 827 | switch (state->demod_type) { |
1da177e4 LT |
828 | case TDA1004X_DEMOD_TDA10045: |
829 | tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); | |
830 | tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); | |
1da177e4 LT |
831 | break; |
832 | ||
833 | case TDA1004X_DEMOD_TDA10046: | |
834 | tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40); | |
1da177e4 LT |
835 | break; |
836 | } | |
837 | ||
7f5e02db JS |
838 | msleep(10); |
839 | ||
1da177e4 LT |
840 | return 0; |
841 | } | |
842 | ||
843 | static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params) | |
844 | { | |
845 | struct tda1004x_state* state = fe->demodulator_priv; | |
846 | dprintk("%s\n", __FUNCTION__); | |
847 | ||
848 | // inversion status | |
849 | fe_params->inversion = INVERSION_OFF; | |
7f5e02db | 850 | if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20) |
1da177e4 | 851 | fe_params->inversion = INVERSION_ON; |
7f5e02db JS |
852 | if (state->config->invert) |
853 | fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON; | |
1da177e4 LT |
854 | |
855 | // bandwidth | |
7f5e02db | 856 | switch (state->demod_type) { |
1da177e4 LT |
857 | case TDA1004X_DEMOD_TDA10045: |
858 | switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) { | |
859 | case 0x14: | |
860 | fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; | |
861 | break; | |
862 | case 0xdb: | |
863 | fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; | |
864 | break; | |
865 | case 0x4f: | |
866 | fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; | |
867 | break; | |
868 | } | |
869 | break; | |
870 | ||
871 | case TDA1004X_DEMOD_TDA10046: | |
872 | switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) { | |
873 | case 0x60: | |
874 | fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; | |
875 | break; | |
876 | case 0x6e: | |
877 | fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; | |
878 | break; | |
879 | case 0x80: | |
880 | fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; | |
881 | break; | |
882 | } | |
883 | break; | |
884 | } | |
885 | ||
886 | // FEC | |
887 | fe_params->u.ofdm.code_rate_HP = | |
888 | tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7); | |
889 | fe_params->u.ofdm.code_rate_LP = | |
890 | tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7); | |
891 | ||
892 | // constellation | |
893 | switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) { | |
894 | case 0: | |
895 | fe_params->u.ofdm.constellation = QPSK; | |
896 | break; | |
897 | case 1: | |
898 | fe_params->u.ofdm.constellation = QAM_16; | |
899 | break; | |
900 | case 2: | |
901 | fe_params->u.ofdm.constellation = QAM_64; | |
902 | break; | |
903 | } | |
904 | ||
905 | // transmission mode | |
906 | fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; | |
7f5e02db | 907 | if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10) |
1da177e4 | 908 | fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; |
1da177e4 LT |
909 | |
910 | // guard interval | |
911 | switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) { | |
912 | case 0: | |
913 | fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; | |
914 | break; | |
915 | case 1: | |
916 | fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; | |
917 | break; | |
918 | case 2: | |
919 | fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; | |
920 | break; | |
921 | case 3: | |
922 | fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; | |
923 | break; | |
924 | } | |
925 | ||
926 | // hierarchy | |
927 | switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) { | |
928 | case 0: | |
929 | fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE; | |
930 | break; | |
931 | case 1: | |
932 | fe_params->u.ofdm.hierarchy_information = HIERARCHY_1; | |
933 | break; | |
934 | case 2: | |
935 | fe_params->u.ofdm.hierarchy_information = HIERARCHY_2; | |
936 | break; | |
937 | case 3: | |
938 | fe_params->u.ofdm.hierarchy_information = HIERARCHY_4; | |
939 | break; | |
940 | } | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
945 | static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status) | |
946 | { | |
947 | struct tda1004x_state* state = fe->demodulator_priv; | |
948 | int status; | |
949 | int cber; | |
950 | int vber; | |
951 | ||
952 | dprintk("%s\n", __FUNCTION__); | |
953 | ||
954 | // read status | |
955 | status = tda1004x_read_byte(state, TDA1004X_STATUS_CD); | |
7f5e02db | 956 | if (status == -1) |
1da177e4 | 957 | return -EIO; |
1da177e4 LT |
958 | |
959 | // decode | |
960 | *fe_status = 0; | |
7f5e02db JS |
961 | if (status & 4) |
962 | *fe_status |= FE_HAS_SIGNAL; | |
963 | if (status & 2) | |
964 | *fe_status |= FE_HAS_CARRIER; | |
965 | if (status & 8) | |
966 | *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; | |
1da177e4 LT |
967 | |
968 | // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi | |
969 | // is getting anything valid | |
970 | if (!(*fe_status & FE_HAS_VITERBI)) { | |
971 | // read the CBER | |
972 | cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB); | |
7f5e02db JS |
973 | if (cber == -1) |
974 | return -EIO; | |
1da177e4 | 975 | status = tda1004x_read_byte(state, TDA1004X_CBER_MSB); |
7f5e02db JS |
976 | if (status == -1) |
977 | return -EIO; | |
1da177e4 LT |
978 | cber |= (status << 8); |
979 | tda1004x_read_byte(state, TDA1004X_CBER_RESET); | |
980 | ||
7f5e02db | 981 | if (cber != 65535) |
1da177e4 | 982 | *fe_status |= FE_HAS_VITERBI; |
1da177e4 LT |
983 | } |
984 | ||
985 | // if we DO have some valid VITERBI output, but don't already have SYNC | |
986 | // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid. | |
987 | if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) { | |
988 | // read the VBER | |
989 | vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB); | |
7f5e02db JS |
990 | if (vber == -1) |
991 | return -EIO; | |
1da177e4 | 992 | status = tda1004x_read_byte(state, TDA1004X_VBER_MID); |
7f5e02db JS |
993 | if (status == -1) |
994 | return -EIO; | |
1da177e4 LT |
995 | vber |= (status << 8); |
996 | status = tda1004x_read_byte(state, TDA1004X_VBER_MSB); | |
7f5e02db JS |
997 | if (status == -1) |
998 | return -EIO; | |
1da177e4 LT |
999 | vber |= ((status << 16) & 0x0f); |
1000 | tda1004x_read_byte(state, TDA1004X_CVBER_LUT); | |
1001 | ||
1002 | // if RS has passed some valid TS packets, then we must be | |
1003 | // getting some SYNC bytes | |
7f5e02db | 1004 | if (vber < 16632) |
1da177e4 | 1005 | *fe_status |= FE_HAS_SYNC; |
1da177e4 LT |
1006 | } |
1007 | ||
1008 | // success | |
1009 | dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status); | |
1010 | return 0; | |
1011 | } | |
1012 | ||
1013 | static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal) | |
1014 | { | |
1015 | struct tda1004x_state* state = fe->demodulator_priv; | |
1016 | int tmp; | |
1017 | int reg = 0; | |
1018 | ||
1019 | dprintk("%s\n", __FUNCTION__); | |
1020 | ||
1021 | // determine the register to use | |
7f5e02db | 1022 | switch (state->demod_type) { |
1da177e4 LT |
1023 | case TDA1004X_DEMOD_TDA10045: |
1024 | reg = TDA10045H_S_AGC; | |
1025 | break; | |
1026 | ||
1027 | case TDA1004X_DEMOD_TDA10046: | |
1028 | reg = TDA10046H_AGC_IF_LEVEL; | |
1029 | break; | |
1030 | } | |
1031 | ||
1032 | // read it | |
1033 | tmp = tda1004x_read_byte(state, reg); | |
1034 | if (tmp < 0) | |
1035 | return -EIO; | |
1036 | ||
1037 | *signal = (tmp << 8) | tmp; | |
1038 | dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal); | |
1039 | return 0; | |
1040 | } | |
1041 | ||
1042 | static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr) | |
1043 | { | |
1044 | struct tda1004x_state* state = fe->demodulator_priv; | |
1045 | int tmp; | |
1046 | ||
1047 | dprintk("%s\n", __FUNCTION__); | |
1048 | ||
1049 | // read it | |
1050 | tmp = tda1004x_read_byte(state, TDA1004X_SNR); | |
1051 | if (tmp < 0) | |
1052 | return -EIO; | |
c2026b3a | 1053 | tmp = 255 - tmp; |
1da177e4 LT |
1054 | |
1055 | *snr = ((tmp << 8) | tmp); | |
1056 | dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr); | |
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) | |
1061 | { | |
1062 | struct tda1004x_state* state = fe->demodulator_priv; | |
1063 | int tmp; | |
1064 | int tmp2; | |
1065 | int counter; | |
1066 | ||
1067 | dprintk("%s\n", __FUNCTION__); | |
1068 | ||
1069 | // read the UCBLOCKS and reset | |
1070 | counter = 0; | |
1071 | tmp = tda1004x_read_byte(state, TDA1004X_UNCOR); | |
1072 | if (tmp < 0) | |
1073 | return -EIO; | |
1074 | tmp &= 0x7f; | |
1075 | while (counter++ < 5) { | |
1076 | tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); | |
1077 | tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); | |
1078 | tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); | |
1079 | ||
1080 | tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR); | |
1081 | if (tmp2 < 0) | |
1082 | return -EIO; | |
1083 | tmp2 &= 0x7f; | |
1084 | if ((tmp2 < tmp) || (tmp2 == 0)) | |
1085 | break; | |
1086 | } | |
1087 | ||
7f5e02db | 1088 | if (tmp != 0x7f) |
1da177e4 | 1089 | *ucblocks = tmp; |
7f5e02db | 1090 | else |
1da177e4 | 1091 | *ucblocks = 0xffffffff; |
7f5e02db | 1092 | |
1da177e4 LT |
1093 | dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks); |
1094 | return 0; | |
1095 | } | |
1096 | ||
1097 | static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber) | |
1098 | { | |
1099 | struct tda1004x_state* state = fe->demodulator_priv; | |
1100 | int tmp; | |
1101 | ||
1102 | dprintk("%s\n", __FUNCTION__); | |
1103 | ||
1104 | // read it in | |
1105 | tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB); | |
7f5e02db JS |
1106 | if (tmp < 0) |
1107 | return -EIO; | |
1da177e4 LT |
1108 | *ber = tmp << 1; |
1109 | tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB); | |
7f5e02db JS |
1110 | if (tmp < 0) |
1111 | return -EIO; | |
1da177e4 LT |
1112 | *ber |= (tmp << 9); |
1113 | tda1004x_read_byte(state, TDA1004X_CBER_RESET); | |
1114 | ||
1115 | dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber); | |
1116 | return 0; | |
1117 | } | |
1118 | ||
1119 | static int tda1004x_sleep(struct dvb_frontend* fe) | |
1120 | { | |
1121 | struct tda1004x_state* state = fe->demodulator_priv; | |
1122 | ||
7f5e02db | 1123 | switch (state->demod_type) { |
1da177e4 LT |
1124 | case TDA1004X_DEMOD_TDA10045: |
1125 | tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10); | |
1126 | break; | |
1127 | ||
1128 | case TDA1004X_DEMOD_TDA10046: | |
f03cbea3 HH |
1129 | if (state->config->pll_sleep != NULL) { |
1130 | tda1004x_enable_tuner_i2c(state); | |
ecb60deb | 1131 | state->config->pll_sleep(fe); |
f03cbea3 HH |
1132 | tda1004x_disable_tuner_i2c(state); |
1133 | } | |
1134 | tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1); | |
1da177e4 LT |
1135 | break; |
1136 | } | |
1137 | state->initialised = 0; | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) | |
1143 | { | |
1144 | fesettings->min_delay_ms = 800; | |
f03cbea3 HH |
1145 | /* Drift compensation makes no sense for DVB-T */ |
1146 | fesettings->step_size = 0; | |
1147 | fesettings->max_drift = 0; | |
1da177e4 LT |
1148 | return 0; |
1149 | } | |
1150 | ||
1151 | static void tda1004x_release(struct dvb_frontend* fe) | |
1152 | { | |
7f5e02db | 1153 | struct tda1004x_state *state = fe->demodulator_priv; |
1da177e4 LT |
1154 | kfree(state); |
1155 | } | |
1156 | ||
1da177e4 | 1157 | static struct dvb_frontend_ops tda10045_ops = { |
1da177e4 LT |
1158 | .info = { |
1159 | .name = "Philips TDA10045H DVB-T", | |
1160 | .type = FE_OFDM, | |
1161 | .frequency_min = 51000000, | |
1162 | .frequency_max = 858000000, | |
1163 | .frequency_stepsize = 166667, | |
1164 | .caps = | |
1165 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
1166 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
1167 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | | |
1168 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | |
1169 | }, | |
1170 | ||
1171 | .release = tda1004x_release, | |
1172 | ||
1173 | .init = tda10045_init, | |
1174 | .sleep = tda1004x_sleep, | |
1175 | ||
1176 | .set_frontend = tda1004x_set_fe, | |
1177 | .get_frontend = tda1004x_get_fe, | |
1178 | .get_tune_settings = tda1004x_get_tune_settings, | |
1179 | ||
1180 | .read_status = tda1004x_read_status, | |
1181 | .read_ber = tda1004x_read_ber, | |
1182 | .read_signal_strength = tda1004x_read_signal_strength, | |
1183 | .read_snr = tda1004x_read_snr, | |
1184 | .read_ucblocks = tda1004x_read_ucblocks, | |
1185 | }; | |
1186 | ||
7f5e02db JS |
1187 | struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config, |
1188 | struct i2c_adapter* i2c) | |
1189 | { | |
1190 | struct tda1004x_state *state; | |
1191 | ||
1192 | /* allocate memory for the internal state */ | |
1193 | state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL); | |
1194 | if (!state) | |
1195 | return NULL; | |
1196 | ||
1197 | /* setup the state */ | |
1198 | state->config = config; | |
1199 | state->i2c = i2c; | |
1200 | memcpy(&state->ops, &tda10045_ops, sizeof(struct dvb_frontend_ops)); | |
1201 | state->initialised = 0; | |
1202 | state->demod_type = TDA1004X_DEMOD_TDA10045; | |
1203 | ||
1204 | /* check if the demod is there */ | |
1205 | if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) { | |
1206 | kfree(state); | |
1207 | return NULL; | |
1208 | } | |
1209 | ||
1210 | /* create dvb_frontend */ | |
1211 | state->frontend.ops = &state->ops; | |
1212 | state->frontend.demodulator_priv = state; | |
1213 | return &state->frontend; | |
1214 | } | |
1da177e4 | 1215 | |
7f5e02db | 1216 | static struct dvb_frontend_ops tda10046_ops = { |
1da177e4 LT |
1217 | .info = { |
1218 | .name = "Philips TDA10046H DVB-T", | |
1219 | .type = FE_OFDM, | |
1220 | .frequency_min = 51000000, | |
1221 | .frequency_max = 858000000, | |
1222 | .frequency_stepsize = 166667, | |
1223 | .caps = | |
1224 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
1225 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
1226 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | | |
1227 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | |
1228 | }, | |
1229 | ||
1230 | .release = tda1004x_release, | |
1231 | ||
1232 | .init = tda10046_init, | |
1233 | .sleep = tda1004x_sleep, | |
1234 | ||
1235 | .set_frontend = tda1004x_set_fe, | |
1236 | .get_frontend = tda1004x_get_fe, | |
1237 | .get_tune_settings = tda1004x_get_tune_settings, | |
1238 | ||
1239 | .read_status = tda1004x_read_status, | |
1240 | .read_ber = tda1004x_read_ber, | |
1241 | .read_signal_strength = tda1004x_read_signal_strength, | |
1242 | .read_snr = tda1004x_read_snr, | |
1243 | .read_ucblocks = tda1004x_read_ucblocks, | |
1244 | }; | |
1245 | ||
7f5e02db JS |
1246 | struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config, |
1247 | struct i2c_adapter* i2c) | |
1248 | { | |
1249 | struct tda1004x_state *state; | |
1250 | ||
1251 | /* allocate memory for the internal state */ | |
1252 | state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL); | |
1253 | if (!state) | |
1254 | return NULL; | |
1255 | ||
1256 | /* setup the state */ | |
1257 | state->config = config; | |
1258 | state->i2c = i2c; | |
1259 | memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops)); | |
1260 | state->initialised = 0; | |
1261 | state->demod_type = TDA1004X_DEMOD_TDA10046; | |
1262 | ||
1263 | /* check if the demod is there */ | |
1264 | if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) { | |
1265 | kfree(state); | |
1266 | return NULL; | |
1267 | } | |
1268 | ||
1269 | /* create dvb_frontend */ | |
1270 | state->frontend.ops = &state->ops; | |
1271 | state->frontend.demodulator_priv = state; | |
1272 | return &state->frontend; | |
1273 | } | |
1274 | ||
1da177e4 LT |
1275 | module_param(debug, int, 0644); |
1276 | MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); | |
1277 | ||
1278 | MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator"); | |
1279 | MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach"); | |
1280 | MODULE_LICENSE("GPL"); | |
1281 | ||
1282 | EXPORT_SYMBOL(tda10045_attach); | |
1283 | EXPORT_SYMBOL(tda10046_attach); | |
1284 | EXPORT_SYMBOL(tda1004x_write_byte); |