projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
V4L/DVB (6957): tda18271: fail table lookups if frequency is out of range
[deliverable/linux.git] / drivers / media / dvb / frontends / tda18271-fe.c
CommitLineData
5bea1cd3 1/*
6ca04de3 2 tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner
5bea1cd3
MK		 3
4 Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org)
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19*/
20
5bea1cd3
MK		 21#include <linux/delay.h>
22#include <linux/videodev2.h>
6ca04de3 23#include "tda18271-priv.h"
5bea1cd3 24
b5f3e1e1 25int tda18271_debug;
54465b08 26module_param_named(debug, tda18271_debug, int, 0644);
293da0ec 27MODULE_PARM_DESC(debug, "set debug level (info=1, map=2, reg=4 (or-able))");
5bea1cd3 28
5bea1cd3
MK		 29/*---------------------------------------------------------------------*/
30
7d11c53c
MK		 31static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
32{
33 struct tda18271_priv *priv = fe->tuner_priv;
e435f95c 34 enum tda18271_i2c_gate gate;
7d11c53c
MK		 35 int ret = 0;
36
e435f95c
MK		 37 switch (priv->gate) {
38 case TDA18271_GATE_DIGITAL:
39 case TDA18271_GATE_ANALOG:
40 gate = priv->gate;
41 break;
42 case TDA18271_GATE_AUTO:
43 default:
44 switch (priv->mode) {
45 case TDA18271_DIGITAL:
46 gate = TDA18271_GATE_DIGITAL;
47 break;
48 case TDA18271_ANALOG:
49 default:
50 gate = TDA18271_GATE_ANALOG;
51 break;
52 }
53 }
54
55 switch (gate) {
56 case TDA18271_GATE_ANALOG:
bc3e5c7f
MK		 57 if (fe->ops.analog_ops.i2c_gate_ctrl)
58 ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
7d11c53c 59 break;
e435f95c 60 case TDA18271_GATE_DIGITAL:
7d11c53c
MK		 61 if (fe->ops.i2c_gate_ctrl)
62 ret = fe->ops.i2c_gate_ctrl(fe, enable);
63 break;
e435f95c
MK		 64 default:
65 ret = -EINVAL;
66 break;
7d11c53c
MK		 67 }
68
69 return ret;
70};
71
5bea1cd3
MK		 72/*---------------------------------------------------------------------*/
73
74static void tda18271_dump_regs(struct dvb_frontend *fe)
75{
76 struct tda18271_priv *priv = fe->tuner_priv;
77 unsigned char *regs = priv->tda18271_regs;
78
182519f4
MK		 79 tda_reg("=== TDA18271 REG DUMP ===\n");
80 tda_reg("ID_BYTE = 0x%02x\n", 0xff & regs[R_ID]);
81 tda_reg("THERMO_BYTE = 0x%02x\n", 0xff & regs[R_TM]);
82 tda_reg("POWER_LEVEL_BYTE = 0x%02x\n", 0xff & regs[R_PL]);
83 tda_reg("EASY_PROG_BYTE_1 = 0x%02x\n", 0xff & regs[R_EP1]);
84 tda_reg("EASY_PROG_BYTE_2 = 0x%02x\n", 0xff & regs[R_EP2]);
85 tda_reg("EASY_PROG_BYTE_3 = 0x%02x\n", 0xff & regs[R_EP3]);
86 tda_reg("EASY_PROG_BYTE_4 = 0x%02x\n", 0xff & regs[R_EP4]);
87 tda_reg("EASY_PROG_BYTE_5 = 0x%02x\n", 0xff & regs[R_EP5]);
88 tda_reg("CAL_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_CPD]);
89 tda_reg("CAL_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_CD1]);
90 tda_reg("CAL_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_CD2]);
91 tda_reg("CAL_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_CD3]);
92 tda_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
93 tda_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]);
94 tda_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]);
95 tda_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]);
5bea1cd3
MK		 96}
97
98static void tda18271_read_regs(struct dvb_frontend *fe)
99{
100 struct tda18271_priv *priv = fe->tuner_priv;
101 unsigned char *regs = priv->tda18271_regs;
102 unsigned char buf = 0x00;
103 int ret;
104 struct i2c_msg msg[] = {
105 { .addr = priv->i2c_addr, .flags = 0,
106 .buf = &buf, .len = 1 },
107 { .addr = priv->i2c_addr, .flags = I2C_M_RD,
108 .buf = regs, .len = 16 }
109 };
110
7d11c53c 111 tda18271_i2c_gate_ctrl(fe, 1);
5bea1cd3
MK		 112
113 /* read all registers */
114 ret = i2c_transfer(priv->i2c_adap, msg, 2);
115
7d11c53c 116 tda18271_i2c_gate_ctrl(fe, 0);
5bea1cd3
MK		 117
118 if (ret != 2)
182519f4 119 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
5bea1cd3 120
293da0ec 121 if (tda18271_debug & DBG_REG)
5bea1cd3
MK		 122 tda18271_dump_regs(fe);
123}
124
125static void tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
126{
127 struct tda18271_priv *priv = fe->tuner_priv;
128 unsigned char *regs = priv->tda18271_regs;
129 unsigned char buf[TDA18271_NUM_REGS+1];
130 struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
131 .buf = buf, .len = len+1 };
132 int i, ret;
133
134 BUG_ON((len == 0) || (idx+len > sizeof(buf)));
135
136 buf[0] = idx;
137 for (i = 1; i <= len; i++) {
138 buf[i] = regs[idx-1+i];
139 }
140
7d11c53c 141 tda18271_i2c_gate_ctrl(fe, 1);
5bea1cd3
MK		 142
143 /* write registers */
144 ret = i2c_transfer(priv->i2c_adap, &msg, 1);
145
7d11c53c 146 tda18271_i2c_gate_ctrl(fe, 0);
5bea1cd3
MK		 147
148 if (ret != 1)
182519f4 149 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
5bea1cd3
MK		 150}
151
152/*---------------------------------------------------------------------*/
153
22ee1250 154static int tda18271_init_regs(struct dvb_frontend *fe)
5bea1cd3
MK		 155{
156 struct tda18271_priv *priv = fe->tuner_priv;
157 unsigned char *regs = priv->tda18271_regs;
158
182519f4
MK		 159 tda_dbg("initializing registers for device @ %d-%04x\n",
160 i2c_adapter_id(priv->i2c_adap), priv->i2c_addr);
5bea1cd3
MK		 161
162 /* initialize registers */
163 regs[R_ID] = 0x83;
164 regs[R_TM] = 0x08;
165 regs[R_PL] = 0x80;
166 regs[R_EP1] = 0xc6;
167 regs[R_EP2] = 0xdf;
168 regs[R_EP3] = 0x16;
169 regs[R_EP4] = 0x60;
170 regs[R_EP5] = 0x80;
171 regs[R_CPD] = 0x80;
172 regs[R_CD1] = 0x00;
173 regs[R_CD2] = 0x00;
174 regs[R_CD3] = 0x00;
175 regs[R_MPD] = 0x00;
176 regs[R_MD1] = 0x00;
177 regs[R_MD2] = 0x00;
178 regs[R_MD3] = 0x00;
179 regs[R_EB1] = 0xff;
180 regs[R_EB2] = 0x01;
181 regs[R_EB3] = 0x84;
182 regs[R_EB4] = 0x41;
183 regs[R_EB5] = 0x01;
184 regs[R_EB6] = 0x84;
185 regs[R_EB7] = 0x40;
186 regs[R_EB8] = 0x07;
187 regs[R_EB9] = 0x00;
188 regs[R_EB10] = 0x00;
189 regs[R_EB11] = 0x96;
190 regs[R_EB12] = 0x0f;
191 regs[R_EB13] = 0xc1;
192 regs[R_EB14] = 0x00;
193 regs[R_EB15] = 0x8f;
194 regs[R_EB16] = 0x00;
195 regs[R_EB17] = 0x00;
196 regs[R_EB18] = 0x00;
197 regs[R_EB19] = 0x00;
198 regs[R_EB20] = 0x20;
199 regs[R_EB21] = 0x33;
200 regs[R_EB22] = 0x48;
201 regs[R_EB23] = 0xb0;
202
203 tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
204 /* setup AGC1 & AGC2 */
205 regs[R_EB17] = 0x00;
206 tda18271_write_regs(fe, R_EB17, 1);
207 regs[R_EB17] = 0x03;
208 tda18271_write_regs(fe, R_EB17, 1);
209 regs[R_EB17] = 0x43;
210 tda18271_write_regs(fe, R_EB17, 1);
211 regs[R_EB17] = 0x4c;
212 tda18271_write_regs(fe, R_EB17, 1);
213
214 regs[R_EB20] = 0xa0;
215 tda18271_write_regs(fe, R_EB20, 1);
216 regs[R_EB20] = 0xa7;
217 tda18271_write_regs(fe, R_EB20, 1);
218 regs[R_EB20] = 0xe7;
219 tda18271_write_regs(fe, R_EB20, 1);
220 regs[R_EB20] = 0xec;
221 tda18271_write_regs(fe, R_EB20, 1);
222
223 /* image rejection calibration */
224
225 /* low-band */
226 regs[R_EP3] = 0x1f;
227 regs[R_EP4] = 0x66;
228 regs[R_EP5] = 0x81;
229 regs[R_CPD] = 0xcc;
230 regs[R_CD1] = 0x6c;
231 regs[R_CD2] = 0x00;
232 regs[R_CD3] = 0x00;
233 regs[R_MPD] = 0xcd;
234 regs[R_MD1] = 0x77;
235 regs[R_MD2] = 0x08;
236 regs[R_MD3] = 0x00;
237
238 tda18271_write_regs(fe, R_EP3, 11);
239 msleep(5); /* pll locking */
240
241 regs[R_EP1] = 0xc6;
242 tda18271_write_regs(fe, R_EP1, 1);
243 msleep(5); /* wanted low measurement */
244
245 regs[R_EP3] = 0x1f;
246 regs[R_EP4] = 0x66;
247 regs[R_EP5] = 0x85;
248 regs[R_CPD] = 0xcb;
249 regs[R_CD1] = 0x66;
250 regs[R_CD2] = 0x70;
251 regs[R_CD3] = 0x00;
252
253 tda18271_write_regs(fe, R_EP3, 7);
254 msleep(5); /* pll locking */
255
256 regs[R_EP2] = 0xdf;
257 tda18271_write_regs(fe, R_EP2, 1);
258 msleep(30); /* image low optimization completion */
259
260 /* mid-band */
261 regs[R_EP3] = 0x1f;
262 regs[R_EP4] = 0x66;
263 regs[R_EP5] = 0x82;
264 regs[R_CPD] = 0xa8;
265 regs[R_CD1] = 0x66;
266 regs[R_CD2] = 0x00;
267 regs[R_CD3] = 0x00;
268 regs[R_MPD] = 0xa9;
269 regs[R_MD1] = 0x73;
270 regs[R_MD2] = 0x1a;
271 regs[R_MD3] = 0x00;
272
273 tda18271_write_regs(fe, R_EP3, 11);
274 msleep(5); /* pll locking */
275
276 regs[R_EP1] = 0xc6;
277 tda18271_write_regs(fe, R_EP1, 1);
278 msleep(5); /* wanted mid measurement */
279
280 regs[R_EP3] = 0x1f;
281 regs[R_EP4] = 0x66;
282 regs[R_EP5] = 0x86;
283 regs[R_CPD] = 0xa8;
284 regs[R_CD1] = 0x66;
285 regs[R_CD2] = 0xa0;
286 regs[R_CD3] = 0x00;
287
288 tda18271_write_regs(fe, R_EP3, 7);
289 msleep(5); /* pll locking */
290
291 regs[R_EP2] = 0xdf;
292 tda18271_write_regs(fe, R_EP2, 1);
293 msleep(30); /* image mid optimization completion */
294
295 /* high-band */
296 regs[R_EP3] = 0x1f;
297 regs[R_EP4] = 0x66;
298 regs[R_EP5] = 0x83;
299 regs[R_CPD] = 0x98;
300 regs[R_CD1] = 0x65;
301 regs[R_CD2] = 0x00;
302 regs[R_CD3] = 0x00;
303 regs[R_MPD] = 0x99;
304 regs[R_MD1] = 0x71;
305 regs[R_MD2] = 0xcd;
306 regs[R_MD3] = 0x00;
307
308 tda18271_write_regs(fe, R_EP3, 11);
309 msleep(5); /* pll locking */
310
311 regs[R_EP1] = 0xc6;
312 tda18271_write_regs(fe, R_EP1, 1);
313 msleep(5); /* wanted high measurement */
314
315 regs[R_EP3] = 0x1f;
316 regs[R_EP4] = 0x66;
317 regs[R_EP5] = 0x87;
318 regs[R_CPD] = 0x98;
319 regs[R_CD1] = 0x65;
320 regs[R_CD2] = 0x50;
321 regs[R_CD3] = 0x00;
322
323 tda18271_write_regs(fe, R_EP3, 7);
324 msleep(5); /* pll locking */
325
326 regs[R_EP2] = 0xdf;
327
328 tda18271_write_regs(fe, R_EP2, 1);
329 msleep(30); /* image high optimization completion */
330
331 regs[R_EP4] = 0x64;
332 tda18271_write_regs(fe, R_EP4, 1);
333
334 regs[R_EP1] = 0xc6;
335 tda18271_write_regs(fe, R_EP1, 1);
22ee1250
MK		 336
337 return 0;
5bea1cd3
MK		 338}
339
efce8410
MK		 340static int tda18271_init(struct dvb_frontend *fe)
341{
342 struct tda18271_priv *priv = fe->tuner_priv;
343 unsigned char *regs = priv->tda18271_regs;
344
345 tda18271_read_regs(fe);
346
347 /* test IR_CAL_OK to see if we need init */
348 if ((regs[R_EP1] & 0x08) == 0)
349 tda18271_init_regs(fe);
350
351 return 0;
352}
353
fe0bf6d7
MK		 354static int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
355{
356 /* Sets Main Post-Divider & Divider bytes, but does not write them */
357 struct tda18271_priv *priv = fe->tuner_priv;
358 unsigned char *regs = priv->tda18271_regs;
359 u8 d, pd;
360 u32 div;
361
2f27dfc9
MK		 362 int ret = tda18271_lookup_pll_map(MAIN_PLL, &freq, &pd, &d);
363 if (ret < 0)
364 goto fail;
fe0bf6d7
MK		 365
366 regs[R_MPD] = (0x77 & pd);
367
368 switch (priv->mode) {
369 case TDA18271_ANALOG:
370 regs[R_MPD] &= ~0x08;
371 break;
372 case TDA18271_DIGITAL:
373 regs[R_MPD] |= 0x08;
374 break;
375 }
376
377 div = ((d * (freq / 1000)) << 7) / 125;
378
379 regs[R_MD1] = 0x7f & (div >> 16);
380 regs[R_MD2] = 0xff & (div >> 8);
381 regs[R_MD3] = 0xff & div;
2f27dfc9
MK		 382fail:
383 return ret;
fe0bf6d7
MK		 384}
385
386static int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
387{
388 /* Sets Cal Post-Divider & Divider bytes, but does not write them */
389 struct tda18271_priv *priv = fe->tuner_priv;
390 unsigned char *regs = priv->tda18271_regs;
391 u8 d, pd;
392 u32 div;
393
2f27dfc9
MK		 394 int ret = tda18271_lookup_pll_map(CAL_PLL, &freq, &pd, &d);
395 if (ret < 0)
396 goto fail;
fe0bf6d7
MK		 397
398 regs[R_CPD] = pd;
399
400 div = ((d * (freq / 1000)) << 7) / 125;
401
402 regs[R_CD1] = 0x7f & (div >> 16);
403 regs[R_CD2] = 0xff & (div >> 8);
404 regs[R_CD3] = 0xff & div;
2f27dfc9
MK		 405fail:
406 return ret;
fe0bf6d7
MK		 407}
408
b92bf0f6
MK		 409static int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq)
410{
411 /* Sets BP filter bits, but does not write them */
412 struct tda18271_priv *priv = fe->tuner_priv;
413 unsigned char *regs = priv->tda18271_regs;
414 u8 val;
415
416 int ret = tda18271_lookup_map(BP_FILTER, freq, &val);
417 if (ret < 0)
418 goto fail;
419
420 regs[R_EP1] &= ~0x07; /* clear bp filter bits */
421 regs[R_EP1] |= (0x07 & val);
422fail:
423 return ret;
424}
425
426static int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq)
427{
428 /* Sets K & M bits, but does not write them */
429 struct tda18271_priv *priv = fe->tuner_priv;
430 unsigned char *regs = priv->tda18271_regs;
431 u8 val;
432
433 int ret = tda18271_lookup_map(RF_CAL_KMCO, freq, &val);
434 if (ret < 0)
435 goto fail;
436
437 regs[R_EB13] &= ~0x7c; /* clear k & m bits */
438 regs[R_EB13] |= (0x7c & val);
439fail:
440 return ret;
441}
442
443static int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq)
444{
445 /* Sets RF Band bits, but does not write them */
446 struct tda18271_priv *priv = fe->tuner_priv;
447 unsigned char *regs = priv->tda18271_regs;
448 u8 val;
449
450 int ret = tda18271_lookup_map(RF_BAND, freq, &val);
451 if (ret < 0)
452 goto fail;
453
454 regs[R_EP2] &= ~0xe0; /* clear rf band bits */
455 regs[R_EP2] |= (0xe0 & (val << 5));
456fail:
457 return ret;
458}
459
460static int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq)
461{
462 /* Sets Gain Taper bits, but does not write them */
463 struct tda18271_priv *priv = fe->tuner_priv;
464 unsigned char *regs = priv->tda18271_regs;
465 u8 val;
466
467 int ret = tda18271_lookup_map(GAIN_TAPER, freq, &val);
468 if (ret < 0)
469 goto fail;
470
471 regs[R_EP2] &= ~0x1f; /* clear gain taper bits */
472 regs[R_EP2] |= (0x1f & val);
473fail:
474 return ret;
475}
476
477static int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq)
478{
479 /* Sets IR Meas bits, but does not write them */
480 struct tda18271_priv *priv = fe->tuner_priv;
481 unsigned char *regs = priv->tda18271_regs;
482 u8 val;
483
484 int ret = tda18271_lookup_map(IR_MEASURE, freq, &val);
485 if (ret < 0)
486 goto fail;
487
488 regs[R_EP5] &= ~0x07;
489 regs[R_EP5] |= (0x07 & val);
490fail:
491 return ret;
492}
493
494static int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq)
495{
496 /* Sets RF Cal bits, but does not write them */
497 struct tda18271_priv *priv = fe->tuner_priv;
498 unsigned char *regs = priv->tda18271_regs;
499 u8 val;
500
501 int ret = tda18271_lookup_map(RF_CAL, freq, &val);
502 if (ret < 0)
503 goto fail;
504
b92bf0f6
MK		 505 regs[R_EB14] = val;
506fail:
507 return ret;
508}
509
5bea1cd3
MK		 510static int tda18271_tune(struct dvb_frontend *fe,
511 u32 ifc, u32 freq, u32 bw, u8 std)
512{
513 struct tda18271_priv *priv = fe->tuner_priv;
514 unsigned char *regs = priv->tda18271_regs;
fe0bf6d7 515 u32 N = 0;
5bea1cd3 516
1457263e 517 tda18271_init(fe);
5bea1cd3 518
182519f4 519 tda_dbg("freq = %d, ifc = %d\n", freq, ifc);
5bea1cd3 520
5bea1cd3
MK		 521 /* RF tracking filter calibration */
522
523 /* calculate BP_Filter */
b92bf0f6 524 tda18271_calc_bp_filter(fe, &freq);
5bea1cd3
MK		 525 tda18271_write_regs(fe, R_EP1, 1);
526
527 regs[R_EB4] &= 0x07;
528 regs[R_EB4] |= 0x60;
529 tda18271_write_regs(fe, R_EB4, 1);
530
531 regs[R_EB7] = 0x60;
532 tda18271_write_regs(fe, R_EB7, 1);
533
534 regs[R_EB14] = 0x00;
535 tda18271_write_regs(fe, R_EB14, 1);
536
537 regs[R_EB20] = 0xcc;
538 tda18271_write_regs(fe, R_EB20, 1);
539
540 /* set CAL mode to RF tracking filter calibration */
26501a70 541 regs[R_EP4] |= 0x03;
5bea1cd3
MK		 542
543 /* calculate CAL PLL */
544
545 switch (priv->mode) {
546 case TDA18271_ANALOG:
547 N = freq - 1250000;
548 break;
549 case TDA18271_DIGITAL:
550 N = freq + bw / 2;
551 break;
552 }
553
fe0bf6d7 554 tda18271_calc_cal_pll(fe, N);
5bea1cd3
MK		 555
556 /* calculate MAIN PLL */
557
558 switch (priv->mode) {
559 case TDA18271_ANALOG:
560 N = freq - 250000;
561 break;
562 case TDA18271_DIGITAL:
563 N = freq + bw / 2 + 1000000;
564 break;
565 }
566
fe0bf6d7 567 tda18271_calc_main_pll(fe, N);
5bea1cd3
MK		 568
569 tda18271_write_regs(fe, R_EP3, 11);
570 msleep(5); /* RF tracking filter calibration initialization */
571
572 /* search for K,M,CO for RF Calibration */
b92bf0f6 573 tda18271_calc_km(fe, &freq);
5bea1cd3
MK		 574 tda18271_write_regs(fe, R_EB13, 1);
575
576 /* search for RF_BAND */
b92bf0f6 577 tda18271_calc_rf_band(fe, &freq);
5bea1cd3
MK		 578
579 /* search for Gain_Taper */
b92bf0f6 580 tda18271_calc_gain_taper(fe, &freq);
5bea1cd3
MK		 581
582 tda18271_write_regs(fe, R_EP2, 1);
583 tda18271_write_regs(fe, R_EP1, 1);
584 tda18271_write_regs(fe, R_EP2, 1);
585 tda18271_write_regs(fe, R_EP1, 1);
586
587 regs[R_EB4] &= 0x07;
588 regs[R_EB4] |= 0x40;
589 tda18271_write_regs(fe, R_EB4, 1);
590
591 regs[R_EB7] = 0x40;
592 tda18271_write_regs(fe, R_EB7, 1);
593 msleep(10);
594
595 regs[R_EB20] = 0xec;
596 tda18271_write_regs(fe, R_EB20, 1);
597 msleep(60); /* RF tracking filter calibration completion */
598
599 regs[R_EP4] &= ~0x03; /* set cal mode to normal */
600 tda18271_write_regs(fe, R_EP4, 1);
601
602 tda18271_write_regs(fe, R_EP1, 1);
603
b92bf0f6
MK		 604 /* RF tracking filter correction for VHF_Low band */
605 if (0 == tda18271_calc_rf_cal(fe, &freq))
5bea1cd3 606 tda18271_write_regs(fe, R_EB14, 1);
5bea1cd3
MK		 607
608 /* Channel Configuration */
609
610 switch (priv->mode) {
611 case TDA18271_ANALOG:
612 regs[R_EB22] = 0x2c;
613 break;
614 case TDA18271_DIGITAL:
615 regs[R_EB22] = 0x37;
616 break;
617 }
618 tda18271_write_regs(fe, R_EB22, 1);
619
620 regs[R_EP1] |= 0x40; /* set dis power level on */
621
622 /* set standard */
623 regs[R_EP3] &= ~0x1f; /* clear std bits */
624
625 /* see table 22 */
626 regs[R_EP3] |= std;
627
5bea1cd3
MK		 628 regs[R_EP4] &= ~0x03; /* set cal mode to normal */
629
630 regs[R_EP4] &= ~0x1c; /* clear if level bits */
631 switch (priv->mode) {
632 case TDA18271_ANALOG:
633 regs[R_MPD] &= ~0x80; /* IF notch = 0 */
634 break;
635 case TDA18271_DIGITAL:
636 regs[R_EP4] |= 0x04;
637 regs[R_MPD] |= 0x80;
638 break;
639 }
640
641 regs[R_EP4] &= ~0x80; /* turn this bit on only for fm */
642
b92bf0f6
MK		 643 /* image rejection validity */
644 tda18271_calc_ir_measure(fe, &freq);
5bea1cd3
MK		 645
646 /* calculate MAIN PLL */
647 N = freq + ifc;
648
fe0bf6d7 649 tda18271_calc_main_pll(fe, N);
5bea1cd3
MK		 650
651 tda18271_write_regs(fe, R_TM, 15);
652 msleep(5);
6ca04de3 653
5bea1cd3
MK		 654 return 0;
655}
656
657/* ------------------------------------------------------------------ */
658
659static int tda18271_set_params(struct dvb_frontend *fe,
660 struct dvb_frontend_parameters *params)
661{
662 struct tda18271_priv *priv = fe->tuner_priv;
663 u8 std;
664 u32 bw, sgIF = 0;
665
666 u32 freq = params->frequency;
667
668 priv->mode = TDA18271_DIGITAL;
669
670 /* see table 22 */
671 if (fe->ops.info.type == FE_ATSC) {
672 switch (params->u.vsb.modulation) {
673 case VSB_8:
674 case VSB_16:
675 std = 0x1b; /* device-specific (spec says 0x1c) */
676 sgIF = 5380000;
677 break;
678 case QAM_64:
679 case QAM_256:
680 std = 0x18; /* device-specific (spec says 0x1d) */
681 sgIF = 4000000;
682 break;
683 default:
182519f4 684 tda_warn("modulation not set!\n");
5bea1cd3
MK		 685 return -EINVAL;
686 }
14e3c152
MK		 687#if 0
688 /* userspace request is already center adjusted */
5bea1cd3 689 freq += 1750000; /* Adjust to center (+1.75MHZ) */
14e3c152 690#endif
5bea1cd3
MK		 691 bw = 6000000;
692 } else if (fe->ops.info.type == FE_OFDM) {
693 switch (params->u.ofdm.bandwidth) {
694 case BANDWIDTH_6_MHZ:
6ca04de3 695 std = 0x1b; /* device-specific (spec says 0x1c) */
5bea1cd3 696 bw = 6000000;
6ca04de3 697 sgIF = 3300000;
5bea1cd3
MK		 698 break;
699 case BANDWIDTH_7_MHZ:
6ca04de3 700 std = 0x19; /* device-specific (spec says 0x1d) */
5bea1cd3 701 bw = 7000000;
6ca04de3 702 sgIF = 3800000;
5bea1cd3
MK		 703 break;
704 case BANDWIDTH_8_MHZ:
6ca04de3 705 std = 0x1a; /* device-specific (spec says 0x1e) */
5bea1cd3 706 bw = 8000000;
6ca04de3 707 sgIF = 4300000;
5bea1cd3
MK		 708 break;
709 default:
182519f4 710 tda_warn("bandwidth not set!\n");
5bea1cd3
MK		 711 return -EINVAL;
712 }
713 } else {
182519f4 714 tda_warn("modulation type not supported!\n");
5bea1cd3
MK		 715 return -EINVAL;
716 }
717
718 return tda18271_tune(fe, sgIF, freq, bw, std);
719}
720
721static int tda18271_set_analog_params(struct dvb_frontend *fe,
722 struct analog_parameters *params)
723{
724 struct tda18271_priv *priv = fe->tuner_priv;
725 u8 std;
726 unsigned int sgIF;
727 char *mode;
728
729 priv->mode = TDA18271_ANALOG;
730
731 /* see table 22 */
732 if (params->std & V4L2_STD_MN) {
733 std = 0x0d;
734 sgIF = 92;
735 mode = "MN";
736 } else if (params->std & V4L2_STD_B) {
737 std = 0x0e;
738 sgIF = 108;
739 mode = "B";
740 } else if (params->std & V4L2_STD_GH) {
741 std = 0x0f;
742 sgIF = 124;
743 mode = "GH";
744 } else if (params->std & V4L2_STD_PAL_I) {
745 std = 0x0f;
746 sgIF = 124;
747 mode = "I";
748 } else if (params->std & V4L2_STD_DK) {
749 std = 0x0f;
750 sgIF = 124;
751 mode = "DK";
752 } else if (params->std & V4L2_STD_SECAM_L) {
753 std = 0x0f;
754 sgIF = 124;
755 mode = "L";
756 } else if (params->std & V4L2_STD_SECAM_LC) {
757 std = 0x0f;
758 sgIF = 20;
759 mode = "LC";
760 } else {
761 std = 0x0f;
762 sgIF = 124;
763 mode = "xx";
764 }
765
766 if (params->mode == V4L2_TUNER_RADIO)
767 sgIF = 88; /* if frequency is 5.5 MHz */
768
182519f4 769 tda_dbg("setting tda18271 to system %s\n", mode);
5bea1cd3
MK		 770
771 return tda18271_tune(fe, sgIF * 62500, params->frequency * 62500,
772 0, std);
773}
774
775static int tda18271_release(struct dvb_frontend *fe)
776{
777 kfree(fe->tuner_priv);
778 fe->tuner_priv = NULL;
779 return 0;
780}
781
782static int tda18271_get_frequency(struct dvb_frontend *fe, u32 *frequency)
783{
784 struct tda18271_priv *priv = fe->tuner_priv;
785 *frequency = priv->frequency;
786 return 0;
787}
788
789static int tda18271_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
790{
791 struct tda18271_priv *priv = fe->tuner_priv;
792 *bandwidth = priv->bandwidth;
793 return 0;
794}
795
49e7aaf0
MK		 796static int tda18271_get_id(struct dvb_frontend *fe)
797{
798 struct tda18271_priv *priv = fe->tuner_priv;
799 unsigned char *regs = priv->tda18271_regs;
800 char *name;
801 int ret = 0;
802
803 tda18271_read_regs(fe);
804
805 switch (regs[R_ID] & 0x7f) {
806 case 3:
807 name = "TDA18271HD/C1";
808 break;
809 case 4:
810 name = "TDA18271HD/C2";
811 ret = -EPROTONOSUPPORT;
812 break;
813 default:
814 name = "Unknown device";
815 ret = -EINVAL;
816 break;
817 }
818
182519f4 819 tda_info("%s detected @ %d-%04x%s\n", name,
49e7aaf0
MK		 820 i2c_adapter_id(priv->i2c_adap), priv->i2c_addr,
821 (0 == ret) ? "" : ", device not supported.");
822
823 return ret;
824}
825
5bea1cd3
MK		 826static struct dvb_tuner_ops tda18271_tuner_ops = {
827 .info = {
828 .name = "NXP TDA18271HD",
829 .frequency_min = 45000000,
830 .frequency_max = 864000000,
831 .frequency_step = 62500
832 },
efce8410 833 .init = tda18271_init,
5bea1cd3
MK		 834 .set_params = tda18271_set_params,
835 .set_analog_params = tda18271_set_analog_params,
836 .release = tda18271_release,
837 .get_frequency = tda18271_get_frequency,
838 .get_bandwidth = tda18271_get_bandwidth,
839};
840
841struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
e435f95c
MK		 842 struct i2c_adapter *i2c,
843 enum tda18271_i2c_gate gate)
5bea1cd3
MK		 844{
845 struct tda18271_priv *priv = NULL;
846
5bea1cd3
MK		 847 priv = kzalloc(sizeof(struct tda18271_priv), GFP_KERNEL);
848 if (priv == NULL)
849 return NULL;
850
851 priv->i2c_addr = addr;
852 priv->i2c_adap = i2c;
e435f95c 853 priv->gate = gate;
5bea1cd3 854
49e7aaf0
MK		 855 fe->tuner_priv = priv;
856
857 if (tda18271_get_id(fe) < 0)
858 goto fail;
859
5bea1cd3
MK		 860 memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops,
861 sizeof(struct dvb_tuner_ops));
862
efce8410
MK		 863 tda18271_init_regs(fe);
864
5bea1cd3 865 return fe;
49e7aaf0
MK		 866fail:
867 tda18271_release(fe);
868 return NULL;
5bea1cd3
MK		 869}
870EXPORT_SYMBOL_GPL(tda18271_attach);
871MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver");
872MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
873MODULE_LICENSE("GPL");
874
875/*
876 * Overrides for Emacs so that we follow Linus's tabbing style.
877 * ---------------------------------------------------------------------------
878 * Local variables:
879 * c-basic-offset: 8
880 * End:
881 */
Linux kernel - Deliverables
This page took 0.096664 seconds and 5 git commands to generate.