Commit | Line | Data |
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780dfef3 CP |
1 | /* |
2 | * Driver for Zarlink DVB-T ZL10353 demodulator | |
3 | * | |
794604c3 | 4 | * Copyright (C) 2006, 2007 Christopher Pascoe <c.pascoe@itee.uq.edu.au> |
780dfef3 CP |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
794604c3 | 19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
780dfef3 CP |
20 | */ |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
780dfef3 CP |
24 | #include <linux/init.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/slab.h> | |
794604c3 | 28 | #include <asm/div64.h> |
780dfef3 CP |
29 | |
30 | #include "dvb_frontend.h" | |
31 | #include "zl10353_priv.h" | |
32 | #include "zl10353.h" | |
33 | ||
34 | struct zl10353_state { | |
35 | struct i2c_adapter *i2c; | |
36 | struct dvb_frontend frontend; | |
780dfef3 CP |
37 | |
38 | struct zl10353_config config; | |
bc514710 CP |
39 | |
40 | enum fe_bandwidth bandwidth; | |
780dfef3 CP |
41 | }; |
42 | ||
f7f57770 AP |
43 | static int debug; |
44 | #define dprintk(args...) \ | |
45 | do { \ | |
46 | if (debug) printk(KERN_DEBUG "zl10353: " args); \ | |
47 | } while (0) | |
48 | ||
ff699e6b | 49 | static int debug_regs; |
780dfef3 CP |
50 | |
51 | static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val) | |
52 | { | |
53 | struct zl10353_state *state = fe->demodulator_priv; | |
54 | u8 buf[2] = { reg, val }; | |
55 | struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0, | |
56 | .buf = buf, .len = 2 }; | |
57 | int err = i2c_transfer(state->i2c, &msg, 1); | |
58 | if (err != 1) { | |
59 | printk("zl10353: write to reg %x failed (err = %d)!\n", reg, err); | |
60 | return err; | |
61 | } | |
62 | return 0; | |
63 | } | |
64 | ||
34630409 | 65 | static int zl10353_write(struct dvb_frontend *fe, u8 *ibuf, int ilen) |
780dfef3 CP |
66 | { |
67 | int err, i; | |
68 | for (i = 0; i < ilen - 1; i++) | |
69 | if ((err = zl10353_single_write(fe, ibuf[0] + i, ibuf[i + 1]))) | |
70 | return err; | |
71 | ||
72 | return 0; | |
73 | } | |
74 | ||
75 | static int zl10353_read_register(struct zl10353_state *state, u8 reg) | |
76 | { | |
77 | int ret; | |
78 | u8 b0[1] = { reg }; | |
79 | u8 b1[1] = { 0 }; | |
80 | struct i2c_msg msg[2] = { { .addr = state->config.demod_address, | |
81 | .flags = 0, | |
82 | .buf = b0, .len = 1 }, | |
83 | { .addr = state->config.demod_address, | |
84 | .flags = I2C_M_RD, | |
85 | .buf = b1, .len = 1 } }; | |
86 | ||
87 | ret = i2c_transfer(state->i2c, msg, 2); | |
88 | ||
89 | if (ret != 2) { | |
90 | printk("%s: readreg error (reg=%d, ret==%i)\n", | |
271ddbf7 | 91 | __func__, reg, ret); |
780dfef3 CP |
92 | return ret; |
93 | } | |
94 | ||
95 | return b1[0]; | |
96 | } | |
97 | ||
c04e89b1 | 98 | static void zl10353_dump_regs(struct dvb_frontend *fe) |
780dfef3 CP |
99 | { |
100 | struct zl10353_state *state = fe->demodulator_priv; | |
101 | char buf[52], buf2[4]; | |
102 | int ret; | |
103 | u8 reg; | |
104 | ||
105 | /* Dump all registers. */ | |
106 | for (reg = 0; ; reg++) { | |
107 | if (reg % 16 == 0) { | |
108 | if (reg) | |
109 | printk(KERN_DEBUG "%s\n", buf); | |
110 | sprintf(buf, "%02x: ", reg); | |
111 | } | |
112 | ret = zl10353_read_register(state, reg); | |
113 | if (ret >= 0) | |
114 | sprintf(buf2, "%02x ", (u8)ret); | |
115 | else | |
116 | strcpy(buf2, "-- "); | |
117 | strcat(buf, buf2); | |
118 | if (reg == 0xff) | |
119 | break; | |
120 | } | |
121 | printk(KERN_DEBUG "%s\n", buf); | |
122 | } | |
123 | ||
f7f57770 AP |
124 | static void zl10353_calc_nominal_rate(struct dvb_frontend *fe, |
125 | enum fe_bandwidth bandwidth, | |
126 | u16 *nominal_rate) | |
127 | { | |
f7f57770 | 128 | struct zl10353_state *state = fe->demodulator_priv; |
a1dcd9de CP |
129 | u32 adc_clock = 450560; /* 45.056 MHz */ |
130 | u64 value; | |
131 | u8 bw; | |
f7f57770 AP |
132 | |
133 | if (state->config.adc_clock) | |
134 | adc_clock = state->config.adc_clock; | |
135 | ||
136 | switch (bandwidth) { | |
137 | case BANDWIDTH_6_MHZ: | |
138 | bw = 6; | |
139 | break; | |
140 | case BANDWIDTH_7_MHZ: | |
141 | bw = 7; | |
142 | break; | |
143 | case BANDWIDTH_8_MHZ: | |
144 | default: | |
145 | bw = 8; | |
146 | break; | |
147 | } | |
148 | ||
18ff605a AM |
149 | value = (u64)10 * (1 << 23) / 7 * 125; |
150 | value = (bw * value) + adc_clock / 2; | |
a1dcd9de CP |
151 | do_div(value, adc_clock); |
152 | *nominal_rate = value; | |
f7f57770 AP |
153 | |
154 | dprintk("%s: bw %d, adc_clock %d => 0x%x\n", | |
271ddbf7 | 155 | __func__, bw, adc_clock, *nominal_rate); |
f7f57770 AP |
156 | } |
157 | ||
794604c3 CP |
158 | static void zl10353_calc_input_freq(struct dvb_frontend *fe, |
159 | u16 *input_freq) | |
160 | { | |
161 | struct zl10353_state *state = fe->demodulator_priv; | |
a1dcd9de CP |
162 | u32 adc_clock = 450560; /* 45.056 MHz */ |
163 | int if2 = 361667; /* 36.1667 MHz */ | |
794604c3 CP |
164 | int ife; |
165 | u64 value; | |
166 | ||
167 | if (state->config.adc_clock) | |
168 | adc_clock = state->config.adc_clock; | |
169 | if (state->config.if2) | |
170 | if2 = state->config.if2; | |
171 | ||
172 | if (adc_clock >= if2 * 2) | |
173 | ife = if2; | |
174 | else { | |
175 | ife = adc_clock - (if2 % adc_clock); | |
176 | if (ife > adc_clock / 2) | |
177 | ife = adc_clock - ife; | |
178 | } | |
a1dcd9de | 179 | value = (u64)65536 * ife + adc_clock / 2; |
794604c3 CP |
180 | do_div(value, adc_clock); |
181 | *input_freq = -value; | |
182 | ||
183 | dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n", | |
271ddbf7 | 184 | __func__, if2, ife, adc_clock, -(int)value, *input_freq); |
794604c3 CP |
185 | } |
186 | ||
780dfef3 CP |
187 | static int zl10353_sleep(struct dvb_frontend *fe) |
188 | { | |
189 | static u8 zl10353_softdown[] = { 0x50, 0x0C, 0x44 }; | |
190 | ||
191 | zl10353_write(fe, zl10353_softdown, sizeof(zl10353_softdown)); | |
192 | return 0; | |
193 | } | |
194 | ||
195 | static int zl10353_set_parameters(struct dvb_frontend *fe, | |
196 | struct dvb_frontend_parameters *param) | |
197 | { | |
8dec0732 | 198 | struct zl10353_state *state = fe->demodulator_priv; |
794604c3 | 199 | u16 nominal_rate, input_freq; |
bc514710 CP |
200 | u8 pllbuf[6] = { 0x67 }, acq_ctl = 0; |
201 | u16 tps = 0; | |
202 | struct dvb_ofdm_parameters *op = ¶m->u.ofdm; | |
780dfef3 | 203 | |
bc514710 | 204 | zl10353_single_write(fe, RESET, 0x80); |
780dfef3 CP |
205 | udelay(200); |
206 | zl10353_single_write(fe, 0xEA, 0x01); | |
207 | udelay(200); | |
208 | zl10353_single_write(fe, 0xEA, 0x00); | |
209 | ||
bc514710 CP |
210 | zl10353_single_write(fe, AGC_TARGET, 0x28); |
211 | ||
212 | if (op->transmission_mode != TRANSMISSION_MODE_AUTO) | |
213 | acq_ctl |= (1 << 0); | |
214 | if (op->guard_interval != GUARD_INTERVAL_AUTO) | |
215 | acq_ctl |= (1 << 1); | |
216 | zl10353_single_write(fe, ACQ_CTL, acq_ctl); | |
f7f57770 | 217 | |
bc514710 CP |
218 | switch (op->bandwidth) { |
219 | case BANDWIDTH_6_MHZ: | |
220 | /* These are extrapolated from the 7 and 8MHz values */ | |
221 | zl10353_single_write(fe, MCLK_RATIO, 0x97); | |
222 | zl10353_single_write(fe, 0x64, 0x34); | |
a9dbe5dc | 223 | zl10353_single_write(fe, 0xcc, 0xdd); |
bc514710 CP |
224 | break; |
225 | case BANDWIDTH_7_MHZ: | |
226 | zl10353_single_write(fe, MCLK_RATIO, 0x86); | |
227 | zl10353_single_write(fe, 0x64, 0x35); | |
a9dbe5dc | 228 | zl10353_single_write(fe, 0xcc, 0x73); |
bc514710 CP |
229 | break; |
230 | case BANDWIDTH_8_MHZ: | |
231 | default: | |
232 | zl10353_single_write(fe, MCLK_RATIO, 0x75); | |
233 | zl10353_single_write(fe, 0x64, 0x36); | |
a9dbe5dc | 234 | zl10353_single_write(fe, 0xcc, 0x73); |
bc514710 CP |
235 | } |
236 | ||
237 | zl10353_calc_nominal_rate(fe, op->bandwidth, &nominal_rate); | |
f7f57770 AP |
238 | zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate)); |
239 | zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate)); | |
bc514710 | 240 | state->bandwidth = op->bandwidth; |
f7f57770 | 241 | |
794604c3 CP |
242 | zl10353_calc_input_freq(fe, &input_freq); |
243 | zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq)); | |
244 | zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq)); | |
245 | ||
bc514710 CP |
246 | /* Hint at TPS settings */ |
247 | switch (op->code_rate_HP) { | |
248 | case FEC_2_3: | |
249 | tps |= (1 << 7); | |
250 | break; | |
251 | case FEC_3_4: | |
252 | tps |= (2 << 7); | |
253 | break; | |
254 | case FEC_5_6: | |
255 | tps |= (3 << 7); | |
256 | break; | |
257 | case FEC_7_8: | |
258 | tps |= (4 << 7); | |
259 | break; | |
260 | case FEC_1_2: | |
261 | case FEC_AUTO: | |
262 | break; | |
263 | default: | |
264 | return -EINVAL; | |
265 | } | |
266 | ||
267 | switch (op->code_rate_LP) { | |
268 | case FEC_2_3: | |
269 | tps |= (1 << 4); | |
270 | break; | |
271 | case FEC_3_4: | |
272 | tps |= (2 << 4); | |
273 | break; | |
274 | case FEC_5_6: | |
275 | tps |= (3 << 4); | |
276 | break; | |
277 | case FEC_7_8: | |
278 | tps |= (4 << 4); | |
279 | break; | |
280 | case FEC_1_2: | |
281 | case FEC_AUTO: | |
282 | break; | |
283 | case FEC_NONE: | |
284 | if (op->hierarchy_information == HIERARCHY_AUTO || | |
285 | op->hierarchy_information == HIERARCHY_NONE) | |
286 | break; | |
287 | default: | |
288 | return -EINVAL; | |
289 | } | |
290 | ||
291 | switch (op->constellation) { | |
292 | case QPSK: | |
293 | break; | |
294 | case QAM_AUTO: | |
295 | case QAM_16: | |
296 | tps |= (1 << 13); | |
297 | break; | |
298 | case QAM_64: | |
299 | tps |= (2 << 13); | |
300 | break; | |
301 | default: | |
302 | return -EINVAL; | |
303 | } | |
304 | ||
305 | switch (op->transmission_mode) { | |
306 | case TRANSMISSION_MODE_2K: | |
307 | case TRANSMISSION_MODE_AUTO: | |
308 | break; | |
309 | case TRANSMISSION_MODE_8K: | |
310 | tps |= (1 << 0); | |
311 | break; | |
312 | default: | |
313 | return -EINVAL; | |
314 | } | |
315 | ||
316 | switch (op->guard_interval) { | |
317 | case GUARD_INTERVAL_1_32: | |
318 | case GUARD_INTERVAL_AUTO: | |
319 | break; | |
320 | case GUARD_INTERVAL_1_16: | |
321 | tps |= (1 << 2); | |
322 | break; | |
323 | case GUARD_INTERVAL_1_8: | |
324 | tps |= (2 << 2); | |
325 | break; | |
326 | case GUARD_INTERVAL_1_4: | |
327 | tps |= (3 << 2); | |
328 | break; | |
329 | default: | |
330 | return -EINVAL; | |
331 | } | |
332 | ||
333 | switch (op->hierarchy_information) { | |
334 | case HIERARCHY_AUTO: | |
335 | case HIERARCHY_NONE: | |
336 | break; | |
337 | case HIERARCHY_1: | |
338 | tps |= (1 << 10); | |
339 | break; | |
340 | case HIERARCHY_2: | |
341 | tps |= (2 << 10); | |
342 | break; | |
343 | case HIERARCHY_4: | |
344 | tps |= (3 << 10); | |
345 | break; | |
346 | default: | |
347 | return -EINVAL; | |
348 | } | |
349 | ||
350 | zl10353_single_write(fe, TPS_GIVEN_1, msb(tps)); | |
351 | zl10353_single_write(fe, TPS_GIVEN_0, lsb(tps)); | |
352 | ||
0a11bb86 AP |
353 | if (fe->ops.i2c_gate_ctrl) |
354 | fe->ops.i2c_gate_ctrl(fe, 0); | |
780dfef3 | 355 | |
58d834ea CP |
356 | /* |
357 | * If there is no tuner attached to the secondary I2C bus, we call | |
358 | * set_params to program a potential tuner attached somewhere else. | |
359 | * Otherwise, we update the PLL registers via calc_regs. | |
360 | */ | |
8dec0732 | 361 | if (state->config.no_tuner) { |
dea74869 PB |
362 | if (fe->ops.tuner_ops.set_params) { |
363 | fe->ops.tuner_ops.set_params(fe, param); | |
0a11bb86 AP |
364 | if (fe->ops.i2c_gate_ctrl) |
365 | fe->ops.i2c_gate_ctrl(fe, 0); | |
8dec0732 | 366 | } |
58d834ea CP |
367 | } else if (fe->ops.tuner_ops.calc_regs) { |
368 | fe->ops.tuner_ops.calc_regs(fe, param, pllbuf + 1, 5); | |
e994b8d9 | 369 | pllbuf[1] <<= 1; |
58d834ea | 370 | zl10353_write(fe, pllbuf, sizeof(pllbuf)); |
e994b8d9 | 371 | } |
780dfef3 | 372 | |
fc3398d8 | 373 | zl10353_single_write(fe, 0x5F, 0x13); |
58d834ea CP |
374 | |
375 | /* If no attached tuner or invalid PLL registers, just start the FSM. */ | |
376 | if (state->config.no_tuner || fe->ops.tuner_ops.calc_regs == NULL) | |
377 | zl10353_single_write(fe, FSM_GO, 0x01); | |
378 | else | |
379 | zl10353_single_write(fe, TUNER_GO, 0x01); | |
380 | ||
bc514710 CP |
381 | return 0; |
382 | } | |
383 | ||
384 | static int zl10353_get_parameters(struct dvb_frontend *fe, | |
385 | struct dvb_frontend_parameters *param) | |
386 | { | |
387 | struct zl10353_state *state = fe->demodulator_priv; | |
388 | struct dvb_ofdm_parameters *op = ¶m->u.ofdm; | |
389 | int s6, s9; | |
390 | u16 tps; | |
391 | static const u8 tps_fec_to_api[8] = { | |
392 | FEC_1_2, | |
393 | FEC_2_3, | |
394 | FEC_3_4, | |
395 | FEC_5_6, | |
396 | FEC_7_8, | |
397 | FEC_AUTO, | |
398 | FEC_AUTO, | |
399 | FEC_AUTO | |
400 | }; | |
401 | ||
402 | s6 = zl10353_read_register(state, STATUS_6); | |
403 | s9 = zl10353_read_register(state, STATUS_9); | |
404 | if (s6 < 0 || s9 < 0) | |
405 | return -EREMOTEIO; | |
406 | if ((s6 & (1 << 5)) == 0 || (s9 & (1 << 4)) == 0) | |
407 | return -EINVAL; /* no FE or TPS lock */ | |
408 | ||
409 | tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 | | |
410 | zl10353_read_register(state, TPS_RECEIVED_0); | |
411 | ||
412 | op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7]; | |
413 | op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7]; | |
414 | ||
415 | switch ((tps >> 13) & 3) { | |
416 | case 0: | |
417 | op->constellation = QPSK; | |
418 | break; | |
419 | case 1: | |
420 | op->constellation = QAM_16; | |
421 | break; | |
422 | case 2: | |
423 | op->constellation = QAM_64; | |
424 | break; | |
425 | default: | |
426 | op->constellation = QAM_AUTO; | |
427 | break; | |
428 | } | |
429 | ||
430 | op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : | |
431 | TRANSMISSION_MODE_2K; | |
432 | ||
433 | switch ((tps >> 2) & 3) { | |
434 | case 0: | |
435 | op->guard_interval = GUARD_INTERVAL_1_32; | |
436 | break; | |
437 | case 1: | |
438 | op->guard_interval = GUARD_INTERVAL_1_16; | |
439 | break; | |
440 | case 2: | |
441 | op->guard_interval = GUARD_INTERVAL_1_8; | |
442 | break; | |
443 | case 3: | |
444 | op->guard_interval = GUARD_INTERVAL_1_4; | |
445 | break; | |
446 | default: | |
447 | op->guard_interval = GUARD_INTERVAL_AUTO; | |
448 | break; | |
449 | } | |
450 | ||
451 | switch ((tps >> 10) & 7) { | |
452 | case 0: | |
453 | op->hierarchy_information = HIERARCHY_NONE; | |
454 | break; | |
455 | case 1: | |
456 | op->hierarchy_information = HIERARCHY_1; | |
457 | break; | |
458 | case 2: | |
459 | op->hierarchy_information = HIERARCHY_2; | |
460 | break; | |
461 | case 3: | |
462 | op->hierarchy_information = HIERARCHY_4; | |
463 | break; | |
464 | default: | |
465 | op->hierarchy_information = HIERARCHY_AUTO; | |
466 | break; | |
467 | } | |
468 | ||
469 | param->frequency = 0; | |
470 | op->bandwidth = state->bandwidth; | |
471 | param->inversion = INVERSION_AUTO; | |
780dfef3 CP |
472 | |
473 | return 0; | |
474 | } | |
475 | ||
476 | static int zl10353_read_status(struct dvb_frontend *fe, fe_status_t *status) | |
477 | { | |
478 | struct zl10353_state *state = fe->demodulator_priv; | |
479 | int s6, s7, s8; | |
480 | ||
481 | if ((s6 = zl10353_read_register(state, STATUS_6)) < 0) | |
482 | return -EREMOTEIO; | |
483 | if ((s7 = zl10353_read_register(state, STATUS_7)) < 0) | |
484 | return -EREMOTEIO; | |
485 | if ((s8 = zl10353_read_register(state, STATUS_8)) < 0) | |
486 | return -EREMOTEIO; | |
487 | ||
488 | *status = 0; | |
489 | if (s6 & (1 << 2)) | |
490 | *status |= FE_HAS_CARRIER; | |
491 | if (s6 & (1 << 1)) | |
492 | *status |= FE_HAS_VITERBI; | |
493 | if (s6 & (1 << 5)) | |
494 | *status |= FE_HAS_LOCK; | |
495 | if (s7 & (1 << 4)) | |
496 | *status |= FE_HAS_SYNC; | |
497 | if (s8 & (1 << 6)) | |
498 | *status |= FE_HAS_SIGNAL; | |
499 | ||
500 | if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) != | |
501 | (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) | |
502 | *status &= ~FE_HAS_LOCK; | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
67b60aad CP |
507 | static int zl10353_read_ber(struct dvb_frontend *fe, u32 *ber) |
508 | { | |
509 | struct zl10353_state *state = fe->demodulator_priv; | |
510 | ||
6345f0f6 CP |
511 | *ber = zl10353_read_register(state, RS_ERR_CNT_2) << 16 | |
512 | zl10353_read_register(state, RS_ERR_CNT_1) << 8 | | |
513 | zl10353_read_register(state, RS_ERR_CNT_0); | |
67b60aad CP |
514 | |
515 | return 0; | |
516 | } | |
517 | ||
518 | static int zl10353_read_signal_strength(struct dvb_frontend *fe, u16 *strength) | |
519 | { | |
520 | struct zl10353_state *state = fe->demodulator_priv; | |
521 | ||
6345f0f6 CP |
522 | u16 signal = zl10353_read_register(state, AGC_GAIN_1) << 10 | |
523 | zl10353_read_register(state, AGC_GAIN_0) << 2 | 3; | |
67b60aad CP |
524 | |
525 | *strength = ~signal; | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
780dfef3 CP |
530 | static int zl10353_read_snr(struct dvb_frontend *fe, u16 *snr) |
531 | { | |
532 | struct zl10353_state *state = fe->demodulator_priv; | |
533 | u8 _snr; | |
534 | ||
535 | if (debug_regs) | |
536 | zl10353_dump_regs(fe); | |
537 | ||
538 | _snr = zl10353_read_register(state, SNR); | |
539 | *snr = (_snr << 8) | _snr; | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
67b60aad CP |
544 | static int zl10353_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) |
545 | { | |
546 | struct zl10353_state *state = fe->demodulator_priv; | |
547 | ||
6345f0f6 CP |
548 | *ucblocks = zl10353_read_register(state, RS_UBC_1) << 8 | |
549 | zl10353_read_register(state, RS_UBC_0); | |
67b60aad CP |
550 | |
551 | return 0; | |
552 | } | |
553 | ||
780dfef3 CP |
554 | static int zl10353_get_tune_settings(struct dvb_frontend *fe, |
555 | struct dvb_frontend_tune_settings | |
556 | *fe_tune_settings) | |
557 | { | |
558 | fe_tune_settings->min_delay_ms = 1000; | |
559 | fe_tune_settings->step_size = 0; | |
560 | fe_tune_settings->max_drift = 0; | |
561 | ||
562 | return 0; | |
563 | } | |
564 | ||
565 | static int zl10353_init(struct dvb_frontend *fe) | |
566 | { | |
567 | struct zl10353_state *state = fe->demodulator_priv; | |
568 | u8 zl10353_reset_attach[6] = { 0x50, 0x03, 0x64, 0x46, 0x15, 0x0F }; | |
569 | int rc = 0; | |
570 | ||
571 | if (debug_regs) | |
572 | zl10353_dump_regs(fe); | |
8fb95784 CP |
573 | if (state->config.parallel_ts) |
574 | zl10353_reset_attach[2] &= ~0x20; | |
780dfef3 CP |
575 | |
576 | /* Do a "hard" reset if not already done */ | |
8fb95784 CP |
577 | if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] || |
578 | zl10353_read_register(state, 0x51) != zl10353_reset_attach[2]) { | |
780dfef3 CP |
579 | rc = zl10353_write(fe, zl10353_reset_attach, |
580 | sizeof(zl10353_reset_attach)); | |
581 | if (debug_regs) | |
582 | zl10353_dump_regs(fe); | |
583 | } | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
0a11bb86 AP |
588 | static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) |
589 | { | |
899a6f67 | 590 | struct zl10353_state *state = fe->demodulator_priv; |
0a11bb86 AP |
591 | u8 val = 0x0a; |
592 | ||
5f77af93 | 593 | if (state->config.disable_i2c_gate_ctrl) { |
899a6f67 DB |
594 | /* No tuner attached to the internal I2C bus */ |
595 | /* If set enable I2C bridge, the main I2C bus stopped hardly */ | |
596 | return 0; | |
597 | } | |
598 | ||
0a11bb86 AP |
599 | if (enable) |
600 | val |= 0x10; | |
601 | ||
602 | return zl10353_single_write(fe, 0x62, val); | |
603 | } | |
604 | ||
780dfef3 CP |
605 | static void zl10353_release(struct dvb_frontend *fe) |
606 | { | |
607 | struct zl10353_state *state = fe->demodulator_priv; | |
780dfef3 CP |
608 | kfree(state); |
609 | } | |
610 | ||
611 | static struct dvb_frontend_ops zl10353_ops; | |
612 | ||
613 | struct dvb_frontend *zl10353_attach(const struct zl10353_config *config, | |
614 | struct i2c_adapter *i2c) | |
615 | { | |
616 | struct zl10353_state *state = NULL; | |
617 | ||
618 | /* allocate memory for the internal state */ | |
619 | state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL); | |
620 | if (state == NULL) | |
621 | goto error; | |
622 | ||
623 | /* setup the state */ | |
624 | state->i2c = i2c; | |
625 | memcpy(&state->config, config, sizeof(struct zl10353_config)); | |
780dfef3 CP |
626 | |
627 | /* check if the demod is there */ | |
628 | if (zl10353_read_register(state, CHIP_ID) != ID_ZL10353) | |
629 | goto error; | |
630 | ||
631 | /* create dvb_frontend */ | |
dea74869 | 632 | memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops)); |
780dfef3 CP |
633 | state->frontend.demodulator_priv = state; |
634 | ||
635 | return &state->frontend; | |
636 | error: | |
637 | kfree(state); | |
638 | return NULL; | |
639 | } | |
640 | ||
641 | static struct dvb_frontend_ops zl10353_ops = { | |
642 | ||
643 | .info = { | |
644 | .name = "Zarlink ZL10353 DVB-T", | |
645 | .type = FE_OFDM, | |
646 | .frequency_min = 174000000, | |
647 | .frequency_max = 862000000, | |
648 | .frequency_stepsize = 166667, | |
649 | .frequency_tolerance = 0, | |
650 | .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | | |
651 | FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | | |
652 | FE_CAN_FEC_AUTO | | |
653 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | | |
654 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | | |
655 | FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | | |
656 | FE_CAN_MUTE_TS | |
657 | }, | |
658 | ||
659 | .release = zl10353_release, | |
660 | ||
661 | .init = zl10353_init, | |
662 | .sleep = zl10353_sleep, | |
0a11bb86 | 663 | .i2c_gate_ctrl = zl10353_i2c_gate_ctrl, |
c10d14d6 | 664 | .write = zl10353_write, |
780dfef3 CP |
665 | |
666 | .set_frontend = zl10353_set_parameters, | |
bc514710 | 667 | .get_frontend = zl10353_get_parameters, |
780dfef3 CP |
668 | .get_tune_settings = zl10353_get_tune_settings, |
669 | ||
670 | .read_status = zl10353_read_status, | |
67b60aad CP |
671 | .read_ber = zl10353_read_ber, |
672 | .read_signal_strength = zl10353_read_signal_strength, | |
780dfef3 | 673 | .read_snr = zl10353_read_snr, |
67b60aad | 674 | .read_ucblocks = zl10353_read_ucblocks, |
780dfef3 CP |
675 | }; |
676 | ||
f7f57770 AP |
677 | module_param(debug, int, 0644); |
678 | MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); | |
679 | ||
780dfef3 CP |
680 | module_param(debug_regs, int, 0644); |
681 | MODULE_PARM_DESC(debug_regs, "Turn on/off frontend register dumps (default:off)."); | |
682 | ||
683 | MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver"); | |
684 | MODULE_AUTHOR("Chris Pascoe"); | |
685 | MODULE_LICENSE("GPL"); | |
686 | ||
687 | EXPORT_SYMBOL(zl10353_attach); |