[deliverable/linux.git] / drivers / media / dvb / mantis / mantis_hif.c

/*
	Mantis PCI bridge driver

	Copyright (C) Manu Abraham (abraham.manu@gmail.com)

	This program is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with this program; if not, write to the Free Software
	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

#include <linux/kernel.h>
#include <linux/signal.h>
#include <linux/sched.h>

#include <linux/interrupt.h>
#include <asm/io.h>

#include "dmxdev.h"
#include "dvbdev.h"
#include "dvb_demux.h"
#include "dvb_frontend.h"
#include "dvb_net.h"

#include "mantis_common.h"

#include "mantis_hif.h"
#include "mantis_link.h" /* temporary due to physical layer stuff */

#include "mantis_reg.h"


static int mantis_hif_sbuf_opdone_wait(struct mantis_ca *ca)
{
	struct mantis_pci *mantis = ca->ca_priv;
	int rc = 0;

	if (wait_event_timeout(ca->hif_opdone_wq,
			       ca->hif_event & MANTIS_SBUF_OPDONE,
			       msecs_to_jiffies(500)) == -ERESTARTSYS) {

		dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Smart buffer operation timeout !", mantis->num);
		rc = -EREMOTEIO;
	}
	dprintk(MANTIS_DEBUG, 1, "Smart Buffer Operation complete");
	ca->hif_event &= ~MANTIS_SBUF_OPDONE;
	return rc;
}

static int mantis_hif_write_wait(struct mantis_ca *ca)
{
	struct mantis_pci *mantis = ca->ca_priv;
	u32 opdone = 0, timeout = 0;
	int rc = 0;

	if (wait_event_timeout(ca->hif_write_wq,
			       mantis->gpif_status & MANTIS_GPIF_WRACK,
			       msecs_to_jiffies(500)) == -ERESTARTSYS) {

		dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Write ACK timed out !", mantis->num);
		rc = -EREMOTEIO;
	}
	dprintk(MANTIS_DEBUG, 1, "Write Acknowledged");
	mantis->gpif_status &= ~MANTIS_GPIF_WRACK;
	while (!opdone) {
		opdone = (mmread(MANTIS_GPIF_STATUS) & MANTIS_SBUF_OPDONE);
		udelay(500);
		timeout++;
		if (timeout > 100) {
			dprintk(MANTIS_ERROR, 1, "Adater(%d) Slot(0): Write operation timed out!", mantis->num);
			rc = -ETIMEDOUT;
			break;
		}
	}
	dprintk(MANTIS_DEBUG, 1, "HIF Write success");
	return rc;
}


int mantis_hif_read_mem(struct mantis_ca *ca, u32 addr)
{
	struct mantis_pci *mantis = ca->ca_priv;
	u32 hif_addr = 0, data, count = 4;

	dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF Mem Read", mantis->num);
	mutex_lock(&ca->ca_lock);
	hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
	hif_addr &= ~MANTIS_GPIF_PCMCIAIOM;
	hif_addr |=  MANTIS_HIF_STATUS;
	hif_addr |=  addr;

	mmwrite(hif_addr, MANTIS_GPIF_BRADDR);
	mmwrite(count, MANTIS_GPIF_BRBYTES);
	udelay(20);
	mmwrite(hif_addr | MANTIS_GPIF_HIFRDWRN, MANTIS_GPIF_ADDR);

	if (mantis_hif_sbuf_opdone_wait(ca) != 0) {
		dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): GPIF Smart Buffer operation failed", mantis->num);
		mutex_unlock(&ca->ca_lock);
		return -EREMOTEIO;
	}
	data = mmread(MANTIS_GPIF_DIN);
	mutex_unlock(&ca->ca_lock);
	dprintk(MANTIS_DEBUG, 1, "Mem Read: 0x%02x", data);
	return (data >> 24) & 0xff;
}

int mantis_hif_write_mem(struct mantis_ca *ca, u32 addr, u8 data)
{
	struct mantis_slot *slot = ca->slot;
	struct mantis_pci *mantis = ca->ca_priv;
	u32 hif_addr = 0;

	dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF Mem Write", mantis->num);
	mutex_lock(&ca->ca_lock);
	hif_addr &= ~MANTIS_GPIF_HIFRDWRN;
	hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
	hif_addr &= ~MANTIS_GPIF_PCMCIAIOM;
	hif_addr |=  MANTIS_HIF_STATUS;
	hif_addr |=  addr;

	mmwrite(slot->slave_cfg, MANTIS_GPIF_CFGSLA); /* Slot0 alone for now */
	mmwrite(hif_addr, MANTIS_GPIF_ADDR);
	mmwrite(data, MANTIS_GPIF_DOUT);

	if (mantis_hif_write_wait(ca) != 0) {
		dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
		mutex_unlock(&ca->ca_lock);
		return -EREMOTEIO;
	}
	dprintk(MANTIS_DEBUG, 1, "Mem Write: (0x%02x to 0x%02x)", data, addr);
	mutex_unlock(&ca->ca_lock);

	return 0;
}

int mantis_hif_read_iom(struct mantis_ca *ca, u32 addr)
{
	struct mantis_pci *mantis = ca->ca_priv;
	u32 data, hif_addr = 0;

	dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF I/O Read", mantis->num);
	mutex_lock(&ca->ca_lock);
	hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
	hif_addr |=  MANTIS_GPIF_PCMCIAIOM;
	hif_addr |=  MANTIS_HIF_STATUS;
	hif_addr |=  addr;

	mmwrite(hif_addr, MANTIS_GPIF_BRADDR);
	mmwrite(1, MANTIS_GPIF_BRBYTES);
	udelay(20);
	mmwrite(hif_addr | MANTIS_GPIF_HIFRDWRN, MANTIS_GPIF_ADDR);

	if (mantis_hif_sbuf_opdone_wait(ca) != 0) {
		dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
		mutex_unlock(&ca->ca_lock);
		return -EREMOTEIO;
	}
	data = mmread(MANTIS_GPIF_DIN);
	dprintk(MANTIS_DEBUG, 1, "I/O Read: 0x%02x", data);
	udelay(50);
	mutex_unlock(&ca->ca_lock);

	return (u8) data;
}

int mantis_hif_write_iom(struct mantis_ca *ca, u32 addr, u8 data)
{
	struct mantis_pci *mantis = ca->ca_priv;
	u32 hif_addr = 0;

	dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF I/O Write", mantis->num);
	mutex_lock(&ca->ca_lock);
	hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
	hif_addr &= ~MANTIS_GPIF_HIFRDWRN;
	hif_addr |=  MANTIS_GPIF_PCMCIAIOM;
	hif_addr |=  MANTIS_HIF_STATUS;
	hif_addr |=  addr;

	mmwrite(hif_addr, MANTIS_GPIF_ADDR);
	mmwrite(data, MANTIS_GPIF_DOUT);

	if (mantis_hif_write_wait(ca) != 0) {
		dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
		mutex_unlock(&ca->ca_lock);
		return -EREMOTEIO;
	}
	dprintk(MANTIS_DEBUG, 1, "I/O Write: (0x%02x to 0x%02x)", data, addr);
	mutex_unlock(&ca->ca_lock);
	udelay(50);

	return 0;
}

int mantis_hif_init(struct mantis_ca *ca)
{
	struct mantis_slot *slot = ca->slot;
	struct mantis_pci *mantis = ca->ca_priv;
	u32 irqcfg;

	slot[0].slave_cfg = 0x70773028;
	dprintk(MANTIS_ERROR, 1, "Adapter(%d) Initializing Mantis Host Interface", mantis->num);

	mutex_lock(&ca->ca_lock);
	irqcfg = mmread(MANTIS_GPIF_IRQCFG);
	irqcfg = MANTIS_MASK_BRRDY	|
		 MANTIS_MASK_WRACK	|
		 MANTIS_MASK_EXTIRQ	|
		 MANTIS_MASK_WSTO	|
		 MANTIS_MASK_OTHERR	|
		 MANTIS_MASK_OVFLW;

	mmwrite(irqcfg, MANTIS_GPIF_IRQCFG);
	mutex_unlock(&ca->ca_lock);

	return 0;
}

void mantis_hif_exit(struct mantis_ca *ca)
{
	struct mantis_pci *mantis = ca->ca_priv;
	u32 irqcfg;

	dprintk(MANTIS_ERROR, 1, "Adapter(%d) Exiting Mantis Host Interface", mantis->num);
	mutex_lock(&ca->ca_lock);
	irqcfg = mmread(MANTIS_GPIF_IRQCFG);
	irqcfg &= ~MANTIS_MASK_BRRDY;
	mmwrite(irqcfg, MANTIS_GPIF_IRQCFG);
	mutex_unlock(&ca->ca_lock);
}
Commit	Line	Data
d8b14f8a MA	1	/*
	2	Mantis PCI bridge driver
	3
8825a097	4	Copyright (C) Manu Abraham (abraham.manu@gmail.com)
d8b14f8a MA	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
b3b96144 MA	21	#include <linux/kernel.h>
	22	#include <linux/signal.h>
	23	#include <linux/sched.h>
	24
b3b96144	25	#include <linux/interrupt.h>
b7f080cf	26	#include <asm/io.h>
b3b96144 MA	27
	28	#include "dmxdev.h"
	29	#include "dvbdev.h"
	30	#include "dvb_demux.h"
	31	#include "dvb_frontend.h"
	32	#include "dvb_net.h"
	33
d8b14f8a	34	#include "mantis_common.h"
b3b96144	35
d8b14f8a MA	36	#include "mantis_hif.h"
	37	#include "mantis_link.h" /* temporary due to physical layer stuff */
	38
b3b96144 MA	39	#include "mantis_reg.h"
b3b96144 MA	40
d8b14f8a MA	41
	42	static int mantis_hif_sbuf_opdone_wait(struct mantis_ca *ca)
	43	{
	44	struct mantis_pci *mantis = ca->ca_priv;
	45	int rc = 0;
	46
ac8f04d2 MA	47	if (wait_event_timeout(ca->hif_opdone_wq,
	48	ca->hif_event & MANTIS_SBUF_OPDONE,
	49	msecs_to_jiffies(500)) == -ERESTARTSYS) {
d8b14f8a	50
b3b96144	51	dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Smart buffer operation timeout !", mantis->num);
d8b14f8a MA	52	rc = -EREMOTEIO;
d8b14f8a MA	53	}
b3b96144	54	dprintk(MANTIS_DEBUG, 1, "Smart Buffer Operation complete");
d8b14f8a	55	ca->hif_event &= ~MANTIS_SBUF_OPDONE;
d8b14f8a MA	56	return rc;
	57	}
	58
e0e099a7 MA	59	static int mantis_hif_write_wait(struct mantis_ca *ca)
	60	{
	61	struct mantis_pci *mantis = ca->ca_priv;
	62	u32 opdone = 0, timeout = 0;
	63	int rc = 0;
	64
	65	if (wait_event_timeout(ca->hif_write_wq,
	66	mantis->gpif_status & MANTIS_GPIF_WRACK,
	67	msecs_to_jiffies(500)) == -ERESTARTSYS) {
	68
b3b96144	69	dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Write ACK timed out !", mantis->num);
e0e099a7 MA	70	rc = -EREMOTEIO;
e0e099a7 MA	71	}
b3b96144	72	dprintk(MANTIS_DEBUG, 1, "Write Acknowledged");
e0e099a7 MA	73	mantis->gpif_status &= ~MANTIS_GPIF_WRACK;
	74	while (!opdone) {
	75	opdone = (mmread(MANTIS_GPIF_STATUS) & MANTIS_SBUF_OPDONE);
	76	udelay(500);
	77	timeout++;
	78	if (timeout > 100) {
b3b96144	79	dprintk(MANTIS_ERROR, 1, "Adater(%d) Slot(0): Write operation timed out!", mantis->num);
e0e099a7 MA	80	rc = -ETIMEDOUT;
	81	break;
	82	}
	83	}
b3b96144	84	dprintk(MANTIS_DEBUG, 1, "HIF Write success");
e0e099a7 MA	85	return rc;
	86	}
	87
b2d8f5ea	88
d8b14f8a MA	89	int mantis_hif_read_mem(struct mantis_ca *ca, u32 addr)
	90	{
	91	struct mantis_pci *mantis = ca->ca_priv;
	92	u32 hif_addr = 0, data, count = 4;
	93
b3b96144	94	dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF Mem Read", mantis->num);
f684336b	95	mutex_lock(&ca->ca_lock);
d8b14f8a MA	96	hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
d8b14f8a MA	97	hif_addr &= ~MANTIS_GPIF_PCMCIAIOM;
b29f6ac2	98	hif_addr \|= MANTIS_HIF_STATUS;
d8b14f8a MA	99	hif_addr \|= addr;
d8b14f8a MA	100
b29f6ac2	101	mmwrite(hif_addr, MANTIS_GPIF_BRADDR);
d8b14f8a	102	mmwrite(count, MANTIS_GPIF_BRBYTES);
d8b14f8a	103	udelay(20);
b29f6ac2	104	mmwrite(hif_addr \| MANTIS_GPIF_HIFRDWRN, MANTIS_GPIF_ADDR);
d8b14f8a	105
d8b14f8a	106	if (mantis_hif_sbuf_opdone_wait(ca) != 0) {
b3b96144	107	dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): GPIF Smart Buffer operation failed", mantis->num);
f684336b	108	mutex_unlock(&ca->ca_lock);
d8b14f8a MA	109	return -EREMOTEIO;
d8b14f8a MA	110	}
a0c59063	111	data = mmread(MANTIS_GPIF_DIN);
f684336b	112	mutex_unlock(&ca->ca_lock);
b3b96144	113	dprintk(MANTIS_DEBUG, 1, "Mem Read: 0x%02x", data);
d8b14f8a MA	114	return (data >> 24) & 0xff;
	115	}
	116
	117	int mantis_hif_write_mem(struct mantis_ca *ca, u32 addr, u8 data)
	118	{
	119	struct mantis_slot *slot = ca->slot;
	120	struct mantis_pci *mantis = ca->ca_priv;
	121	u32 hif_addr = 0;
	122
b3b96144	123	dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF Mem Write", mantis->num);
f684336b	124	mutex_lock(&ca->ca_lock);
d8b14f8a MA	125	hif_addr &= ~MANTIS_GPIF_HIFRDWRN;
	126	hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
	127	hif_addr &= ~MANTIS_GPIF_PCMCIAIOM;
b29f6ac2 MA	128	hif_addr \|= MANTIS_HIF_STATUS;
b29f6ac2 MA	129	hif_addr \|= addr;
d8b14f8a MA	130
d8b14f8a MA	131	mmwrite(slot->slave_cfg, MANTIS_GPIF_CFGSLA); /* Slot0 alone for now */
b29f6ac2	132	mmwrite(hif_addr, MANTIS_GPIF_ADDR);
a0c59063	133	mmwrite(data, MANTIS_GPIF_DOUT);
d8b14f8a	134
e0e099a7	135	if (mantis_hif_write_wait(ca) != 0) {
b3b96144	136	dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
f684336b	137	mutex_unlock(&ca->ca_lock);
d8b14f8a MA	138	return -EREMOTEIO;
d8b14f8a MA	139	}
b3b96144	140	dprintk(MANTIS_DEBUG, 1, "Mem Write: (0x%02x to 0x%02x)", data, addr);
f684336b	141	mutex_unlock(&ca->ca_lock);
8b9c385f	142
d8b14f8a MA	143	return 0;
	144	}
	145
6053240f	146	int mantis_hif_read_iom(struct mantis_ca *ca, u32 addr)
c9a750c9 MA	147	{
c9a750c9 MA	148	struct mantis_pci *mantis = ca->ca_priv;
6053240f	149	u32 data, hif_addr = 0;
c9a750c9	150
b3b96144	151	dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF I/O Read", mantis->num);
f684336b	152	mutex_lock(&ca->ca_lock);
c9a750c9	153	hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
c9a750c9	154	hif_addr \|= MANTIS_GPIF_PCMCIAIOM;
b29f6ac2	155	hif_addr \|= MANTIS_HIF_STATUS;
c9a750c9 MA	156	hif_addr \|= addr;
c9a750c9 MA	157
b29f6ac2	158	mmwrite(hif_addr, MANTIS_GPIF_BRADDR);
c63e5073	159	mmwrite(1, MANTIS_GPIF_BRBYTES);
c63e5073	160	udelay(20);
b29f6ac2	161	mmwrite(hif_addr \| MANTIS_GPIF_HIFRDWRN, MANTIS_GPIF_ADDR);
c9a750c9 MA	162
c9a750c9 MA	163	if (mantis_hif_sbuf_opdone_wait(ca) != 0) {
b3b96144	164	dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
f684336b	165	mutex_unlock(&ca->ca_lock);
c9a750c9 MA	166	return -EREMOTEIO;
c9a750c9 MA	167	}
a0c59063	168	data = mmread(MANTIS_GPIF_DIN);
b3b96144	169	dprintk(MANTIS_DEBUG, 1, "I/O Read: 0x%02x", data);
8e0d58ec	170	udelay(50);
f684336b	171	mutex_unlock(&ca->ca_lock);
c9a750c9	172
9c867955	173	return (u8) data;
c9a750c9 MA	174	}
c9a750c9 MA	175
6053240f	176	int mantis_hif_write_iom(struct mantis_ca *ca, u32 addr, u8 data)
c9a750c9 MA	177	{
	178	struct mantis_pci *mantis = ca->ca_priv;
	179	u32 hif_addr = 0;
	180
b3b96144	181	dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF I/O Write", mantis->num);
f684336b	182	mutex_lock(&ca->ca_lock);
c9a750c9 MA	183	hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
	184	hif_addr &= ~MANTIS_GPIF_HIFRDWRN;
	185	hif_addr \|= MANTIS_GPIF_PCMCIAIOM;
b29f6ac2	186	hif_addr \|= MANTIS_HIF_STATUS;
c9a750c9 MA	187	hif_addr \|= addr;
c9a750c9 MA	188
b29f6ac2	189	mmwrite(hif_addr, MANTIS_GPIF_ADDR);
a0c59063	190	mmwrite(data, MANTIS_GPIF_DOUT);
c9a750c9	191
e0e099a7	192	if (mantis_hif_write_wait(ca) != 0) {
b3b96144	193	dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
f684336b	194	mutex_unlock(&ca->ca_lock);
c9a750c9 MA	195	return -EREMOTEIO;
c9a750c9 MA	196	}
b3b96144	197	dprintk(MANTIS_DEBUG, 1, "I/O Write: (0x%02x to 0x%02x)", data, addr);
f684336b	198	mutex_unlock(&ca->ca_lock);
8e0d58ec	199	udelay(50);
c9a750c9 MA	200
	201	return 0;
	202	}
	203
d8b14f8a MA	204	int mantis_hif_init(struct mantis_ca *ca)
d8b14f8a MA	205	{
ac23f4c8	206	struct mantis_slot *slot = ca->slot;
d8b14f8a MA	207	struct mantis_pci *mantis = ca->ca_priv;
	208	u32 irqcfg;
	209
ac23f4c8	210	slot[0].slave_cfg = 0x70773028;
b3b96144	211	dprintk(MANTIS_ERROR, 1, "Adapter(%d) Initializing Mantis Host Interface", mantis->num);
d8b14f8a	212
f684336b	213	mutex_lock(&ca->ca_lock);
c90d345f MA	214	irqcfg = mmread(MANTIS_GPIF_IRQCFG);
	215	irqcfg = MANTIS_MASK_BRRDY \|
	216	MANTIS_MASK_WRACK \|
	217	MANTIS_MASK_EXTIRQ \|
	218	MANTIS_MASK_WSTO \|
	219	MANTIS_MASK_OTHERR \|
	220	MANTIS_MASK_OVFLW;
	221
d8b14f8a	222	mmwrite(irqcfg, MANTIS_GPIF_IRQCFG);
f684336b	223	mutex_unlock(&ca->ca_lock);
d8b14f8a MA	224
	225	return 0;
	226	}
	227
	228	void mantis_hif_exit(struct mantis_ca *ca)
	229	{
	230	struct mantis_pci *mantis = ca->ca_priv;
	231	u32 irqcfg;
	232
b3b96144	233	dprintk(MANTIS_ERROR, 1, "Adapter(%d) Exiting Mantis Host Interface", mantis->num);
f684336b	234	mutex_lock(&ca->ca_lock);
d8b14f8a MA	235	irqcfg = mmread(MANTIS_GPIF_IRQCFG);
	236	irqcfg &= ~MANTIS_MASK_BRRDY;
	237	mmwrite(irqcfg, MANTIS_GPIF_IRQCFG);
f684336b	238	mutex_unlock(&ca->ca_lock);
d8b14f8a	239	}