Commit | Line | Data |
---|---|---|
4b64bb26 AP |
1 | /* |
2 | * Afatech AF9033 demodulator driver | |
3 | * | |
4 | * Copyright (C) 2009 Antti Palosaari <crope@iki.fi> | |
5 | * Copyright (C) 2012 Antti Palosaari <crope@iki.fi> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
20 | */ | |
21 | ||
22 | #include "af9033_priv.h" | |
23 | ||
37ebaf68 MCC |
24 | /* Max transfer size done by I2C transfer functions */ |
25 | #define MAX_XFER_SIZE 64 | |
26 | ||
09611caa | 27 | struct af9033_dev { |
f5b00a76 | 28 | struct i2c_client *client; |
4b64bb26 AP |
29 | struct dvb_frontend fe; |
30 | struct af9033_config cfg; | |
83f11619 AP |
31 | bool is_af9035; |
32 | bool is_it9135; | |
4b64bb26 AP |
33 | |
34 | u32 bandwidth_hz; | |
35 | bool ts_mode_parallel; | |
36 | bool ts_mode_serial; | |
47eafa54 | 37 | |
0df289a2 | 38 | enum fe_status fe_status; |
e53c4744 | 39 | u64 post_bit_error_prev; /* for old read_ber we return (curr - prev) */ |
6bb096c9 AP |
40 | u64 post_bit_error; |
41 | u64 post_bit_count; | |
204f4319 AP |
42 | u64 error_block_count; |
43 | u64 total_block_count; | |
83f11619 | 44 | struct delayed_work stat_work; |
4b64bb26 AP |
45 | }; |
46 | ||
47 | /* write multiple registers */ | |
09611caa | 48 | static int af9033_wr_regs(struct af9033_dev *dev, u32 reg, const u8 *val, |
4b64bb26 AP |
49 | int len) |
50 | { | |
51 | int ret; | |
37ebaf68 | 52 | u8 buf[MAX_XFER_SIZE]; |
4b64bb26 AP |
53 | struct i2c_msg msg[1] = { |
54 | { | |
f5b00a76 | 55 | .addr = dev->client->addr, |
4b64bb26 | 56 | .flags = 0, |
37ebaf68 | 57 | .len = 3 + len, |
4b64bb26 AP |
58 | .buf = buf, |
59 | } | |
60 | }; | |
61 | ||
37ebaf68 | 62 | if (3 + len > sizeof(buf)) { |
f5b00a76 | 63 | dev_warn(&dev->client->dev, |
6a087f1f AP |
64 | "i2c wr reg=%04x: len=%d is too big!\n", |
65 | reg, len); | |
37ebaf68 MCC |
66 | return -EINVAL; |
67 | } | |
68 | ||
4b64bb26 AP |
69 | buf[0] = (reg >> 16) & 0xff; |
70 | buf[1] = (reg >> 8) & 0xff; | |
71 | buf[2] = (reg >> 0) & 0xff; | |
72 | memcpy(&buf[3], val, len); | |
73 | ||
f5b00a76 | 74 | ret = i2c_transfer(dev->client->adapter, msg, 1); |
4b64bb26 AP |
75 | if (ret == 1) { |
76 | ret = 0; | |
77 | } else { | |
6a087f1f AP |
78 | dev_warn(&dev->client->dev, "i2c wr failed=%d reg=%06x len=%d\n", |
79 | ret, reg, len); | |
4b64bb26 AP |
80 | ret = -EREMOTEIO; |
81 | } | |
82 | ||
83 | return ret; | |
84 | } | |
85 | ||
86 | /* read multiple registers */ | |
09611caa | 87 | static int af9033_rd_regs(struct af9033_dev *dev, u32 reg, u8 *val, int len) |
4b64bb26 AP |
88 | { |
89 | int ret; | |
90 | u8 buf[3] = { (reg >> 16) & 0xff, (reg >> 8) & 0xff, | |
91 | (reg >> 0) & 0xff }; | |
92 | struct i2c_msg msg[2] = { | |
93 | { | |
f5b00a76 | 94 | .addr = dev->client->addr, |
4b64bb26 AP |
95 | .flags = 0, |
96 | .len = sizeof(buf), | |
97 | .buf = buf | |
98 | }, { | |
f5b00a76 | 99 | .addr = dev->client->addr, |
4b64bb26 AP |
100 | .flags = I2C_M_RD, |
101 | .len = len, | |
102 | .buf = val | |
103 | } | |
104 | }; | |
105 | ||
f5b00a76 | 106 | ret = i2c_transfer(dev->client->adapter, msg, 2); |
4b64bb26 AP |
107 | if (ret == 2) { |
108 | ret = 0; | |
109 | } else { | |
6a087f1f AP |
110 | dev_warn(&dev->client->dev, "i2c rd failed=%d reg=%06x len=%d\n", |
111 | ret, reg, len); | |
4b64bb26 AP |
112 | ret = -EREMOTEIO; |
113 | } | |
114 | ||
115 | return ret; | |
116 | } | |
117 | ||
118 | ||
119 | /* write single register */ | |
09611caa | 120 | static int af9033_wr_reg(struct af9033_dev *dev, u32 reg, u8 val) |
4b64bb26 | 121 | { |
09611caa | 122 | return af9033_wr_regs(dev, reg, &val, 1); |
4b64bb26 AP |
123 | } |
124 | ||
125 | /* read single register */ | |
09611caa | 126 | static int af9033_rd_reg(struct af9033_dev *dev, u32 reg, u8 *val) |
4b64bb26 | 127 | { |
09611caa | 128 | return af9033_rd_regs(dev, reg, val, 1); |
4b64bb26 AP |
129 | } |
130 | ||
131 | /* write single register with mask */ | |
09611caa | 132 | static int af9033_wr_reg_mask(struct af9033_dev *dev, u32 reg, u8 val, |
4b64bb26 AP |
133 | u8 mask) |
134 | { | |
135 | int ret; | |
136 | u8 tmp; | |
137 | ||
138 | /* no need for read if whole reg is written */ | |
139 | if (mask != 0xff) { | |
09611caa | 140 | ret = af9033_rd_regs(dev, reg, &tmp, 1); |
4b64bb26 AP |
141 | if (ret) |
142 | return ret; | |
143 | ||
144 | val &= mask; | |
145 | tmp &= ~mask; | |
146 | val |= tmp; | |
147 | } | |
148 | ||
09611caa | 149 | return af9033_wr_regs(dev, reg, &val, 1); |
4b64bb26 AP |
150 | } |
151 | ||
152 | /* read single register with mask */ | |
09611caa | 153 | static int af9033_rd_reg_mask(struct af9033_dev *dev, u32 reg, u8 *val, |
4b64bb26 AP |
154 | u8 mask) |
155 | { | |
156 | int ret, i; | |
157 | u8 tmp; | |
158 | ||
09611caa | 159 | ret = af9033_rd_regs(dev, reg, &tmp, 1); |
4b64bb26 AP |
160 | if (ret) |
161 | return ret; | |
162 | ||
163 | tmp &= mask; | |
164 | ||
165 | /* find position of the first bit */ | |
166 | for (i = 0; i < 8; i++) { | |
167 | if ((mask >> i) & 0x01) | |
168 | break; | |
169 | } | |
170 | *val = tmp >> i; | |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
3bf5e552 | 175 | /* write reg val table using reg addr auto increment */ |
09611caa | 176 | static int af9033_wr_reg_val_tab(struct af9033_dev *dev, |
3bf5e552 AP |
177 | const struct reg_val *tab, int tab_len) |
178 | { | |
d18a88b1 | 179 | #define MAX_TAB_LEN 212 |
3bf5e552 | 180 | int ret, i, j; |
d18a88b1 AP |
181 | u8 buf[1 + MAX_TAB_LEN]; |
182 | ||
6a087f1f | 183 | dev_dbg(&dev->client->dev, "tab_len=%d\n", tab_len); |
37ebaf68 MCC |
184 | |
185 | if (tab_len > sizeof(buf)) { | |
6a087f1f | 186 | dev_warn(&dev->client->dev, "tab len %d is too big\n", tab_len); |
37ebaf68 MCC |
187 | return -EINVAL; |
188 | } | |
3bf5e552 | 189 | |
3bf5e552 AP |
190 | for (i = 0, j = 0; i < tab_len; i++) { |
191 | buf[j] = tab[i].val; | |
192 | ||
193 | if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) { | |
09611caa | 194 | ret = af9033_wr_regs(dev, tab[i].reg - j, buf, j + 1); |
3bf5e552 AP |
195 | if (ret < 0) |
196 | goto err; | |
197 | ||
198 | j = 0; | |
199 | } else { | |
200 | j++; | |
201 | } | |
202 | } | |
203 | ||
204 | return 0; | |
205 | ||
206 | err: | |
6a087f1f | 207 | dev_dbg(&dev->client->dev, "failed=%d\n", ret); |
3bf5e552 AP |
208 | |
209 | return ret; | |
210 | } | |
211 | ||
09611caa | 212 | static u32 af9033_div(struct af9033_dev *dev, u32 a, u32 b, u32 x) |
4b64bb26 AP |
213 | { |
214 | u32 r = 0, c = 0, i; | |
215 | ||
6a087f1f | 216 | dev_dbg(&dev->client->dev, "a=%d b=%d x=%d\n", a, b, x); |
4b64bb26 AP |
217 | |
218 | if (a > b) { | |
219 | c = a / b; | |
220 | a = a - c * b; | |
221 | } | |
222 | ||
223 | for (i = 0; i < x; i++) { | |
224 | if (a >= b) { | |
225 | r += 1; | |
226 | a -= b; | |
227 | } | |
228 | a <<= 1; | |
229 | r <<= 1; | |
230 | } | |
231 | r = (c << (u32)x) + r; | |
232 | ||
6a087f1f | 233 | dev_dbg(&dev->client->dev, "a=%d b=%d x=%d r=%d r=%x\n", a, b, x, r, r); |
4b64bb26 AP |
234 | |
235 | return r; | |
236 | } | |
237 | ||
4b64bb26 AP |
238 | static int af9033_init(struct dvb_frontend *fe) |
239 | { | |
09611caa | 240 | struct af9033_dev *dev = fe->demodulator_priv; |
2db4d179 | 241 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
4b64bb26 AP |
242 | int ret, i, len; |
243 | const struct reg_val *init; | |
244 | u8 buf[4]; | |
245 | u32 adc_cw, clock_cw; | |
246 | struct reg_val_mask tab[] = { | |
247 | { 0x80fb24, 0x00, 0x08 }, | |
248 | { 0x80004c, 0x00, 0xff }, | |
09611caa | 249 | { 0x00f641, dev->cfg.tuner, 0xff }, |
4b64bb26 AP |
250 | { 0x80f5ca, 0x01, 0x01 }, |
251 | { 0x80f715, 0x01, 0x01 }, | |
252 | { 0x00f41f, 0x04, 0x04 }, | |
253 | { 0x00f41a, 0x01, 0x01 }, | |
254 | { 0x80f731, 0x00, 0x01 }, | |
255 | { 0x00d91e, 0x00, 0x01 }, | |
256 | { 0x00d919, 0x00, 0x01 }, | |
257 | { 0x80f732, 0x00, 0x01 }, | |
258 | { 0x00d91f, 0x00, 0x01 }, | |
259 | { 0x00d91a, 0x00, 0x01 }, | |
260 | { 0x80f730, 0x00, 0x01 }, | |
261 | { 0x80f778, 0x00, 0xff }, | |
262 | { 0x80f73c, 0x01, 0x01 }, | |
263 | { 0x80f776, 0x00, 0x01 }, | |
264 | { 0x00d8fd, 0x01, 0xff }, | |
265 | { 0x00d830, 0x01, 0xff }, | |
266 | { 0x00d831, 0x00, 0xff }, | |
267 | { 0x00d832, 0x00, 0xff }, | |
09611caa AP |
268 | { 0x80f985, dev->ts_mode_serial, 0x01 }, |
269 | { 0x80f986, dev->ts_mode_parallel, 0x01 }, | |
4b64bb26 AP |
270 | { 0x00d827, 0x00, 0xff }, |
271 | { 0x00d829, 0x00, 0xff }, | |
09611caa | 272 | { 0x800045, dev->cfg.adc_multiplier, 0xff }, |
4b64bb26 AP |
273 | }; |
274 | ||
275 | /* program clock control */ | |
09611caa | 276 | clock_cw = af9033_div(dev, dev->cfg.clock, 1000000ul, 19ul); |
4b64bb26 AP |
277 | buf[0] = (clock_cw >> 0) & 0xff; |
278 | buf[1] = (clock_cw >> 8) & 0xff; | |
279 | buf[2] = (clock_cw >> 16) & 0xff; | |
280 | buf[3] = (clock_cw >> 24) & 0xff; | |
281 | ||
6a087f1f AP |
282 | dev_dbg(&dev->client->dev, "clock=%d clock_cw=%08x\n", |
283 | dev->cfg.clock, clock_cw); | |
4b64bb26 | 284 | |
09611caa | 285 | ret = af9033_wr_regs(dev, 0x800025, buf, 4); |
4b64bb26 AP |
286 | if (ret < 0) |
287 | goto err; | |
288 | ||
289 | /* program ADC control */ | |
290 | for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { | |
09611caa | 291 | if (clock_adc_lut[i].clock == dev->cfg.clock) |
4b64bb26 AP |
292 | break; |
293 | } | |
060f79d5 MCC |
294 | if (i == ARRAY_SIZE(clock_adc_lut)) { |
295 | dev_err(&dev->client->dev, | |
296 | "Couldn't find ADC config for clock=%d\n", | |
297 | dev->cfg.clock); | |
298 | goto err; | |
299 | } | |
4b64bb26 | 300 | |
09611caa | 301 | adc_cw = af9033_div(dev, clock_adc_lut[i].adc, 1000000ul, 19ul); |
4b64bb26 AP |
302 | buf[0] = (adc_cw >> 0) & 0xff; |
303 | buf[1] = (adc_cw >> 8) & 0xff; | |
304 | buf[2] = (adc_cw >> 16) & 0xff; | |
305 | ||
6a087f1f AP |
306 | dev_dbg(&dev->client->dev, "adc=%d adc_cw=%06x\n", |
307 | clock_adc_lut[i].adc, adc_cw); | |
4b64bb26 | 308 | |
09611caa | 309 | ret = af9033_wr_regs(dev, 0x80f1cd, buf, 3); |
4b64bb26 AP |
310 | if (ret < 0) |
311 | goto err; | |
312 | ||
313 | /* program register table */ | |
314 | for (i = 0; i < ARRAY_SIZE(tab); i++) { | |
09611caa | 315 | ret = af9033_wr_reg_mask(dev, tab[i].reg, tab[i].val, |
4b64bb26 AP |
316 | tab[i].mask); |
317 | if (ret < 0) | |
318 | goto err; | |
319 | } | |
320 | ||
ca681fe0 | 321 | /* clock output */ |
09611caa AP |
322 | if (dev->cfg.dyn0_clk) { |
323 | ret = af9033_wr_reg(dev, 0x80fba8, 0x00); | |
9dc0f3fe AP |
324 | if (ret < 0) |
325 | goto err; | |
326 | } | |
327 | ||
4b64bb26 | 328 | /* settings for TS interface */ |
09611caa AP |
329 | if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) { |
330 | ret = af9033_wr_reg_mask(dev, 0x80f9a5, 0x00, 0x01); | |
4b64bb26 AP |
331 | if (ret < 0) |
332 | goto err; | |
333 | ||
09611caa | 334 | ret = af9033_wr_reg_mask(dev, 0x80f9b5, 0x01, 0x01); |
4b64bb26 AP |
335 | if (ret < 0) |
336 | goto err; | |
337 | } else { | |
09611caa | 338 | ret = af9033_wr_reg_mask(dev, 0x80f990, 0x00, 0x01); |
4b64bb26 AP |
339 | if (ret < 0) |
340 | goto err; | |
341 | ||
09611caa | 342 | ret = af9033_wr_reg_mask(dev, 0x80f9b5, 0x00, 0x01); |
4b64bb26 AP |
343 | if (ret < 0) |
344 | goto err; | |
345 | } | |
346 | ||
347 | /* load OFSM settings */ | |
6a087f1f | 348 | dev_dbg(&dev->client->dev, "load ofsm settings\n"); |
09611caa | 349 | switch (dev->cfg.tuner) { |
fe8eece1 AP |
350 | case AF9033_TUNER_IT9135_38: |
351 | case AF9033_TUNER_IT9135_51: | |
352 | case AF9033_TUNER_IT9135_52: | |
463c399c AP |
353 | len = ARRAY_SIZE(ofsm_init_it9135_v1); |
354 | init = ofsm_init_it9135_v1; | |
355 | break; | |
fe8eece1 AP |
356 | case AF9033_TUNER_IT9135_60: |
357 | case AF9033_TUNER_IT9135_61: | |
358 | case AF9033_TUNER_IT9135_62: | |
463c399c AP |
359 | len = ARRAY_SIZE(ofsm_init_it9135_v2); |
360 | init = ofsm_init_it9135_v2; | |
fe8eece1 AP |
361 | break; |
362 | default: | |
363 | len = ARRAY_SIZE(ofsm_init); | |
364 | init = ofsm_init; | |
365 | break; | |
366 | } | |
367 | ||
09611caa | 368 | ret = af9033_wr_reg_val_tab(dev, init, len); |
3bf5e552 AP |
369 | if (ret < 0) |
370 | goto err; | |
4b64bb26 AP |
371 | |
372 | /* load tuner specific settings */ | |
6a087f1f | 373 | dev_dbg(&dev->client->dev, "load tuner specific settings\n"); |
09611caa | 374 | switch (dev->cfg.tuner) { |
4b64bb26 AP |
375 | case AF9033_TUNER_TUA9001: |
376 | len = ARRAY_SIZE(tuner_init_tua9001); | |
377 | init = tuner_init_tua9001; | |
378 | break; | |
ffc501f6 MB |
379 | case AF9033_TUNER_FC0011: |
380 | len = ARRAY_SIZE(tuner_init_fc0011); | |
381 | init = tuner_init_fc0011; | |
382 | break; | |
540fd4ba HFV |
383 | case AF9033_TUNER_MXL5007T: |
384 | len = ARRAY_SIZE(tuner_init_mxl5007t); | |
385 | init = tuner_init_mxl5007t; | |
386 | break; | |
ce1fe379 GG |
387 | case AF9033_TUNER_TDA18218: |
388 | len = ARRAY_SIZE(tuner_init_tda18218); | |
389 | init = tuner_init_tda18218; | |
390 | break; | |
d67ceb33 OS |
391 | case AF9033_TUNER_FC2580: |
392 | len = ARRAY_SIZE(tuner_init_fc2580); | |
393 | init = tuner_init_fc2580; | |
394 | break; | |
e713ad15 AP |
395 | case AF9033_TUNER_FC0012: |
396 | len = ARRAY_SIZE(tuner_init_fc0012); | |
397 | init = tuner_init_fc0012; | |
398 | break; | |
4902bb39 | 399 | case AF9033_TUNER_IT9135_38: |
a72cbb77 AP |
400 | len = ARRAY_SIZE(tuner_init_it9135_38); |
401 | init = tuner_init_it9135_38; | |
402 | break; | |
4902bb39 | 403 | case AF9033_TUNER_IT9135_51: |
bb2e12a6 AP |
404 | len = ARRAY_SIZE(tuner_init_it9135_51); |
405 | init = tuner_init_it9135_51; | |
406 | break; | |
4902bb39 | 407 | case AF9033_TUNER_IT9135_52: |
22d729f3 AP |
408 | len = ARRAY_SIZE(tuner_init_it9135_52); |
409 | init = tuner_init_it9135_52; | |
410 | break; | |
4902bb39 | 411 | case AF9033_TUNER_IT9135_60: |
a49f53a0 AP |
412 | len = ARRAY_SIZE(tuner_init_it9135_60); |
413 | init = tuner_init_it9135_60; | |
414 | break; | |
4902bb39 | 415 | case AF9033_TUNER_IT9135_61: |
85211323 AP |
416 | len = ARRAY_SIZE(tuner_init_it9135_61); |
417 | init = tuner_init_it9135_61; | |
418 | break; | |
4902bb39 | 419 | case AF9033_TUNER_IT9135_62: |
dc4a2c40 AP |
420 | len = ARRAY_SIZE(tuner_init_it9135_62); |
421 | init = tuner_init_it9135_62; | |
4902bb39 | 422 | break; |
4b64bb26 | 423 | default: |
6a087f1f AP |
424 | dev_dbg(&dev->client->dev, "unsupported tuner ID=%d\n", |
425 | dev->cfg.tuner); | |
4b64bb26 AP |
426 | ret = -ENODEV; |
427 | goto err; | |
428 | } | |
429 | ||
09611caa | 430 | ret = af9033_wr_reg_val_tab(dev, init, len); |
3bf5e552 AP |
431 | if (ret < 0) |
432 | goto err; | |
4b64bb26 | 433 | |
09611caa AP |
434 | if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { |
435 | ret = af9033_wr_reg_mask(dev, 0x00d91c, 0x01, 0x01); | |
9805992f JAR |
436 | if (ret < 0) |
437 | goto err; | |
bf97b637 | 438 | |
09611caa | 439 | ret = af9033_wr_reg_mask(dev, 0x00d917, 0x00, 0x01); |
9805992f JAR |
440 | if (ret < 0) |
441 | goto err; | |
bf97b637 | 442 | |
09611caa | 443 | ret = af9033_wr_reg_mask(dev, 0x00d916, 0x00, 0x01); |
9805992f JAR |
444 | if (ret < 0) |
445 | goto err; | |
446 | } | |
447 | ||
09611caa | 448 | switch (dev->cfg.tuner) { |
086991dd AP |
449 | case AF9033_TUNER_IT9135_60: |
450 | case AF9033_TUNER_IT9135_61: | |
451 | case AF9033_TUNER_IT9135_62: | |
09611caa | 452 | ret = af9033_wr_reg(dev, 0x800000, 0x01); |
086991dd AP |
453 | if (ret < 0) |
454 | goto err; | |
455 | } | |
456 | ||
09611caa | 457 | dev->bandwidth_hz = 0; /* force to program all parameters */ |
2db4d179 AP |
458 | /* init stats here in order signal app which stats are supported */ |
459 | c->strength.len = 1; | |
460 | c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
461 | c->cnr.len = 1; | |
462 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
463 | c->block_count.len = 1; | |
464 | c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
465 | c->block_error.len = 1; | |
466 | c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
467 | c->post_bit_count.len = 1; | |
468 | c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
469 | c->post_bit_error.len = 1; | |
470 | c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
83f11619 AP |
471 | /* start statistics polling */ |
472 | schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000)); | |
4b64bb26 AP |
473 | |
474 | return 0; | |
475 | ||
476 | err: | |
6a087f1f | 477 | dev_dbg(&dev->client->dev, "failed=%d\n", ret); |
4b64bb26 AP |
478 | |
479 | return ret; | |
480 | } | |
481 | ||
482 | static int af9033_sleep(struct dvb_frontend *fe) | |
483 | { | |
09611caa | 484 | struct af9033_dev *dev = fe->demodulator_priv; |
4b64bb26 AP |
485 | int ret, i; |
486 | u8 tmp; | |
487 | ||
83f11619 AP |
488 | /* stop statistics polling */ |
489 | cancel_delayed_work_sync(&dev->stat_work); | |
490 | ||
09611caa | 491 | ret = af9033_wr_reg(dev, 0x80004c, 1); |
4b64bb26 AP |
492 | if (ret < 0) |
493 | goto err; | |
494 | ||
09611caa | 495 | ret = af9033_wr_reg(dev, 0x800000, 0); |
4b64bb26 AP |
496 | if (ret < 0) |
497 | goto err; | |
498 | ||
499 | for (i = 100, tmp = 1; i && tmp; i--) { | |
09611caa | 500 | ret = af9033_rd_reg(dev, 0x80004c, &tmp); |
4b64bb26 AP |
501 | if (ret < 0) |
502 | goto err; | |
503 | ||
504 | usleep_range(200, 10000); | |
505 | } | |
506 | ||
6a087f1f | 507 | dev_dbg(&dev->client->dev, "loop=%d\n", i); |
4b64bb26 AP |
508 | |
509 | if (i == 0) { | |
510 | ret = -ETIMEDOUT; | |
511 | goto err; | |
512 | } | |
513 | ||
09611caa | 514 | ret = af9033_wr_reg_mask(dev, 0x80fb24, 0x08, 0x08); |
4b64bb26 AP |
515 | if (ret < 0) |
516 | goto err; | |
517 | ||
518 | /* prevent current leak (?) */ | |
09611caa | 519 | if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { |
4b64bb26 | 520 | /* enable parallel TS */ |
09611caa | 521 | ret = af9033_wr_reg_mask(dev, 0x00d917, 0x00, 0x01); |
4b64bb26 AP |
522 | if (ret < 0) |
523 | goto err; | |
524 | ||
09611caa | 525 | ret = af9033_wr_reg_mask(dev, 0x00d916, 0x01, 0x01); |
4b64bb26 AP |
526 | if (ret < 0) |
527 | goto err; | |
528 | } | |
529 | ||
530 | return 0; | |
531 | ||
532 | err: | |
6a087f1f | 533 | dev_dbg(&dev->client->dev, "failed=%d\n", ret); |
4b64bb26 AP |
534 | |
535 | return ret; | |
536 | } | |
537 | ||
538 | static int af9033_get_tune_settings(struct dvb_frontend *fe, | |
539 | struct dvb_frontend_tune_settings *fesettings) | |
540 | { | |
fe8eece1 AP |
541 | /* 800 => 2000 because IT9135 v2 is slow to gain lock */ |
542 | fesettings->min_delay_ms = 2000; | |
4b64bb26 AP |
543 | fesettings->step_size = 0; |
544 | fesettings->max_drift = 0; | |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
549 | static int af9033_set_frontend(struct dvb_frontend *fe) | |
550 | { | |
09611caa | 551 | struct af9033_dev *dev = fe->demodulator_priv; |
4b64bb26 | 552 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
182b967e | 553 | int ret, i, spec_inv, sampling_freq; |
4b64bb26 | 554 | u8 tmp, buf[3], bandwidth_reg_val; |
540fd4ba | 555 | u32 if_frequency, freq_cw, adc_freq; |
4b64bb26 | 556 | |
6a087f1f AP |
557 | dev_dbg(&dev->client->dev, "frequency=%d bandwidth_hz=%d\n", |
558 | c->frequency, c->bandwidth_hz); | |
4b64bb26 AP |
559 | |
560 | /* check bandwidth */ | |
561 | switch (c->bandwidth_hz) { | |
562 | case 6000000: | |
563 | bandwidth_reg_val = 0x00; | |
564 | break; | |
565 | case 7000000: | |
566 | bandwidth_reg_val = 0x01; | |
567 | break; | |
568 | case 8000000: | |
569 | bandwidth_reg_val = 0x02; | |
570 | break; | |
571 | default: | |
6a087f1f | 572 | dev_dbg(&dev->client->dev, "invalid bandwidth_hz\n"); |
4b64bb26 AP |
573 | ret = -EINVAL; |
574 | goto err; | |
575 | } | |
576 | ||
577 | /* program tuner */ | |
578 | if (fe->ops.tuner_ops.set_params) | |
579 | fe->ops.tuner_ops.set_params(fe); | |
580 | ||
581 | /* program CFOE coefficients */ | |
09611caa | 582 | if (c->bandwidth_hz != dev->bandwidth_hz) { |
4b64bb26 | 583 | for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) { |
09611caa | 584 | if (coeff_lut[i].clock == dev->cfg.clock && |
4b64bb26 AP |
585 | coeff_lut[i].bandwidth_hz == c->bandwidth_hz) { |
586 | break; | |
587 | } | |
588 | } | |
060f79d5 MCC |
589 | if (i == ARRAY_SIZE(coeff_lut)) { |
590 | dev_err(&dev->client->dev, | |
591 | "Couldn't find LUT config for clock=%d\n", | |
592 | dev->cfg.clock); | |
593 | ret = -EINVAL; | |
594 | goto err; | |
595 | } | |
596 | ||
597 | ret = af9033_wr_regs(dev, 0x800001, | |
4b64bb26 AP |
598 | coeff_lut[i].val, sizeof(coeff_lut[i].val)); |
599 | } | |
600 | ||
601 | /* program frequency control */ | |
09611caa AP |
602 | if (c->bandwidth_hz != dev->bandwidth_hz) { |
603 | spec_inv = dev->cfg.spec_inv ? -1 : 1; | |
540fd4ba HFV |
604 | |
605 | for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { | |
09611caa | 606 | if (clock_adc_lut[i].clock == dev->cfg.clock) |
540fd4ba HFV |
607 | break; |
608 | } | |
060f79d5 MCC |
609 | if (i == ARRAY_SIZE(clock_adc_lut)) { |
610 | dev_err(&dev->client->dev, | |
611 | "Couldn't find ADC clock for clock=%d\n", | |
612 | dev->cfg.clock); | |
613 | ret = -EINVAL; | |
614 | goto err; | |
615 | } | |
540fd4ba HFV |
616 | adc_freq = clock_adc_lut[i].adc; |
617 | ||
4b64bb26 AP |
618 | /* get used IF frequency */ |
619 | if (fe->ops.tuner_ops.get_if_frequency) | |
620 | fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency); | |
621 | else | |
622 | if_frequency = 0; | |
623 | ||
182b967e | 624 | sampling_freq = if_frequency; |
4b64bb26 | 625 | |
182b967e HFV |
626 | while (sampling_freq > (adc_freq / 2)) |
627 | sampling_freq -= adc_freq; | |
628 | ||
629 | if (sampling_freq >= 0) | |
540fd4ba HFV |
630 | spec_inv *= -1; |
631 | else | |
182b967e | 632 | sampling_freq *= -1; |
540fd4ba | 633 | |
09611caa | 634 | freq_cw = af9033_div(dev, sampling_freq, adc_freq, 23ul); |
540fd4ba HFV |
635 | |
636 | if (spec_inv == -1) | |
182b967e | 637 | freq_cw = 0x800000 - freq_cw; |
540fd4ba | 638 | |
09611caa | 639 | if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X) |
540fd4ba HFV |
640 | freq_cw /= 2; |
641 | ||
4b64bb26 AP |
642 | buf[0] = (freq_cw >> 0) & 0xff; |
643 | buf[1] = (freq_cw >> 8) & 0xff; | |
644 | buf[2] = (freq_cw >> 16) & 0x7f; | |
fe8eece1 AP |
645 | |
646 | /* FIXME: there seems to be calculation error here... */ | |
647 | if (if_frequency == 0) | |
648 | buf[2] = 0; | |
649 | ||
09611caa | 650 | ret = af9033_wr_regs(dev, 0x800029, buf, 3); |
4b64bb26 AP |
651 | if (ret < 0) |
652 | goto err; | |
653 | ||
09611caa | 654 | dev->bandwidth_hz = c->bandwidth_hz; |
4b64bb26 AP |
655 | } |
656 | ||
09611caa | 657 | ret = af9033_wr_reg_mask(dev, 0x80f904, bandwidth_reg_val, 0x03); |
4b64bb26 AP |
658 | if (ret < 0) |
659 | goto err; | |
660 | ||
09611caa | 661 | ret = af9033_wr_reg(dev, 0x800040, 0x00); |
4b64bb26 AP |
662 | if (ret < 0) |
663 | goto err; | |
664 | ||
09611caa | 665 | ret = af9033_wr_reg(dev, 0x800047, 0x00); |
4b64bb26 AP |
666 | if (ret < 0) |
667 | goto err; | |
668 | ||
09611caa | 669 | ret = af9033_wr_reg_mask(dev, 0x80f999, 0x00, 0x01); |
4b64bb26 AP |
670 | if (ret < 0) |
671 | goto err; | |
672 | ||
673 | if (c->frequency <= 230000000) | |
674 | tmp = 0x00; /* VHF */ | |
675 | else | |
676 | tmp = 0x01; /* UHF */ | |
677 | ||
09611caa | 678 | ret = af9033_wr_reg(dev, 0x80004b, tmp); |
4b64bb26 AP |
679 | if (ret < 0) |
680 | goto err; | |
681 | ||
09611caa | 682 | ret = af9033_wr_reg(dev, 0x800000, 0x00); |
4b64bb26 AP |
683 | if (ret < 0) |
684 | goto err; | |
685 | ||
686 | return 0; | |
687 | ||
688 | err: | |
6a087f1f | 689 | dev_dbg(&dev->client->dev, "failed=%d\n", ret); |
4b64bb26 AP |
690 | |
691 | return ret; | |
692 | } | |
693 | ||
0a4df239 GG |
694 | static int af9033_get_frontend(struct dvb_frontend *fe) |
695 | { | |
09611caa | 696 | struct af9033_dev *dev = fe->demodulator_priv; |
de7f14fc | 697 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
0a4df239 GG |
698 | int ret; |
699 | u8 buf[8]; | |
700 | ||
6a087f1f | 701 | dev_dbg(&dev->client->dev, "\n"); |
0a4df239 GG |
702 | |
703 | /* read all needed registers */ | |
09611caa | 704 | ret = af9033_rd_regs(dev, 0x80f900, buf, sizeof(buf)); |
de7f14fc AP |
705 | if (ret < 0) |
706 | goto err; | |
0a4df239 GG |
707 | |
708 | switch ((buf[0] >> 0) & 3) { | |
709 | case 0: | |
de7f14fc | 710 | c->transmission_mode = TRANSMISSION_MODE_2K; |
0a4df239 GG |
711 | break; |
712 | case 1: | |
de7f14fc | 713 | c->transmission_mode = TRANSMISSION_MODE_8K; |
0a4df239 GG |
714 | break; |
715 | } | |
716 | ||
717 | switch ((buf[1] >> 0) & 3) { | |
718 | case 0: | |
de7f14fc | 719 | c->guard_interval = GUARD_INTERVAL_1_32; |
0a4df239 GG |
720 | break; |
721 | case 1: | |
de7f14fc | 722 | c->guard_interval = GUARD_INTERVAL_1_16; |
0a4df239 GG |
723 | break; |
724 | case 2: | |
de7f14fc | 725 | c->guard_interval = GUARD_INTERVAL_1_8; |
0a4df239 GG |
726 | break; |
727 | case 3: | |
de7f14fc | 728 | c->guard_interval = GUARD_INTERVAL_1_4; |
0a4df239 GG |
729 | break; |
730 | } | |
731 | ||
732 | switch ((buf[2] >> 0) & 7) { | |
733 | case 0: | |
de7f14fc | 734 | c->hierarchy = HIERARCHY_NONE; |
0a4df239 GG |
735 | break; |
736 | case 1: | |
de7f14fc | 737 | c->hierarchy = HIERARCHY_1; |
0a4df239 GG |
738 | break; |
739 | case 2: | |
de7f14fc | 740 | c->hierarchy = HIERARCHY_2; |
0a4df239 GG |
741 | break; |
742 | case 3: | |
de7f14fc | 743 | c->hierarchy = HIERARCHY_4; |
0a4df239 GG |
744 | break; |
745 | } | |
746 | ||
747 | switch ((buf[3] >> 0) & 3) { | |
748 | case 0: | |
de7f14fc | 749 | c->modulation = QPSK; |
0a4df239 GG |
750 | break; |
751 | case 1: | |
de7f14fc | 752 | c->modulation = QAM_16; |
0a4df239 GG |
753 | break; |
754 | case 2: | |
de7f14fc | 755 | c->modulation = QAM_64; |
0a4df239 GG |
756 | break; |
757 | } | |
758 | ||
759 | switch ((buf[4] >> 0) & 3) { | |
760 | case 0: | |
de7f14fc | 761 | c->bandwidth_hz = 6000000; |
0a4df239 GG |
762 | break; |
763 | case 1: | |
de7f14fc | 764 | c->bandwidth_hz = 7000000; |
0a4df239 GG |
765 | break; |
766 | case 2: | |
de7f14fc | 767 | c->bandwidth_hz = 8000000; |
0a4df239 GG |
768 | break; |
769 | } | |
770 | ||
771 | switch ((buf[6] >> 0) & 7) { | |
772 | case 0: | |
de7f14fc | 773 | c->code_rate_HP = FEC_1_2; |
0a4df239 GG |
774 | break; |
775 | case 1: | |
de7f14fc | 776 | c->code_rate_HP = FEC_2_3; |
0a4df239 GG |
777 | break; |
778 | case 2: | |
de7f14fc | 779 | c->code_rate_HP = FEC_3_4; |
0a4df239 GG |
780 | break; |
781 | case 3: | |
de7f14fc | 782 | c->code_rate_HP = FEC_5_6; |
0a4df239 GG |
783 | break; |
784 | case 4: | |
de7f14fc | 785 | c->code_rate_HP = FEC_7_8; |
0a4df239 GG |
786 | break; |
787 | case 5: | |
de7f14fc | 788 | c->code_rate_HP = FEC_NONE; |
0a4df239 GG |
789 | break; |
790 | } | |
791 | ||
792 | switch ((buf[7] >> 0) & 7) { | |
793 | case 0: | |
de7f14fc | 794 | c->code_rate_LP = FEC_1_2; |
0a4df239 GG |
795 | break; |
796 | case 1: | |
de7f14fc | 797 | c->code_rate_LP = FEC_2_3; |
0a4df239 GG |
798 | break; |
799 | case 2: | |
de7f14fc | 800 | c->code_rate_LP = FEC_3_4; |
0a4df239 GG |
801 | break; |
802 | case 3: | |
de7f14fc | 803 | c->code_rate_LP = FEC_5_6; |
0a4df239 GG |
804 | break; |
805 | case 4: | |
de7f14fc | 806 | c->code_rate_LP = FEC_7_8; |
0a4df239 GG |
807 | break; |
808 | case 5: | |
de7f14fc | 809 | c->code_rate_LP = FEC_NONE; |
0a4df239 GG |
810 | break; |
811 | } | |
812 | ||
de7f14fc | 813 | return 0; |
0a4df239 | 814 | |
de7f14fc | 815 | err: |
6a087f1f | 816 | dev_dbg(&dev->client->dev, "failed=%d\n", ret); |
0a4df239 GG |
817 | |
818 | return ret; | |
819 | } | |
820 | ||
0df289a2 | 821 | static int af9033_read_status(struct dvb_frontend *fe, enum fe_status *status) |
4b64bb26 | 822 | { |
09611caa | 823 | struct af9033_dev *dev = fe->demodulator_priv; |
4b64bb26 AP |
824 | int ret; |
825 | u8 tmp; | |
826 | ||
827 | *status = 0; | |
828 | ||
829 | /* radio channel status, 0=no result, 1=has signal, 2=no signal */ | |
09611caa | 830 | ret = af9033_rd_reg(dev, 0x800047, &tmp); |
4b64bb26 AP |
831 | if (ret < 0) |
832 | goto err; | |
833 | ||
834 | /* has signal */ | |
835 | if (tmp == 0x01) | |
836 | *status |= FE_HAS_SIGNAL; | |
837 | ||
838 | if (tmp != 0x02) { | |
839 | /* TPS lock */ | |
09611caa | 840 | ret = af9033_rd_reg_mask(dev, 0x80f5a9, &tmp, 0x01); |
4b64bb26 AP |
841 | if (ret < 0) |
842 | goto err; | |
843 | ||
844 | if (tmp) | |
845 | *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | | |
846 | FE_HAS_VITERBI; | |
847 | ||
848 | /* full lock */ | |
09611caa | 849 | ret = af9033_rd_reg_mask(dev, 0x80f999, &tmp, 0x01); |
4b64bb26 AP |
850 | if (ret < 0) |
851 | goto err; | |
852 | ||
853 | if (tmp) | |
854 | *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | | |
855 | FE_HAS_VITERBI | FE_HAS_SYNC | | |
856 | FE_HAS_LOCK; | |
857 | } | |
858 | ||
83f11619 AP |
859 | dev->fe_status = *status; |
860 | ||
4b64bb26 AP |
861 | return 0; |
862 | ||
863 | err: | |
6a087f1f | 864 | dev_dbg(&dev->client->dev, "failed=%d\n", ret); |
4b64bb26 AP |
865 | |
866 | return ret; | |
867 | } | |
868 | ||
869 | static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr) | |
870 | { | |
09611caa | 871 | struct af9033_dev *dev = fe->demodulator_priv; |
6b457786 | 872 | struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache; |
6d03f6a8 BC |
873 | int ret; |
874 | u8 u8tmp; | |
e898ef62 | 875 | |
6b457786 | 876 | /* use DVBv5 CNR */ |
6d03f6a8 | 877 | if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) { |
c3a80cd0 AP |
878 | /* Return 0.1 dB for AF9030 and 0-0xffff for IT9130. */ |
879 | if (dev->is_af9035) { | |
880 | /* 1000x => 10x (0.1 dB) */ | |
881 | *snr = div_s64(c->cnr.stat[0].svalue, 100); | |
882 | } else { | |
883 | /* 1000x => 1x (1 dB) */ | |
884 | *snr = div_s64(c->cnr.stat[0].svalue, 1000); | |
6d03f6a8 | 885 | |
c3a80cd0 AP |
886 | /* read current modulation */ |
887 | ret = af9033_rd_reg(dev, 0x80f903, &u8tmp); | |
888 | if (ret) | |
889 | goto err; | |
6d03f6a8 | 890 | |
c3a80cd0 AP |
891 | /* scale value to 0x0000-0xffff */ |
892 | switch ((u8tmp >> 0) & 3) { | |
893 | case 0: | |
894 | *snr = *snr * 0xffff / 23; | |
895 | break; | |
896 | case 1: | |
897 | *snr = *snr * 0xffff / 26; | |
898 | break; | |
899 | case 2: | |
900 | *snr = *snr * 0xffff / 32; | |
901 | break; | |
902 | default: | |
903 | goto err; | |
904 | } | |
6d03f6a8 BC |
905 | } |
906 | } else { | |
6b457786 | 907 | *snr = 0; |
6d03f6a8 | 908 | } |
4b64bb26 AP |
909 | |
910 | return 0; | |
6d03f6a8 BC |
911 | |
912 | err: | |
913 | dev_dbg(&dev->client->dev, "failed=%d\n", ret); | |
914 | ||
915 | return ret; | |
4b64bb26 AP |
916 | } |
917 | ||
918 | static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength) | |
919 | { | |
09611caa | 920 | struct af9033_dev *dev = fe->demodulator_priv; |
3adec272 BC |
921 | struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache; |
922 | int ret, tmp, power_real; | |
923 | u8 u8tmp, gain_offset, buf[7]; | |
4b64bb26 | 924 | |
3adec272 | 925 | if (dev->is_af9035) { |
0b0d9628 AP |
926 | /* read signal strength of 0-100 scale */ |
927 | ret = af9033_rd_reg(dev, 0x800048, &u8tmp); | |
928 | if (ret < 0) | |
929 | goto err; | |
930 | ||
3adec272 BC |
931 | /* scale value to 0x0000-0xffff */ |
932 | *strength = u8tmp * 0xffff / 100; | |
933 | } else { | |
934 | ret = af9033_rd_reg(dev, 0x8000f7, &u8tmp); | |
1620d221 AP |
935 | if (ret < 0) |
936 | goto err; | |
937 | ||
938 | ret = af9033_rd_regs(dev, 0x80f900, buf, 7); | |
939 | if (ret < 0) | |
940 | goto err; | |
3adec272 BC |
941 | |
942 | if (c->frequency <= 300000000) | |
943 | gain_offset = 7; /* VHF */ | |
944 | else | |
945 | gain_offset = 4; /* UHF */ | |
946 | ||
947 | power_real = (u8tmp - 100 - gain_offset) - | |
948 | power_reference[((buf[3] >> 0) & 3)][((buf[6] >> 0) & 7)]; | |
949 | ||
950 | if (power_real < -15) | |
951 | tmp = 0; | |
952 | else if ((power_real >= -15) && (power_real < 0)) | |
953 | tmp = (2 * (power_real + 15)) / 3; | |
954 | else if ((power_real >= 0) && (power_real < 20)) | |
955 | tmp = 4 * power_real + 10; | |
956 | else if ((power_real >= 20) && (power_real < 35)) | |
957 | tmp = (2 * (power_real - 20)) / 3 + 90; | |
958 | else | |
959 | tmp = 100; | |
960 | ||
961 | /* scale value to 0x0000-0xffff */ | |
962 | *strength = tmp * 0xffff / 100; | |
963 | } | |
4b64bb26 | 964 | |
4b64bb26 AP |
965 | return 0; |
966 | ||
967 | err: | |
6a087f1f | 968 | dev_dbg(&dev->client->dev, "failed=%d\n", ret); |
4b64bb26 AP |
969 | |
970 | return ret; | |
971 | } | |
972 | ||
973 | static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber) | |
974 | { | |
09611caa | 975 | struct af9033_dev *dev = fe->demodulator_priv; |
47eafa54 | 976 | |
e53c4744 AP |
977 | *ber = (dev->post_bit_error - dev->post_bit_error_prev); |
978 | dev->post_bit_error_prev = dev->post_bit_error; | |
4b64bb26 AP |
979 | |
980 | return 0; | |
981 | } | |
982 | ||
983 | static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) | |
984 | { | |
09611caa | 985 | struct af9033_dev *dev = fe->demodulator_priv; |
4b64bb26 | 986 | |
1d0ceae4 | 987 | *ucblocks = dev->error_block_count; |
4b64bb26 AP |
988 | return 0; |
989 | } | |
990 | ||
991 | static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) | |
992 | { | |
09611caa | 993 | struct af9033_dev *dev = fe->demodulator_priv; |
4b64bb26 AP |
994 | int ret; |
995 | ||
6a087f1f | 996 | dev_dbg(&dev->client->dev, "enable=%d\n", enable); |
4b64bb26 | 997 | |
09611caa | 998 | ret = af9033_wr_reg_mask(dev, 0x00fa04, enable, 0x01); |
4b64bb26 AP |
999 | if (ret < 0) |
1000 | goto err; | |
1001 | ||
1002 | return 0; | |
1003 | ||
1004 | err: | |
6a087f1f | 1005 | dev_dbg(&dev->client->dev, "failed=%d\n", ret); |
4b64bb26 AP |
1006 | |
1007 | return ret; | |
1008 | } | |
1009 | ||
ed97a6fe | 1010 | static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff) |
040cf86c | 1011 | { |
09611caa | 1012 | struct af9033_dev *dev = fe->demodulator_priv; |
040cf86c AP |
1013 | int ret; |
1014 | ||
6a087f1f | 1015 | dev_dbg(&dev->client->dev, "onoff=%d\n", onoff); |
040cf86c | 1016 | |
09611caa | 1017 | ret = af9033_wr_reg_mask(dev, 0x80f993, onoff, 0x01); |
040cf86c AP |
1018 | if (ret < 0) |
1019 | goto err; | |
1020 | ||
1021 | return 0; | |
1022 | ||
1023 | err: | |
6a087f1f | 1024 | dev_dbg(&dev->client->dev, "failed=%d\n", ret); |
040cf86c AP |
1025 | |
1026 | return ret; | |
1027 | } | |
040cf86c | 1028 | |
24e419a0 AP |
1029 | static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid, |
1030 | int onoff) | |
040cf86c | 1031 | { |
09611caa | 1032 | struct af9033_dev *dev = fe->demodulator_priv; |
040cf86c AP |
1033 | int ret; |
1034 | u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff}; | |
1035 | ||
6a087f1f AP |
1036 | dev_dbg(&dev->client->dev, "index=%d pid=%04x onoff=%d\n", |
1037 | index, pid, onoff); | |
040cf86c AP |
1038 | |
1039 | if (pid > 0x1fff) | |
1040 | return 0; | |
1041 | ||
09611caa | 1042 | ret = af9033_wr_regs(dev, 0x80f996, wbuf, 2); |
040cf86c AP |
1043 | if (ret < 0) |
1044 | goto err; | |
1045 | ||
09611caa | 1046 | ret = af9033_wr_reg(dev, 0x80f994, onoff); |
040cf86c AP |
1047 | if (ret < 0) |
1048 | goto err; | |
1049 | ||
09611caa | 1050 | ret = af9033_wr_reg(dev, 0x80f995, index); |
040cf86c AP |
1051 | if (ret < 0) |
1052 | goto err; | |
1053 | ||
1054 | return 0; | |
1055 | ||
1056 | err: | |
6a087f1f | 1057 | dev_dbg(&dev->client->dev, "failed=%d\n", ret); |
040cf86c AP |
1058 | |
1059 | return ret; | |
1060 | } | |
040cf86c | 1061 | |
83f11619 AP |
1062 | static void af9033_stat_work(struct work_struct *work) |
1063 | { | |
1064 | struct af9033_dev *dev = container_of(work, struct af9033_dev, stat_work.work); | |
1065 | struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache; | |
3e41313a | 1066 | int ret, tmp, i, len; |
204f4319 | 1067 | u8 u8tmp, buf[7]; |
83f11619 AP |
1068 | |
1069 | dev_dbg(&dev->client->dev, "\n"); | |
1070 | ||
3e41313a | 1071 | /* signal strength */ |
83f11619 AP |
1072 | if (dev->fe_status & FE_HAS_SIGNAL) { |
1073 | if (dev->is_af9035) { | |
1074 | ret = af9033_rd_reg(dev, 0x80004a, &u8tmp); | |
1075 | tmp = -u8tmp * 1000; | |
1076 | } else { | |
1077 | ret = af9033_rd_reg(dev, 0x8000f7, &u8tmp); | |
1078 | tmp = (u8tmp - 100) * 1000; | |
1079 | } | |
1080 | if (ret) | |
1081 | goto err; | |
1082 | ||
1083 | c->strength.len = 1; | |
1084 | c->strength.stat[0].scale = FE_SCALE_DECIBEL; | |
1085 | c->strength.stat[0].svalue = tmp; | |
1086 | } else { | |
1087 | c->strength.len = 1; | |
1088 | c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
1089 | } | |
1090 | ||
3e41313a AP |
1091 | /* CNR */ |
1092 | if (dev->fe_status & FE_HAS_VITERBI) { | |
1093 | u32 snr_val; | |
1094 | const struct val_snr *snr_lut; | |
1095 | ||
1096 | /* read value */ | |
1097 | ret = af9033_rd_regs(dev, 0x80002c, buf, 3); | |
1098 | if (ret) | |
1099 | goto err; | |
1100 | ||
1101 | snr_val = (buf[2] << 16) | (buf[1] << 8) | (buf[0] << 0); | |
1102 | ||
6d03f6a8 BC |
1103 | /* read superframe number */ |
1104 | ret = af9033_rd_reg(dev, 0x80f78b, &u8tmp); | |
1105 | if (ret) | |
1106 | goto err; | |
1107 | ||
1108 | if (u8tmp) | |
1109 | snr_val /= u8tmp; | |
1110 | ||
1111 | /* read current transmission mode */ | |
1112 | ret = af9033_rd_reg(dev, 0x80f900, &u8tmp); | |
1113 | if (ret) | |
1114 | goto err; | |
1115 | ||
1116 | switch ((u8tmp >> 0) & 3) { | |
1117 | case 0: | |
1118 | snr_val *= 4; | |
1119 | break; | |
1120 | case 1: | |
1121 | snr_val *= 1; | |
1122 | break; | |
1123 | case 2: | |
1124 | snr_val *= 2; | |
1125 | break; | |
1126 | default: | |
fdc533a9 | 1127 | goto err_schedule_delayed_work; |
6d03f6a8 BC |
1128 | } |
1129 | ||
3e41313a AP |
1130 | /* read current modulation */ |
1131 | ret = af9033_rd_reg(dev, 0x80f903, &u8tmp); | |
1132 | if (ret) | |
1133 | goto err; | |
1134 | ||
1135 | switch ((u8tmp >> 0) & 3) { | |
1136 | case 0: | |
1137 | len = ARRAY_SIZE(qpsk_snr_lut); | |
1138 | snr_lut = qpsk_snr_lut; | |
1139 | break; | |
1140 | case 1: | |
1141 | len = ARRAY_SIZE(qam16_snr_lut); | |
1142 | snr_lut = qam16_snr_lut; | |
1143 | break; | |
1144 | case 2: | |
1145 | len = ARRAY_SIZE(qam64_snr_lut); | |
1146 | snr_lut = qam64_snr_lut; | |
1147 | break; | |
1148 | default: | |
1149 | goto err_schedule_delayed_work; | |
1150 | } | |
1151 | ||
1152 | for (i = 0; i < len; i++) { | |
1153 | tmp = snr_lut[i].snr * 1000; | |
1154 | if (snr_val < snr_lut[i].val) | |
1155 | break; | |
1156 | } | |
1157 | ||
1158 | c->cnr.len = 1; | |
1159 | c->cnr.stat[0].scale = FE_SCALE_DECIBEL; | |
1160 | c->cnr.stat[0].svalue = tmp; | |
1161 | } else { | |
1162 | c->cnr.len = 1; | |
1163 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
1164 | } | |
1165 | ||
204f4319 AP |
1166 | /* UCB/PER/BER */ |
1167 | if (dev->fe_status & FE_HAS_LOCK) { | |
1168 | /* outer FEC, 204 byte packets */ | |
1169 | u16 abort_packet_count, rsd_packet_count; | |
6bb096c9 AP |
1170 | /* inner FEC, bits */ |
1171 | u32 rsd_bit_err_count; | |
204f4319 AP |
1172 | |
1173 | /* | |
1174 | * Packet count used for measurement is 10000 | |
1175 | * (rsd_packet_count). Maybe it should be increased? | |
1176 | */ | |
1177 | ||
1178 | ret = af9033_rd_regs(dev, 0x800032, buf, 7); | |
1179 | if (ret) | |
1180 | goto err; | |
1181 | ||
1182 | abort_packet_count = (buf[1] << 8) | (buf[0] << 0); | |
6bb096c9 | 1183 | rsd_bit_err_count = (buf[4] << 16) | (buf[3] << 8) | buf[2]; |
204f4319 AP |
1184 | rsd_packet_count = (buf[6] << 8) | (buf[5] << 0); |
1185 | ||
1186 | dev->error_block_count += abort_packet_count; | |
1187 | dev->total_block_count += rsd_packet_count; | |
6bb096c9 AP |
1188 | dev->post_bit_error += rsd_bit_err_count; |
1189 | dev->post_bit_count += rsd_packet_count * 204 * 8; | |
204f4319 AP |
1190 | |
1191 | c->block_count.len = 1; | |
1192 | c->block_count.stat[0].scale = FE_SCALE_COUNTER; | |
1193 | c->block_count.stat[0].uvalue = dev->total_block_count; | |
1194 | ||
1195 | c->block_error.len = 1; | |
1196 | c->block_error.stat[0].scale = FE_SCALE_COUNTER; | |
1197 | c->block_error.stat[0].uvalue = dev->error_block_count; | |
6bb096c9 AP |
1198 | |
1199 | c->post_bit_count.len = 1; | |
1200 | c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; | |
1201 | c->post_bit_count.stat[0].uvalue = dev->post_bit_count; | |
1202 | ||
1203 | c->post_bit_error.len = 1; | |
1204 | c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; | |
1205 | c->post_bit_error.stat[0].uvalue = dev->post_bit_error; | |
204f4319 AP |
1206 | } |
1207 | ||
3e41313a | 1208 | err_schedule_delayed_work: |
83f11619 AP |
1209 | schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000)); |
1210 | return; | |
1211 | err: | |
1212 | dev_dbg(&dev->client->dev, "failed=%d\n", ret); | |
1213 | } | |
1214 | ||
f5b00a76 AP |
1215 | static struct dvb_frontend_ops af9033_ops = { |
1216 | .delsys = { SYS_DVBT }, | |
1217 | .info = { | |
1218 | .name = "Afatech AF9033 (DVB-T)", | |
1219 | .frequency_min = 174000000, | |
1220 | .frequency_max = 862000000, | |
1221 | .frequency_stepsize = 250000, | |
1222 | .frequency_tolerance = 0, | |
1223 | .caps = FE_CAN_FEC_1_2 | | |
1224 | FE_CAN_FEC_2_3 | | |
1225 | FE_CAN_FEC_3_4 | | |
1226 | FE_CAN_FEC_5_6 | | |
1227 | FE_CAN_FEC_7_8 | | |
1228 | FE_CAN_FEC_AUTO | | |
1229 | FE_CAN_QPSK | | |
1230 | FE_CAN_QAM_16 | | |
1231 | FE_CAN_QAM_64 | | |
1232 | FE_CAN_QAM_AUTO | | |
1233 | FE_CAN_TRANSMISSION_MODE_AUTO | | |
1234 | FE_CAN_GUARD_INTERVAL_AUTO | | |
1235 | FE_CAN_HIERARCHY_AUTO | | |
1236 | FE_CAN_RECOVER | | |
1237 | FE_CAN_MUTE_TS | |
1238 | }, | |
1239 | ||
1240 | .init = af9033_init, | |
1241 | .sleep = af9033_sleep, | |
1242 | ||
1243 | .get_tune_settings = af9033_get_tune_settings, | |
1244 | .set_frontend = af9033_set_frontend, | |
1245 | .get_frontend = af9033_get_frontend, | |
1246 | ||
1247 | .read_status = af9033_read_status, | |
1248 | .read_snr = af9033_read_snr, | |
1249 | .read_signal_strength = af9033_read_signal_strength, | |
1250 | .read_ber = af9033_read_ber, | |
1251 | .read_ucblocks = af9033_read_ucblocks, | |
1252 | ||
1253 | .i2c_gate_ctrl = af9033_i2c_gate_ctrl, | |
1254 | }; | |
4b64bb26 | 1255 | |
f5b00a76 AP |
1256 | static int af9033_probe(struct i2c_client *client, |
1257 | const struct i2c_device_id *id) | |
4b64bb26 | 1258 | { |
f5b00a76 | 1259 | struct af9033_config *cfg = client->dev.platform_data; |
09611caa | 1260 | struct af9033_dev *dev; |
f5b00a76 | 1261 | int ret; |
4b64bb26 | 1262 | u8 buf[8]; |
ef5211fd | 1263 | u32 reg; |
4b64bb26 | 1264 | |
4b64bb26 | 1265 | /* allocate memory for the internal state */ |
09611caa | 1266 | dev = kzalloc(sizeof(struct af9033_dev), GFP_KERNEL); |
f5b00a76 AP |
1267 | if (dev == NULL) { |
1268 | ret = -ENOMEM; | |
1269 | dev_err(&client->dev, "Could not allocate memory for state\n"); | |
4b64bb26 | 1270 | goto err; |
f5b00a76 | 1271 | } |
4b64bb26 AP |
1272 | |
1273 | /* setup the state */ | |
f5b00a76 | 1274 | dev->client = client; |
83f11619 | 1275 | INIT_DELAYED_WORK(&dev->stat_work, af9033_stat_work); |
f5b00a76 | 1276 | memcpy(&dev->cfg, cfg, sizeof(struct af9033_config)); |
4b64bb26 | 1277 | |
09611caa | 1278 | if (dev->cfg.clock != 12000000) { |
f5b00a76 AP |
1279 | ret = -ENODEV; |
1280 | dev_err(&dev->client->dev, | |
6a087f1f AP |
1281 | "unsupported clock %d Hz, only 12000000 Hz is supported currently\n", |
1282 | dev->cfg.clock); | |
f5b00a76 | 1283 | goto err_kfree; |
8e8a5ac7 AP |
1284 | } |
1285 | ||
4b64bb26 | 1286 | /* firmware version */ |
09611caa | 1287 | switch (dev->cfg.tuner) { |
ef5211fd AP |
1288 | case AF9033_TUNER_IT9135_38: |
1289 | case AF9033_TUNER_IT9135_51: | |
1290 | case AF9033_TUNER_IT9135_52: | |
1291 | case AF9033_TUNER_IT9135_60: | |
1292 | case AF9033_TUNER_IT9135_61: | |
1293 | case AF9033_TUNER_IT9135_62: | |
83f11619 | 1294 | dev->is_it9135 = true; |
ef5211fd AP |
1295 | reg = 0x004bfc; |
1296 | break; | |
1297 | default: | |
83f11619 | 1298 | dev->is_af9035 = true; |
ef5211fd AP |
1299 | reg = 0x0083e9; |
1300 | break; | |
1301 | } | |
1302 | ||
09611caa | 1303 | ret = af9033_rd_regs(dev, reg, &buf[0], 4); |
4b64bb26 | 1304 | if (ret < 0) |
f5b00a76 | 1305 | goto err_kfree; |
4b64bb26 | 1306 | |
09611caa | 1307 | ret = af9033_rd_regs(dev, 0x804191, &buf[4], 4); |
4b64bb26 | 1308 | if (ret < 0) |
f5b00a76 | 1309 | goto err_kfree; |
4b64bb26 | 1310 | |
f5b00a76 | 1311 | dev_info(&dev->client->dev, |
6a087f1f AP |
1312 | "firmware version: LINK %d.%d.%d.%d - OFDM %d.%d.%d.%d\n", |
1313 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], | |
1314 | buf[7]); | |
4b64bb26 | 1315 | |
0c13c54d | 1316 | /* sleep */ |
09611caa | 1317 | switch (dev->cfg.tuner) { |
0c13c54d AP |
1318 | case AF9033_TUNER_IT9135_38: |
1319 | case AF9033_TUNER_IT9135_51: | |
1320 | case AF9033_TUNER_IT9135_52: | |
1321 | case AF9033_TUNER_IT9135_60: | |
1322 | case AF9033_TUNER_IT9135_61: | |
1323 | case AF9033_TUNER_IT9135_62: | |
1324 | /* IT9135 did not like to sleep at that early */ | |
1325 | break; | |
1326 | default: | |
09611caa | 1327 | ret = af9033_wr_reg(dev, 0x80004c, 1); |
4902bb39 | 1328 | if (ret < 0) |
f5b00a76 | 1329 | goto err_kfree; |
4902bb39 | 1330 | |
09611caa | 1331 | ret = af9033_wr_reg(dev, 0x800000, 0); |
4902bb39 | 1332 | if (ret < 0) |
f5b00a76 | 1333 | goto err_kfree; |
4902bb39 | 1334 | } |
12897dc3 | 1335 | |
4b64bb26 | 1336 | /* configure internal TS mode */ |
09611caa | 1337 | switch (dev->cfg.ts_mode) { |
4b64bb26 | 1338 | case AF9033_TS_MODE_PARALLEL: |
09611caa | 1339 | dev->ts_mode_parallel = true; |
4b64bb26 AP |
1340 | break; |
1341 | case AF9033_TS_MODE_SERIAL: | |
09611caa | 1342 | dev->ts_mode_serial = true; |
4b64bb26 AP |
1343 | break; |
1344 | case AF9033_TS_MODE_USB: | |
1345 | /* usb mode for AF9035 */ | |
1346 | default: | |
1347 | break; | |
1348 | } | |
1349 | ||
1350 | /* create dvb_frontend */ | |
09611caa AP |
1351 | memcpy(&dev->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops)); |
1352 | dev->fe.demodulator_priv = dev; | |
f5b00a76 AP |
1353 | *cfg->fe = &dev->fe; |
1354 | if (cfg->ops) { | |
1355 | cfg->ops->pid_filter = af9033_pid_filter; | |
1356 | cfg->ops->pid_filter_ctrl = af9033_pid_filter_ctrl; | |
ed97a6fe | 1357 | } |
f5b00a76 | 1358 | i2c_set_clientdata(client, dev); |
ed97a6fe | 1359 | |
f5b00a76 AP |
1360 | dev_info(&dev->client->dev, "Afatech AF9033 successfully attached\n"); |
1361 | return 0; | |
1362 | err_kfree: | |
09611caa | 1363 | kfree(dev); |
f5b00a76 | 1364 | err: |
6a087f1f | 1365 | dev_dbg(&client->dev, "failed=%d\n", ret); |
f5b00a76 | 1366 | return ret; |
4b64bb26 | 1367 | } |
4b64bb26 | 1368 | |
f5b00a76 AP |
1369 | static int af9033_remove(struct i2c_client *client) |
1370 | { | |
1371 | struct af9033_dev *dev = i2c_get_clientdata(client); | |
4b64bb26 | 1372 | |
6a087f1f | 1373 | dev_dbg(&dev->client->dev, "\n"); |
4b64bb26 | 1374 | |
f5b00a76 AP |
1375 | dev->fe.ops.release = NULL; |
1376 | dev->fe.demodulator_priv = NULL; | |
1377 | kfree(dev); | |
4b64bb26 | 1378 | |
f5b00a76 AP |
1379 | return 0; |
1380 | } | |
4b64bb26 | 1381 | |
f5b00a76 AP |
1382 | static const struct i2c_device_id af9033_id_table[] = { |
1383 | {"af9033", 0}, | |
1384 | {} | |
1385 | }; | |
1386 | MODULE_DEVICE_TABLE(i2c, af9033_id_table); | |
4b64bb26 | 1387 | |
f5b00a76 AP |
1388 | static struct i2c_driver af9033_driver = { |
1389 | .driver = { | |
f5b00a76 AP |
1390 | .name = "af9033", |
1391 | }, | |
1392 | .probe = af9033_probe, | |
1393 | .remove = af9033_remove, | |
1394 | .id_table = af9033_id_table, | |
4b64bb26 AP |
1395 | }; |
1396 | ||
f5b00a76 AP |
1397 | module_i2c_driver(af9033_driver); |
1398 | ||
4b64bb26 AP |
1399 | MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); |
1400 | MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver"); | |
1401 | MODULE_LICENSE("GPL"); |