Commit | Line | Data |
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43dd07f7 RM |
1 | /* |
2 | * drxk_hard: DRX-K DVB-C/T demodulator driver | |
3 | * | |
4 | * Copyright (C) 2010-2011 Digital Devices GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 only, as published by the Free Software Foundation. | |
9 | * | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
20 | * 02110-1301, USA | |
21 | * Or, point your browser to http://www.gnu.org/copyleft/gpl.html | |
22 | */ | |
23 | ||
3a4398f5 MCC |
24 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
25 | ||
43dd07f7 RM |
26 | #include <linux/kernel.h> |
27 | #include <linux/module.h> | |
28 | #include <linux/moduleparam.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/firmware.h> | |
32 | #include <linux/i2c.h> | |
20bfe7ae | 33 | #include <linux/hardirq.h> |
43dd07f7 RM |
34 | #include <asm/div64.h> |
35 | ||
36 | #include "dvb_frontend.h" | |
37 | #include "drxk.h" | |
38 | #include "drxk_hard.h" | |
b5e9eb6f | 39 | #include "dvb_math.h" |
43dd07f7 | 40 | |
cd7a67a4 MCC |
41 | static int power_down_dvbt(struct drxk_state *state, bool set_power_mode); |
42 | static int power_down_qam(struct drxk_state *state); | |
43 | static int set_dvbt_standard(struct drxk_state *state, | |
44 | enum operation_mode o_mode); | |
45 | static int set_qam_standard(struct drxk_state *state, | |
46 | enum operation_mode o_mode); | |
47 | static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, | |
48 | s32 tuner_freq_offset); | |
49 | static int set_dvbt_standard(struct drxk_state *state, | |
50 | enum operation_mode o_mode); | |
51 | static int dvbt_start(struct drxk_state *state); | |
52 | static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, | |
53 | s32 tuner_freq_offset); | |
54 | static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status); | |
55 | static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status); | |
56 | static int switch_antenna_to_qam(struct drxk_state *state); | |
57 | static int switch_antenna_to_dvbt(struct drxk_state *state); | |
58 | ||
59 | static bool is_dvbt(struct drxk_state *state) | |
43dd07f7 | 60 | { |
cd7a67a4 | 61 | return state->m_operation_mode == OM_DVBT; |
43dd07f7 RM |
62 | } |
63 | ||
cd7a67a4 | 64 | static bool is_qam(struct drxk_state *state) |
43dd07f7 | 65 | { |
cd7a67a4 MCC |
66 | return state->m_operation_mode == OM_QAM_ITU_A || |
67 | state->m_operation_mode == OM_QAM_ITU_B || | |
68 | state->m_operation_mode == OM_QAM_ITU_C; | |
43dd07f7 RM |
69 | } |
70 | ||
43dd07f7 RM |
71 | #define NOA1ROM 0 |
72 | ||
43dd07f7 RM |
73 | #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) |
74 | #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) | |
75 | ||
76 | #define DEFAULT_MER_83 165 | |
77 | #define DEFAULT_MER_93 250 | |
78 | ||
79 | #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH | |
80 | #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02) | |
81 | #endif | |
82 | ||
83 | #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH | |
84 | #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03) | |
85 | #endif | |
86 | ||
43dd07f7 RM |
87 | #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700 |
88 | #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500 | |
89 | ||
90 | #ifndef DRXK_KI_RAGC_ATV | |
91 | #define DRXK_KI_RAGC_ATV 4 | |
92 | #endif | |
93 | #ifndef DRXK_KI_IAGC_ATV | |
94 | #define DRXK_KI_IAGC_ATV 6 | |
95 | #endif | |
96 | #ifndef DRXK_KI_DAGC_ATV | |
97 | #define DRXK_KI_DAGC_ATV 7 | |
98 | #endif | |
99 | ||
100 | #ifndef DRXK_KI_RAGC_QAM | |
101 | #define DRXK_KI_RAGC_QAM 3 | |
102 | #endif | |
103 | #ifndef DRXK_KI_IAGC_QAM | |
104 | #define DRXK_KI_IAGC_QAM 4 | |
105 | #endif | |
106 | #ifndef DRXK_KI_DAGC_QAM | |
107 | #define DRXK_KI_DAGC_QAM 7 | |
108 | #endif | |
109 | #ifndef DRXK_KI_RAGC_DVBT | |
110 | #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2) | |
111 | #endif | |
112 | #ifndef DRXK_KI_IAGC_DVBT | |
113 | #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2) | |
114 | #endif | |
115 | #ifndef DRXK_KI_DAGC_DVBT | |
116 | #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7) | |
117 | #endif | |
118 | ||
119 | #ifndef DRXK_AGC_DAC_OFFSET | |
120 | #define DRXK_AGC_DAC_OFFSET (0x800) | |
121 | #endif | |
122 | ||
123 | #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ | |
124 | #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) | |
125 | #endif | |
126 | ||
127 | #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ | |
128 | #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) | |
129 | #endif | |
130 | ||
131 | #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ | |
132 | #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) | |
133 | #endif | |
134 | ||
135 | #ifndef DRXK_QAM_SYMBOLRATE_MAX | |
136 | #define DRXK_QAM_SYMBOLRATE_MAX (7233000) | |
137 | #endif | |
138 | ||
139 | #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56 | |
140 | #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64 | |
141 | #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0 | |
142 | #define DRXK_BL_ROM_OFFSET_TAPS_BG 24 | |
143 | #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32 | |
144 | #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40 | |
145 | #define DRXK_BL_ROM_OFFSET_TAPS_FM 48 | |
146 | #define DRXK_BL_ROM_OFFSET_UCODE 0 | |
147 | ||
148 | #define DRXK_BLC_TIMEOUT 100 | |
149 | ||
150 | #define DRXK_BLCC_NR_ELEMENTS_TAPS 2 | |
151 | #define DRXK_BLCC_NR_ELEMENTS_UCODE 6 | |
152 | ||
153 | #define DRXK_BLDC_NR_ELEMENTS_TAPS 28 | |
154 | ||
155 | #ifndef DRXK_OFDM_NE_NOTCH_WIDTH | |
156 | #define DRXK_OFDM_NE_NOTCH_WIDTH (4) | |
157 | #endif | |
158 | ||
159 | #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960) | |
160 | #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480) | |
161 | #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008) | |
162 | #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992) | |
163 | #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) | |
164 | ||
2da67501 MCC |
165 | static unsigned int debug; |
166 | module_param(debug, int, 0644); | |
167 | MODULE_PARM_DESC(debug, "enable debug messages"); | |
168 | ||
52ee29fe MCC |
169 | #define dprintk(level, fmt, arg...) do { \ |
170 | if (debug >= level) \ | |
171 | printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg); \ | |
2da67501 MCC |
172 | } while (0) |
173 | ||
174 | ||
b01fbc10 | 175 | static inline u32 MulDiv32(u32 a, u32 b, u32 c) |
43dd07f7 RM |
176 | { |
177 | u64 tmp64; | |
178 | ||
ebc7de22 | 179 | tmp64 = (u64) a * (u64) b; |
43dd07f7 RM |
180 | do_div(tmp64, c); |
181 | ||
182 | return (u32) tmp64; | |
183 | } | |
184 | ||
ff38c216 | 185 | static inline u32 Frac28a(u32 a, u32 c) |
43dd07f7 RM |
186 | { |
187 | int i = 0; | |
188 | u32 Q1 = 0; | |
189 | u32 R0 = 0; | |
190 | ||
ebc7de22 | 191 | R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ |
ab5060cd MCC |
192 | Q1 = a / c; /* |
193 | * integer part, only the 4 least significant | |
194 | * bits will be visible in the result | |
195 | */ | |
43dd07f7 RM |
196 | |
197 | /* division using radix 16, 7 nibbles in the result */ | |
198 | for (i = 0; i < 7; i++) { | |
199 | Q1 = (Q1 << 4) | (R0 / c); | |
200 | R0 = (R0 % c) << 4; | |
201 | } | |
202 | /* rounding */ | |
203 | if ((R0 >> 3) >= c) | |
204 | Q1++; | |
205 | ||
206 | return Q1; | |
207 | } | |
208 | ||
b5e9eb6f | 209 | static inline u32 log10times100(u32 value) |
43dd07f7 | 210 | { |
b5e9eb6f | 211 | return (100L * intlog10(value)) >> 24; |
43dd07f7 RM |
212 | } |
213 | ||
214 | /****************************************************************************/ | |
215 | /* I2C **********************************************************************/ | |
216 | /****************************************************************************/ | |
217 | ||
20bfe7ae MCC |
218 | static int drxk_i2c_lock(struct drxk_state *state) |
219 | { | |
220 | i2c_lock_adapter(state->i2c); | |
221 | state->drxk_i2c_exclusive_lock = true; | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | static void drxk_i2c_unlock(struct drxk_state *state) | |
227 | { | |
228 | if (!state->drxk_i2c_exclusive_lock) | |
229 | return; | |
230 | ||
231 | i2c_unlock_adapter(state->i2c); | |
232 | state->drxk_i2c_exclusive_lock = false; | |
233 | } | |
234 | ||
2a5f6720 MCC |
235 | static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs, |
236 | unsigned len) | |
237 | { | |
20bfe7ae MCC |
238 | if (state->drxk_i2c_exclusive_lock) |
239 | return __i2c_transfer(state->i2c, msgs, len); | |
240 | else | |
241 | return i2c_transfer(state->i2c, msgs, len); | |
2a5f6720 MCC |
242 | } |
243 | ||
244 | static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val) | |
43dd07f7 | 245 | { |
ebc7de22 OE |
246 | struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD, |
247 | .buf = val, .len = 1} | |
248 | }; | |
be44eb28 | 249 | |
2a5f6720 | 250 | return drxk_i2c_transfer(state, msgs, 1); |
43dd07f7 RM |
251 | } |
252 | ||
2a5f6720 | 253 | static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len) |
43dd07f7 | 254 | { |
be44eb28 | 255 | int status; |
ebc7de22 OE |
256 | struct i2c_msg msg = { |
257 | .addr = adr, .flags = 0, .buf = data, .len = len }; | |
43dd07f7 | 258 | |
2da67501 MCC |
259 | dprintk(3, ":"); |
260 | if (debug > 2) { | |
261 | int i; | |
262 | for (i = 0; i < len; i++) | |
0fb220f2 MCC |
263 | pr_cont(" %02x", data[i]); |
264 | pr_cont("\n"); | |
2da67501 | 265 | } |
2a5f6720 | 266 | status = drxk_i2c_transfer(state, &msg, 1); |
be44eb28 MCC |
267 | if (status >= 0 && status != 1) |
268 | status = -EIO; | |
269 | ||
270 | if (status < 0) | |
3a4398f5 | 271 | pr_err("i2c write error at addr 0x%02x\n", adr); |
be44eb28 MCC |
272 | |
273 | return status; | |
43dd07f7 RM |
274 | } |
275 | ||
2a5f6720 | 276 | static int i2c_read(struct drxk_state *state, |
43dd07f7 RM |
277 | u8 adr, u8 *msg, int len, u8 *answ, int alen) |
278 | { | |
be44eb28 | 279 | int status; |
e4f4f875 MCC |
280 | struct i2c_msg msgs[2] = { |
281 | {.addr = adr, .flags = 0, | |
ebc7de22 | 282 | .buf = msg, .len = len}, |
e4f4f875 MCC |
283 | {.addr = adr, .flags = I2C_M_RD, |
284 | .buf = answ, .len = alen} | |
ebc7de22 | 285 | }; |
f07a0bc1 | 286 | |
2a5f6720 | 287 | status = drxk_i2c_transfer(state, msgs, 2); |
be44eb28 | 288 | if (status != 2) { |
2da67501 | 289 | if (debug > 2) |
0fb220f2 | 290 | pr_cont(": ERROR!\n"); |
be44eb28 MCC |
291 | if (status >= 0) |
292 | status = -EIO; | |
2da67501 | 293 | |
3a4398f5 | 294 | pr_err("i2c read error at addr 0x%02x\n", adr); |
be44eb28 | 295 | return status; |
43dd07f7 | 296 | } |
2da67501 MCC |
297 | if (debug > 2) { |
298 | int i; | |
0d3e6fe7 | 299 | dprintk(2, ": read from"); |
2da67501 | 300 | for (i = 0; i < len; i++) |
0fb220f2 MCC |
301 | pr_cont(" %02x", msg[i]); |
302 | pr_cont(", value = "); | |
f07a0bc1 | 303 | for (i = 0; i < alen; i++) |
0fb220f2 MCC |
304 | pr_cont(" %02x", answ[i]); |
305 | pr_cont("\n"); | |
2da67501 | 306 | } |
43dd07f7 RM |
307 | return 0; |
308 | } | |
309 | ||
5e66b878 | 310 | static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) |
43dd07f7 | 311 | { |
be44eb28 | 312 | int status; |
ebc7de22 | 313 | u8 adr = state->demod_address, mm1[4], mm2[2], len; |
e076c92e MCC |
314 | |
315 | if (state->single_master) | |
316 | flags |= 0xC0; | |
317 | ||
43dd07f7 RM |
318 | if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { |
319 | mm1[0] = (((reg << 1) & 0xFF) | 0x01); | |
320 | mm1[1] = ((reg >> 16) & 0xFF); | |
321 | mm1[2] = ((reg >> 24) & 0xFF) | flags; | |
322 | mm1[3] = ((reg >> 7) & 0xFF); | |
323 | len = 4; | |
324 | } else { | |
325 | mm1[0] = ((reg << 1) & 0xFF); | |
326 | mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); | |
327 | len = 2; | |
328 | } | |
2da67501 | 329 | dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); |
2a5f6720 | 330 | status = i2c_read(state, adr, mm1, len, mm2, 2); |
be44eb28 MCC |
331 | if (status < 0) |
332 | return status; | |
43dd07f7 RM |
333 | if (data) |
334 | *data = mm2[0] | (mm2[1] << 8); | |
2da67501 | 335 | |
43dd07f7 RM |
336 | return 0; |
337 | } | |
338 | ||
5e66b878 | 339 | static int read16(struct drxk_state *state, u32 reg, u16 *data) |
43dd07f7 | 340 | { |
5e66b878 | 341 | return read16_flags(state, reg, data, 0); |
43dd07f7 RM |
342 | } |
343 | ||
5e66b878 | 344 | static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) |
43dd07f7 | 345 | { |
be44eb28 | 346 | int status; |
43dd07f7 | 347 | u8 adr = state->demod_address, mm1[4], mm2[4], len; |
e076c92e MCC |
348 | |
349 | if (state->single_master) | |
350 | flags |= 0xC0; | |
351 | ||
43dd07f7 RM |
352 | if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { |
353 | mm1[0] = (((reg << 1) & 0xFF) | 0x01); | |
354 | mm1[1] = ((reg >> 16) & 0xFF); | |
355 | mm1[2] = ((reg >> 24) & 0xFF) | flags; | |
356 | mm1[3] = ((reg >> 7) & 0xFF); | |
357 | len = 4; | |
358 | } else { | |
359 | mm1[0] = ((reg << 1) & 0xFF); | |
360 | mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); | |
361 | len = 2; | |
362 | } | |
2da67501 | 363 | dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); |
2a5f6720 | 364 | status = i2c_read(state, adr, mm1, len, mm2, 4); |
be44eb28 MCC |
365 | if (status < 0) |
366 | return status; | |
43dd07f7 RM |
367 | if (data) |
368 | *data = mm2[0] | (mm2[1] << 8) | | |
ebc7de22 | 369 | (mm2[2] << 16) | (mm2[3] << 24); |
2da67501 | 370 | |
43dd07f7 RM |
371 | return 0; |
372 | } | |
373 | ||
5e66b878 MCC |
374 | static int read32(struct drxk_state *state, u32 reg, u32 *data) |
375 | { | |
376 | return read32_flags(state, reg, data, 0); | |
377 | } | |
378 | ||
379 | static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) | |
43dd07f7 RM |
380 | { |
381 | u8 adr = state->demod_address, mm[6], len; | |
e076c92e MCC |
382 | |
383 | if (state->single_master) | |
384 | flags |= 0xC0; | |
43dd07f7 RM |
385 | if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { |
386 | mm[0] = (((reg << 1) & 0xFF) | 0x01); | |
387 | mm[1] = ((reg >> 16) & 0xFF); | |
388 | mm[2] = ((reg >> 24) & 0xFF) | flags; | |
389 | mm[3] = ((reg >> 7) & 0xFF); | |
390 | len = 4; | |
391 | } else { | |
392 | mm[0] = ((reg << 1) & 0xFF); | |
393 | mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); | |
394 | len = 2; | |
395 | } | |
396 | mm[len] = data & 0xff; | |
ebc7de22 | 397 | mm[len + 1] = (data >> 8) & 0xff; |
2da67501 MCC |
398 | |
399 | dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags); | |
2a5f6720 | 400 | return i2c_write(state, adr, mm, len + 2); |
43dd07f7 RM |
401 | } |
402 | ||
5e66b878 | 403 | static int write16(struct drxk_state *state, u32 reg, u16 data) |
43dd07f7 | 404 | { |
5e66b878 | 405 | return write16_flags(state, reg, data, 0); |
43dd07f7 RM |
406 | } |
407 | ||
5e66b878 | 408 | static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) |
43dd07f7 RM |
409 | { |
410 | u8 adr = state->demod_address, mm[8], len; | |
e076c92e MCC |
411 | |
412 | if (state->single_master) | |
413 | flags |= 0xC0; | |
43dd07f7 RM |
414 | if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { |
415 | mm[0] = (((reg << 1) & 0xFF) | 0x01); | |
416 | mm[1] = ((reg >> 16) & 0xFF); | |
417 | mm[2] = ((reg >> 24) & 0xFF) | flags; | |
418 | mm[3] = ((reg >> 7) & 0xFF); | |
419 | len = 4; | |
420 | } else { | |
421 | mm[0] = ((reg << 1) & 0xFF); | |
422 | mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); | |
423 | len = 2; | |
424 | } | |
425 | mm[len] = data & 0xff; | |
ebc7de22 OE |
426 | mm[len + 1] = (data >> 8) & 0xff; |
427 | mm[len + 2] = (data >> 16) & 0xff; | |
428 | mm[len + 3] = (data >> 24) & 0xff; | |
2da67501 | 429 | dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags); |
be44eb28 | 430 | |
2a5f6720 | 431 | return i2c_write(state, adr, mm, len + 4); |
43dd07f7 RM |
432 | } |
433 | ||
5e66b878 MCC |
434 | static int write32(struct drxk_state *state, u32 reg, u32 data) |
435 | { | |
436 | return write32_flags(state, reg, data, 0); | |
437 | } | |
438 | ||
cd7a67a4 MCC |
439 | static int write_block(struct drxk_state *state, u32 address, |
440 | const int block_size, const u8 p_block[]) | |
43dd07f7 | 441 | { |
cd7a67a4 MCC |
442 | int status = 0, blk_size = block_size; |
443 | u8 flags = 0; | |
e076c92e MCC |
444 | |
445 | if (state->single_master) | |
cd7a67a4 MCC |
446 | flags |= 0xC0; |
447 | ||
448 | while (blk_size > 0) { | |
449 | int chunk = blk_size > state->m_chunk_size ? | |
450 | state->m_chunk_size : blk_size; | |
451 | u8 *adr_buf = &state->chunk[0]; | |
452 | u32 adr_length = 0; | |
453 | ||
454 | if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) { | |
455 | adr_buf[0] = (((address << 1) & 0xFF) | 0x01); | |
456 | adr_buf[1] = ((address >> 16) & 0xFF); | |
457 | adr_buf[2] = ((address >> 24) & 0xFF); | |
458 | adr_buf[3] = ((address >> 7) & 0xFF); | |
459 | adr_buf[2] |= flags; | |
460 | adr_length = 4; | |
461 | if (chunk == state->m_chunk_size) | |
462 | chunk -= 2; | |
ebc7de22 | 463 | } else { |
cd7a67a4 MCC |
464 | adr_buf[0] = ((address << 1) & 0xFF); |
465 | adr_buf[1] = (((address >> 16) & 0x0F) | | |
466 | ((address >> 18) & 0xF0)); | |
467 | adr_length = 2; | |
43dd07f7 | 468 | } |
cd7a67a4 MCC |
469 | memcpy(&state->chunk[adr_length], p_block, chunk); |
470 | dprintk(2, "(0x%08x, 0x%02x)\n", address, flags); | |
2da67501 MCC |
471 | if (debug > 1) { |
472 | int i; | |
cd7a67a4 MCC |
473 | if (p_block) |
474 | for (i = 0; i < chunk; i++) | |
0fb220f2 MCC |
475 | pr_cont(" %02x", p_block[i]); |
476 | pr_cont("\n"); | |
2da67501 | 477 | } |
2a5f6720 | 478 | status = i2c_write(state, state->demod_address, |
cd7a67a4 | 479 | &state->chunk[0], chunk + adr_length); |
ebc7de22 | 480 | if (status < 0) { |
3a4398f5 | 481 | pr_err("%s: i2c write error at addr 0x%02x\n", |
cd7a67a4 | 482 | __func__, address); |
43dd07f7 RM |
483 | break; |
484 | } | |
cd7a67a4 MCC |
485 | p_block += chunk; |
486 | address += (chunk >> 1); | |
487 | blk_size -= chunk; | |
43dd07f7 | 488 | } |
ebc7de22 | 489 | return status; |
43dd07f7 RM |
490 | } |
491 | ||
492 | #ifndef DRXK_MAX_RETRIES_POWERUP | |
493 | #define DRXK_MAX_RETRIES_POWERUP 20 | |
494 | #endif | |
495 | ||
cd7a67a4 | 496 | static int power_up_device(struct drxk_state *state) |
43dd07f7 RM |
497 | { |
498 | int status; | |
499 | u8 data = 0; | |
cd7a67a4 | 500 | u16 retry_count = 0; |
43dd07f7 | 501 | |
2da67501 MCC |
502 | dprintk(1, "\n"); |
503 | ||
2a5f6720 | 504 | status = i2c_read1(state, state->demod_address, &data); |
be44eb28 | 505 | if (status < 0) { |
43dd07f7 RM |
506 | do { |
507 | data = 0; | |
2a5f6720 | 508 | status = i2c_write(state, state->demod_address, |
be44eb28 | 509 | &data, 1); |
b72852ba | 510 | usleep_range(10000, 11000); |
cd7a67a4 | 511 | retry_count++; |
be44eb28 MCC |
512 | if (status < 0) |
513 | continue; | |
2a5f6720 | 514 | status = i2c_read1(state, state->demod_address, |
be44eb28 MCC |
515 | &data); |
516 | } while (status < 0 && | |
cd7a67a4 MCC |
517 | (retry_count < DRXK_MAX_RETRIES_POWERUP)); |
518 | if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP) | |
be44eb28 MCC |
519 | goto error; |
520 | } | |
521 | ||
522 | /* Make sure all clk domains are active */ | |
523 | status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); | |
524 | if (status < 0) | |
525 | goto error; | |
526 | status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); | |
527 | if (status < 0) | |
528 | goto error; | |
529 | /* Enable pll lock tests */ | |
530 | status = write16(state, SIO_CC_PLL_LOCK__A, 1); | |
531 | if (status < 0) | |
532 | goto error; | |
533 | ||
cd7a67a4 | 534 | state->m_current_power_mode = DRX_POWER_UP; |
be44eb28 MCC |
535 | |
536 | error: | |
537 | if (status < 0) | |
3a4398f5 | 538 | pr_err("Error %d on %s\n", status, __func__); |
be44eb28 | 539 | |
43dd07f7 RM |
540 | return status; |
541 | } | |
542 | ||
543 | ||
544 | static int init_state(struct drxk_state *state) | |
545 | { | |
147e110b | 546 | /* |
5a13e40b | 547 | * FIXME: most (all?) of the values below should be moved into |
147e110b MCC |
548 | * struct drxk_config, as they are probably board-specific |
549 | */ | |
cd7a67a4 MCC |
550 | u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO; |
551 | u32 ul_vsb_if_agc_output_level = 0; | |
552 | u32 ul_vsb_if_agc_min_level = 0; | |
553 | u32 ul_vsb_if_agc_max_level = 0x7FFF; | |
554 | u32 ul_vsb_if_agc_speed = 3; | |
555 | ||
556 | u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO; | |
557 | u32 ul_vsb_rf_agc_output_level = 0; | |
558 | u32 ul_vsb_rf_agc_min_level = 0; | |
559 | u32 ul_vsb_rf_agc_max_level = 0x7FFF; | |
560 | u32 ul_vsb_rf_agc_speed = 3; | |
561 | u32 ul_vsb_rf_agc_top = 9500; | |
562 | u32 ul_vsb_rf_agc_cut_off_current = 4000; | |
563 | ||
564 | u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO; | |
565 | u32 ul_atv_if_agc_output_level = 0; | |
566 | u32 ul_atv_if_agc_min_level = 0; | |
567 | u32 ul_atv_if_agc_max_level = 0; | |
568 | u32 ul_atv_if_agc_speed = 3; | |
569 | ||
570 | u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF; | |
571 | u32 ul_atv_rf_agc_output_level = 0; | |
572 | u32 ul_atv_rf_agc_min_level = 0; | |
573 | u32 ul_atv_rf_agc_max_level = 0; | |
574 | u32 ul_atv_rf_agc_top = 9500; | |
575 | u32 ul_atv_rf_agc_cut_off_current = 4000; | |
576 | u32 ul_atv_rf_agc_speed = 3; | |
43dd07f7 RM |
577 | |
578 | u32 ulQual83 = DEFAULT_MER_83; | |
579 | u32 ulQual93 = DEFAULT_MER_93; | |
580 | ||
cd7a67a4 MCC |
581 | u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; |
582 | u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; | |
43dd07f7 RM |
583 | |
584 | /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ | |
585 | /* io_pad_cfg_mode output mode is drive always */ | |
586 | /* io_pad_cfg_drive is set to power 2 (23 mA) */ | |
cd7a67a4 MCC |
587 | u32 ul_gpio_cfg = 0x0113; |
588 | u32 ul_invert_ts_clock = 0; | |
589 | u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; | |
590 | u32 ul_dvbt_bitrate = 50000000; | |
591 | u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; | |
43dd07f7 | 592 | |
cd7a67a4 | 593 | u32 ul_insert_rs_byte = 0; |
43dd07f7 | 594 | |
cd7a67a4 MCC |
595 | u32 ul_rf_mirror = 1; |
596 | u32 ul_power_down = 0; | |
43dd07f7 | 597 | |
2da67501 MCC |
598 | dprintk(1, "\n"); |
599 | ||
cd7a67a4 MCC |
600 | state->m_has_lna = false; |
601 | state->m_has_dvbt = false; | |
602 | state->m_has_dvbc = false; | |
603 | state->m_has_atv = false; | |
604 | state->m_has_oob = false; | |
605 | state->m_has_audio = false; | |
43dd07f7 | 606 | |
cd7a67a4 MCC |
607 | if (!state->m_chunk_size) |
608 | state->m_chunk_size = 124; | |
43dd07f7 | 609 | |
cd7a67a4 MCC |
610 | state->m_osc_clock_freq = 0; |
611 | state->m_smart_ant_inverted = false; | |
612 | state->m_b_p_down_open_bridge = false; | |
43dd07f7 RM |
613 | |
614 | /* real system clock frequency in kHz */ | |
cd7a67a4 | 615 | state->m_sys_clock_freq = 151875; |
43dd07f7 RM |
616 | /* Timing div, 250ns/Psys */ |
617 | /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ | |
cd7a67a4 | 618 | state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) * |
43dd07f7 RM |
619 | HI_I2C_DELAY) / 1000; |
620 | /* Clipping */ | |
cd7a67a4 MCC |
621 | if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) |
622 | state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; | |
623 | state->m_hi_cfg_wake_up_key = (state->demod_address << 1); | |
43dd07f7 | 624 | /* port/bridge/power down ctrl */ |
cd7a67a4 | 625 | state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; |
43dd07f7 | 626 | |
cd7a67a4 | 627 | state->m_b_power_down = (ul_power_down != 0); |
43dd07f7 | 628 | |
cd7a67a4 | 629 | state->m_drxk_a3_patch_code = false; |
43dd07f7 RM |
630 | |
631 | /* Init AGC and PGA parameters */ | |
632 | /* VSB IF */ | |
949dd08d MCC |
633 | state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode; |
634 | state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level; | |
635 | state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level; | |
636 | state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level; | |
637 | state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed; | |
cd7a67a4 | 638 | state->m_vsb_pga_cfg = 140; |
43dd07f7 RM |
639 | |
640 | /* VSB RF */ | |
949dd08d MCC |
641 | state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode; |
642 | state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level; | |
643 | state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level; | |
644 | state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level; | |
645 | state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed; | |
646 | state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top; | |
647 | state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current; | |
cd7a67a4 MCC |
648 | state->m_vsb_pre_saw_cfg.reference = 0x07; |
649 | state->m_vsb_pre_saw_cfg.use_pre_saw = true; | |
43dd07f7 RM |
650 | |
651 | state->m_Quality83percent = DEFAULT_MER_83; | |
652 | state->m_Quality93percent = DEFAULT_MER_93; | |
653 | if (ulQual93 <= 500 && ulQual83 < ulQual93) { | |
654 | state->m_Quality83percent = ulQual83; | |
655 | state->m_Quality93percent = ulQual93; | |
656 | } | |
657 | ||
658 | /* ATV IF */ | |
949dd08d MCC |
659 | state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode; |
660 | state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level; | |
661 | state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level; | |
662 | state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level; | |
663 | state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed; | |
43dd07f7 RM |
664 | |
665 | /* ATV RF */ | |
949dd08d MCC |
666 | state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode; |
667 | state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level; | |
668 | state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level; | |
669 | state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level; | |
670 | state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed; | |
671 | state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top; | |
672 | state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current; | |
cd7a67a4 MCC |
673 | state->m_atv_pre_saw_cfg.reference = 0x04; |
674 | state->m_atv_pre_saw_cfg.use_pre_saw = true; | |
43dd07f7 RM |
675 | |
676 | ||
677 | /* DVBT RF */ | |
cd7a67a4 MCC |
678 | state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; |
679 | state->m_dvbt_rf_agc_cfg.output_level = 0; | |
680 | state->m_dvbt_rf_agc_cfg.min_output_level = 0; | |
681 | state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF; | |
682 | state->m_dvbt_rf_agc_cfg.top = 0x2100; | |
683 | state->m_dvbt_rf_agc_cfg.cut_off_current = 4000; | |
684 | state->m_dvbt_rf_agc_cfg.speed = 1; | |
43dd07f7 RM |
685 | |
686 | ||
687 | /* DVBT IF */ | |
cd7a67a4 MCC |
688 | state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; |
689 | state->m_dvbt_if_agc_cfg.output_level = 0; | |
690 | state->m_dvbt_if_agc_cfg.min_output_level = 0; | |
691 | state->m_dvbt_if_agc_cfg.max_output_level = 9000; | |
692 | state->m_dvbt_if_agc_cfg.top = 13424; | |
693 | state->m_dvbt_if_agc_cfg.cut_off_current = 0; | |
694 | state->m_dvbt_if_agc_cfg.speed = 3; | |
695 | state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30; | |
696 | state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000; | |
ebc7de22 | 697 | /* state->m_dvbtPgaCfg = 140; */ |
43dd07f7 | 698 | |
cd7a67a4 MCC |
699 | state->m_dvbt_pre_saw_cfg.reference = 4; |
700 | state->m_dvbt_pre_saw_cfg.use_pre_saw = false; | |
43dd07f7 RM |
701 | |
702 | /* QAM RF */ | |
cd7a67a4 MCC |
703 | state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; |
704 | state->m_qam_rf_agc_cfg.output_level = 0; | |
705 | state->m_qam_rf_agc_cfg.min_output_level = 6023; | |
706 | state->m_qam_rf_agc_cfg.max_output_level = 27000; | |
707 | state->m_qam_rf_agc_cfg.top = 0x2380; | |
708 | state->m_qam_rf_agc_cfg.cut_off_current = 4000; | |
709 | state->m_qam_rf_agc_cfg.speed = 3; | |
43dd07f7 RM |
710 | |
711 | /* QAM IF */ | |
cd7a67a4 MCC |
712 | state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; |
713 | state->m_qam_if_agc_cfg.output_level = 0; | |
714 | state->m_qam_if_agc_cfg.min_output_level = 0; | |
715 | state->m_qam_if_agc_cfg.max_output_level = 9000; | |
716 | state->m_qam_if_agc_cfg.top = 0x0511; | |
717 | state->m_qam_if_agc_cfg.cut_off_current = 0; | |
718 | state->m_qam_if_agc_cfg.speed = 3; | |
719 | state->m_qam_if_agc_cfg.ingain_tgt_max = 5119; | |
720 | state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50; | |
721 | ||
722 | state->m_qam_pga_cfg = 140; | |
723 | state->m_qam_pre_saw_cfg.reference = 4; | |
724 | state->m_qam_pre_saw_cfg.use_pre_saw = false; | |
725 | ||
726 | state->m_operation_mode = OM_NONE; | |
727 | state->m_drxk_state = DRXK_UNINITIALIZED; | |
43dd07f7 RM |
728 | |
729 | /* MPEG output configuration */ | |
cd7a67a4 MCC |
730 | state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG ouput */ |
731 | state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */ | |
732 | state->m_invert_data = false; /* If TRUE; invert DATA signals */ | |
733 | state->m_invert_err = false; /* If TRUE; invert ERR signal */ | |
734 | state->m_invert_str = false; /* If TRUE; invert STR signals */ | |
735 | state->m_invert_val = false; /* If TRUE; invert VAL signals */ | |
736 | state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */ | |
67f04617 | 737 | |
43dd07f7 RM |
738 | /* If TRUE; static MPEG clockrate will be used; |
739 | otherwise clockrate will adapt to the bitrate of the TS */ | |
740 | ||
cd7a67a4 MCC |
741 | state->m_dvbt_bitrate = ul_dvbt_bitrate; |
742 | state->m_dvbc_bitrate = ul_dvbc_bitrate; | |
43dd07f7 | 743 | |
cd7a67a4 | 744 | state->m_ts_data_strength = (ul_ts_data_strength & 0x07); |
43dd07f7 RM |
745 | |
746 | /* Maximum bitrate in b/s in case static clockrate is selected */ | |
cd7a67a4 MCC |
747 | state->m_mpeg_ts_static_bitrate = 19392658; |
748 | state->m_disable_te_ihandling = false; | |
43dd07f7 | 749 | |
cd7a67a4 MCC |
750 | if (ul_insert_rs_byte) |
751 | state->m_insert_rs_byte = true; | |
43dd07f7 | 752 | |
cd7a67a4 MCC |
753 | state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; |
754 | if (ul_mpeg_lock_time_out < 10000) | |
755 | state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out; | |
756 | state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; | |
757 | if (ul_demod_lock_time_out < 10000) | |
758 | state->m_demod_lock_time_out = ul_demod_lock_time_out; | |
43dd07f7 | 759 | |
ebc7de22 | 760 | /* QAM defaults */ |
cd7a67a4 MCC |
761 | state->m_constellation = DRX_CONSTELLATION_AUTO; |
762 | state->m_qam_interleave_mode = DRXK_QAM_I12_J17; | |
763 | state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */ | |
764 | state->m_fec_rs_prescale = 1; | |
43dd07f7 | 765 | |
cd7a67a4 MCC |
766 | state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM; |
767 | state->m_agcfast_clip_ctrl_delay = 0; | |
43dd07f7 | 768 | |
949dd08d | 769 | state->m_gpio_cfg = ul_gpio_cfg; |
43dd07f7 | 770 | |
cd7a67a4 MCC |
771 | state->m_b_power_down = false; |
772 | state->m_current_power_mode = DRX_POWER_DOWN; | |
43dd07f7 | 773 | |
cd7a67a4 MCC |
774 | state->m_rfmirror = (ul_rf_mirror == 0); |
775 | state->m_if_agc_pol = false; | |
43dd07f7 RM |
776 | return 0; |
777 | } | |
778 | ||
cd7a67a4 | 779 | static int drxx_open(struct drxk_state *state) |
43dd07f7 RM |
780 | { |
781 | int status = 0; | |
782 | u32 jtag = 0; | |
783 | u16 bid = 0; | |
784 | u16 key = 0; | |
785 | ||
2da67501 | 786 | dprintk(1, "\n"); |
be44eb28 | 787 | /* stop lock indicator process */ |
ab5060cd MCC |
788 | status = write16(state, SCU_RAM_GPIO__A, |
789 | SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); | |
be44eb28 MCC |
790 | if (status < 0) |
791 | goto error; | |
792 | /* Check device id */ | |
793 | status = read16(state, SIO_TOP_COMM_KEY__A, &key); | |
794 | if (status < 0) | |
795 | goto error; | |
796 | status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); | |
797 | if (status < 0) | |
798 | goto error; | |
799 | status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag); | |
800 | if (status < 0) | |
801 | goto error; | |
802 | status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid); | |
803 | if (status < 0) | |
804 | goto error; | |
805 | status = write16(state, SIO_TOP_COMM_KEY__A, key); | |
806 | error: | |
807 | if (status < 0) | |
3a4398f5 | 808 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
809 | return status; |
810 | } | |
811 | ||
cd7a67a4 | 812 | static int get_device_capabilities(struct drxk_state *state) |
43dd07f7 | 813 | { |
cd7a67a4 MCC |
814 | u16 sio_pdr_ohw_cfg = 0; |
815 | u32 sio_top_jtagid_lo = 0; | |
43dd07f7 | 816 | int status; |
9c6e1828 | 817 | const char *spin = ""; |
43dd07f7 | 818 | |
2da67501 | 819 | dprintk(1, "\n"); |
43dd07f7 | 820 | |
be44eb28 MCC |
821 | /* driver 0.9.0 */ |
822 | /* stop lock indicator process */ | |
ab5060cd MCC |
823 | status = write16(state, SCU_RAM_GPIO__A, |
824 | SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); | |
be44eb28 MCC |
825 | if (status < 0) |
826 | goto error; | |
8418366d | 827 | status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); |
be44eb28 MCC |
828 | if (status < 0) |
829 | goto error; | |
cd7a67a4 | 830 | status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg); |
be44eb28 MCC |
831 | if (status < 0) |
832 | goto error; | |
833 | status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); | |
834 | if (status < 0) | |
835 | goto error; | |
43dd07f7 | 836 | |
cd7a67a4 | 837 | switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { |
be44eb28 MCC |
838 | case 0: |
839 | /* ignore (bypass ?) */ | |
840 | break; | |
841 | case 1: | |
842 | /* 27 MHz */ | |
cd7a67a4 | 843 | state->m_osc_clock_freq = 27000; |
be44eb28 MCC |
844 | break; |
845 | case 2: | |
846 | /* 20.25 MHz */ | |
cd7a67a4 | 847 | state->m_osc_clock_freq = 20250; |
be44eb28 MCC |
848 | break; |
849 | case 3: | |
850 | /* 4 MHz */ | |
cd7a67a4 | 851 | state->m_osc_clock_freq = 20250; |
be44eb28 MCC |
852 | break; |
853 | default: | |
3a4398f5 | 854 | pr_err("Clock Frequency is unknown\n"); |
be44eb28 MCC |
855 | return -EINVAL; |
856 | } | |
857 | /* | |
858 | Determine device capabilities | |
859 | Based on pinning v14 | |
860 | */ | |
cd7a67a4 | 861 | status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo); |
be44eb28 MCC |
862 | if (status < 0) |
863 | goto error; | |
0d3e6fe7 | 864 | |
3a4398f5 | 865 | pr_info("status = 0x%08x\n", sio_top_jtagid_lo); |
0d3e6fe7 | 866 | |
be44eb28 | 867 | /* driver 0.9.0 */ |
cd7a67a4 | 868 | switch ((sio_top_jtagid_lo >> 29) & 0xF) { |
be44eb28 | 869 | case 0: |
cd7a67a4 | 870 | state->m_device_spin = DRXK_SPIN_A1; |
9c6e1828 | 871 | spin = "A1"; |
be44eb28 MCC |
872 | break; |
873 | case 2: | |
cd7a67a4 | 874 | state->m_device_spin = DRXK_SPIN_A2; |
9c6e1828 | 875 | spin = "A2"; |
be44eb28 MCC |
876 | break; |
877 | case 3: | |
cd7a67a4 | 878 | state->m_device_spin = DRXK_SPIN_A3; |
9c6e1828 | 879 | spin = "A3"; |
be44eb28 MCC |
880 | break; |
881 | default: | |
cd7a67a4 | 882 | state->m_device_spin = DRXK_SPIN_UNKNOWN; |
be44eb28 | 883 | status = -EINVAL; |
3a4398f5 | 884 | pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF); |
be44eb28 MCC |
885 | goto error2; |
886 | } | |
cd7a67a4 | 887 | switch ((sio_top_jtagid_lo >> 12) & 0xFF) { |
be44eb28 MCC |
888 | case 0x13: |
889 | /* typeId = DRX3913K_TYPE_ID */ | |
cd7a67a4 MCC |
890 | state->m_has_lna = false; |
891 | state->m_has_oob = false; | |
892 | state->m_has_atv = false; | |
893 | state->m_has_audio = false; | |
894 | state->m_has_dvbt = true; | |
895 | state->m_has_dvbc = true; | |
896 | state->m_has_sawsw = true; | |
897 | state->m_has_gpio2 = false; | |
898 | state->m_has_gpio1 = false; | |
899 | state->m_has_irqn = false; | |
be44eb28 MCC |
900 | break; |
901 | case 0x15: | |
902 | /* typeId = DRX3915K_TYPE_ID */ | |
cd7a67a4 MCC |
903 | state->m_has_lna = false; |
904 | state->m_has_oob = false; | |
905 | state->m_has_atv = true; | |
906 | state->m_has_audio = false; | |
907 | state->m_has_dvbt = true; | |
908 | state->m_has_dvbc = false; | |
909 | state->m_has_sawsw = true; | |
910 | state->m_has_gpio2 = true; | |
911 | state->m_has_gpio1 = true; | |
912 | state->m_has_irqn = false; | |
be44eb28 MCC |
913 | break; |
914 | case 0x16: | |
915 | /* typeId = DRX3916K_TYPE_ID */ | |
cd7a67a4 MCC |
916 | state->m_has_lna = false; |
917 | state->m_has_oob = false; | |
918 | state->m_has_atv = true; | |
919 | state->m_has_audio = false; | |
920 | state->m_has_dvbt = true; | |
921 | state->m_has_dvbc = false; | |
922 | state->m_has_sawsw = true; | |
923 | state->m_has_gpio2 = true; | |
924 | state->m_has_gpio1 = true; | |
925 | state->m_has_irqn = false; | |
be44eb28 MCC |
926 | break; |
927 | case 0x18: | |
928 | /* typeId = DRX3918K_TYPE_ID */ | |
cd7a67a4 MCC |
929 | state->m_has_lna = false; |
930 | state->m_has_oob = false; | |
931 | state->m_has_atv = true; | |
932 | state->m_has_audio = true; | |
933 | state->m_has_dvbt = true; | |
934 | state->m_has_dvbc = false; | |
935 | state->m_has_sawsw = true; | |
936 | state->m_has_gpio2 = true; | |
937 | state->m_has_gpio1 = true; | |
938 | state->m_has_irqn = false; | |
be44eb28 MCC |
939 | break; |
940 | case 0x21: | |
941 | /* typeId = DRX3921K_TYPE_ID */ | |
cd7a67a4 MCC |
942 | state->m_has_lna = false; |
943 | state->m_has_oob = false; | |
944 | state->m_has_atv = true; | |
945 | state->m_has_audio = true; | |
946 | state->m_has_dvbt = true; | |
947 | state->m_has_dvbc = true; | |
948 | state->m_has_sawsw = true; | |
949 | state->m_has_gpio2 = true; | |
950 | state->m_has_gpio1 = true; | |
951 | state->m_has_irqn = false; | |
be44eb28 MCC |
952 | break; |
953 | case 0x23: | |
954 | /* typeId = DRX3923K_TYPE_ID */ | |
cd7a67a4 MCC |
955 | state->m_has_lna = false; |
956 | state->m_has_oob = false; | |
957 | state->m_has_atv = true; | |
958 | state->m_has_audio = true; | |
959 | state->m_has_dvbt = true; | |
960 | state->m_has_dvbc = true; | |
961 | state->m_has_sawsw = true; | |
962 | state->m_has_gpio2 = true; | |
963 | state->m_has_gpio1 = true; | |
964 | state->m_has_irqn = false; | |
be44eb28 MCC |
965 | break; |
966 | case 0x25: | |
967 | /* typeId = DRX3925K_TYPE_ID */ | |
cd7a67a4 MCC |
968 | state->m_has_lna = false; |
969 | state->m_has_oob = false; | |
970 | state->m_has_atv = true; | |
971 | state->m_has_audio = true; | |
972 | state->m_has_dvbt = true; | |
973 | state->m_has_dvbc = true; | |
974 | state->m_has_sawsw = true; | |
975 | state->m_has_gpio2 = true; | |
976 | state->m_has_gpio1 = true; | |
977 | state->m_has_irqn = false; | |
be44eb28 MCC |
978 | break; |
979 | case 0x26: | |
980 | /* typeId = DRX3926K_TYPE_ID */ | |
cd7a67a4 MCC |
981 | state->m_has_lna = false; |
982 | state->m_has_oob = false; | |
983 | state->m_has_atv = true; | |
984 | state->m_has_audio = false; | |
985 | state->m_has_dvbt = true; | |
986 | state->m_has_dvbc = true; | |
987 | state->m_has_sawsw = true; | |
988 | state->m_has_gpio2 = true; | |
989 | state->m_has_gpio1 = true; | |
990 | state->m_has_irqn = false; | |
be44eb28 MCC |
991 | break; |
992 | default: | |
3a4398f5 | 993 | pr_err("DeviceID 0x%02x not supported\n", |
cd7a67a4 | 994 | ((sio_top_jtagid_lo >> 12) & 0xFF)); |
be44eb28 MCC |
995 | status = -EINVAL; |
996 | goto error2; | |
997 | } | |
998 | ||
3a4398f5 | 999 | pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n", |
cd7a67a4 MCC |
1000 | ((sio_top_jtagid_lo >> 12) & 0xFF), spin, |
1001 | state->m_osc_clock_freq / 1000, | |
1002 | state->m_osc_clock_freq % 1000); | |
9c6e1828 | 1003 | |
be44eb28 MCC |
1004 | error: |
1005 | if (status < 0) | |
3a4398f5 | 1006 | pr_err("Error %d on %s\n", status, __func__); |
be44eb28 MCC |
1007 | |
1008 | error2: | |
43dd07f7 RM |
1009 | return status; |
1010 | } | |
1011 | ||
cd7a67a4 | 1012 | static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result) |
43dd07f7 RM |
1013 | { |
1014 | int status; | |
1015 | bool powerdown_cmd; | |
1016 | ||
2da67501 MCC |
1017 | dprintk(1, "\n"); |
1018 | ||
43dd07f7 | 1019 | /* Write command */ |
5e66b878 | 1020 | status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd); |
43dd07f7 | 1021 | if (status < 0) |
be44eb28 | 1022 | goto error; |
43dd07f7 | 1023 | if (cmd == SIO_HI_RA_RAM_CMD_RESET) |
b72852ba | 1024 | usleep_range(1000, 2000); |
43dd07f7 RM |
1025 | |
1026 | powerdown_cmd = | |
ebc7de22 | 1027 | (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && |
cd7a67a4 | 1028 | ((state->m_hi_cfg_ctrl) & |
ebc7de22 OE |
1029 | SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == |
1030 | SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); | |
5a7f7b79 | 1031 | if (!powerdown_cmd) { |
43dd07f7 | 1032 | /* Wait until command rdy */ |
cd7a67a4 MCC |
1033 | u32 retry_count = 0; |
1034 | u16 wait_cmd; | |
43dd07f7 RM |
1035 | |
1036 | do { | |
b72852ba | 1037 | usleep_range(1000, 2000); |
cd7a67a4 | 1038 | retry_count += 1; |
5e66b878 | 1039 | status = read16(state, SIO_HI_RA_RAM_CMD__A, |
cd7a67a4 MCC |
1040 | &wait_cmd); |
1041 | } while ((status < 0) && (retry_count < DRXK_MAX_RETRIES) | |
1042 | && (wait_cmd != 0)); | |
be44eb28 MCC |
1043 | if (status < 0) |
1044 | goto error; | |
cd7a67a4 | 1045 | status = read16(state, SIO_HI_RA_RAM_RES__A, p_result); |
43dd07f7 | 1046 | } |
be44eb28 MCC |
1047 | error: |
1048 | if (status < 0) | |
3a4398f5 | 1049 | pr_err("Error %d on %s\n", status, __func__); |
be44eb28 | 1050 | |
43dd07f7 RM |
1051 | return status; |
1052 | } | |
1053 | ||
cd7a67a4 | 1054 | static int hi_cfg_command(struct drxk_state *state) |
43dd07f7 RM |
1055 | { |
1056 | int status; | |
1057 | ||
2da67501 MCC |
1058 | dprintk(1, "\n"); |
1059 | ||
43dd07f7 | 1060 | mutex_lock(&state->mutex); |
43dd07f7 | 1061 | |
ab5060cd MCC |
1062 | status = write16(state, SIO_HI_RA_RAM_PAR_6__A, |
1063 | state->m_hi_cfg_timeout); | |
be44eb28 MCC |
1064 | if (status < 0) |
1065 | goto error; | |
ab5060cd MCC |
1066 | status = write16(state, SIO_HI_RA_RAM_PAR_5__A, |
1067 | state->m_hi_cfg_ctrl); | |
be44eb28 MCC |
1068 | if (status < 0) |
1069 | goto error; | |
ab5060cd MCC |
1070 | status = write16(state, SIO_HI_RA_RAM_PAR_4__A, |
1071 | state->m_hi_cfg_wake_up_key); | |
be44eb28 MCC |
1072 | if (status < 0) |
1073 | goto error; | |
ab5060cd MCC |
1074 | status = write16(state, SIO_HI_RA_RAM_PAR_3__A, |
1075 | state->m_hi_cfg_bridge_delay); | |
be44eb28 MCC |
1076 | if (status < 0) |
1077 | goto error; | |
ab5060cd MCC |
1078 | status = write16(state, SIO_HI_RA_RAM_PAR_2__A, |
1079 | state->m_hi_cfg_timing_div); | |
be44eb28 MCC |
1080 | if (status < 0) |
1081 | goto error; | |
ab5060cd MCC |
1082 | status = write16(state, SIO_HI_RA_RAM_PAR_1__A, |
1083 | SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); | |
be44eb28 MCC |
1084 | if (status < 0) |
1085 | goto error; | |
b1cf2019 | 1086 | status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL); |
be44eb28 MCC |
1087 | if (status < 0) |
1088 | goto error; | |
1089 | ||
cd7a67a4 | 1090 | state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; |
be44eb28 | 1091 | error: |
43dd07f7 | 1092 | mutex_unlock(&state->mutex); |
be44eb28 | 1093 | if (status < 0) |
3a4398f5 | 1094 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
1095 | return status; |
1096 | } | |
1097 | ||
cd7a67a4 | 1098 | static int init_hi(struct drxk_state *state) |
43dd07f7 | 1099 | { |
2da67501 MCC |
1100 | dprintk(1, "\n"); |
1101 | ||
cd7a67a4 MCC |
1102 | state->m_hi_cfg_wake_up_key = (state->demod_address << 1); |
1103 | state->m_hi_cfg_timeout = 0x96FF; | |
43dd07f7 | 1104 | /* port/bridge/power down ctrl */ |
cd7a67a4 | 1105 | state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; |
be44eb28 | 1106 | |
cd7a67a4 | 1107 | return hi_cfg_command(state); |
43dd07f7 RM |
1108 | } |
1109 | ||
cd7a67a4 | 1110 | static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable) |
43dd07f7 RM |
1111 | { |
1112 | int status = -1; | |
cd7a67a4 MCC |
1113 | u16 sio_pdr_mclk_cfg = 0; |
1114 | u16 sio_pdr_mdx_cfg = 0; | |
d5856813 | 1115 | u16 err_cfg = 0; |
43dd07f7 | 1116 | |
534e0481 | 1117 | dprintk(1, ": mpeg %s, %s mode\n", |
cd7a67a4 MCC |
1118 | mpeg_enable ? "enable" : "disable", |
1119 | state->m_enable_parallel ? "parallel" : "serial"); | |
43dd07f7 | 1120 | |
be44eb28 | 1121 | /* stop lock indicator process */ |
ab5060cd MCC |
1122 | status = write16(state, SCU_RAM_GPIO__A, |
1123 | SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); | |
be44eb28 MCC |
1124 | if (status < 0) |
1125 | goto error; | |
1126 | ||
1127 | /* MPEG TS pad configuration */ | |
8418366d | 1128 | status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); |
be44eb28 MCC |
1129 | if (status < 0) |
1130 | goto error; | |
1131 | ||
5a7f7b79 | 1132 | if (!mpeg_enable) { |
be44eb28 MCC |
1133 | /* Set MPEG TS pads to inputmode */ |
1134 | status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); | |
ea90f011 | 1135 | if (status < 0) |
be44eb28 MCC |
1136 | goto error; |
1137 | status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); | |
1138 | if (status < 0) | |
1139 | goto error; | |
1140 | status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000); | |
1141 | if (status < 0) | |
1142 | goto error; | |
1143 | status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); | |
1144 | if (status < 0) | |
1145 | goto error; | |
1146 | status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000); | |
1147 | if (status < 0) | |
1148 | goto error; | |
1149 | status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); | |
1150 | if (status < 0) | |
1151 | goto error; | |
1152 | status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); | |
1153 | if (status < 0) | |
1154 | goto error; | |
1155 | status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); | |
1156 | if (status < 0) | |
1157 | goto error; | |
1158 | status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); | |
1159 | if (status < 0) | |
1160 | goto error; | |
1161 | status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); | |
1162 | if (status < 0) | |
1163 | goto error; | |
1164 | status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); | |
1165 | if (status < 0) | |
1166 | goto error; | |
1167 | status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); | |
1168 | if (status < 0) | |
1169 | goto error; | |
1170 | } else { | |
1171 | /* Enable MPEG output */ | |
cd7a67a4 MCC |
1172 | sio_pdr_mdx_cfg = |
1173 | ((state->m_ts_data_strength << | |
be44eb28 | 1174 | SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); |
cd7a67a4 | 1175 | sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength << |
be44eb28 MCC |
1176 | SIO_PDR_MCLK_CFG_DRIVE__B) | |
1177 | 0x0003); | |
43dd07f7 | 1178 | |
cd7a67a4 | 1179 | status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg); |
be44eb28 MCC |
1180 | if (status < 0) |
1181 | goto error; | |
d5856813 MCC |
1182 | |
1183 | if (state->enable_merr_cfg) | |
cd7a67a4 | 1184 | err_cfg = sio_pdr_mdx_cfg; |
d5856813 MCC |
1185 | |
1186 | status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg); | |
be44eb28 MCC |
1187 | if (status < 0) |
1188 | goto error; | |
d5856813 | 1189 | status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg); |
be44eb28 MCC |
1190 | if (status < 0) |
1191 | goto error; | |
d5856813 | 1192 | |
5a7f7b79 | 1193 | if (state->m_enable_parallel) { |
39c1cb2b | 1194 | /* parallel -> enable MD1 to MD7 */ |
ab5060cd MCC |
1195 | status = write16(state, SIO_PDR_MD1_CFG__A, |
1196 | sio_pdr_mdx_cfg); | |
ea90f011 | 1197 | if (status < 0) |
be44eb28 | 1198 | goto error; |
ab5060cd MCC |
1199 | status = write16(state, SIO_PDR_MD2_CFG__A, |
1200 | sio_pdr_mdx_cfg); | |
ea90f011 | 1201 | if (status < 0) |
be44eb28 | 1202 | goto error; |
ab5060cd MCC |
1203 | status = write16(state, SIO_PDR_MD3_CFG__A, |
1204 | sio_pdr_mdx_cfg); | |
ea90f011 | 1205 | if (status < 0) |
be44eb28 | 1206 | goto error; |
ab5060cd MCC |
1207 | status = write16(state, SIO_PDR_MD4_CFG__A, |
1208 | sio_pdr_mdx_cfg); | |
ea90f011 | 1209 | if (status < 0) |
be44eb28 | 1210 | goto error; |
ab5060cd MCC |
1211 | status = write16(state, SIO_PDR_MD5_CFG__A, |
1212 | sio_pdr_mdx_cfg); | |
ea90f011 | 1213 | if (status < 0) |
be44eb28 | 1214 | goto error; |
ab5060cd MCC |
1215 | status = write16(state, SIO_PDR_MD6_CFG__A, |
1216 | sio_pdr_mdx_cfg); | |
be44eb28 MCC |
1217 | if (status < 0) |
1218 | goto error; | |
ab5060cd MCC |
1219 | status = write16(state, SIO_PDR_MD7_CFG__A, |
1220 | sio_pdr_mdx_cfg); | |
be44eb28 MCC |
1221 | if (status < 0) |
1222 | goto error; | |
1223 | } else { | |
cd7a67a4 | 1224 | sio_pdr_mdx_cfg = ((state->m_ts_data_strength << |
be44eb28 MCC |
1225 | SIO_PDR_MD0_CFG_DRIVE__B) |
1226 | | 0x0003); | |
1227 | /* serial -> disable MD1 to MD7 */ | |
5e66b878 | 1228 | status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); |
ea90f011 | 1229 | if (status < 0) |
be44eb28 | 1230 | goto error; |
5e66b878 | 1231 | status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); |
ea90f011 | 1232 | if (status < 0) |
be44eb28 | 1233 | goto error; |
5e66b878 | 1234 | status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); |
ea90f011 | 1235 | if (status < 0) |
be44eb28 | 1236 | goto error; |
5e66b878 | 1237 | status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); |
ea90f011 | 1238 | if (status < 0) |
be44eb28 | 1239 | goto error; |
5e66b878 | 1240 | status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); |
ea90f011 | 1241 | if (status < 0) |
be44eb28 | 1242 | goto error; |
5e66b878 | 1243 | status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); |
ea90f011 | 1244 | if (status < 0) |
be44eb28 | 1245 | goto error; |
5e66b878 | 1246 | status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); |
ea90f011 | 1247 | if (status < 0) |
be44eb28 | 1248 | goto error; |
43dd07f7 | 1249 | } |
cd7a67a4 | 1250 | status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg); |
ea90f011 | 1251 | if (status < 0) |
be44eb28 | 1252 | goto error; |
cd7a67a4 | 1253 | status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg); |
ea90f011 | 1254 | if (status < 0) |
be44eb28 MCC |
1255 | goto error; |
1256 | } | |
1257 | /* Enable MB output over MPEG pads and ctl input */ | |
1258 | status = write16(state, SIO_PDR_MON_CFG__A, 0x0000); | |
1259 | if (status < 0) | |
1260 | goto error; | |
1261 | /* Write nomagic word to enable pdr reg write */ | |
1262 | status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); | |
1263 | error: | |
1264 | if (status < 0) | |
3a4398f5 | 1265 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
1266 | return status; |
1267 | } | |
1268 | ||
cd7a67a4 | 1269 | static int mpegts_disable(struct drxk_state *state) |
43dd07f7 | 1270 | { |
2da67501 MCC |
1271 | dprintk(1, "\n"); |
1272 | ||
cd7a67a4 | 1273 | return mpegts_configure_pins(state, false); |
43dd07f7 RM |
1274 | } |
1275 | ||
cd7a67a4 MCC |
1276 | static int bl_chain_cmd(struct drxk_state *state, |
1277 | u16 rom_offset, u16 nr_of_elements, u32 time_out) | |
43dd07f7 | 1278 | { |
cd7a67a4 | 1279 | u16 bl_status = 0; |
43dd07f7 RM |
1280 | int status; |
1281 | unsigned long end; | |
1282 | ||
2da67501 | 1283 | dprintk(1, "\n"); |
43dd07f7 | 1284 | mutex_lock(&state->mutex); |
be44eb28 MCC |
1285 | status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); |
1286 | if (status < 0) | |
1287 | goto error; | |
cd7a67a4 | 1288 | status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset); |
be44eb28 MCC |
1289 | if (status < 0) |
1290 | goto error; | |
cd7a67a4 | 1291 | status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements); |
be44eb28 MCC |
1292 | if (status < 0) |
1293 | goto error; | |
1294 | status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); | |
1295 | if (status < 0) | |
1296 | goto error; | |
1297 | ||
cd7a67a4 | 1298 | end = jiffies + msecs_to_jiffies(time_out); |
43dd07f7 | 1299 | do { |
b72852ba | 1300 | usleep_range(1000, 2000); |
cd7a67a4 | 1301 | status = read16(state, SIO_BL_STATUS__A, &bl_status); |
ea90f011 | 1302 | if (status < 0) |
be44eb28 | 1303 | goto error; |
cd7a67a4 | 1304 | } while ((bl_status == 0x1) && |
be44eb28 | 1305 | ((time_is_after_jiffies(end)))); |
43dd07f7 | 1306 | |
cd7a67a4 | 1307 | if (bl_status == 0x1) { |
3a4398f5 | 1308 | pr_err("SIO not ready\n"); |
be44eb28 MCC |
1309 | status = -EINVAL; |
1310 | goto error2; | |
1311 | } | |
1312 | error: | |
1313 | if (status < 0) | |
3a4398f5 | 1314 | pr_err("Error %d on %s\n", status, __func__); |
be44eb28 | 1315 | error2: |
43dd07f7 RM |
1316 | mutex_unlock(&state->mutex); |
1317 | return status; | |
1318 | } | |
1319 | ||
1320 | ||
cd7a67a4 MCC |
1321 | static int download_microcode(struct drxk_state *state, |
1322 | const u8 p_mc_image[], u32 length) | |
43dd07f7 | 1323 | { |
cd7a67a4 MCC |
1324 | const u8 *p_src = p_mc_image; |
1325 | u32 address; | |
1326 | u16 n_blocks; | |
1327 | u16 block_size; | |
43dd07f7 RM |
1328 | u32 offset = 0; |
1329 | u32 i; | |
1bd09ddc | 1330 | int status = 0; |
43dd07f7 | 1331 | |
2da67501 MCC |
1332 | dprintk(1, "\n"); |
1333 | ||
5becbc58 HV |
1334 | /* down the drain (we don't care about MAGIC_WORD) */ |
1335 | #if 0 | |
1336 | /* For future reference */ | |
cd7a67a4 | 1337 | drain = (p_src[0] << 8) | p_src[1]; |
5becbc58 | 1338 | #endif |
cd7a67a4 | 1339 | p_src += sizeof(u16); |
ebc7de22 | 1340 | offset += sizeof(u16); |
cd7a67a4 MCC |
1341 | n_blocks = (p_src[0] << 8) | p_src[1]; |
1342 | p_src += sizeof(u16); | |
ebc7de22 | 1343 | offset += sizeof(u16); |
43dd07f7 | 1344 | |
cd7a67a4 MCC |
1345 | for (i = 0; i < n_blocks; i += 1) { |
1346 | address = (p_src[0] << 24) | (p_src[1] << 16) | | |
1347 | (p_src[2] << 8) | p_src[3]; | |
1348 | p_src += sizeof(u32); | |
ebc7de22 | 1349 | offset += sizeof(u32); |
43dd07f7 | 1350 | |
cd7a67a4 MCC |
1351 | block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16); |
1352 | p_src += sizeof(u16); | |
ebc7de22 | 1353 | offset += sizeof(u16); |
43dd07f7 | 1354 | |
5becbc58 HV |
1355 | #if 0 |
1356 | /* For future reference */ | |
cd7a67a4 | 1357 | flags = (p_src[0] << 8) | p_src[1]; |
5becbc58 | 1358 | #endif |
cd7a67a4 | 1359 | p_src += sizeof(u16); |
ebc7de22 | 1360 | offset += sizeof(u16); |
43dd07f7 | 1361 | |
5becbc58 HV |
1362 | #if 0 |
1363 | /* For future reference */ | |
cd7a67a4 | 1364 | block_crc = (p_src[0] << 8) | p_src[1]; |
5becbc58 | 1365 | #endif |
cd7a67a4 | 1366 | p_src += sizeof(u16); |
ebc7de22 | 1367 | offset += sizeof(u16); |
bcd2ebb7 | 1368 | |
cd7a67a4 | 1369 | if (offset + block_size > length) { |
3a4398f5 | 1370 | pr_err("Firmware is corrupted.\n"); |
bcd2ebb7 MCC |
1371 | return -EINVAL; |
1372 | } | |
1373 | ||
cd7a67a4 | 1374 | status = write_block(state, address, block_size, p_src); |
39624f7e | 1375 | if (status < 0) { |
3a4398f5 | 1376 | pr_err("Error %d while loading firmware\n", status); |
43dd07f7 | 1377 | break; |
39624f7e | 1378 | } |
cd7a67a4 MCC |
1379 | p_src += block_size; |
1380 | offset += block_size; | |
43dd07f7 RM |
1381 | } |
1382 | return status; | |
1383 | } | |
1384 | ||
cd7a67a4 | 1385 | static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable) |
43dd07f7 RM |
1386 | { |
1387 | int status; | |
ebc7de22 | 1388 | u16 data = 0; |
cd7a67a4 MCC |
1389 | u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; |
1390 | u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; | |
43dd07f7 RM |
1391 | unsigned long end; |
1392 | ||
2da67501 MCC |
1393 | dprintk(1, "\n"); |
1394 | ||
5a7f7b79 | 1395 | if (!enable) { |
cd7a67a4 MCC |
1396 | desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; |
1397 | desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; | |
43dd07f7 RM |
1398 | } |
1399 | ||
be44eb28 | 1400 | status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); |
cd7a67a4 | 1401 | if (status >= 0 && data == desired_status) { |
43dd07f7 RM |
1402 | /* tokenring already has correct status */ |
1403 | return status; | |
1404 | } | |
1405 | /* Disable/enable dvbt tokenring bridge */ | |
cd7a67a4 | 1406 | status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl); |
43dd07f7 | 1407 | |
ebc7de22 | 1408 | end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); |
ea90f011 | 1409 | do { |
5e66b878 | 1410 | status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); |
ab5060cd MCC |
1411 | if ((status >= 0 && data == desired_status) |
1412 | || time_is_after_jiffies(end)) | |
ea90f011 | 1413 | break; |
b72852ba | 1414 | usleep_range(1000, 2000); |
be44eb28 | 1415 | } while (1); |
cd7a67a4 | 1416 | if (data != desired_status) { |
3a4398f5 | 1417 | pr_err("SIO not ready\n"); |
be44eb28 | 1418 | return -EINVAL; |
43dd07f7 RM |
1419 | } |
1420 | return status; | |
1421 | } | |
1422 | ||
cd7a67a4 | 1423 | static int mpegts_stop(struct drxk_state *state) |
43dd07f7 RM |
1424 | { |
1425 | int status = 0; | |
cd7a67a4 MCC |
1426 | u16 fec_oc_snc_mode = 0; |
1427 | u16 fec_oc_ipr_mode = 0; | |
43dd07f7 | 1428 | |
2da67501 MCC |
1429 | dprintk(1, "\n"); |
1430 | ||
39c1cb2b | 1431 | /* Graceful shutdown (byte boundaries) */ |
cd7a67a4 | 1432 | status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); |
be44eb28 MCC |
1433 | if (status < 0) |
1434 | goto error; | |
cd7a67a4 MCC |
1435 | fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M; |
1436 | status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); | |
be44eb28 MCC |
1437 | if (status < 0) |
1438 | goto error; | |
1439 | ||
1440 | /* Suppress MCLK during absence of data */ | |
cd7a67a4 | 1441 | status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode); |
be44eb28 MCC |
1442 | if (status < 0) |
1443 | goto error; | |
cd7a67a4 MCC |
1444 | fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; |
1445 | status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode); | |
be44eb28 MCC |
1446 | |
1447 | error: | |
1448 | if (status < 0) | |
3a4398f5 | 1449 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 | 1450 | |
43dd07f7 RM |
1451 | return status; |
1452 | } | |
1453 | ||
1454 | static int scu_command(struct drxk_state *state, | |
cd7a67a4 MCC |
1455 | u16 cmd, u8 parameter_len, |
1456 | u16 *parameter, u8 result_len, u16 *result) | |
43dd07f7 RM |
1457 | { |
1458 | #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 | |
1459 | #error DRXK register mapping no longer compatible with this routine! | |
1460 | #endif | |
cd7a67a4 | 1461 | u16 cur_cmd = 0; |
be44eb28 | 1462 | int status = -EINVAL; |
43dd07f7 | 1463 | unsigned long end; |
be44eb28 MCC |
1464 | u8 buffer[34]; |
1465 | int cnt = 0, ii; | |
7558977a MCC |
1466 | const char *p; |
1467 | char errname[30]; | |
43dd07f7 | 1468 | |
2da67501 MCC |
1469 | dprintk(1, "\n"); |
1470 | ||
cd7a67a4 MCC |
1471 | if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) || |
1472 | ((result_len > 0) && (result == NULL))) { | |
3a4398f5 | 1473 | pr_err("Error %d on %s\n", status, __func__); |
e4459e16 AK |
1474 | return status; |
1475 | } | |
43dd07f7 RM |
1476 | |
1477 | mutex_lock(&state->mutex); | |
be44eb28 MCC |
1478 | |
1479 | /* assume that the command register is ready | |
1480 | since it is checked afterwards */ | |
cd7a67a4 | 1481 | for (ii = parameter_len - 1; ii >= 0; ii -= 1) { |
be44eb28 MCC |
1482 | buffer[cnt++] = (parameter[ii] & 0xFF); |
1483 | buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); | |
1484 | } | |
1485 | buffer[cnt++] = (cmd & 0xFF); | |
1486 | buffer[cnt++] = ((cmd >> 8) & 0xFF); | |
1487 | ||
1488 | write_block(state, SCU_RAM_PARAM_0__A - | |
cd7a67a4 | 1489 | (parameter_len - 1), cnt, buffer); |
be44eb28 MCC |
1490 | /* Wait until SCU has processed command */ |
1491 | end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME); | |
43dd07f7 | 1492 | do { |
b72852ba | 1493 | usleep_range(1000, 2000); |
cd7a67a4 | 1494 | status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd); |
be44eb28 MCC |
1495 | if (status < 0) |
1496 | goto error; | |
cd7a67a4 MCC |
1497 | } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end))); |
1498 | if (cur_cmd != DRX_SCU_READY) { | |
3a4398f5 | 1499 | pr_err("SCU not ready\n"); |
be44eb28 MCC |
1500 | status = -EIO; |
1501 | goto error2; | |
1502 | } | |
1503 | /* read results */ | |
cd7a67a4 | 1504 | if ((result_len > 0) && (result != NULL)) { |
be44eb28 MCC |
1505 | s16 err; |
1506 | int ii; | |
43dd07f7 | 1507 | |
cd7a67a4 | 1508 | for (ii = result_len - 1; ii >= 0; ii -= 1) { |
ab5060cd MCC |
1509 | status = read16(state, SCU_RAM_PARAM_0__A - ii, |
1510 | &result[ii]); | |
ea90f011 | 1511 | if (status < 0) |
be44eb28 | 1512 | goto error; |
43dd07f7 | 1513 | } |
be44eb28 MCC |
1514 | |
1515 | /* Check if an error was reported by SCU */ | |
1516 | err = (s16)result[0]; | |
7558977a MCC |
1517 | if (err >= 0) |
1518 | goto error; | |
be44eb28 | 1519 | |
7558977a MCC |
1520 | /* check for the known error codes */ |
1521 | switch (err) { | |
1522 | case SCU_RESULT_UNKCMD: | |
1523 | p = "SCU_RESULT_UNKCMD"; | |
1524 | break; | |
1525 | case SCU_RESULT_UNKSTD: | |
1526 | p = "SCU_RESULT_UNKSTD"; | |
1527 | break; | |
1528 | case SCU_RESULT_SIZE: | |
1529 | p = "SCU_RESULT_SIZE"; | |
1530 | break; | |
1531 | case SCU_RESULT_INVPAR: | |
1532 | p = "SCU_RESULT_INVPAR"; | |
1533 | break; | |
1534 | default: /* Other negative values are errors */ | |
1535 | sprintf(errname, "ERROR: %d\n", err); | |
1536 | p = errname; | |
43dd07f7 | 1537 | } |
3a4398f5 | 1538 | pr_err("%s while sending cmd 0x%04x with params:", p, cmd); |
7558977a MCC |
1539 | print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt); |
1540 | status = -EINVAL; | |
1541 | goto error2; | |
be44eb28 MCC |
1542 | } |
1543 | ||
1544 | error: | |
ebc7de22 | 1545 | if (status < 0) |
3a4398f5 | 1546 | pr_err("Error %d on %s\n", status, __func__); |
be44eb28 MCC |
1547 | error2: |
1548 | mutex_unlock(&state->mutex); | |
43dd07f7 RM |
1549 | return status; |
1550 | } | |
1551 | ||
cd7a67a4 | 1552 | static int set_iqm_af(struct drxk_state *state, bool active) |
43dd07f7 RM |
1553 | { |
1554 | u16 data = 0; | |
1555 | int status; | |
1556 | ||
2da67501 MCC |
1557 | dprintk(1, "\n"); |
1558 | ||
be44eb28 MCC |
1559 | /* Configure IQM */ |
1560 | status = read16(state, IQM_AF_STDBY__A, &data); | |
1561 | if (status < 0) | |
1562 | goto error; | |
1563 | ||
1564 | if (!active) { | |
1565 | data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY | |
1566 | | IQM_AF_STDBY_STDBY_AMP_STANDBY | |
1567 | | IQM_AF_STDBY_STDBY_PD_STANDBY | |
1568 | | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY | |
1569 | | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY); | |
1570 | } else { | |
1571 | data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) | |
1572 | & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) | |
1573 | & (~IQM_AF_STDBY_STDBY_PD_STANDBY) | |
1574 | & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) | |
1575 | & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) | |
1576 | ); | |
1577 | } | |
1578 | status = write16(state, IQM_AF_STDBY__A, data); | |
1579 | ||
1580 | error: | |
1581 | if (status < 0) | |
3a4398f5 | 1582 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
1583 | return status; |
1584 | } | |
1585 | ||
cd7a67a4 | 1586 | static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode) |
43dd07f7 RM |
1587 | { |
1588 | int status = 0; | |
cd7a67a4 | 1589 | u16 sio_cc_pwd_mode = 0; |
43dd07f7 | 1590 | |
2da67501 MCC |
1591 | dprintk(1, "\n"); |
1592 | ||
43dd07f7 RM |
1593 | /* Check arguments */ |
1594 | if (mode == NULL) | |
be44eb28 | 1595 | return -EINVAL; |
43dd07f7 RM |
1596 | |
1597 | switch (*mode) { | |
1598 | case DRX_POWER_UP: | |
cd7a67a4 | 1599 | sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE; |
43dd07f7 RM |
1600 | break; |
1601 | case DRXK_POWER_DOWN_OFDM: | |
cd7a67a4 | 1602 | sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM; |
43dd07f7 RM |
1603 | break; |
1604 | case DRXK_POWER_DOWN_CORE: | |
cd7a67a4 | 1605 | sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK; |
43dd07f7 RM |
1606 | break; |
1607 | case DRXK_POWER_DOWN_PLL: | |
cd7a67a4 | 1608 | sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL; |
43dd07f7 RM |
1609 | break; |
1610 | case DRX_POWER_DOWN: | |
cd7a67a4 | 1611 | sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC; |
43dd07f7 RM |
1612 | break; |
1613 | default: | |
1614 | /* Unknow sleep mode */ | |
be44eb28 | 1615 | return -EINVAL; |
43dd07f7 RM |
1616 | } |
1617 | ||
1618 | /* If already in requested power mode, do nothing */ | |
cd7a67a4 | 1619 | if (state->m_current_power_mode == *mode) |
43dd07f7 RM |
1620 | return 0; |
1621 | ||
1622 | /* For next steps make sure to start from DRX_POWER_UP mode */ | |
cd7a67a4 MCC |
1623 | if (state->m_current_power_mode != DRX_POWER_UP) { |
1624 | status = power_up_device(state); | |
be44eb28 MCC |
1625 | if (status < 0) |
1626 | goto error; | |
cd7a67a4 | 1627 | status = dvbt_enable_ofdm_token_ring(state, true); |
be44eb28 MCC |
1628 | if (status < 0) |
1629 | goto error; | |
43dd07f7 RM |
1630 | } |
1631 | ||
1632 | if (*mode == DRX_POWER_UP) { | |
1633 | /* Restore analog & pin configuartion */ | |
1634 | } else { | |
1635 | /* Power down to requested mode */ | |
1636 | /* Backup some register settings */ | |
1637 | /* Set pins with possible pull-ups connected | |
1638 | to them in input mode */ | |
1639 | /* Analog power down */ | |
1640 | /* ADC power down */ | |
1641 | /* Power down device */ | |
1642 | /* stop all comm_exec */ | |
1643 | /* Stop and power down previous standard */ | |
cd7a67a4 | 1644 | switch (state->m_operation_mode) { |
be44eb28 | 1645 | case OM_DVBT: |
cd7a67a4 | 1646 | status = mpegts_stop(state); |
ea90f011 | 1647 | if (status < 0) |
be44eb28 | 1648 | goto error; |
cd7a67a4 | 1649 | status = power_down_dvbt(state, false); |
ea90f011 | 1650 | if (status < 0) |
be44eb28 MCC |
1651 | goto error; |
1652 | break; | |
1653 | case OM_QAM_ITU_A: | |
1654 | case OM_QAM_ITU_C: | |
cd7a67a4 | 1655 | status = mpegts_stop(state); |
ea90f011 | 1656 | if (status < 0) |
be44eb28 | 1657 | goto error; |
cd7a67a4 | 1658 | status = power_down_qam(state); |
be44eb28 MCC |
1659 | if (status < 0) |
1660 | goto error; | |
1661 | break; | |
1662 | default: | |
1663 | break; | |
1664 | } | |
cd7a67a4 | 1665 | status = dvbt_enable_ofdm_token_ring(state, false); |
be44eb28 MCC |
1666 | if (status < 0) |
1667 | goto error; | |
cd7a67a4 | 1668 | status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode); |
be44eb28 MCC |
1669 | if (status < 0) |
1670 | goto error; | |
1671 | status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); | |
1672 | if (status < 0) | |
1673 | goto error; | |
43dd07f7 | 1674 | |
be44eb28 | 1675 | if (*mode != DRXK_POWER_DOWN_OFDM) { |
cd7a67a4 | 1676 | state->m_hi_cfg_ctrl |= |
be44eb28 | 1677 | SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; |
cd7a67a4 | 1678 | status = hi_cfg_command(state); |
be44eb28 MCC |
1679 | if (status < 0) |
1680 | goto error; | |
1681 | } | |
43dd07f7 | 1682 | } |
cd7a67a4 | 1683 | state->m_current_power_mode = *mode; |
be44eb28 MCC |
1684 | |
1685 | error: | |
1686 | if (status < 0) | |
3a4398f5 | 1687 | pr_err("Error %d on %s\n", status, __func__); |
be44eb28 | 1688 | |
ebc7de22 | 1689 | return status; |
43dd07f7 RM |
1690 | } |
1691 | ||
cd7a67a4 | 1692 | static int power_down_dvbt(struct drxk_state *state, bool set_power_mode) |
43dd07f7 | 1693 | { |
cd7a67a4 MCC |
1694 | enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; |
1695 | u16 cmd_result = 0; | |
43dd07f7 RM |
1696 | u16 data = 0; |
1697 | int status; | |
1698 | ||
2da67501 MCC |
1699 | dprintk(1, "\n"); |
1700 | ||
be44eb28 MCC |
1701 | status = read16(state, SCU_COMM_EXEC__A, &data); |
1702 | if (status < 0) | |
1703 | goto error; | |
1704 | if (data == SCU_COMM_EXEC_ACTIVE) { | |
1705 | /* Send OFDM stop command */ | |
ab5060cd MCC |
1706 | status = scu_command(state, |
1707 | SCU_RAM_COMMAND_STANDARD_OFDM | |
1708 | | SCU_RAM_COMMAND_CMD_DEMOD_STOP, | |
1709 | 0, NULL, 1, &cmd_result); | |
ea90f011 | 1710 | if (status < 0) |
be44eb28 MCC |
1711 | goto error; |
1712 | /* Send OFDM reset command */ | |
ab5060cd MCC |
1713 | status = scu_command(state, |
1714 | SCU_RAM_COMMAND_STANDARD_OFDM | |
1715 | | SCU_RAM_COMMAND_CMD_DEMOD_RESET, | |
1716 | 0, NULL, 1, &cmd_result); | |
ea90f011 | 1717 | if (status < 0) |
be44eb28 MCC |
1718 | goto error; |
1719 | } | |
43dd07f7 | 1720 | |
be44eb28 MCC |
1721 | /* Reset datapath for OFDM, processors first */ |
1722 | status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); | |
1723 | if (status < 0) | |
1724 | goto error; | |
1725 | status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); | |
1726 | if (status < 0) | |
1727 | goto error; | |
1728 | status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); | |
1729 | if (status < 0) | |
1730 | goto error; | |
43dd07f7 | 1731 | |
be44eb28 | 1732 | /* powerdown AFE */ |
cd7a67a4 | 1733 | status = set_iqm_af(state, false); |
be44eb28 MCC |
1734 | if (status < 0) |
1735 | goto error; | |
1736 | ||
1737 | /* powerdown to OFDM mode */ | |
cd7a67a4 MCC |
1738 | if (set_power_mode) { |
1739 | status = ctrl_power_mode(state, &power_mode); | |
be44eb28 MCC |
1740 | if (status < 0) |
1741 | goto error; | |
1742 | } | |
1743 | error: | |
1744 | if (status < 0) | |
3a4398f5 | 1745 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
1746 | return status; |
1747 | } | |
1748 | ||
cd7a67a4 MCC |
1749 | static int setoperation_mode(struct drxk_state *state, |
1750 | enum operation_mode o_mode) | |
43dd07f7 RM |
1751 | { |
1752 | int status = 0; | |
1753 | ||
2da67501 | 1754 | dprintk(1, "\n"); |
43dd07f7 | 1755 | /* |
ebc7de22 OE |
1756 | Stop and power down previous standard |
1757 | TODO investigate total power down instead of partial | |
1758 | power down depending on "previous" standard. | |
1759 | */ | |
43dd07f7 | 1760 | |
be44eb28 | 1761 | /* disable HW lock indicator */ |
ab5060cd MCC |
1762 | status = write16(state, SCU_RAM_GPIO__A, |
1763 | SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); | |
be44eb28 MCC |
1764 | if (status < 0) |
1765 | goto error; | |
43dd07f7 | 1766 | |
f1b82970 | 1767 | /* Device is already at the required mode */ |
cd7a67a4 | 1768 | if (state->m_operation_mode == o_mode) |
f1b82970 MCC |
1769 | return 0; |
1770 | ||
cd7a67a4 | 1771 | switch (state->m_operation_mode) { |
f1b82970 MCC |
1772 | /* OM_NONE was added for start up */ |
1773 | case OM_NONE: | |
1774 | break; | |
1775 | case OM_DVBT: | |
cd7a67a4 | 1776 | status = mpegts_stop(state); |
f1b82970 | 1777 | if (status < 0) |
be44eb28 | 1778 | goto error; |
cd7a67a4 | 1779 | status = power_down_dvbt(state, true); |
f1b82970 MCC |
1780 | if (status < 0) |
1781 | goto error; | |
cd7a67a4 | 1782 | state->m_operation_mode = OM_NONE; |
f1b82970 MCC |
1783 | break; |
1784 | case OM_QAM_ITU_A: /* fallthrough */ | |
1785 | case OM_QAM_ITU_C: | |
cd7a67a4 | 1786 | status = mpegts_stop(state); |
f1b82970 MCC |
1787 | if (status < 0) |
1788 | goto error; | |
cd7a67a4 | 1789 | status = power_down_qam(state); |
f1b82970 MCC |
1790 | if (status < 0) |
1791 | goto error; | |
cd7a67a4 | 1792 | state->m_operation_mode = OM_NONE; |
f1b82970 MCC |
1793 | break; |
1794 | case OM_QAM_ITU_B: | |
1795 | default: | |
1796 | status = -EINVAL; | |
1797 | goto error; | |
1798 | } | |
be44eb28 | 1799 | |
f1b82970 MCC |
1800 | /* |
1801 | Power up new standard | |
1802 | */ | |
cd7a67a4 | 1803 | switch (o_mode) { |
f1b82970 | 1804 | case OM_DVBT: |
48763e2c | 1805 | dprintk(1, ": DVB-T\n"); |
cd7a67a4 MCC |
1806 | state->m_operation_mode = o_mode; |
1807 | status = set_dvbt_standard(state, o_mode); | |
f1b82970 MCC |
1808 | if (status < 0) |
1809 | goto error; | |
1810 | break; | |
1811 | case OM_QAM_ITU_A: /* fallthrough */ | |
1812 | case OM_QAM_ITU_C: | |
48763e2c | 1813 | dprintk(1, ": DVB-C Annex %c\n", |
cd7a67a4 MCC |
1814 | (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C'); |
1815 | state->m_operation_mode = o_mode; | |
1816 | status = set_qam_standard(state, o_mode); | |
f1b82970 MCC |
1817 | if (status < 0) |
1818 | goto error; | |
1819 | break; | |
1820 | case OM_QAM_ITU_B: | |
1821 | default: | |
1822 | status = -EINVAL; | |
be44eb28 MCC |
1823 | } |
1824 | error: | |
1825 | if (status < 0) | |
3a4398f5 | 1826 | pr_err("Error %d on %s\n", status, __func__); |
be44eb28 | 1827 | return status; |
43dd07f7 RM |
1828 | } |
1829 | ||
cd7a67a4 MCC |
1830 | static int start(struct drxk_state *state, s32 offset_freq, |
1831 | s32 intermediate_frequency) | |
43dd07f7 | 1832 | { |
be44eb28 MCC |
1833 | int status = -EINVAL; |
1834 | ||
cd7a67a4 MCC |
1835 | u16 i_freqk_hz; |
1836 | s32 offsetk_hz = offset_freq / 1000; | |
43dd07f7 | 1837 | |
2da67501 | 1838 | dprintk(1, "\n"); |
cd7a67a4 MCC |
1839 | if (state->m_drxk_state != DRXK_STOPPED && |
1840 | state->m_drxk_state != DRXK_DTV_STARTED) | |
be44eb28 | 1841 | goto error; |
43dd07f7 | 1842 | |
cd7a67a4 | 1843 | state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON); |
43dd07f7 | 1844 | |
cd7a67a4 MCC |
1845 | if (intermediate_frequency < 0) { |
1846 | state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect; | |
1847 | intermediate_frequency = -intermediate_frequency; | |
be44eb28 | 1848 | } |
43dd07f7 | 1849 | |
cd7a67a4 | 1850 | switch (state->m_operation_mode) { |
be44eb28 MCC |
1851 | case OM_QAM_ITU_A: |
1852 | case OM_QAM_ITU_C: | |
cd7a67a4 MCC |
1853 | i_freqk_hz = (intermediate_frequency / 1000); |
1854 | status = set_qam(state, i_freqk_hz, offsetk_hz); | |
be44eb28 MCC |
1855 | if (status < 0) |
1856 | goto error; | |
cd7a67a4 | 1857 | state->m_drxk_state = DRXK_DTV_STARTED; |
be44eb28 MCC |
1858 | break; |
1859 | case OM_DVBT: | |
cd7a67a4 MCC |
1860 | i_freqk_hz = (intermediate_frequency / 1000); |
1861 | status = mpegts_stop(state); | |
be44eb28 MCC |
1862 | if (status < 0) |
1863 | goto error; | |
cd7a67a4 | 1864 | status = set_dvbt(state, i_freqk_hz, offsetk_hz); |
be44eb28 MCC |
1865 | if (status < 0) |
1866 | goto error; | |
cd7a67a4 | 1867 | status = dvbt_start(state); |
be44eb28 MCC |
1868 | if (status < 0) |
1869 | goto error; | |
cd7a67a4 | 1870 | state->m_drxk_state = DRXK_DTV_STARTED; |
be44eb28 MCC |
1871 | break; |
1872 | default: | |
1873 | break; | |
1874 | } | |
1875 | error: | |
1876 | if (status < 0) | |
3a4398f5 | 1877 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
1878 | return status; |
1879 | } | |
1880 | ||
cd7a67a4 | 1881 | static int shut_down(struct drxk_state *state) |
43dd07f7 | 1882 | { |
2da67501 MCC |
1883 | dprintk(1, "\n"); |
1884 | ||
cd7a67a4 | 1885 | mpegts_stop(state); |
43dd07f7 RM |
1886 | return 0; |
1887 | } | |
1888 | ||
cd7a67a4 | 1889 | static int get_lock_status(struct drxk_state *state, u32 *p_lock_status) |
43dd07f7 | 1890 | { |
be44eb28 | 1891 | int status = -EINVAL; |
43dd07f7 | 1892 | |
2da67501 MCC |
1893 | dprintk(1, "\n"); |
1894 | ||
cd7a67a4 | 1895 | if (p_lock_status == NULL) |
be44eb28 | 1896 | goto error; |
43dd07f7 | 1897 | |
cd7a67a4 | 1898 | *p_lock_status = NOT_LOCKED; |
43dd07f7 RM |
1899 | |
1900 | /* define the SCU command code */ | |
cd7a67a4 | 1901 | switch (state->m_operation_mode) { |
43dd07f7 RM |
1902 | case OM_QAM_ITU_A: |
1903 | case OM_QAM_ITU_B: | |
1904 | case OM_QAM_ITU_C: | |
cd7a67a4 | 1905 | status = get_qam_lock_status(state, p_lock_status); |
43dd07f7 RM |
1906 | break; |
1907 | case OM_DVBT: | |
cd7a67a4 | 1908 | status = get_dvbt_lock_status(state, p_lock_status); |
43dd07f7 RM |
1909 | break; |
1910 | default: | |
1911 | break; | |
1912 | } | |
be44eb28 MCC |
1913 | error: |
1914 | if (status < 0) | |
3a4398f5 | 1915 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
1916 | return status; |
1917 | } | |
1918 | ||
cd7a67a4 | 1919 | static int mpegts_start(struct drxk_state *state) |
43dd07f7 | 1920 | { |
be44eb28 | 1921 | int status; |
43dd07f7 | 1922 | |
cd7a67a4 | 1923 | u16 fec_oc_snc_mode = 0; |
43dd07f7 | 1924 | |
be44eb28 | 1925 | /* Allow OC to sync again */ |
cd7a67a4 | 1926 | status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); |
be44eb28 MCC |
1927 | if (status < 0) |
1928 | goto error; | |
cd7a67a4 MCC |
1929 | fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; |
1930 | status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); | |
be44eb28 MCC |
1931 | if (status < 0) |
1932 | goto error; | |
1933 | status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); | |
1934 | error: | |
1935 | if (status < 0) | |
3a4398f5 | 1936 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
1937 | return status; |
1938 | } | |
1939 | ||
cd7a67a4 | 1940 | static int mpegts_dto_init(struct drxk_state *state) |
43dd07f7 | 1941 | { |
be44eb28 | 1942 | int status; |
43dd07f7 | 1943 | |
2da67501 MCC |
1944 | dprintk(1, "\n"); |
1945 | ||
be44eb28 MCC |
1946 | /* Rate integration settings */ |
1947 | status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000); | |
1948 | if (status < 0) | |
1949 | goto error; | |
1950 | status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C); | |
1951 | if (status < 0) | |
1952 | goto error; | |
1953 | status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A); | |
1954 | if (status < 0) | |
1955 | goto error; | |
1956 | status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008); | |
1957 | if (status < 0) | |
1958 | goto error; | |
1959 | status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006); | |
1960 | if (status < 0) | |
1961 | goto error; | |
1962 | status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680); | |
1963 | if (status < 0) | |
1964 | goto error; | |
1965 | status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080); | |
1966 | if (status < 0) | |
1967 | goto error; | |
1968 | status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4); | |
1969 | if (status < 0) | |
1970 | goto error; | |
1971 | ||
1972 | /* Additional configuration */ | |
1973 | status = write16(state, FEC_OC_OCR_INVERT__A, 0); | |
1974 | if (status < 0) | |
1975 | goto error; | |
1976 | status = write16(state, FEC_OC_SNC_LWM__A, 2); | |
1977 | if (status < 0) | |
1978 | goto error; | |
1979 | status = write16(state, FEC_OC_SNC_HWM__A, 12); | |
1980 | error: | |
1981 | if (status < 0) | |
3a4398f5 | 1982 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 | 1983 | |
43dd07f7 RM |
1984 | return status; |
1985 | } | |
1986 | ||
cd7a67a4 MCC |
1987 | static int mpegts_dto_setup(struct drxk_state *state, |
1988 | enum operation_mode o_mode) | |
43dd07f7 | 1989 | { |
be44eb28 | 1990 | int status; |
43dd07f7 | 1991 | |
cd7a67a4 MCC |
1992 | u16 fec_oc_reg_mode = 0; /* FEC_OC_MODE register value */ |
1993 | u16 fec_oc_reg_ipr_mode = 0; /* FEC_OC_IPR_MODE register value */ | |
1994 | u16 fec_oc_dto_mode = 0; /* FEC_OC_IPR_INVERT register value */ | |
1995 | u16 fec_oc_fct_mode = 0; /* FEC_OC_IPR_INVERT register value */ | |
1996 | u16 fec_oc_dto_period = 2; /* FEC_OC_IPR_INVERT register value */ | |
1997 | u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */ | |
1998 | u32 fec_oc_rcn_ctl_rate = 0; /* FEC_OC_IPR_INVERT register value */ | |
1999 | u16 fec_oc_tmd_mode = 0; | |
2000 | u16 fec_oc_tmd_int_upd_rate = 0; | |
2001 | u32 max_bit_rate = 0; | |
2002 | bool static_clk = false; | |
43dd07f7 | 2003 | |
2da67501 MCC |
2004 | dprintk(1, "\n"); |
2005 | ||
be44eb28 | 2006 | /* Check insertion of the Reed-Solomon parity bytes */ |
cd7a67a4 | 2007 | status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode); |
be44eb28 MCC |
2008 | if (status < 0) |
2009 | goto error; | |
cd7a67a4 | 2010 | status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode); |
be44eb28 MCC |
2011 | if (status < 0) |
2012 | goto error; | |
cd7a67a4 MCC |
2013 | fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M); |
2014 | fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); | |
5a7f7b79 | 2015 | if (state->m_insert_rs_byte) { |
be44eb28 | 2016 | /* enable parity symbol forward */ |
cd7a67a4 | 2017 | fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M; |
be44eb28 | 2018 | /* MVAL disable during parity bytes */ |
cd7a67a4 | 2019 | fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; |
be44eb28 | 2020 | /* TS burst length to 204 */ |
cd7a67a4 | 2021 | fec_oc_dto_burst_len = 204; |
be44eb28 | 2022 | } |
43dd07f7 | 2023 | |
39c1cb2b | 2024 | /* Check serial or parallel output */ |
cd7a67a4 | 2025 | fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); |
5a7f7b79 | 2026 | if (!state->m_enable_parallel) { |
be44eb28 | 2027 | /* MPEG data output is serial -> set ipr_mode[0] */ |
cd7a67a4 | 2028 | fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M; |
be44eb28 | 2029 | } |
43dd07f7 | 2030 | |
cd7a67a4 | 2031 | switch (o_mode) { |
be44eb28 | 2032 | case OM_DVBT: |
cd7a67a4 MCC |
2033 | max_bit_rate = state->m_dvbt_bitrate; |
2034 | fec_oc_tmd_mode = 3; | |
2035 | fec_oc_rcn_ctl_rate = 0xC00000; | |
2036 | static_clk = state->m_dvbt_static_clk; | |
be44eb28 MCC |
2037 | break; |
2038 | case OM_QAM_ITU_A: /* fallthrough */ | |
2039 | case OM_QAM_ITU_C: | |
cd7a67a4 MCC |
2040 | fec_oc_tmd_mode = 0x0004; |
2041 | fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */ | |
2042 | max_bit_rate = state->m_dvbc_bitrate; | |
2043 | static_clk = state->m_dvbc_static_clk; | |
be44eb28 MCC |
2044 | break; |
2045 | default: | |
2046 | status = -EINVAL; | |
2047 | } /* switch (standard) */ | |
2048 | if (status < 0) | |
2049 | goto error; | |
2050 | ||
2051 | /* Configure DTO's */ | |
cd7a67a4 MCC |
2052 | if (static_clk) { |
2053 | u32 bit_rate = 0; | |
be44eb28 MCC |
2054 | |
2055 | /* Rational DTO for MCLK source (static MCLK rate), | |
2056 | Dynamic DTO for optimal grouping | |
2057 | (avoid intra-packet gaps), | |
2058 | DTO offset enable to sync TS burst with MSTRT */ | |
cd7a67a4 | 2059 | fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M | |
be44eb28 | 2060 | FEC_OC_DTO_MODE_OFFSET_ENABLE__M); |
cd7a67a4 | 2061 | fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M | |
be44eb28 MCC |
2062 | FEC_OC_FCT_MODE_VIRT_ENA__M); |
2063 | ||
2064 | /* Check user defined bitrate */ | |
cd7a67a4 MCC |
2065 | bit_rate = max_bit_rate; |
2066 | if (bit_rate > 75900000UL) { /* max is 75.9 Mb/s */ | |
2067 | bit_rate = 75900000UL; | |
43dd07f7 | 2068 | } |
be44eb28 MCC |
2069 | /* Rational DTO period: |
2070 | dto_period = (Fsys / bitrate) - 2 | |
2071 | ||
cd7a67a4 | 2072 | result should be floored, |
be44eb28 MCC |
2073 | to make sure >= requested bitrate |
2074 | */ | |
cd7a67a4 MCC |
2075 | fec_oc_dto_period = (u16) (((state->m_sys_clock_freq) |
2076 | * 1000) / bit_rate); | |
2077 | if (fec_oc_dto_period <= 2) | |
2078 | fec_oc_dto_period = 0; | |
be44eb28 | 2079 | else |
cd7a67a4 MCC |
2080 | fec_oc_dto_period -= 2; |
2081 | fec_oc_tmd_int_upd_rate = 8; | |
be44eb28 | 2082 | } else { |
cd7a67a4 MCC |
2083 | /* (commonAttr->static_clk == false) => dynamic mode */ |
2084 | fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M; | |
2085 | fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE; | |
2086 | fec_oc_tmd_int_upd_rate = 5; | |
be44eb28 | 2087 | } |
43dd07f7 | 2088 | |
be44eb28 | 2089 | /* Write appropriate registers with requested configuration */ |
cd7a67a4 | 2090 | status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len); |
be44eb28 MCC |
2091 | if (status < 0) |
2092 | goto error; | |
cd7a67a4 | 2093 | status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period); |
be44eb28 MCC |
2094 | if (status < 0) |
2095 | goto error; | |
cd7a67a4 | 2096 | status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode); |
be44eb28 MCC |
2097 | if (status < 0) |
2098 | goto error; | |
cd7a67a4 | 2099 | status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode); |
be44eb28 MCC |
2100 | if (status < 0) |
2101 | goto error; | |
cd7a67a4 | 2102 | status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode); |
be44eb28 MCC |
2103 | if (status < 0) |
2104 | goto error; | |
cd7a67a4 | 2105 | status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode); |
be44eb28 MCC |
2106 | if (status < 0) |
2107 | goto error; | |
43dd07f7 | 2108 | |
be44eb28 | 2109 | /* Rate integration settings */ |
cd7a67a4 | 2110 | status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate); |
be44eb28 MCC |
2111 | if (status < 0) |
2112 | goto error; | |
ab5060cd MCC |
2113 | status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, |
2114 | fec_oc_tmd_int_upd_rate); | |
be44eb28 MCC |
2115 | if (status < 0) |
2116 | goto error; | |
cd7a67a4 | 2117 | status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode); |
be44eb28 MCC |
2118 | error: |
2119 | if (status < 0) | |
3a4398f5 | 2120 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
2121 | return status; |
2122 | } | |
2123 | ||
cd7a67a4 | 2124 | static int mpegts_configure_polarity(struct drxk_state *state) |
43dd07f7 | 2125 | { |
cd7a67a4 | 2126 | u16 fec_oc_reg_ipr_invert = 0; |
43dd07f7 RM |
2127 | |
2128 | /* Data mask for the output data byte */ | |
cd7a67a4 | 2129 | u16 invert_data_mask = |
ebc7de22 OE |
2130 | FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | |
2131 | FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | | |
2132 | FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | | |
2133 | FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; | |
43dd07f7 | 2134 | |
be44eb28 MCC |
2135 | dprintk(1, "\n"); |
2136 | ||
43dd07f7 | 2137 | /* Control selective inversion of output bits */ |
cd7a67a4 | 2138 | fec_oc_reg_ipr_invert &= (~(invert_data_mask)); |
5a7f7b79 | 2139 | if (state->m_invert_data) |
cd7a67a4 MCC |
2140 | fec_oc_reg_ipr_invert |= invert_data_mask; |
2141 | fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M)); | |
5a7f7b79 | 2142 | if (state->m_invert_err) |
cd7a67a4 MCC |
2143 | fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M; |
2144 | fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); | |
5a7f7b79 | 2145 | if (state->m_invert_str) |
cd7a67a4 MCC |
2146 | fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M; |
2147 | fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); | |
5a7f7b79 | 2148 | if (state->m_invert_val) |
cd7a67a4 MCC |
2149 | fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M; |
2150 | fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); | |
5a7f7b79 | 2151 | if (state->m_invert_clk) |
cd7a67a4 MCC |
2152 | fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M; |
2153 | ||
2154 | return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert); | |
43dd07f7 RM |
2155 | } |
2156 | ||
2157 | #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 | |
2158 | ||
cd7a67a4 MCC |
2159 | static int set_agc_rf(struct drxk_state *state, |
2160 | struct s_cfg_agc *p_agc_cfg, bool is_dtv) | |
43dd07f7 | 2161 | { |
be44eb28 MCC |
2162 | int status = -EINVAL; |
2163 | u16 data = 0; | |
cd7a67a4 | 2164 | struct s_cfg_agc *p_if_agc_settings; |
43dd07f7 | 2165 | |
2da67501 MCC |
2166 | dprintk(1, "\n"); |
2167 | ||
cd7a67a4 | 2168 | if (p_agc_cfg == NULL) |
be44eb28 | 2169 | goto error; |
43dd07f7 | 2170 | |
cd7a67a4 | 2171 | switch (p_agc_cfg->ctrl_mode) { |
be44eb28 MCC |
2172 | case DRXK_AGC_CTRL_AUTO: |
2173 | /* Enable RF AGC DAC */ | |
2174 | status = read16(state, IQM_AF_STDBY__A, &data); | |
2175 | if (status < 0) | |
2176 | goto error; | |
2177 | data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; | |
2178 | status = write16(state, IQM_AF_STDBY__A, data); | |
2179 | if (status < 0) | |
2180 | goto error; | |
2181 | status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); | |
2182 | if (status < 0) | |
2183 | goto error; | |
43dd07f7 | 2184 | |
be44eb28 MCC |
2185 | /* Enable SCU RF AGC loop */ |
2186 | data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; | |
43dd07f7 | 2187 | |
be44eb28 | 2188 | /* Polarity */ |
cd7a67a4 | 2189 | if (state->m_rf_agc_pol) |
be44eb28 MCC |
2190 | data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; |
2191 | else | |
2192 | data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; | |
2193 | status = write16(state, SCU_RAM_AGC_CONFIG__A, data); | |
2194 | if (status < 0) | |
2195 | goto error; | |
43dd07f7 | 2196 | |
be44eb28 MCC |
2197 | /* Set speed (using complementary reduction value) */ |
2198 | status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); | |
2199 | if (status < 0) | |
2200 | goto error; | |
43dd07f7 | 2201 | |
be44eb28 | 2202 | data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; |
cd7a67a4 | 2203 | data |= (~(p_agc_cfg->speed << |
be44eb28 MCC |
2204 | SCU_RAM_AGC_KI_RED_RAGC_RED__B) |
2205 | & SCU_RAM_AGC_KI_RED_RAGC_RED__M); | |
43dd07f7 | 2206 | |
be44eb28 MCC |
2207 | status = write16(state, SCU_RAM_AGC_KI_RED__A, data); |
2208 | if (status < 0) | |
2209 | goto error; | |
43dd07f7 | 2210 | |
cd7a67a4 MCC |
2211 | if (is_dvbt(state)) |
2212 | p_if_agc_settings = &state->m_dvbt_if_agc_cfg; | |
2213 | else if (is_qam(state)) | |
2214 | p_if_agc_settings = &state->m_qam_if_agc_cfg; | |
be44eb28 | 2215 | else |
cd7a67a4 MCC |
2216 | p_if_agc_settings = &state->m_atv_if_agc_cfg; |
2217 | if (p_if_agc_settings == NULL) { | |
be44eb28 MCC |
2218 | status = -EINVAL; |
2219 | goto error; | |
2220 | } | |
43dd07f7 | 2221 | |
be44eb28 | 2222 | /* Set TOP, only if IF-AGC is in AUTO mode */ |
89fffac8 | 2223 | if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) { |
ab5060cd MCC |
2224 | status = write16(state, |
2225 | SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, | |
2226 | p_agc_cfg->top); | |
ea90f011 | 2227 | if (status < 0) |
be44eb28 | 2228 | goto error; |
89fffac8 | 2229 | } |
43dd07f7 | 2230 | |
be44eb28 | 2231 | /* Cut-Off current */ |
ab5060cd MCC |
2232 | status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, |
2233 | p_agc_cfg->cut_off_current); | |
be44eb28 MCC |
2234 | if (status < 0) |
2235 | goto error; | |
43dd07f7 | 2236 | |
be44eb28 | 2237 | /* Max. output level */ |
ab5060cd MCC |
2238 | status = write16(state, SCU_RAM_AGC_RF_MAX__A, |
2239 | p_agc_cfg->max_output_level); | |
be44eb28 MCC |
2240 | if (status < 0) |
2241 | goto error; | |
43dd07f7 | 2242 | |
be44eb28 | 2243 | break; |
43dd07f7 | 2244 | |
be44eb28 MCC |
2245 | case DRXK_AGC_CTRL_USER: |
2246 | /* Enable RF AGC DAC */ | |
2247 | status = read16(state, IQM_AF_STDBY__A, &data); | |
2248 | if (status < 0) | |
2249 | goto error; | |
2250 | data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; | |
2251 | status = write16(state, IQM_AF_STDBY__A, data); | |
2252 | if (status < 0) | |
2253 | goto error; | |
43dd07f7 | 2254 | |
be44eb28 MCC |
2255 | /* Disable SCU RF AGC loop */ |
2256 | status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); | |
2257 | if (status < 0) | |
2258 | goto error; | |
2259 | data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; | |
cd7a67a4 | 2260 | if (state->m_rf_agc_pol) |
be44eb28 MCC |
2261 | data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; |
2262 | else | |
2263 | data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; | |
2264 | status = write16(state, SCU_RAM_AGC_CONFIG__A, data); | |
2265 | if (status < 0) | |
2266 | goto error; | |
43dd07f7 | 2267 | |
be44eb28 MCC |
2268 | /* SCU c.o.c. to 0, enabling full control range */ |
2269 | status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0); | |
2270 | if (status < 0) | |
2271 | goto error; | |
43dd07f7 | 2272 | |
be44eb28 | 2273 | /* Write value to output pin */ |
ab5060cd MCC |
2274 | status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, |
2275 | p_agc_cfg->output_level); | |
be44eb28 MCC |
2276 | if (status < 0) |
2277 | goto error; | |
2278 | break; | |
43dd07f7 | 2279 | |
be44eb28 MCC |
2280 | case DRXK_AGC_CTRL_OFF: |
2281 | /* Disable RF AGC DAC */ | |
2282 | status = read16(state, IQM_AF_STDBY__A, &data); | |
2283 | if (status < 0) | |
2284 | goto error; | |
2285 | data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; | |
2286 | status = write16(state, IQM_AF_STDBY__A, data); | |
2287 | if (status < 0) | |
2288 | goto error; | |
43dd07f7 | 2289 | |
be44eb28 MCC |
2290 | /* Disable SCU RF AGC loop */ |
2291 | status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); | |
2292 | if (status < 0) | |
2293 | goto error; | |
2294 | data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; | |
2295 | status = write16(state, SCU_RAM_AGC_CONFIG__A, data); | |
2296 | if (status < 0) | |
2297 | goto error; | |
2298 | break; | |
43dd07f7 | 2299 | |
be44eb28 MCC |
2300 | default: |
2301 | status = -EINVAL; | |
43dd07f7 | 2302 | |
be44eb28 MCC |
2303 | } |
2304 | error: | |
2305 | if (status < 0) | |
3a4398f5 | 2306 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
2307 | return status; |
2308 | } | |
2309 | ||
2310 | #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 | |
2311 | ||
cd7a67a4 MCC |
2312 | static int set_agc_if(struct drxk_state *state, |
2313 | struct s_cfg_agc *p_agc_cfg, bool is_dtv) | |
43dd07f7 RM |
2314 | { |
2315 | u16 data = 0; | |
2316 | int status = 0; | |
cd7a67a4 | 2317 | struct s_cfg_agc *p_rf_agc_settings; |
43dd07f7 | 2318 | |
2da67501 MCC |
2319 | dprintk(1, "\n"); |
2320 | ||
cd7a67a4 | 2321 | switch (p_agc_cfg->ctrl_mode) { |
be44eb28 | 2322 | case DRXK_AGC_CTRL_AUTO: |
43dd07f7 | 2323 | |
be44eb28 MCC |
2324 | /* Enable IF AGC DAC */ |
2325 | status = read16(state, IQM_AF_STDBY__A, &data); | |
2326 | if (status < 0) | |
2327 | goto error; | |
2328 | data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; | |
2329 | status = write16(state, IQM_AF_STDBY__A, data); | |
2330 | if (status < 0) | |
2331 | goto error; | |
43dd07f7 | 2332 | |
be44eb28 MCC |
2333 | status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); |
2334 | if (status < 0) | |
2335 | goto error; | |
43dd07f7 | 2336 | |
be44eb28 MCC |
2337 | /* Enable SCU IF AGC loop */ |
2338 | data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; | |
43dd07f7 | 2339 | |
be44eb28 | 2340 | /* Polarity */ |
cd7a67a4 | 2341 | if (state->m_if_agc_pol) |
be44eb28 MCC |
2342 | data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; |
2343 | else | |
2344 | data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; | |
2345 | status = write16(state, SCU_RAM_AGC_CONFIG__A, data); | |
2346 | if (status < 0) | |
2347 | goto error; | |
43dd07f7 | 2348 | |
be44eb28 MCC |
2349 | /* Set speed (using complementary reduction value) */ |
2350 | status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); | |
2351 | if (status < 0) | |
2352 | goto error; | |
2353 | data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; | |
cd7a67a4 | 2354 | data |= (~(p_agc_cfg->speed << |
be44eb28 MCC |
2355 | SCU_RAM_AGC_KI_RED_IAGC_RED__B) |
2356 | & SCU_RAM_AGC_KI_RED_IAGC_RED__M); | |
43dd07f7 | 2357 | |
be44eb28 MCC |
2358 | status = write16(state, SCU_RAM_AGC_KI_RED__A, data); |
2359 | if (status < 0) | |
2360 | goto error; | |
43dd07f7 | 2361 | |
cd7a67a4 MCC |
2362 | if (is_qam(state)) |
2363 | p_rf_agc_settings = &state->m_qam_rf_agc_cfg; | |
be44eb28 | 2364 | else |
cd7a67a4 MCC |
2365 | p_rf_agc_settings = &state->m_atv_rf_agc_cfg; |
2366 | if (p_rf_agc_settings == NULL) | |
be44eb28 MCC |
2367 | return -1; |
2368 | /* Restore TOP */ | |
ab5060cd MCC |
2369 | status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, |
2370 | p_rf_agc_settings->top); | |
be44eb28 MCC |
2371 | if (status < 0) |
2372 | goto error; | |
2373 | break; | |
43dd07f7 | 2374 | |
be44eb28 | 2375 | case DRXK_AGC_CTRL_USER: |
43dd07f7 | 2376 | |
be44eb28 MCC |
2377 | /* Enable IF AGC DAC */ |
2378 | status = read16(state, IQM_AF_STDBY__A, &data); | |
2379 | if (status < 0) | |
2380 | goto error; | |
2381 | data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; | |
2382 | status = write16(state, IQM_AF_STDBY__A, data); | |
2383 | if (status < 0) | |
2384 | goto error; | |
43dd07f7 | 2385 | |
be44eb28 MCC |
2386 | status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); |
2387 | if (status < 0) | |
2388 | goto error; | |
43dd07f7 | 2389 | |
be44eb28 MCC |
2390 | /* Disable SCU IF AGC loop */ |
2391 | data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; | |
43dd07f7 | 2392 | |
be44eb28 | 2393 | /* Polarity */ |
cd7a67a4 | 2394 | if (state->m_if_agc_pol) |
be44eb28 MCC |
2395 | data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; |
2396 | else | |
2397 | data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; | |
2398 | status = write16(state, SCU_RAM_AGC_CONFIG__A, data); | |
2399 | if (status < 0) | |
2400 | goto error; | |
43dd07f7 | 2401 | |
be44eb28 | 2402 | /* Write value to output pin */ |
ab5060cd MCC |
2403 | status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, |
2404 | p_agc_cfg->output_level); | |
be44eb28 MCC |
2405 | if (status < 0) |
2406 | goto error; | |
2407 | break; | |
43dd07f7 | 2408 | |
be44eb28 | 2409 | case DRXK_AGC_CTRL_OFF: |
43dd07f7 | 2410 | |
be44eb28 MCC |
2411 | /* Disable If AGC DAC */ |
2412 | status = read16(state, IQM_AF_STDBY__A, &data); | |
ea90f011 | 2413 | if (status < 0) |
be44eb28 MCC |
2414 | goto error; |
2415 | data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; | |
2416 | status = write16(state, IQM_AF_STDBY__A, data); | |
2417 | if (status < 0) | |
2418 | goto error; | |
43dd07f7 | 2419 | |
be44eb28 MCC |
2420 | /* Disable SCU IF AGC loop */ |
2421 | status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); | |
2422 | if (status < 0) | |
2423 | goto error; | |
2424 | data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; | |
2425 | status = write16(state, SCU_RAM_AGC_CONFIG__A, data); | |
2426 | if (status < 0) | |
2427 | goto error; | |
2428 | break; | |
cd7a67a4 | 2429 | } /* switch (agcSettingsIf->ctrl_mode) */ |
43dd07f7 | 2430 | |
be44eb28 MCC |
2431 | /* always set the top to support |
2432 | configurations without if-loop */ | |
cd7a67a4 | 2433 | status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top); |
be44eb28 MCC |
2434 | error: |
2435 | if (status < 0) | |
3a4398f5 | 2436 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
2437 | return status; |
2438 | } | |
2439 | ||
cd7a67a4 MCC |
2440 | static int get_qam_signal_to_noise(struct drxk_state *state, |
2441 | s32 *p_signal_to_noise) | |
43dd07f7 RM |
2442 | { |
2443 | int status = 0; | |
cd7a67a4 | 2444 | u16 qam_sl_err_power = 0; /* accum. error between |
be44eb28 | 2445 | raw and sliced symbols */ |
cd7a67a4 | 2446 | u32 qam_sl_sig_power = 0; /* used for MER, depends of |
ed5452a2 | 2447 | QAM modulation */ |
cd7a67a4 | 2448 | u32 qam_sl_mer = 0; /* QAM MER */ |
43dd07f7 | 2449 | |
2da67501 MCC |
2450 | dprintk(1, "\n"); |
2451 | ||
be44eb28 | 2452 | /* MER calculation */ |
43dd07f7 | 2453 | |
be44eb28 | 2454 | /* get the register value needed for MER */ |
cd7a67a4 | 2455 | status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power); |
be44eb28 | 2456 | if (status < 0) { |
3a4398f5 | 2457 | pr_err("Error %d on %s\n", status, __func__); |
be44eb28 MCC |
2458 | return -EINVAL; |
2459 | } | |
2460 | ||
ed5452a2 | 2461 | switch (state->props.modulation) { |
be44eb28 | 2462 | case QAM_16: |
cd7a67a4 | 2463 | qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; |
be44eb28 MCC |
2464 | break; |
2465 | case QAM_32: | |
cd7a67a4 | 2466 | qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; |
be44eb28 MCC |
2467 | break; |
2468 | case QAM_64: | |
cd7a67a4 | 2469 | qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; |
be44eb28 MCC |
2470 | break; |
2471 | case QAM_128: | |
cd7a67a4 | 2472 | qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; |
be44eb28 MCC |
2473 | break; |
2474 | default: | |
2475 | case QAM_256: | |
cd7a67a4 | 2476 | qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; |
be44eb28 MCC |
2477 | break; |
2478 | } | |
2479 | ||
cd7a67a4 MCC |
2480 | if (qam_sl_err_power > 0) { |
2481 | qam_sl_mer = log10times100(qam_sl_sig_power) - | |
2482 | log10times100((u32) qam_sl_err_power); | |
be44eb28 | 2483 | } |
cd7a67a4 | 2484 | *p_signal_to_noise = qam_sl_mer; |
43dd07f7 | 2485 | |
43dd07f7 RM |
2486 | return status; |
2487 | } | |
2488 | ||
cd7a67a4 MCC |
2489 | static int get_dvbt_signal_to_noise(struct drxk_state *state, |
2490 | s32 *p_signal_to_noise) | |
43dd07f7 | 2491 | { |
be44eb28 | 2492 | int status; |
cd7a67a4 MCC |
2493 | u16 reg_data = 0; |
2494 | u32 eq_reg_td_sqr_err_i = 0; | |
2495 | u32 eq_reg_td_sqr_err_q = 0; | |
2496 | u16 eq_reg_td_sqr_err_exp = 0; | |
2497 | u16 eq_reg_td_tps_pwr_ofs = 0; | |
2498 | u16 eq_reg_td_req_smb_cnt = 0; | |
2499 | u32 tps_cnt = 0; | |
2500 | u32 sqr_err_iq = 0; | |
ebc7de22 OE |
2501 | u32 a = 0; |
2502 | u32 b = 0; | |
2503 | u32 c = 0; | |
cd7a67a4 MCC |
2504 | u32 i_mer = 0; |
2505 | u16 transmission_params = 0; | |
43dd07f7 | 2506 | |
2da67501 | 2507 | dprintk(1, "\n"); |
43dd07f7 | 2508 | |
ab5060cd MCC |
2509 | status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, |
2510 | &eq_reg_td_tps_pwr_ofs); | |
be44eb28 MCC |
2511 | if (status < 0) |
2512 | goto error; | |
ab5060cd MCC |
2513 | status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, |
2514 | &eq_reg_td_req_smb_cnt); | |
be44eb28 MCC |
2515 | if (status < 0) |
2516 | goto error; | |
ab5060cd MCC |
2517 | status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, |
2518 | &eq_reg_td_sqr_err_exp); | |
be44eb28 MCC |
2519 | if (status < 0) |
2520 | goto error; | |
ab5060cd MCC |
2521 | status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, |
2522 | ®_data); | |
be44eb28 MCC |
2523 | if (status < 0) |
2524 | goto error; | |
2525 | /* Extend SQR_ERR_I operational range */ | |
cd7a67a4 MCC |
2526 | eq_reg_td_sqr_err_i = (u32) reg_data; |
2527 | if ((eq_reg_td_sqr_err_exp > 11) && | |
2528 | (eq_reg_td_sqr_err_i < 0x00000FFFUL)) { | |
2529 | eq_reg_td_sqr_err_i += 0x00010000UL; | |
be44eb28 | 2530 | } |
cd7a67a4 | 2531 | status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data); |
be44eb28 MCC |
2532 | if (status < 0) |
2533 | goto error; | |
2534 | /* Extend SQR_ERR_Q operational range */ | |
cd7a67a4 MCC |
2535 | eq_reg_td_sqr_err_q = (u32) reg_data; |
2536 | if ((eq_reg_td_sqr_err_exp > 11) && | |
2537 | (eq_reg_td_sqr_err_q < 0x00000FFFUL)) | |
2538 | eq_reg_td_sqr_err_q += 0x00010000UL; | |
be44eb28 | 2539 | |
ab5060cd MCC |
2540 | status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, |
2541 | &transmission_params); | |
be44eb28 MCC |
2542 | if (status < 0) |
2543 | goto error; | |
2544 | ||
2545 | /* Check input data for MER */ | |
2546 | ||
2547 | /* MER calculation (in 0.1 dB) without math.h */ | |
cd7a67a4 MCC |
2548 | if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0)) |
2549 | i_mer = 0; | |
2550 | else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) { | |
be44eb28 MCC |
2551 | /* No error at all, this must be the HW reset value |
2552 | * Apparently no first measurement yet | |
2553 | * Set MER to 0.0 */ | |
cd7a67a4 | 2554 | i_mer = 0; |
be44eb28 | 2555 | } else { |
cd7a67a4 MCC |
2556 | sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) << |
2557 | eq_reg_td_sqr_err_exp; | |
2558 | if ((transmission_params & | |
be44eb28 MCC |
2559 | OFDM_SC_RA_RAM_OP_PARAM_MODE__M) |
2560 | == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) | |
cd7a67a4 | 2561 | tps_cnt = 17; |
be44eb28 | 2562 | else |
cd7a67a4 | 2563 | tps_cnt = 68; |
be44eb28 MCC |
2564 | |
2565 | /* IMER = 100 * log10 (x) | |
cd7a67a4 MCC |
2566 | where x = (eq_reg_td_tps_pwr_ofs^2 * |
2567 | eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq | |
be44eb28 MCC |
2568 | |
2569 | => IMER = a + b -c | |
cd7a67a4 MCC |
2570 | where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2) |
2571 | b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt) | |
2572 | c = 100 * log10 (sqr_err_iq) | |
be44eb28 MCC |
2573 | */ |
2574 | ||
2575 | /* log(x) x = 9bits * 9bits->18 bits */ | |
cd7a67a4 MCC |
2576 | a = log10times100(eq_reg_td_tps_pwr_ofs * |
2577 | eq_reg_td_tps_pwr_ofs); | |
be44eb28 | 2578 | /* log(x) x = 16bits * 7bits->23 bits */ |
cd7a67a4 | 2579 | b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt); |
be44eb28 | 2580 | /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ |
cd7a67a4 | 2581 | c = log10times100(sqr_err_iq); |
be44eb28 | 2582 | |
cd7a67a4 | 2583 | i_mer = a + b - c; |
be44eb28 | 2584 | } |
cd7a67a4 | 2585 | *p_signal_to_noise = i_mer; |
43dd07f7 | 2586 | |
be44eb28 MCC |
2587 | error: |
2588 | if (status < 0) | |
3a4398f5 | 2589 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
2590 | return status; |
2591 | } | |
2592 | ||
cd7a67a4 | 2593 | static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise) |
43dd07f7 | 2594 | { |
2da67501 MCC |
2595 | dprintk(1, "\n"); |
2596 | ||
cd7a67a4 MCC |
2597 | *p_signal_to_noise = 0; |
2598 | switch (state->m_operation_mode) { | |
43dd07f7 | 2599 | case OM_DVBT: |
cd7a67a4 | 2600 | return get_dvbt_signal_to_noise(state, p_signal_to_noise); |
43dd07f7 RM |
2601 | case OM_QAM_ITU_A: |
2602 | case OM_QAM_ITU_C: | |
cd7a67a4 | 2603 | return get_qam_signal_to_noise(state, p_signal_to_noise); |
43dd07f7 RM |
2604 | default: |
2605 | break; | |
2606 | } | |
2607 | return 0; | |
2608 | } | |
2609 | ||
2610 | #if 0 | |
cd7a67a4 | 2611 | static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality) |
43dd07f7 RM |
2612 | { |
2613 | /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ | |
2614 | int status = 0; | |
2615 | ||
2da67501 MCC |
2616 | dprintk(1, "\n"); |
2617 | ||
ebc7de22 OE |
2618 | static s32 QE_SN[] = { |
2619 | 51, /* QPSK 1/2 */ | |
2620 | 69, /* QPSK 2/3 */ | |
2621 | 79, /* QPSK 3/4 */ | |
2622 | 89, /* QPSK 5/6 */ | |
2623 | 97, /* QPSK 7/8 */ | |
2624 | 108, /* 16-QAM 1/2 */ | |
2625 | 131, /* 16-QAM 2/3 */ | |
2626 | 146, /* 16-QAM 3/4 */ | |
2627 | 156, /* 16-QAM 5/6 */ | |
2628 | 160, /* 16-QAM 7/8 */ | |
2629 | 165, /* 64-QAM 1/2 */ | |
2630 | 187, /* 64-QAM 2/3 */ | |
2631 | 202, /* 64-QAM 3/4 */ | |
2632 | 216, /* 64-QAM 5/6 */ | |
2633 | 225, /* 64-QAM 7/8 */ | |
2634 | }; | |
43dd07f7 | 2635 | |
cd7a67a4 | 2636 | *p_quality = 0; |
43dd07f7 RM |
2637 | |
2638 | do { | |
cd7a67a4 MCC |
2639 | s32 signal_to_noise = 0; |
2640 | u16 constellation = 0; | |
2641 | u16 code_rate = 0; | |
2642 | u32 signal_to_noise_rel; | |
2643 | u32 ber_quality; | |
43dd07f7 | 2644 | |
cd7a67a4 | 2645 | status = get_dvbt_signal_to_noise(state, &signal_to_noise); |
ea90f011 MCC |
2646 | if (status < 0) |
2647 | break; | |
ab5060cd MCC |
2648 | status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, |
2649 | &constellation); | |
ea90f011 MCC |
2650 | if (status < 0) |
2651 | break; | |
cd7a67a4 | 2652 | constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; |
43dd07f7 | 2653 | |
ab5060cd MCC |
2654 | status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, |
2655 | &code_rate); | |
ea90f011 MCC |
2656 | if (status < 0) |
2657 | break; | |
cd7a67a4 | 2658 | code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; |
43dd07f7 | 2659 | |
cd7a67a4 MCC |
2660 | if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || |
2661 | code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) | |
43dd07f7 | 2662 | break; |
cd7a67a4 MCC |
2663 | signal_to_noise_rel = signal_to_noise - |
2664 | QE_SN[constellation * 5 + code_rate]; | |
2665 | ber_quality = 100; | |
2666 | ||
2667 | if (signal_to_noise_rel < -70) | |
2668 | *p_quality = 0; | |
2669 | else if (signal_to_noise_rel < 30) | |
2670 | *p_quality = ((signal_to_noise_rel + 70) * | |
2671 | ber_quality) / 100; | |
43dd07f7 | 2672 | else |
cd7a67a4 | 2673 | *p_quality = ber_quality; |
ebc7de22 | 2674 | } while (0); |
43dd07f7 RM |
2675 | return 0; |
2676 | }; | |
2677 | ||
cd7a67a4 | 2678 | static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality) |
43dd07f7 RM |
2679 | { |
2680 | int status = 0; | |
cd7a67a4 | 2681 | *p_quality = 0; |
43dd07f7 | 2682 | |
2da67501 MCC |
2683 | dprintk(1, "\n"); |
2684 | ||
43dd07f7 | 2685 | do { |
cd7a67a4 MCC |
2686 | u32 signal_to_noise = 0; |
2687 | u32 ber_quality = 100; | |
2688 | u32 signal_to_noise_rel = 0; | |
43dd07f7 | 2689 | |
cd7a67a4 | 2690 | status = get_qam_signal_to_noise(state, &signal_to_noise); |
ea90f011 MCC |
2691 | if (status < 0) |
2692 | break; | |
43dd07f7 | 2693 | |
ed5452a2 | 2694 | switch (state->props.modulation) { |
43dd07f7 | 2695 | case QAM_16: |
cd7a67a4 | 2696 | signal_to_noise_rel = signal_to_noise - 200; |
43dd07f7 RM |
2697 | break; |
2698 | case QAM_32: | |
cd7a67a4 | 2699 | signal_to_noise_rel = signal_to_noise - 230; |
ebc7de22 | 2700 | break; /* Not in NorDig */ |
43dd07f7 | 2701 | case QAM_64: |
cd7a67a4 | 2702 | signal_to_noise_rel = signal_to_noise - 260; |
43dd07f7 RM |
2703 | break; |
2704 | case QAM_128: | |
cd7a67a4 | 2705 | signal_to_noise_rel = signal_to_noise - 290; |
43dd07f7 RM |
2706 | break; |
2707 | default: | |
2708 | case QAM_256: | |
cd7a67a4 | 2709 | signal_to_noise_rel = signal_to_noise - 320; |
43dd07f7 RM |
2710 | break; |
2711 | } | |
2712 | ||
cd7a67a4 MCC |
2713 | if (signal_to_noise_rel < -70) |
2714 | *p_quality = 0; | |
2715 | else if (signal_to_noise_rel < 30) | |
2716 | *p_quality = ((signal_to_noise_rel + 70) * | |
2717 | ber_quality) / 100; | |
43dd07f7 | 2718 | else |
cd7a67a4 | 2719 | *p_quality = ber_quality; |
ebc7de22 | 2720 | } while (0); |
43dd07f7 RM |
2721 | |
2722 | return status; | |
2723 | } | |
2724 | ||
cd7a67a4 | 2725 | static int get_quality(struct drxk_state *state, s32 *p_quality) |
43dd07f7 | 2726 | { |
2da67501 MCC |
2727 | dprintk(1, "\n"); |
2728 | ||
cd7a67a4 | 2729 | switch (state->m_operation_mode) { |
ebc7de22 | 2730 | case OM_DVBT: |
cd7a67a4 | 2731 | return get_dvbt_quality(state, p_quality); |
ebc7de22 | 2732 | case OM_QAM_ITU_A: |
cd7a67a4 | 2733 | return get_dvbc_quality(state, p_quality); |
43dd07f7 RM |
2734 | default: |
2735 | break; | |
2736 | } | |
2737 | ||
2738 | return 0; | |
2739 | } | |
2740 | #endif | |
2741 | ||
2742 | /* Free data ram in SIO HI */ | |
2743 | #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 | |
2744 | #define SIO_HI_RA_RAM_USR_END__A 0x420060 | |
2745 | ||
2746 | #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) | |
2747 | #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) | |
2748 | #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ | |
2749 | #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE | |
2750 | ||
2751 | #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F) | |
2752 | #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) | |
2753 | #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) | |
2754 | ||
cd7a67a4 | 2755 | static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge) |
43dd07f7 | 2756 | { |
be44eb28 | 2757 | int status = -EINVAL; |
43dd07f7 | 2758 | |
2da67501 MCC |
2759 | dprintk(1, "\n"); |
2760 | ||
cd7a67a4 | 2761 | if (state->m_drxk_state == DRXK_UNINITIALIZED) |
704a28e8 | 2762 | return 0; |
cd7a67a4 | 2763 | if (state->m_drxk_state == DRXK_POWERED_DOWN) |
be44eb28 | 2764 | goto error; |
43dd07f7 | 2765 | |
f1fe1b75 MCC |
2766 | if (state->no_i2c_bridge) |
2767 | return 0; | |
43dd07f7 | 2768 | |
ab5060cd MCC |
2769 | status = write16(state, SIO_HI_RA_RAM_PAR_1__A, |
2770 | SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); | |
be44eb28 MCC |
2771 | if (status < 0) |
2772 | goto error; | |
cd7a67a4 | 2773 | if (b_enable_bridge) { |
ab5060cd MCC |
2774 | status = write16(state, SIO_HI_RA_RAM_PAR_2__A, |
2775 | SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); | |
ea90f011 | 2776 | if (status < 0) |
be44eb28 MCC |
2777 | goto error; |
2778 | } else { | |
ab5060cd MCC |
2779 | status = write16(state, SIO_HI_RA_RAM_PAR_2__A, |
2780 | SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); | |
be44eb28 MCC |
2781 | if (status < 0) |
2782 | goto error; | |
2783 | } | |
2784 | ||
b1cf2019 | 2785 | status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL); |
be44eb28 MCC |
2786 | |
2787 | error: | |
2788 | if (status < 0) | |
3a4398f5 | 2789 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
2790 | return status; |
2791 | } | |
2792 | ||
cd7a67a4 MCC |
2793 | static int set_pre_saw(struct drxk_state *state, |
2794 | struct s_cfg_pre_saw *p_pre_saw_cfg) | |
43dd07f7 | 2795 | { |
be44eb28 | 2796 | int status = -EINVAL; |
43dd07f7 | 2797 | |
2da67501 MCC |
2798 | dprintk(1, "\n"); |
2799 | ||
cd7a67a4 MCC |
2800 | if ((p_pre_saw_cfg == NULL) |
2801 | || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M)) | |
be44eb28 | 2802 | goto error; |
43dd07f7 | 2803 | |
cd7a67a4 | 2804 | status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference); |
be44eb28 MCC |
2805 | error: |
2806 | if (status < 0) | |
3a4398f5 | 2807 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
2808 | return status; |
2809 | } | |
2810 | ||
cd7a67a4 MCC |
2811 | static int bl_direct_cmd(struct drxk_state *state, u32 target_addr, |
2812 | u16 rom_offset, u16 nr_of_elements, u32 time_out) | |
43dd07f7 | 2813 | { |
cd7a67a4 MCC |
2814 | u16 bl_status = 0; |
2815 | u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF); | |
2816 | u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF); | |
ebc7de22 | 2817 | int status; |
43dd07f7 RM |
2818 | unsigned long end; |
2819 | ||
2da67501 MCC |
2820 | dprintk(1, "\n"); |
2821 | ||
43dd07f7 | 2822 | mutex_lock(&state->mutex); |
be44eb28 MCC |
2823 | status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); |
2824 | if (status < 0) | |
2825 | goto error; | |
2826 | status = write16(state, SIO_BL_TGT_HDR__A, blockbank); | |
2827 | if (status < 0) | |
2828 | goto error; | |
2829 | status = write16(state, SIO_BL_TGT_ADDR__A, offset); | |
2830 | if (status < 0) | |
2831 | goto error; | |
cd7a67a4 | 2832 | status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset); |
be44eb28 MCC |
2833 | if (status < 0) |
2834 | goto error; | |
cd7a67a4 | 2835 | status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements); |
be44eb28 MCC |
2836 | if (status < 0) |
2837 | goto error; | |
2838 | status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); | |
2839 | if (status < 0) | |
2840 | goto error; | |
2841 | ||
cd7a67a4 | 2842 | end = jiffies + msecs_to_jiffies(time_out); |
43dd07f7 | 2843 | do { |
cd7a67a4 | 2844 | status = read16(state, SIO_BL_STATUS__A, &bl_status); |
ea90f011 | 2845 | if (status < 0) |
be44eb28 | 2846 | goto error; |
cd7a67a4 MCC |
2847 | } while ((bl_status == 0x1) && time_is_after_jiffies(end)); |
2848 | if (bl_status == 0x1) { | |
3a4398f5 | 2849 | pr_err("SIO not ready\n"); |
be44eb28 MCC |
2850 | status = -EINVAL; |
2851 | goto error2; | |
2852 | } | |
2853 | error: | |
2854 | if (status < 0) | |
3a4398f5 | 2855 | pr_err("Error %d on %s\n", status, __func__); |
be44eb28 | 2856 | error2: |
43dd07f7 RM |
2857 | mutex_unlock(&state->mutex); |
2858 | return status; | |
2859 | ||
2860 | } | |
2861 | ||
cd7a67a4 | 2862 | static int adc_sync_measurement(struct drxk_state *state, u16 *count) |
43dd07f7 RM |
2863 | { |
2864 | u16 data = 0; | |
2865 | int status; | |
2866 | ||
2da67501 MCC |
2867 | dprintk(1, "\n"); |
2868 | ||
cd7a67a4 | 2869 | /* start measurement */ |
be44eb28 MCC |
2870 | status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); |
2871 | if (status < 0) | |
2872 | goto error; | |
2873 | status = write16(state, IQM_AF_START_LOCK__A, 1); | |
2874 | if (status < 0) | |
2875 | goto error; | |
43dd07f7 | 2876 | |
be44eb28 MCC |
2877 | *count = 0; |
2878 | status = read16(state, IQM_AF_PHASE0__A, &data); | |
2879 | if (status < 0) | |
2880 | goto error; | |
2881 | if (data == 127) | |
2882 | *count = *count + 1; | |
2883 | status = read16(state, IQM_AF_PHASE1__A, &data); | |
2884 | if (status < 0) | |
2885 | goto error; | |
2886 | if (data == 127) | |
2887 | *count = *count + 1; | |
2888 | status = read16(state, IQM_AF_PHASE2__A, &data); | |
2889 | if (status < 0) | |
2890 | goto error; | |
2891 | if (data == 127) | |
2892 | *count = *count + 1; | |
2893 | ||
2894 | error: | |
2895 | if (status < 0) | |
3a4398f5 | 2896 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
2897 | return status; |
2898 | } | |
2899 | ||
cd7a67a4 | 2900 | static int adc_synchronization(struct drxk_state *state) |
43dd07f7 RM |
2901 | { |
2902 | u16 count = 0; | |
2903 | int status; | |
2904 | ||
2da67501 MCC |
2905 | dprintk(1, "\n"); |
2906 | ||
cd7a67a4 | 2907 | status = adc_sync_measurement(state, &count); |
be44eb28 MCC |
2908 | if (status < 0) |
2909 | goto error; | |
43dd07f7 | 2910 | |
be44eb28 | 2911 | if (count == 1) { |
39c1cb2b | 2912 | /* Try sampling on a different edge */ |
cd7a67a4 | 2913 | u16 clk_neg = 0; |
43dd07f7 | 2914 | |
cd7a67a4 | 2915 | status = read16(state, IQM_AF_CLKNEG__A, &clk_neg); |
be44eb28 MCC |
2916 | if (status < 0) |
2917 | goto error; | |
cd7a67a4 | 2918 | if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) == |
be44eb28 | 2919 | IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { |
cd7a67a4 MCC |
2920 | clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); |
2921 | clk_neg |= | |
be44eb28 MCC |
2922 | IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; |
2923 | } else { | |
cd7a67a4 MCC |
2924 | clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); |
2925 | clk_neg |= | |
be44eb28 | 2926 | IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; |
43dd07f7 | 2927 | } |
cd7a67a4 | 2928 | status = write16(state, IQM_AF_CLKNEG__A, clk_neg); |
be44eb28 MCC |
2929 | if (status < 0) |
2930 | goto error; | |
cd7a67a4 | 2931 | status = adc_sync_measurement(state, &count); |
be44eb28 MCC |
2932 | if (status < 0) |
2933 | goto error; | |
2934 | } | |
43dd07f7 | 2935 | |
be44eb28 MCC |
2936 | if (count < 2) |
2937 | status = -EINVAL; | |
2938 | error: | |
2939 | if (status < 0) | |
3a4398f5 | 2940 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
2941 | return status; |
2942 | } | |
2943 | ||
cd7a67a4 MCC |
2944 | static int set_frequency_shifter(struct drxk_state *state, |
2945 | u16 intermediate_freqk_hz, | |
2946 | s32 tuner_freq_offset, bool is_dtv) | |
43dd07f7 | 2947 | { |
cd7a67a4 MCC |
2948 | bool select_pos_image = false; |
2949 | u32 rf_freq_residual = tuner_freq_offset; | |
2950 | u32 fm_frequency_shift = 0; | |
2951 | bool tuner_mirror = !state->m_b_mirror_freq_spect; | |
2952 | u32 adc_freq; | |
2953 | bool adc_flip; | |
43dd07f7 | 2954 | int status; |
cd7a67a4 MCC |
2955 | u32 if_freq_actual; |
2956 | u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3); | |
2957 | u32 frequency_shift; | |
2958 | bool image_to_select; | |
43dd07f7 | 2959 | |
2da67501 MCC |
2960 | dprintk(1, "\n"); |
2961 | ||
43dd07f7 | 2962 | /* |
ebc7de22 OE |
2963 | Program frequency shifter |
2964 | No need to account for mirroring on RF | |
2965 | */ | |
cd7a67a4 MCC |
2966 | if (is_dtv) { |
2967 | if ((state->m_operation_mode == OM_QAM_ITU_A) || | |
2968 | (state->m_operation_mode == OM_QAM_ITU_C) || | |
2969 | (state->m_operation_mode == OM_DVBT)) | |
2970 | select_pos_image = true; | |
ebc7de22 | 2971 | else |
cd7a67a4 | 2972 | select_pos_image = false; |
43dd07f7 | 2973 | } |
cd7a67a4 | 2974 | if (tuner_mirror) |
43dd07f7 | 2975 | /* tuner doesn't mirror */ |
cd7a67a4 MCC |
2976 | if_freq_actual = intermediate_freqk_hz + |
2977 | rf_freq_residual + fm_frequency_shift; | |
43dd07f7 RM |
2978 | else |
2979 | /* tuner mirrors */ | |
cd7a67a4 MCC |
2980 | if_freq_actual = intermediate_freqk_hz - |
2981 | rf_freq_residual - fm_frequency_shift; | |
2982 | if (if_freq_actual > sampling_frequency / 2) { | |
43dd07f7 | 2983 | /* adc mirrors */ |
cd7a67a4 MCC |
2984 | adc_freq = sampling_frequency - if_freq_actual; |
2985 | adc_flip = true; | |
43dd07f7 RM |
2986 | } else { |
2987 | /* adc doesn't mirror */ | |
cd7a67a4 MCC |
2988 | adc_freq = if_freq_actual; |
2989 | adc_flip = false; | |
43dd07f7 RM |
2990 | } |
2991 | ||
cd7a67a4 MCC |
2992 | frequency_shift = adc_freq; |
2993 | image_to_select = state->m_rfmirror ^ tuner_mirror ^ | |
2994 | adc_flip ^ select_pos_image; | |
2995 | state->m_iqm_fs_rate_ofs = | |
2996 | Frac28a((frequency_shift), sampling_frequency); | |
43dd07f7 | 2997 | |
cd7a67a4 MCC |
2998 | if (image_to_select) |
2999 | state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1; | |
43dd07f7 RM |
3000 | |
3001 | /* Program frequency shifter with tuner offset compensation */ | |
cd7a67a4 | 3002 | /* frequency_shift += tuner_freq_offset; TODO */ |
5e66b878 | 3003 | status = write32(state, IQM_FS_RATE_OFS_LO__A, |
cd7a67a4 | 3004 | state->m_iqm_fs_rate_ofs); |
be44eb28 | 3005 | if (status < 0) |
3a4398f5 | 3006 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
3007 | return status; |
3008 | } | |
3009 | ||
cd7a67a4 | 3010 | static int init_agc(struct drxk_state *state, bool is_dtv) |
43dd07f7 | 3011 | { |
cd7a67a4 MCC |
3012 | u16 ingain_tgt = 0; |
3013 | u16 ingain_tgt_min = 0; | |
3014 | u16 ingain_tgt_max = 0; | |
3015 | u16 clp_cyclen = 0; | |
3016 | u16 clp_sum_min = 0; | |
3017 | u16 clp_dir_to = 0; | |
3018 | u16 sns_sum_min = 0; | |
3019 | u16 sns_sum_max = 0; | |
3020 | u16 clp_sum_max = 0; | |
3021 | u16 sns_dir_to = 0; | |
3022 | u16 ki_innergain_min = 0; | |
3023 | u16 if_iaccu_hi_tgt = 0; | |
3024 | u16 if_iaccu_hi_tgt_min = 0; | |
3025 | u16 if_iaccu_hi_tgt_max = 0; | |
ebc7de22 | 3026 | u16 data = 0; |
cd7a67a4 MCC |
3027 | u16 fast_clp_ctrl_delay = 0; |
3028 | u16 clp_ctrl_mode = 0; | |
43dd07f7 RM |
3029 | int status = 0; |
3030 | ||
2da67501 MCC |
3031 | dprintk(1, "\n"); |
3032 | ||
be44eb28 | 3033 | /* Common settings */ |
cd7a67a4 MCC |
3034 | sns_sum_max = 1023; |
3035 | if_iaccu_hi_tgt_min = 2047; | |
3036 | clp_cyclen = 500; | |
3037 | clp_sum_max = 1023; | |
be44eb28 | 3038 | |
f1b82970 | 3039 | /* AGCInit() not available for DVBT; init done in microcode */ |
cd7a67a4 | 3040 | if (!is_qam(state)) { |
3a4398f5 MCC |
3041 | pr_err("%s: mode %d is not DVB-C\n", |
3042 | __func__, state->m_operation_mode); | |
f1b82970 | 3043 | return -EINVAL; |
be44eb28 | 3044 | } |
f1b82970 MCC |
3045 | |
3046 | /* FIXME: Analog TV AGC require different settings */ | |
3047 | ||
3048 | /* Standard specific settings */ | |
cd7a67a4 MCC |
3049 | clp_sum_min = 8; |
3050 | clp_dir_to = (u16) -9; | |
3051 | clp_ctrl_mode = 0; | |
3052 | sns_sum_min = 8; | |
3053 | sns_dir_to = (u16) -9; | |
3054 | ki_innergain_min = (u16) -1030; | |
3055 | if_iaccu_hi_tgt_max = 0x2380; | |
3056 | if_iaccu_hi_tgt = 0x2380; | |
3057 | ingain_tgt_min = 0x0511; | |
3058 | ingain_tgt = 0x0511; | |
3059 | ingain_tgt_max = 5119; | |
3060 | fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay; | |
f1b82970 | 3061 | |
ab5060cd MCC |
3062 | status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, |
3063 | fast_clp_ctrl_delay); | |
be44eb28 MCC |
3064 | if (status < 0) |
3065 | goto error; | |
ea90f011 | 3066 | |
cd7a67a4 | 3067 | status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode); |
be44eb28 MCC |
3068 | if (status < 0) |
3069 | goto error; | |
cd7a67a4 | 3070 | status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt); |
be44eb28 MCC |
3071 | if (status < 0) |
3072 | goto error; | |
cd7a67a4 | 3073 | status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min); |
be44eb28 MCC |
3074 | if (status < 0) |
3075 | goto error; | |
cd7a67a4 | 3076 | status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max); |
be44eb28 MCC |
3077 | if (status < 0) |
3078 | goto error; | |
ab5060cd MCC |
3079 | status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, |
3080 | if_iaccu_hi_tgt_min); | |
be44eb28 MCC |
3081 | if (status < 0) |
3082 | goto error; | |
ab5060cd MCC |
3083 | status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, |
3084 | if_iaccu_hi_tgt_max); | |
be44eb28 MCC |
3085 | if (status < 0) |
3086 | goto error; | |
3087 | status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); | |
3088 | if (status < 0) | |
3089 | goto error; | |
3090 | status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0); | |
3091 | if (status < 0) | |
3092 | goto error; | |
3093 | status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0); | |
3094 | if (status < 0) | |
3095 | goto error; | |
3096 | status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); | |
3097 | if (status < 0) | |
3098 | goto error; | |
cd7a67a4 | 3099 | status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max); |
be44eb28 MCC |
3100 | if (status < 0) |
3101 | goto error; | |
cd7a67a4 | 3102 | status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max); |
be44eb28 MCC |
3103 | if (status < 0) |
3104 | goto error; | |
ea90f011 | 3105 | |
ab5060cd MCC |
3106 | status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, |
3107 | ki_innergain_min); | |
be44eb28 MCC |
3108 | if (status < 0) |
3109 | goto error; | |
ab5060cd MCC |
3110 | status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, |
3111 | if_iaccu_hi_tgt); | |
be44eb28 MCC |
3112 | if (status < 0) |
3113 | goto error; | |
cd7a67a4 | 3114 | status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen); |
be44eb28 MCC |
3115 | if (status < 0) |
3116 | goto error; | |
ea90f011 | 3117 | |
be44eb28 MCC |
3118 | status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023); |
3119 | if (status < 0) | |
3120 | goto error; | |
3121 | status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); | |
3122 | if (status < 0) | |
3123 | goto error; | |
3124 | status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); | |
3125 | if (status < 0) | |
3126 | goto error; | |
ea90f011 | 3127 | |
be44eb28 MCC |
3128 | status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); |
3129 | if (status < 0) | |
3130 | goto error; | |
cd7a67a4 | 3131 | status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min); |
be44eb28 MCC |
3132 | if (status < 0) |
3133 | goto error; | |
cd7a67a4 | 3134 | status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min); |
be44eb28 MCC |
3135 | if (status < 0) |
3136 | goto error; | |
cd7a67a4 | 3137 | status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to); |
be44eb28 MCC |
3138 | if (status < 0) |
3139 | goto error; | |
cd7a67a4 | 3140 | status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to); |
be44eb28 MCC |
3141 | if (status < 0) |
3142 | goto error; | |
3143 | status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); | |
3144 | if (status < 0) | |
3145 | goto error; | |
3146 | status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); | |
3147 | if (status < 0) | |
3148 | goto error; | |
3149 | status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117); | |
3150 | if (status < 0) | |
3151 | goto error; | |
3152 | status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657); | |
3153 | if (status < 0) | |
3154 | goto error; | |
3155 | status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0); | |
3156 | if (status < 0) | |
3157 | goto error; | |
3158 | status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0); | |
3159 | if (status < 0) | |
3160 | goto error; | |
3161 | status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0); | |
3162 | if (status < 0) | |
3163 | goto error; | |
3164 | status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1); | |
3165 | if (status < 0) | |
3166 | goto error; | |
3167 | status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0); | |
3168 | if (status < 0) | |
3169 | goto error; | |
3170 | status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0); | |
3171 | if (status < 0) | |
3172 | goto error; | |
3173 | status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0); | |
3174 | if (status < 0) | |
3175 | goto error; | |
3176 | status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1); | |
3177 | if (status < 0) | |
3178 | goto error; | |
3179 | status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500); | |
3180 | if (status < 0) | |
3181 | goto error; | |
3182 | status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500); | |
3183 | if (status < 0) | |
3184 | goto error; | |
43dd07f7 | 3185 | |
be44eb28 MCC |
3186 | /* Initialize inner-loop KI gain factors */ |
3187 | status = read16(state, SCU_RAM_AGC_KI__A, &data); | |
3188 | if (status < 0) | |
3189 | goto error; | |
f1b82970 MCC |
3190 | |
3191 | data = 0x0657; | |
3192 | data &= ~SCU_RAM_AGC_KI_RF__M; | |
3193 | data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); | |
3194 | data &= ~SCU_RAM_AGC_KI_IF__M; | |
3195 | data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); | |
3196 | ||
be44eb28 MCC |
3197 | status = write16(state, SCU_RAM_AGC_KI__A, data); |
3198 | error: | |
3199 | if (status < 0) | |
3a4398f5 | 3200 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
3201 | return status; |
3202 | } | |
3203 | ||
cd7a67a4 | 3204 | static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err) |
43dd07f7 RM |
3205 | { |
3206 | int status; | |
3207 | ||
2da67501 | 3208 | dprintk(1, "\n"); |
cd7a67a4 | 3209 | if (packet_err == NULL) |
be44eb28 MCC |
3210 | status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); |
3211 | else | |
ab5060cd MCC |
3212 | status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, |
3213 | packet_err); | |
be44eb28 | 3214 | if (status < 0) |
3a4398f5 | 3215 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
3216 | return status; |
3217 | } | |
3218 | ||
cd7a67a4 | 3219 | static int dvbt_sc_command(struct drxk_state *state, |
43dd07f7 RM |
3220 | u16 cmd, u16 subcmd, |
3221 | u16 param0, u16 param1, u16 param2, | |
3222 | u16 param3, u16 param4) | |
3223 | { | |
cd7a67a4 MCC |
3224 | u16 cur_cmd = 0; |
3225 | u16 err_code = 0; | |
3226 | u16 retry_cnt = 0; | |
3227 | u16 sc_exec = 0; | |
ebc7de22 | 3228 | int status; |
43dd07f7 | 3229 | |
2da67501 | 3230 | dprintk(1, "\n"); |
cd7a67a4 MCC |
3231 | status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec); |
3232 | if (sc_exec != 1) { | |
43dd07f7 | 3233 | /* SC is not running */ |
be44eb28 | 3234 | status = -EINVAL; |
43dd07f7 | 3235 | } |
be44eb28 MCC |
3236 | if (status < 0) |
3237 | goto error; | |
43dd07f7 RM |
3238 | |
3239 | /* Wait until sc is ready to receive command */ | |
cd7a67a4 | 3240 | retry_cnt = 0; |
43dd07f7 | 3241 | do { |
b72852ba | 3242 | usleep_range(1000, 2000); |
cd7a67a4 MCC |
3243 | status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); |
3244 | retry_cnt++; | |
3245 | } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES)); | |
3246 | if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0)) | |
be44eb28 MCC |
3247 | goto error; |
3248 | ||
43dd07f7 RM |
3249 | /* Write sub-command */ |
3250 | switch (cmd) { | |
3251 | /* All commands using sub-cmd */ | |
3252 | case OFDM_SC_RA_RAM_CMD_PROC_START: | |
3253 | case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: | |
3254 | case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: | |
be44eb28 MCC |
3255 | status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); |
3256 | if (status < 0) | |
3257 | goto error; | |
43dd07f7 RM |
3258 | break; |
3259 | default: | |
3260 | /* Do nothing */ | |
3261 | break; | |
be44eb28 | 3262 | } |
43dd07f7 RM |
3263 | |
3264 | /* Write needed parameters and the command */ | |
2f60f13c | 3265 | status = 0; |
43dd07f7 RM |
3266 | switch (cmd) { |
3267 | /* All commands using 5 parameters */ | |
3268 | /* All commands using 4 parameters */ | |
3269 | /* All commands using 3 parameters */ | |
3270 | /* All commands using 2 parameters */ | |
3271 | case OFDM_SC_RA_RAM_CMD_PROC_START: | |
3272 | case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: | |
3273 | case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: | |
2f60f13c | 3274 | status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1); |
43dd07f7 RM |
3275 | /* All commands using 1 parameters */ |
3276 | case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: | |
3277 | case OFDM_SC_RA_RAM_CMD_USER_IO: | |
2f60f13c | 3278 | status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0); |
43dd07f7 RM |
3279 | /* All commands using 0 parameters */ |
3280 | case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: | |
3281 | case OFDM_SC_RA_RAM_CMD_NULL: | |
3282 | /* Write command */ | |
2f60f13c | 3283 | status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd); |
43dd07f7 RM |
3284 | break; |
3285 | default: | |
3286 | /* Unknown command */ | |
be44eb28 MCC |
3287 | status = -EINVAL; |
3288 | } | |
3289 | if (status < 0) | |
3290 | goto error; | |
43dd07f7 RM |
3291 | |
3292 | /* Wait until sc is ready processing command */ | |
cd7a67a4 | 3293 | retry_cnt = 0; |
ebc7de22 | 3294 | do { |
b72852ba | 3295 | usleep_range(1000, 2000); |
cd7a67a4 MCC |
3296 | status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); |
3297 | retry_cnt++; | |
3298 | } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES)); | |
3299 | if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0)) | |
be44eb28 | 3300 | goto error; |
43dd07f7 RM |
3301 | |
3302 | /* Check for illegal cmd */ | |
cd7a67a4 MCC |
3303 | status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code); |
3304 | if (err_code == 0xFFFF) { | |
43dd07f7 | 3305 | /* illegal command */ |
be44eb28 | 3306 | status = -EINVAL; |
43dd07f7 | 3307 | } |
be44eb28 MCC |
3308 | if (status < 0) |
3309 | goto error; | |
43dd07f7 | 3310 | |
39c1cb2b | 3311 | /* Retrieve results parameters from SC */ |
43dd07f7 RM |
3312 | switch (cmd) { |
3313 | /* All commands yielding 5 results */ | |
3314 | /* All commands yielding 4 results */ | |
3315 | /* All commands yielding 3 results */ | |
3316 | /* All commands yielding 2 results */ | |
3317 | /* All commands yielding 1 result */ | |
3318 | case OFDM_SC_RA_RAM_CMD_USER_IO: | |
3319 | case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: | |
be44eb28 | 3320 | status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); |
43dd07f7 RM |
3321 | /* All commands yielding 0 results */ |
3322 | case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: | |
3323 | case OFDM_SC_RA_RAM_CMD_SET_TIMER: | |
3324 | case OFDM_SC_RA_RAM_CMD_PROC_START: | |
3325 | case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: | |
3326 | case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: | |
3327 | case OFDM_SC_RA_RAM_CMD_NULL: | |
3328 | break; | |
3329 | default: | |
3330 | /* Unknown command */ | |
be44eb28 | 3331 | status = -EINVAL; |
43dd07f7 | 3332 | break; |
ebc7de22 | 3333 | } /* switch (cmd->cmd) */ |
be44eb28 MCC |
3334 | error: |
3335 | if (status < 0) | |
3a4398f5 | 3336 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
3337 | return status; |
3338 | } | |
3339 | ||
cd7a67a4 | 3340 | static int power_up_dvbt(struct drxk_state *state) |
43dd07f7 | 3341 | { |
cd7a67a4 | 3342 | enum drx_power_mode power_mode = DRX_POWER_UP; |
43dd07f7 RM |
3343 | int status; |
3344 | ||
2da67501 | 3345 | dprintk(1, "\n"); |
cd7a67a4 | 3346 | status = ctrl_power_mode(state, &power_mode); |
be44eb28 | 3347 | if (status < 0) |
3a4398f5 | 3348 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
3349 | return status; |
3350 | } | |
3351 | ||
cd7a67a4 | 3352 | static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled) |
43dd07f7 | 3353 | { |
ebc7de22 OE |
3354 | int status; |
3355 | ||
2da67501 | 3356 | dprintk(1, "\n"); |
5a7f7b79 | 3357 | if (*enabled) |
5e66b878 | 3358 | status = write16(state, IQM_CF_BYPASSDET__A, 0); |
ebc7de22 | 3359 | else |
5e66b878 | 3360 | status = write16(state, IQM_CF_BYPASSDET__A, 1); |
be44eb28 | 3361 | if (status < 0) |
3a4398f5 | 3362 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 3363 | return status; |
43dd07f7 | 3364 | } |
ebc7de22 OE |
3365 | |
3366 | #define DEFAULT_FR_THRES_8K 4000 | |
cd7a67a4 | 3367 | static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled) |
43dd07f7 RM |
3368 | { |
3369 | ||
ebc7de22 OE |
3370 | int status; |
3371 | ||
2da67501 | 3372 | dprintk(1, "\n"); |
5a7f7b79 | 3373 | if (*enabled) { |
ebc7de22 | 3374 | /* write mask to 1 */ |
5e66b878 | 3375 | status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, |
ebc7de22 OE |
3376 | DEFAULT_FR_THRES_8K); |
3377 | } else { | |
3378 | /* write mask to 0 */ | |
5e66b878 | 3379 | status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); |
ebc7de22 | 3380 | } |
be44eb28 | 3381 | if (status < 0) |
3a4398f5 | 3382 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 OE |
3383 | |
3384 | return status; | |
43dd07f7 RM |
3385 | } |
3386 | ||
cd7a67a4 | 3387 | static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, |
ab5060cd | 3388 | struct drxk_cfg_dvbt_echo_thres_t *echo_thres) |
43dd07f7 | 3389 | { |
ebc7de22 | 3390 | u16 data = 0; |
43dd07f7 | 3391 | int status; |
43dd07f7 | 3392 | |
2da67501 | 3393 | dprintk(1, "\n"); |
be44eb28 MCC |
3394 | status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); |
3395 | if (status < 0) | |
3396 | goto error; | |
3397 | ||
cd7a67a4 | 3398 | switch (echo_thres->fft_mode) { |
be44eb28 MCC |
3399 | case DRX_FFTMODE_2K: |
3400 | data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M; | |
cd7a67a4 | 3401 | data |= ((echo_thres->threshold << |
be44eb28 MCC |
3402 | OFDM_SC_RA_RAM_ECHO_THRES_2K__B) |
3403 | & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); | |
320ed23e | 3404 | break; |
be44eb28 MCC |
3405 | case DRX_FFTMODE_8K: |
3406 | data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M; | |
cd7a67a4 | 3407 | data |= ((echo_thres->threshold << |
be44eb28 MCC |
3408 | OFDM_SC_RA_RAM_ECHO_THRES_8K__B) |
3409 | & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); | |
320ed23e | 3410 | break; |
be44eb28 MCC |
3411 | default: |
3412 | return -EINVAL; | |
be44eb28 | 3413 | } |
ebc7de22 | 3414 | |
be44eb28 MCC |
3415 | status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); |
3416 | error: | |
3417 | if (status < 0) | |
3a4398f5 | 3418 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 3419 | return status; |
43dd07f7 RM |
3420 | } |
3421 | ||
cd7a67a4 MCC |
3422 | static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state, |
3423 | enum drxk_cfg_dvbt_sqi_speed *speed) | |
43dd07f7 | 3424 | { |
be44eb28 | 3425 | int status = -EINVAL; |
43dd07f7 | 3426 | |
2da67501 MCC |
3427 | dprintk(1, "\n"); |
3428 | ||
43dd07f7 RM |
3429 | switch (*speed) { |
3430 | case DRXK_DVBT_SQI_SPEED_FAST: | |
3431 | case DRXK_DVBT_SQI_SPEED_MEDIUM: | |
3432 | case DRXK_DVBT_SQI_SPEED_SLOW: | |
3433 | break; | |
3434 | default: | |
be44eb28 | 3435 | goto error; |
43dd07f7 | 3436 | } |
5e66b878 | 3437 | status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, |
ebc7de22 | 3438 | (u16) *speed); |
be44eb28 MCC |
3439 | error: |
3440 | if (status < 0) | |
3a4398f5 | 3441 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
3442 | return status; |
3443 | } | |
3444 | ||
3445 | /*============================================================================*/ | |
3446 | ||
3447 | /** | |
3448 | * \brief Activate DVBT specific presets | |
3449 | * \param demod instance of demodulator. | |
3450 | * \return DRXStatus_t. | |
3451 | * | |
3452 | * Called in DVBTSetStandard | |
3453 | * | |
3454 | */ | |
cd7a67a4 | 3455 | static int dvbt_activate_presets(struct drxk_state *state) |
43dd07f7 | 3456 | { |
ebc7de22 | 3457 | int status; |
be44eb28 MCC |
3458 | bool setincenable = false; |
3459 | bool setfrenable = true; | |
ebc7de22 | 3460 | |
cd7a67a4 MCC |
3461 | struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K }; |
3462 | struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K }; | |
ebc7de22 | 3463 | |
2da67501 | 3464 | dprintk(1, "\n"); |
cd7a67a4 | 3465 | status = dvbt_ctrl_set_inc_enable(state, &setincenable); |
be44eb28 MCC |
3466 | if (status < 0) |
3467 | goto error; | |
cd7a67a4 | 3468 | status = dvbt_ctrl_set_fr_enable(state, &setfrenable); |
be44eb28 MCC |
3469 | if (status < 0) |
3470 | goto error; | |
cd7a67a4 | 3471 | status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k); |
be44eb28 MCC |
3472 | if (status < 0) |
3473 | goto error; | |
cd7a67a4 | 3474 | status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k); |
be44eb28 MCC |
3475 | if (status < 0) |
3476 | goto error; | |
ab5060cd MCC |
3477 | status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, |
3478 | state->m_dvbt_if_agc_cfg.ingain_tgt_max); | |
be44eb28 MCC |
3479 | error: |
3480 | if (status < 0) | |
3a4398f5 | 3481 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 3482 | return status; |
43dd07f7 | 3483 | } |
ebc7de22 | 3484 | |
43dd07f7 RM |
3485 | /*============================================================================*/ |
3486 | ||
3487 | /** | |
3488 | * \brief Initialize channelswitch-independent settings for DVBT. | |
3489 | * \param demod instance of demodulator. | |
3490 | * \return DRXStatus_t. | |
3491 | * | |
3492 | * For ROM code channel filter taps are loaded from the bootloader. For microcode | |
3493 | * the DVB-T taps from the drxk_filters.h are used. | |
3494 | */ | |
cd7a67a4 MCC |
3495 | static int set_dvbt_standard(struct drxk_state *state, |
3496 | enum operation_mode o_mode) | |
43dd07f7 | 3497 | { |
cd7a67a4 | 3498 | u16 cmd_result = 0; |
ebc7de22 OE |
3499 | u16 data = 0; |
3500 | int status; | |
43dd07f7 | 3501 | |
2da67501 | 3502 | dprintk(1, "\n"); |
43dd07f7 | 3503 | |
cd7a67a4 | 3504 | power_up_dvbt(state); |
be44eb28 | 3505 | /* added antenna switch */ |
cd7a67a4 | 3506 | switch_antenna_to_dvbt(state); |
be44eb28 | 3507 | /* send OFDM reset command */ |
ab5060cd MCC |
3508 | status = scu_command(state, |
3509 | SCU_RAM_COMMAND_STANDARD_OFDM | |
3510 | | SCU_RAM_COMMAND_CMD_DEMOD_RESET, | |
3511 | 0, NULL, 1, &cmd_result); | |
be44eb28 MCC |
3512 | if (status < 0) |
3513 | goto error; | |
43dd07f7 | 3514 | |
be44eb28 | 3515 | /* send OFDM setenv command */ |
ab5060cd MCC |
3516 | status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM |
3517 | | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, | |
3518 | 0, NULL, 1, &cmd_result); | |
be44eb28 MCC |
3519 | if (status < 0) |
3520 | goto error; | |
43dd07f7 | 3521 | |
be44eb28 MCC |
3522 | /* reset datapath for OFDM, processors first */ |
3523 | status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); | |
3524 | if (status < 0) | |
3525 | goto error; | |
3526 | status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); | |
3527 | if (status < 0) | |
3528 | goto error; | |
3529 | status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); | |
3530 | if (status < 0) | |
3531 | goto error; | |
43dd07f7 | 3532 | |
be44eb28 MCC |
3533 | /* IQM setup */ |
3534 | /* synchronize on ofdstate->m_festart */ | |
3535 | status = write16(state, IQM_AF_UPD_SEL__A, 1); | |
3536 | if (status < 0) | |
3537 | goto error; | |
3538 | /* window size for clipping ADC detection */ | |
3539 | status = write16(state, IQM_AF_CLP_LEN__A, 0); | |
3540 | if (status < 0) | |
3541 | goto error; | |
3542 | /* window size for for sense pre-SAW detection */ | |
3543 | status = write16(state, IQM_AF_SNS_LEN__A, 0); | |
3544 | if (status < 0) | |
3545 | goto error; | |
3546 | /* sense threshold for sense pre-SAW detection */ | |
3547 | status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); | |
3548 | if (status < 0) | |
3549 | goto error; | |
cd7a67a4 | 3550 | status = set_iqm_af(state, true); |
be44eb28 MCC |
3551 | if (status < 0) |
3552 | goto error; | |
43dd07f7 | 3553 | |
be44eb28 MCC |
3554 | status = write16(state, IQM_AF_AGC_RF__A, 0); |
3555 | if (status < 0) | |
3556 | goto error; | |
43dd07f7 | 3557 | |
be44eb28 MCC |
3558 | /* Impulse noise cruncher setup */ |
3559 | status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */ | |
3560 | if (status < 0) | |
3561 | goto error; | |
3562 | status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */ | |
3563 | if (status < 0) | |
3564 | goto error; | |
3565 | status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */ | |
3566 | if (status < 0) | |
3567 | goto error; | |
43dd07f7 | 3568 | |
be44eb28 MCC |
3569 | status = write16(state, IQM_RC_STRETCH__A, 16); |
3570 | if (status < 0) | |
3571 | goto error; | |
ab5060cd | 3572 | status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ |
be44eb28 MCC |
3573 | if (status < 0) |
3574 | goto error; | |
3575 | status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ | |
3576 | if (status < 0) | |
3577 | goto error; | |
3578 | status = write16(state, IQM_CF_SCALE__A, 1600); | |
3579 | if (status < 0) | |
3580 | goto error; | |
3581 | status = write16(state, IQM_CF_SCALE_SH__A, 0); | |
3582 | if (status < 0) | |
3583 | goto error; | |
43dd07f7 | 3584 | |
be44eb28 MCC |
3585 | /* virtual clipping threshold for clipping ADC detection */ |
3586 | status = write16(state, IQM_AF_CLP_TH__A, 448); | |
3587 | if (status < 0) | |
3588 | goto error; | |
3589 | status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */ | |
3590 | if (status < 0) | |
3591 | goto error; | |
43dd07f7 | 3592 | |
ab5060cd MCC |
3593 | status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, |
3594 | DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); | |
be44eb28 MCC |
3595 | if (status < 0) |
3596 | goto error; | |
43dd07f7 | 3597 | |
be44eb28 MCC |
3598 | status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */ |
3599 | if (status < 0) | |
3600 | goto error; | |
3601 | status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2); | |
3602 | if (status < 0) | |
3603 | goto error; | |
3604 | /* enable power measurement interrupt */ | |
3605 | status = write16(state, IQM_CF_COMM_INT_MSK__A, 1); | |
3606 | if (status < 0) | |
3607 | goto error; | |
3608 | status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); | |
3609 | if (status < 0) | |
3610 | goto error; | |
43dd07f7 | 3611 | |
be44eb28 | 3612 | /* IQM will not be reset from here, sync ADC and update/init AGC */ |
cd7a67a4 | 3613 | status = adc_synchronization(state); |
be44eb28 MCC |
3614 | if (status < 0) |
3615 | goto error; | |
cd7a67a4 | 3616 | status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg); |
be44eb28 MCC |
3617 | if (status < 0) |
3618 | goto error; | |
43dd07f7 | 3619 | |
be44eb28 MCC |
3620 | /* Halt SCU to enable safe non-atomic accesses */ |
3621 | status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); | |
3622 | if (status < 0) | |
3623 | goto error; | |
43dd07f7 | 3624 | |
cd7a67a4 | 3625 | status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true); |
be44eb28 MCC |
3626 | if (status < 0) |
3627 | goto error; | |
cd7a67a4 | 3628 | status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true); |
be44eb28 MCC |
3629 | if (status < 0) |
3630 | goto error; | |
43dd07f7 | 3631 | |
be44eb28 MCC |
3632 | /* Set Noise Estimation notch width and enable DC fix */ |
3633 | status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data); | |
3634 | if (status < 0) | |
3635 | goto error; | |
3636 | data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; | |
3637 | status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data); | |
3638 | if (status < 0) | |
3639 | goto error; | |
43dd07f7 | 3640 | |
be44eb28 MCC |
3641 | /* Activate SCU to enable SCU commands */ |
3642 | status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); | |
3643 | if (status < 0) | |
3644 | goto error; | |
43dd07f7 | 3645 | |
cd7a67a4 MCC |
3646 | if (!state->m_drxk_a3_rom_code) { |
3647 | /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay */ | |
ab5060cd MCC |
3648 | status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, |
3649 | state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay); | |
be44eb28 MCC |
3650 | if (status < 0) |
3651 | goto error; | |
3652 | } | |
43dd07f7 | 3653 | |
be44eb28 | 3654 | /* OFDM_SC setup */ |
43dd07f7 | 3655 | #ifdef COMPILE_FOR_NONRT |
be44eb28 MCC |
3656 | status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1); |
3657 | if (status < 0) | |
3658 | goto error; | |
3659 | status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2); | |
3660 | if (status < 0) | |
3661 | goto error; | |
43dd07f7 RM |
3662 | #endif |
3663 | ||
be44eb28 MCC |
3664 | /* FEC setup */ |
3665 | status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */ | |
3666 | if (status < 0) | |
3667 | goto error; | |
43dd07f7 RM |
3668 | |
3669 | ||
3670 | #ifdef COMPILE_FOR_NONRT | |
be44eb28 MCC |
3671 | status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400); |
3672 | if (status < 0) | |
3673 | goto error; | |
43dd07f7 | 3674 | #else |
be44eb28 MCC |
3675 | status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000); |
3676 | if (status < 0) | |
3677 | goto error; | |
43dd07f7 | 3678 | #endif |
be44eb28 MCC |
3679 | status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001); |
3680 | if (status < 0) | |
3681 | goto error; | |
43dd07f7 | 3682 | |
be44eb28 | 3683 | /* Setup MPEG bus */ |
cd7a67a4 | 3684 | status = mpegts_dto_setup(state, OM_DVBT); |
ebc7de22 | 3685 | if (status < 0) |
be44eb28 MCC |
3686 | goto error; |
3687 | /* Set DVBT Presets */ | |
cd7a67a4 | 3688 | status = dvbt_activate_presets(state); |
be44eb28 MCC |
3689 | if (status < 0) |
3690 | goto error; | |
43dd07f7 | 3691 | |
be44eb28 MCC |
3692 | error: |
3693 | if (status < 0) | |
3a4398f5 | 3694 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
3695 | return status; |
3696 | } | |
3697 | ||
3698 | /*============================================================================*/ | |
3699 | /** | |
cd7a67a4 | 3700 | * \brief start dvbt demodulating for channel. |
43dd07f7 RM |
3701 | * \param demod instance of demodulator. |
3702 | * \return DRXStatus_t. | |
3703 | */ | |
cd7a67a4 | 3704 | static int dvbt_start(struct drxk_state *state) |
43dd07f7 | 3705 | { |
ebc7de22 OE |
3706 | u16 param1; |
3707 | int status; | |
cd7a67a4 | 3708 | /* drxk_ofdm_sc_cmd_t scCmd; */ |
ebc7de22 | 3709 | |
2da67501 | 3710 | dprintk(1, "\n"); |
cd7a67a4 | 3711 | /* start correct processes to get in lock */ |
ebc7de22 | 3712 | /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ |
be44eb28 | 3713 | param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; |
ab5060cd MCC |
3714 | status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, |
3715 | OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, | |
3716 | 0, 0, 0); | |
be44eb28 MCC |
3717 | if (status < 0) |
3718 | goto error; | |
cd7a67a4 MCC |
3719 | /* start FEC OC */ |
3720 | status = mpegts_start(state); | |
be44eb28 MCC |
3721 | if (status < 0) |
3722 | goto error; | |
3723 | status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); | |
3724 | if (status < 0) | |
3725 | goto error; | |
3726 | error: | |
3727 | if (status < 0) | |
3a4398f5 | 3728 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 3729 | return status; |
43dd07f7 RM |
3730 | } |
3731 | ||
3732 | ||
3733 | /*============================================================================*/ | |
3734 | ||
3735 | /** | |
3736 | * \brief Set up dvbt demodulator for channel. | |
3737 | * \param demod instance of demodulator. | |
3738 | * \return DRXStatus_t. | |
3739 | * // original DVBTSetChannel() | |
3740 | */ | |
cd7a67a4 MCC |
3741 | static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, |
3742 | s32 tuner_freq_offset) | |
43dd07f7 | 3743 | { |
cd7a67a4 MCC |
3744 | u16 cmd_result = 0; |
3745 | u16 transmission_params = 0; | |
3746 | u16 operation_mode = 0; | |
3747 | u32 iqm_rc_rate_ofs = 0; | |
ebc7de22 OE |
3748 | u32 bandwidth = 0; |
3749 | u16 param1; | |
43dd07f7 RM |
3750 | int status; |
3751 | ||
ab5060cd MCC |
3752 | dprintk(1, "IF =%d, TFO = %d\n", |
3753 | intermediate_freqk_hz, tuner_freq_offset); | |
43dd07f7 | 3754 | |
ab5060cd MCC |
3755 | status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM |
3756 | | SCU_RAM_COMMAND_CMD_DEMOD_STOP, | |
3757 | 0, NULL, 1, &cmd_result); | |
be44eb28 MCC |
3758 | if (status < 0) |
3759 | goto error; | |
43dd07f7 | 3760 | |
be44eb28 MCC |
3761 | /* Halt SCU to enable safe non-atomic accesses */ |
3762 | status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); | |
3763 | if (status < 0) | |
3764 | goto error; | |
43dd07f7 | 3765 | |
be44eb28 MCC |
3766 | /* Stop processors */ |
3767 | status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); | |
3768 | if (status < 0) | |
3769 | goto error; | |
3770 | status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); | |
3771 | if (status < 0) | |
3772 | goto error; | |
43dd07f7 | 3773 | |
be44eb28 MCC |
3774 | /* Mandatory fix, always stop CP, required to set spl offset back to |
3775 | hardware default (is set to 0 by ucode during pilot detection */ | |
3776 | status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP); | |
3777 | if (status < 0) | |
3778 | goto error; | |
43dd07f7 | 3779 | |
ab5060cd | 3780 | /*== Write channel settings to device ================================*/ |
43dd07f7 | 3781 | |
be44eb28 | 3782 | /* mode */ |
ed5452a2 | 3783 | switch (state->props.transmission_mode) { |
be44eb28 MCC |
3784 | case TRANSMISSION_MODE_AUTO: |
3785 | default: | |
cd7a67a4 | 3786 | operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; |
be44eb28 MCC |
3787 | /* fall through , try first guess DRX_FFTMODE_8K */ |
3788 | case TRANSMISSION_MODE_8K: | |
cd7a67a4 | 3789 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; |
320ed23e | 3790 | break; |
be44eb28 | 3791 | case TRANSMISSION_MODE_2K: |
cd7a67a4 | 3792 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; |
320ed23e | 3793 | break; |
be44eb28 | 3794 | } |
43dd07f7 | 3795 | |
be44eb28 | 3796 | /* guard */ |
ed5452a2 | 3797 | switch (state->props.guard_interval) { |
be44eb28 MCC |
3798 | default: |
3799 | case GUARD_INTERVAL_AUTO: | |
cd7a67a4 | 3800 | operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; |
be44eb28 MCC |
3801 | /* fall through , try first guess DRX_GUARD_1DIV4 */ |
3802 | case GUARD_INTERVAL_1_4: | |
cd7a67a4 | 3803 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; |
320ed23e | 3804 | break; |
be44eb28 | 3805 | case GUARD_INTERVAL_1_32: |
cd7a67a4 | 3806 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; |
320ed23e | 3807 | break; |
be44eb28 | 3808 | case GUARD_INTERVAL_1_16: |
cd7a67a4 | 3809 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; |
320ed23e | 3810 | break; |
be44eb28 | 3811 | case GUARD_INTERVAL_1_8: |
cd7a67a4 | 3812 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; |
320ed23e | 3813 | break; |
be44eb28 | 3814 | } |
43dd07f7 | 3815 | |
be44eb28 | 3816 | /* hierarchy */ |
ed5452a2 | 3817 | switch (state->props.hierarchy) { |
be44eb28 MCC |
3818 | case HIERARCHY_AUTO: |
3819 | case HIERARCHY_NONE: | |
3820 | default: | |
cd7a67a4 | 3821 | operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; |
be44eb28 | 3822 | /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ |
cd7a67a4 | 3823 | /* transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */ |
be44eb28 MCC |
3824 | /* break; */ |
3825 | case HIERARCHY_1: | |
cd7a67a4 | 3826 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; |
be44eb28 MCC |
3827 | break; |
3828 | case HIERARCHY_2: | |
cd7a67a4 | 3829 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; |
be44eb28 MCC |
3830 | break; |
3831 | case HIERARCHY_4: | |
cd7a67a4 | 3832 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; |
be44eb28 MCC |
3833 | break; |
3834 | } | |
3835 | ||
3836 | ||
ed5452a2 MCC |
3837 | /* modulation */ |
3838 | switch (state->props.modulation) { | |
be44eb28 MCC |
3839 | case QAM_AUTO: |
3840 | default: | |
cd7a67a4 | 3841 | operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; |
be44eb28 MCC |
3842 | /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ |
3843 | case QAM_64: | |
cd7a67a4 | 3844 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; |
be44eb28 MCC |
3845 | break; |
3846 | case QPSK: | |
cd7a67a4 | 3847 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; |
be44eb28 MCC |
3848 | break; |
3849 | case QAM_16: | |
cd7a67a4 | 3850 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; |
be44eb28 MCC |
3851 | break; |
3852 | } | |
43dd07f7 | 3853 | #if 0 |
39c1cb2b | 3854 | /* No hierarchical channels support in BDA */ |
be44eb28 MCC |
3855 | /* Priority (only for hierarchical channels) */ |
3856 | switch (channel->priority) { | |
3857 | case DRX_PRIORITY_LOW: | |
cd7a67a4 MCC |
3858 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; |
3859 | WR16(dev_addr, OFDM_EC_SB_PRIOR__A, | |
be44eb28 MCC |
3860 | OFDM_EC_SB_PRIOR_LO); |
3861 | break; | |
3862 | case DRX_PRIORITY_HIGH: | |
cd7a67a4 MCC |
3863 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; |
3864 | WR16(dev_addr, OFDM_EC_SB_PRIOR__A, | |
be44eb28 MCC |
3865 | OFDM_EC_SB_PRIOR_HI)); |
3866 | break; | |
3867 | case DRX_PRIORITY_UNKNOWN: /* fall through */ | |
3868 | default: | |
3869 | status = -EINVAL; | |
3870 | goto error; | |
3871 | } | |
3872 | #else | |
3873 | /* Set Priorty high */ | |
cd7a67a4 | 3874 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; |
be44eb28 MCC |
3875 | status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); |
3876 | if (status < 0) | |
3877 | goto error; | |
43dd07f7 RM |
3878 | #endif |
3879 | ||
be44eb28 | 3880 | /* coderate */ |
ed5452a2 | 3881 | switch (state->props.code_rate_HP) { |
be44eb28 MCC |
3882 | case FEC_AUTO: |
3883 | default: | |
cd7a67a4 | 3884 | operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; |
be44eb28 MCC |
3885 | /* fall through , try first guess DRX_CODERATE_2DIV3 */ |
3886 | case FEC_2_3: | |
cd7a67a4 | 3887 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; |
be44eb28 MCC |
3888 | break; |
3889 | case FEC_1_2: | |
cd7a67a4 | 3890 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; |
be44eb28 MCC |
3891 | break; |
3892 | case FEC_3_4: | |
cd7a67a4 | 3893 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; |
be44eb28 MCC |
3894 | break; |
3895 | case FEC_5_6: | |
cd7a67a4 | 3896 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; |
be44eb28 MCC |
3897 | break; |
3898 | case FEC_7_8: | |
cd7a67a4 | 3899 | transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; |
be44eb28 MCC |
3900 | break; |
3901 | } | |
43dd07f7 | 3902 | |
ab5060cd MCC |
3903 | /* |
3904 | * SAW filter selection: normaly not necesarry, but if wanted | |
3905 | * the application can select a SAW filter via the driver by | |
3906 | * using UIOs | |
3907 | */ | |
3908 | ||
be44eb28 MCC |
3909 | /* First determine real bandwidth (Hz) */ |
3910 | /* Also set delay for impulse noise cruncher */ | |
ab5060cd MCC |
3911 | /* |
3912 | * Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is | |
3913 | * changed by SC for fix for some 8K,1/8 guard but is restored by | |
3914 | * InitEC and ResetEC functions | |
3915 | */ | |
ed5452a2 MCC |
3916 | switch (state->props.bandwidth_hz) { |
3917 | case 0: | |
3918 | state->props.bandwidth_hz = 8000000; | |
3919 | /* fall though */ | |
3920 | case 8000000: | |
be44eb28 | 3921 | bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; |
ab5060cd MCC |
3922 | status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, |
3923 | 3052); | |
be44eb28 MCC |
3924 | if (status < 0) |
3925 | goto error; | |
3926 | /* cochannel protection for PAL 8 MHz */ | |
ab5060cd MCC |
3927 | status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, |
3928 | 7); | |
be44eb28 MCC |
3929 | if (status < 0) |
3930 | goto error; | |
ab5060cd MCC |
3931 | status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, |
3932 | 7); | |
be44eb28 MCC |
3933 | if (status < 0) |
3934 | goto error; | |
ab5060cd MCC |
3935 | status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, |
3936 | 7); | |
be44eb28 MCC |
3937 | if (status < 0) |
3938 | goto error; | |
ab5060cd MCC |
3939 | status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, |
3940 | 1); | |
be44eb28 MCC |
3941 | if (status < 0) |
3942 | goto error; | |
3943 | break; | |
ed5452a2 | 3944 | case 7000000: |
be44eb28 | 3945 | bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; |
ab5060cd MCC |
3946 | status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, |
3947 | 3491); | |
be44eb28 MCC |
3948 | if (status < 0) |
3949 | goto error; | |
3950 | /* cochannel protection for PAL 7 MHz */ | |
ab5060cd MCC |
3951 | status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, |
3952 | 8); | |
be44eb28 MCC |
3953 | if (status < 0) |
3954 | goto error; | |
ab5060cd MCC |
3955 | status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, |
3956 | 8); | |
be44eb28 MCC |
3957 | if (status < 0) |
3958 | goto error; | |
ab5060cd MCC |
3959 | status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, |
3960 | 4); | |
be44eb28 MCC |
3961 | if (status < 0) |
3962 | goto error; | |
ab5060cd MCC |
3963 | status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, |
3964 | 1); | |
be44eb28 MCC |
3965 | if (status < 0) |
3966 | goto error; | |
3967 | break; | |
ed5452a2 | 3968 | case 6000000: |
be44eb28 | 3969 | bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; |
ab5060cd MCC |
3970 | status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, |
3971 | 4073); | |
be44eb28 MCC |
3972 | if (status < 0) |
3973 | goto error; | |
3974 | /* cochannel protection for NTSC 6 MHz */ | |
ab5060cd MCC |
3975 | status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, |
3976 | 19); | |
be44eb28 MCC |
3977 | if (status < 0) |
3978 | goto error; | |
ab5060cd MCC |
3979 | status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, |
3980 | 19); | |
be44eb28 MCC |
3981 | if (status < 0) |
3982 | goto error; | |
ab5060cd MCC |
3983 | status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, |
3984 | 14); | |
be44eb28 MCC |
3985 | if (status < 0) |
3986 | goto error; | |
ab5060cd MCC |
3987 | status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, |
3988 | 1); | |
be44eb28 MCC |
3989 | if (status < 0) |
3990 | goto error; | |
3991 | break; | |
3992 | default: | |
3993 | status = -EINVAL; | |
3994 | goto error; | |
3995 | } | |
43dd07f7 | 3996 | |
cd7a67a4 | 3997 | if (iqm_rc_rate_ofs == 0) { |
be44eb28 MCC |
3998 | /* Now compute IQM_RC_RATE_OFS |
3999 | (((SysFreq/BandWidth)/2)/2) -1) * 2^23) | |
4000 | => | |
4001 | ((SysFreq / BandWidth) * (2^21)) - (2^23) | |
4002 | */ | |
4003 | /* (SysFreq / BandWidth) * (2^28) */ | |
ab5060cd MCC |
4004 | /* |
4005 | * assert (MAX(sysClk)/MIN(bandwidth) < 16) | |
4006 | * => assert(MAX(sysClk) < 16*MIN(bandwidth)) | |
4007 | * => assert(109714272 > 48000000) = true | |
4008 | * so Frac 28 can be used | |
4009 | */ | |
cd7a67a4 MCC |
4010 | iqm_rc_rate_ofs = Frac28a((u32) |
4011 | ((state->m_sys_clock_freq * | |
be44eb28 | 4012 | 1000) / 3), bandwidth); |
ab5060cd | 4013 | /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ |
cd7a67a4 MCC |
4014 | if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40) |
4015 | iqm_rc_rate_ofs += 0x80L; | |
4016 | iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7; | |
be44eb28 | 4017 | /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ |
cd7a67a4 | 4018 | iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23); |
be44eb28 | 4019 | } |
43dd07f7 | 4020 | |
cd7a67a4 | 4021 | iqm_rc_rate_ofs &= |
be44eb28 MCC |
4022 | ((((u32) IQM_RC_RATE_OFS_HI__M) << |
4023 | IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M); | |
cd7a67a4 | 4024 | status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs); |
be44eb28 MCC |
4025 | if (status < 0) |
4026 | goto error; | |
43dd07f7 | 4027 | |
be44eb28 | 4028 | /* Bandwidth setting done */ |
43dd07f7 | 4029 | |
ea90f011 | 4030 | #if 0 |
cd7a67a4 | 4031 | status = dvbt_set_frequency_shift(demod, channel, tuner_offset); |
be44eb28 MCC |
4032 | if (status < 0) |
4033 | goto error; | |
ea90f011 | 4034 | #endif |
ab5060cd MCC |
4035 | status = set_frequency_shifter(state, intermediate_freqk_hz, |
4036 | tuner_freq_offset, true); | |
be44eb28 MCC |
4037 | if (status < 0) |
4038 | goto error; | |
43dd07f7 | 4039 | |
ab5060cd | 4040 | /*== start SC, write channel settings to SC ==========================*/ |
43dd07f7 | 4041 | |
be44eb28 MCC |
4042 | /* Activate SCU to enable SCU commands */ |
4043 | status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); | |
4044 | if (status < 0) | |
4045 | goto error; | |
43dd07f7 | 4046 | |
be44eb28 MCC |
4047 | /* Enable SC after setting all other parameters */ |
4048 | status = write16(state, OFDM_SC_COMM_STATE__A, 0); | |
4049 | if (status < 0) | |
4050 | goto error; | |
4051 | status = write16(state, OFDM_SC_COMM_EXEC__A, 1); | |
4052 | if (status < 0) | |
4053 | goto error; | |
43dd07f7 | 4054 | |
43dd07f7 | 4055 | |
ab5060cd MCC |
4056 | status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM |
4057 | | SCU_RAM_COMMAND_CMD_DEMOD_START, | |
4058 | 0, NULL, 1, &cmd_result); | |
be44eb28 MCC |
4059 | if (status < 0) |
4060 | goto error; | |
4061 | ||
4062 | /* Write SC parameter registers, set all AUTO flags in operation mode */ | |
4063 | param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M | | |
4064 | OFDM_SC_RA_RAM_OP_AUTO_GUARD__M | | |
4065 | OFDM_SC_RA_RAM_OP_AUTO_CONST__M | | |
4066 | OFDM_SC_RA_RAM_OP_AUTO_HIER__M | | |
4067 | OFDM_SC_RA_RAM_OP_AUTO_RATE__M); | |
cd7a67a4 MCC |
4068 | status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, |
4069 | 0, transmission_params, param1, 0, 0, 0); | |
be44eb28 MCC |
4070 | if (status < 0) |
4071 | goto error; | |
43dd07f7 | 4072 | |
cd7a67a4 MCC |
4073 | if (!state->m_drxk_a3_rom_code) |
4074 | status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed); | |
be44eb28 MCC |
4075 | error: |
4076 | if (status < 0) | |
3a4398f5 | 4077 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
4078 | |
4079 | return status; | |
4080 | } | |
4081 | ||
4082 | ||
4083 | /*============================================================================*/ | |
4084 | ||
4085 | /** | |
39c1cb2b | 4086 | * \brief Retrieve lock status . |
43dd07f7 RM |
4087 | * \param demod Pointer to demodulator instance. |
4088 | * \param lockStat Pointer to lock status structure. | |
4089 | * \return DRXStatus_t. | |
4090 | * | |
4091 | */ | |
cd7a67a4 | 4092 | static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status) |
43dd07f7 | 4093 | { |
ebc7de22 OE |
4094 | int status; |
4095 | const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | | |
4096 | OFDM_SC_RA_RAM_LOCK_FEC__M); | |
4097 | const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); | |
4098 | const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M; | |
4099 | ||
cd7a67a4 MCC |
4100 | u16 sc_ra_ram_lock = 0; |
4101 | u16 sc_comm_exec = 0; | |
ebc7de22 | 4102 | |
2da67501 MCC |
4103 | dprintk(1, "\n"); |
4104 | ||
cd7a67a4 | 4105 | *p_lock_status = NOT_LOCKED; |
ebc7de22 OE |
4106 | /* driver 0.9.0 */ |
4107 | /* Check if SC is running */ | |
cd7a67a4 | 4108 | status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec); |
be44eb28 MCC |
4109 | if (status < 0) |
4110 | goto end; | |
cd7a67a4 | 4111 | if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP) |
be44eb28 | 4112 | goto end; |
ebc7de22 | 4113 | |
cd7a67a4 | 4114 | status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock); |
be44eb28 MCC |
4115 | if (status < 0) |
4116 | goto end; | |
ebc7de22 | 4117 | |
cd7a67a4 MCC |
4118 | if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask) |
4119 | *p_lock_status = MPEG_LOCK; | |
4120 | else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask) | |
4121 | *p_lock_status = FEC_LOCK; | |
4122 | else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask) | |
4123 | *p_lock_status = DEMOD_LOCK; | |
4124 | else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) | |
4125 | *p_lock_status = NEVER_LOCK; | |
be44eb28 MCC |
4126 | end: |
4127 | if (status < 0) | |
3a4398f5 | 4128 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 OE |
4129 | |
4130 | return status; | |
43dd07f7 RM |
4131 | } |
4132 | ||
cd7a67a4 | 4133 | static int power_up_qam(struct drxk_state *state) |
43dd07f7 | 4134 | { |
cd7a67a4 | 4135 | enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; |
be44eb28 | 4136 | int status; |
43dd07f7 | 4137 | |
2da67501 | 4138 | dprintk(1, "\n"); |
cd7a67a4 | 4139 | status = ctrl_power_mode(state, &power_mode); |
be44eb28 | 4140 | if (status < 0) |
3a4398f5 | 4141 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 | 4142 | |
ebc7de22 | 4143 | return status; |
43dd07f7 RM |
4144 | } |
4145 | ||
4146 | ||
ebc7de22 | 4147 | /** Power Down QAM */ |
cd7a67a4 | 4148 | static int power_down_qam(struct drxk_state *state) |
43dd07f7 | 4149 | { |
ebc7de22 | 4150 | u16 data = 0; |
cd7a67a4 | 4151 | u16 cmd_result; |
ebc7de22 OE |
4152 | int status = 0; |
4153 | ||
2da67501 | 4154 | dprintk(1, "\n"); |
be44eb28 MCC |
4155 | status = read16(state, SCU_COMM_EXEC__A, &data); |
4156 | if (status < 0) | |
4157 | goto error; | |
4158 | if (data == SCU_COMM_EXEC_ACTIVE) { | |
4159 | /* | |
4160 | STOP demodulator | |
4161 | QAM and HW blocks | |
4162 | */ | |
4163 | /* stop all comstate->m_exec */ | |
4164 | status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); | |
ea90f011 | 4165 | if (status < 0) |
be44eb28 | 4166 | goto error; |
ab5060cd MCC |
4167 | status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM |
4168 | | SCU_RAM_COMMAND_CMD_DEMOD_STOP, | |
4169 | 0, NULL, 1, &cmd_result); | |
ea90f011 | 4170 | if (status < 0) |
be44eb28 MCC |
4171 | goto error; |
4172 | } | |
4173 | /* powerdown AFE */ | |
cd7a67a4 | 4174 | status = set_iqm_af(state, false); |
be44eb28 MCC |
4175 | |
4176 | error: | |
4177 | if (status < 0) | |
3a4398f5 | 4178 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 OE |
4179 | |
4180 | return status; | |
43dd07f7 | 4181 | } |
ebc7de22 | 4182 | |
43dd07f7 RM |
4183 | /*============================================================================*/ |
4184 | ||
4185 | /** | |
4186 | * \brief Setup of the QAM Measurement intervals for signal quality | |
4187 | * \param demod instance of demod. | |
ed5452a2 | 4188 | * \param modulation current modulation. |
43dd07f7 RM |
4189 | * \return DRXStatus_t. |
4190 | * | |
4191 | * NOTE: | |
4192 | * Take into account that for certain settings the errorcounters can overflow. | |
4193 | * The implementation does not check this. | |
4194 | * | |
4195 | */ | |
cd7a67a4 MCC |
4196 | static int set_qam_measurement(struct drxk_state *state, |
4197 | enum e_drxk_constellation modulation, | |
4198 | u32 symbol_rate) | |
43dd07f7 | 4199 | { |
cd7a67a4 MCC |
4200 | u32 fec_bits_desired = 0; /* BER accounting period */ |
4201 | u32 fec_rs_period_total = 0; /* Total period */ | |
4202 | u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ | |
4203 | u16 fec_rs_period = 0; /* Value for corresponding I2C register */ | |
43dd07f7 RM |
4204 | int status = 0; |
4205 | ||
2da67501 | 4206 | dprintk(1, "\n"); |
43dd07f7 | 4207 | |
cd7a67a4 MCC |
4208 | fec_rs_prescale = 1; |
4209 | /* fec_bits_desired = symbol_rate [kHz] * | |
be44eb28 | 4210 | FrameLenght [ms] * |
ed5452a2 | 4211 | (modulation + 1) * |
be44eb28 MCC |
4212 | SyncLoss (== 1) * |
4213 | ViterbiLoss (==1) | |
4214 | */ | |
ed5452a2 | 4215 | switch (modulation) { |
be44eb28 | 4216 | case DRX_CONSTELLATION_QAM16: |
cd7a67a4 | 4217 | fec_bits_desired = 4 * symbol_rate; |
be44eb28 MCC |
4218 | break; |
4219 | case DRX_CONSTELLATION_QAM32: | |
cd7a67a4 | 4220 | fec_bits_desired = 5 * symbol_rate; |
be44eb28 MCC |
4221 | break; |
4222 | case DRX_CONSTELLATION_QAM64: | |
cd7a67a4 | 4223 | fec_bits_desired = 6 * symbol_rate; |
be44eb28 MCC |
4224 | break; |
4225 | case DRX_CONSTELLATION_QAM128: | |
cd7a67a4 | 4226 | fec_bits_desired = 7 * symbol_rate; |
be44eb28 MCC |
4227 | break; |
4228 | case DRX_CONSTELLATION_QAM256: | |
cd7a67a4 | 4229 | fec_bits_desired = 8 * symbol_rate; |
be44eb28 MCC |
4230 | break; |
4231 | default: | |
4232 | status = -EINVAL; | |
4233 | } | |
4234 | if (status < 0) | |
4235 | goto error; | |
43dd07f7 | 4236 | |
ab5060cd | 4237 | fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */ |
cd7a67a4 | 4238 | fec_bits_desired *= 500; /* meas. period [ms] */ |
43dd07f7 | 4239 | |
be44eb28 | 4240 | /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ |
cd7a67a4 MCC |
4241 | /* fec_rs_period_total = fec_bits_desired / 1632 */ |
4242 | fec_rs_period_total = (fec_bits_desired / 1632UL) + 1; /* roughly ceil */ | |
43dd07f7 | 4243 | |
cd7a67a4 MCC |
4244 | /* fec_rs_period_total = fec_rs_prescale * fec_rs_period */ |
4245 | fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16); | |
4246 | if (fec_rs_prescale == 0) { | |
be44eb28 MCC |
4247 | /* Divide by zero (though impossible) */ |
4248 | status = -EINVAL; | |
ea90f011 | 4249 | if (status < 0) |
be44eb28 MCC |
4250 | goto error; |
4251 | } | |
cd7a67a4 MCC |
4252 | fec_rs_period = |
4253 | ((u16) fec_rs_period_total + | |
4254 | (fec_rs_prescale >> 1)) / fec_rs_prescale; | |
43dd07f7 | 4255 | |
be44eb28 | 4256 | /* write corresponding registers */ |
cd7a67a4 | 4257 | status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period); |
ebc7de22 | 4258 | if (status < 0) |
be44eb28 | 4259 | goto error; |
ab5060cd MCC |
4260 | status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, |
4261 | fec_rs_prescale); | |
be44eb28 MCC |
4262 | if (status < 0) |
4263 | goto error; | |
cd7a67a4 | 4264 | status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period); |
be44eb28 MCC |
4265 | error: |
4266 | if (status < 0) | |
3a4398f5 | 4267 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
4268 | return status; |
4269 | } | |
4270 | ||
cd7a67a4 | 4271 | static int set_qam16(struct drxk_state *state) |
43dd07f7 | 4272 | { |
ebc7de22 OE |
4273 | int status = 0; |
4274 | ||
2da67501 | 4275 | dprintk(1, "\n"); |
be44eb28 MCC |
4276 | /* QAM Equalizer Setup */ |
4277 | /* Equalizer */ | |
4278 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517); | |
4279 | if (status < 0) | |
4280 | goto error; | |
4281 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517); | |
4282 | if (status < 0) | |
4283 | goto error; | |
4284 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517); | |
4285 | if (status < 0) | |
4286 | goto error; | |
4287 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517); | |
4288 | if (status < 0) | |
4289 | goto error; | |
4290 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517); | |
4291 | if (status < 0) | |
4292 | goto error; | |
4293 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517); | |
4294 | if (status < 0) | |
4295 | goto error; | |
4296 | /* Decision Feedback Equalizer */ | |
4297 | status = write16(state, QAM_DQ_QUAL_FUN0__A, 2); | |
4298 | if (status < 0) | |
4299 | goto error; | |
4300 | status = write16(state, QAM_DQ_QUAL_FUN1__A, 2); | |
4301 | if (status < 0) | |
4302 | goto error; | |
4303 | status = write16(state, QAM_DQ_QUAL_FUN2__A, 2); | |
4304 | if (status < 0) | |
4305 | goto error; | |
4306 | status = write16(state, QAM_DQ_QUAL_FUN3__A, 2); | |
4307 | if (status < 0) | |
4308 | goto error; | |
4309 | status = write16(state, QAM_DQ_QUAL_FUN4__A, 2); | |
4310 | if (status < 0) | |
4311 | goto error; | |
4312 | status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); | |
4313 | if (status < 0) | |
4314 | goto error; | |
ebc7de22 | 4315 | |
be44eb28 MCC |
4316 | status = write16(state, QAM_SY_SYNC_HWM__A, 5); |
4317 | if (status < 0) | |
4318 | goto error; | |
4319 | status = write16(state, QAM_SY_SYNC_AWM__A, 4); | |
4320 | if (status < 0) | |
4321 | goto error; | |
4322 | status = write16(state, QAM_SY_SYNC_LWM__A, 3); | |
4323 | if (status < 0) | |
4324 | goto error; | |
ebc7de22 | 4325 | |
be44eb28 | 4326 | /* QAM Slicer Settings */ |
ab5060cd MCC |
4327 | status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, |
4328 | DRXK_QAM_SL_SIG_POWER_QAM16); | |
be44eb28 MCC |
4329 | if (status < 0) |
4330 | goto error; | |
ebc7de22 | 4331 | |
be44eb28 MCC |
4332 | /* QAM Loop Controller Coeficients */ |
4333 | status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); | |
4334 | if (status < 0) | |
4335 | goto error; | |
4336 | status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); | |
4337 | if (status < 0) | |
4338 | goto error; | |
4339 | status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); | |
4340 | if (status < 0) | |
4341 | goto error; | |
4342 | status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); | |
4343 | if (status < 0) | |
4344 | goto error; | |
4345 | status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); | |
4346 | if (status < 0) | |
4347 | goto error; | |
4348 | status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); | |
4349 | if (status < 0) | |
4350 | goto error; | |
4351 | status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); | |
4352 | if (status < 0) | |
4353 | goto error; | |
4354 | status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); | |
4355 | if (status < 0) | |
4356 | goto error; | |
ea90f011 | 4357 | |
be44eb28 MCC |
4358 | status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); |
4359 | if (status < 0) | |
4360 | goto error; | |
4361 | status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); | |
4362 | if (status < 0) | |
4363 | goto error; | |
4364 | status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); | |
4365 | if (status < 0) | |
4366 | goto error; | |
4367 | status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); | |
4368 | if (status < 0) | |
4369 | goto error; | |
4370 | status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); | |
4371 | if (status < 0) | |
4372 | goto error; | |
4373 | status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); | |
4374 | if (status < 0) | |
4375 | goto error; | |
4376 | status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); | |
4377 | if (status < 0) | |
4378 | goto error; | |
4379 | status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); | |
4380 | if (status < 0) | |
4381 | goto error; | |
4382 | status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32); | |
4383 | if (status < 0) | |
4384 | goto error; | |
4385 | status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); | |
4386 | if (status < 0) | |
4387 | goto error; | |
4388 | status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); | |
4389 | if (status < 0) | |
4390 | goto error; | |
4391 | status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); | |
4392 | if (status < 0) | |
4393 | goto error; | |
ebc7de22 OE |
4394 | |
4395 | ||
be44eb28 | 4396 | /* QAM State Machine (FSM) Thresholds */ |
ebc7de22 | 4397 | |
be44eb28 MCC |
4398 | status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140); |
4399 | if (status < 0) | |
4400 | goto error; | |
4401 | status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); | |
4402 | if (status < 0) | |
4403 | goto error; | |
4404 | status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95); | |
4405 | if (status < 0) | |
4406 | goto error; | |
4407 | status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120); | |
4408 | if (status < 0) | |
4409 | goto error; | |
4410 | status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230); | |
4411 | if (status < 0) | |
4412 | goto error; | |
4413 | status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105); | |
4414 | if (status < 0) | |
4415 | goto error; | |
ebc7de22 | 4416 | |
be44eb28 MCC |
4417 | status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); |
4418 | if (status < 0) | |
4419 | goto error; | |
4420 | status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); | |
4421 | if (status < 0) | |
4422 | goto error; | |
4423 | status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24); | |
4424 | if (status < 0) | |
4425 | goto error; | |
ebc7de22 OE |
4426 | |
4427 | ||
be44eb28 | 4428 | /* QAM FSM Tracking Parameters */ |
ebc7de22 | 4429 | |
be44eb28 MCC |
4430 | status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16); |
4431 | if (status < 0) | |
4432 | goto error; | |
4433 | status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220); | |
4434 | if (status < 0) | |
4435 | goto error; | |
4436 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25); | |
4437 | if (status < 0) | |
4438 | goto error; | |
4439 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6); | |
4440 | if (status < 0) | |
4441 | goto error; | |
4442 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); | |
4443 | if (status < 0) | |
4444 | goto error; | |
4445 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); | |
4446 | if (status < 0) | |
4447 | goto error; | |
4448 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); | |
4449 | if (status < 0) | |
4450 | goto error; | |
ebc7de22 | 4451 | |
be44eb28 MCC |
4452 | error: |
4453 | if (status < 0) | |
3a4398f5 | 4454 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 4455 | return status; |
43dd07f7 RM |
4456 | } |
4457 | ||
4458 | /*============================================================================*/ | |
4459 | ||
4460 | /** | |
4461 | * \brief QAM32 specific setup | |
4462 | * \param demod instance of demod. | |
4463 | * \return DRXStatus_t. | |
4464 | */ | |
cd7a67a4 | 4465 | static int set_qam32(struct drxk_state *state) |
43dd07f7 | 4466 | { |
ebc7de22 OE |
4467 | int status = 0; |
4468 | ||
2da67501 | 4469 | dprintk(1, "\n"); |
ebc7de22 | 4470 | |
be44eb28 MCC |
4471 | /* QAM Equalizer Setup */ |
4472 | /* Equalizer */ | |
4473 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707); | |
4474 | if (status < 0) | |
4475 | goto error; | |
4476 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707); | |
4477 | if (status < 0) | |
4478 | goto error; | |
4479 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707); | |
4480 | if (status < 0) | |
4481 | goto error; | |
4482 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707); | |
4483 | if (status < 0) | |
4484 | goto error; | |
4485 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707); | |
4486 | if (status < 0) | |
4487 | goto error; | |
4488 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707); | |
4489 | if (status < 0) | |
4490 | goto error; | |
ebc7de22 | 4491 | |
be44eb28 MCC |
4492 | /* Decision Feedback Equalizer */ |
4493 | status = write16(state, QAM_DQ_QUAL_FUN0__A, 3); | |
4494 | if (status < 0) | |
4495 | goto error; | |
4496 | status = write16(state, QAM_DQ_QUAL_FUN1__A, 3); | |
4497 | if (status < 0) | |
4498 | goto error; | |
4499 | status = write16(state, QAM_DQ_QUAL_FUN2__A, 3); | |
4500 | if (status < 0) | |
4501 | goto error; | |
4502 | status = write16(state, QAM_DQ_QUAL_FUN3__A, 3); | |
4503 | if (status < 0) | |
4504 | goto error; | |
4505 | status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); | |
4506 | if (status < 0) | |
4507 | goto error; | |
4508 | status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); | |
4509 | if (status < 0) | |
4510 | goto error; | |
ebc7de22 | 4511 | |
be44eb28 MCC |
4512 | status = write16(state, QAM_SY_SYNC_HWM__A, 6); |
4513 | if (status < 0) | |
4514 | goto error; | |
4515 | status = write16(state, QAM_SY_SYNC_AWM__A, 5); | |
4516 | if (status < 0) | |
4517 | goto error; | |
4518 | status = write16(state, QAM_SY_SYNC_LWM__A, 3); | |
4519 | if (status < 0) | |
4520 | goto error; | |
ebc7de22 | 4521 | |
be44eb28 | 4522 | /* QAM Slicer Settings */ |
ebc7de22 | 4523 | |
ab5060cd MCC |
4524 | status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, |
4525 | DRXK_QAM_SL_SIG_POWER_QAM32); | |
be44eb28 MCC |
4526 | if (status < 0) |
4527 | goto error; | |
ebc7de22 | 4528 | |
ebc7de22 | 4529 | |
be44eb28 | 4530 | /* QAM Loop Controller Coeficients */ |
ea90f011 | 4531 | |
be44eb28 MCC |
4532 | status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); |
4533 | if (status < 0) | |
4534 | goto error; | |
4535 | status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); | |
4536 | if (status < 0) | |
4537 | goto error; | |
4538 | status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); | |
4539 | if (status < 0) | |
4540 | goto error; | |
4541 | status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); | |
4542 | if (status < 0) | |
4543 | goto error; | |
4544 | status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); | |
4545 | if (status < 0) | |
4546 | goto error; | |
4547 | status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); | |
4548 | if (status < 0) | |
4549 | goto error; | |
4550 | status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); | |
4551 | if (status < 0) | |
4552 | goto error; | |
4553 | status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); | |
4554 | if (status < 0) | |
4555 | goto error; | |
ebc7de22 | 4556 | |
be44eb28 MCC |
4557 | status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); |
4558 | if (status < 0) | |
4559 | goto error; | |
4560 | status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); | |
4561 | if (status < 0) | |
4562 | goto error; | |
4563 | status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); | |
4564 | if (status < 0) | |
4565 | goto error; | |
4566 | status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); | |
4567 | if (status < 0) | |
4568 | goto error; | |
4569 | status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); | |
4570 | if (status < 0) | |
4571 | goto error; | |
4572 | status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); | |
4573 | if (status < 0) | |
4574 | goto error; | |
4575 | status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); | |
4576 | if (status < 0) | |
4577 | goto error; | |
4578 | status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); | |
4579 | if (status < 0) | |
4580 | goto error; | |
4581 | status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16); | |
4582 | if (status < 0) | |
4583 | goto error; | |
4584 | status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); | |
4585 | if (status < 0) | |
4586 | goto error; | |
4587 | status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); | |
4588 | if (status < 0) | |
4589 | goto error; | |
4590 | status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); | |
4591 | if (status < 0) | |
4592 | goto error; | |
ebc7de22 | 4593 | |
ebc7de22 | 4594 | |
be44eb28 | 4595 | /* QAM State Machine (FSM) Thresholds */ |
ebc7de22 | 4596 | |
be44eb28 MCC |
4597 | status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90); |
4598 | if (status < 0) | |
4599 | goto error; | |
4600 | status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); | |
4601 | if (status < 0) | |
4602 | goto error; | |
4603 | status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); | |
4604 | if (status < 0) | |
4605 | goto error; | |
4606 | status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); | |
4607 | if (status < 0) | |
4608 | goto error; | |
4609 | status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170); | |
4610 | if (status < 0) | |
4611 | goto error; | |
4612 | status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); | |
4613 | if (status < 0) | |
4614 | goto error; | |
ebc7de22 | 4615 | |
be44eb28 MCC |
4616 | status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); |
4617 | if (status < 0) | |
4618 | goto error; | |
4619 | status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); | |
4620 | if (status < 0) | |
4621 | goto error; | |
4622 | status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10); | |
4623 | if (status < 0) | |
4624 | goto error; | |
ebc7de22 | 4625 | |
ebc7de22 | 4626 | |
be44eb28 | 4627 | /* QAM FSM Tracking Parameters */ |
ebc7de22 | 4628 | |
be44eb28 MCC |
4629 | status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); |
4630 | if (status < 0) | |
4631 | goto error; | |
4632 | status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140); | |
4633 | if (status < 0) | |
4634 | goto error; | |
4635 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); | |
4636 | if (status < 0) | |
4637 | goto error; | |
4638 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); | |
4639 | if (status < 0) | |
4640 | goto error; | |
4641 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); | |
4642 | if (status < 0) | |
4643 | goto error; | |
4644 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); | |
4645 | if (status < 0) | |
4646 | goto error; | |
4647 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); | |
4648 | error: | |
4649 | if (status < 0) | |
3a4398f5 | 4650 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 4651 | return status; |
43dd07f7 RM |
4652 | } |
4653 | ||
4654 | /*============================================================================*/ | |
4655 | ||
4656 | /** | |
4657 | * \brief QAM64 specific setup | |
4658 | * \param demod instance of demod. | |
4659 | * \return DRXStatus_t. | |
4660 | */ | |
cd7a67a4 | 4661 | static int set_qam64(struct drxk_state *state) |
43dd07f7 | 4662 | { |
ebc7de22 OE |
4663 | int status = 0; |
4664 | ||
2da67501 | 4665 | dprintk(1, "\n"); |
be44eb28 MCC |
4666 | /* QAM Equalizer Setup */ |
4667 | /* Equalizer */ | |
4668 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336); | |
4669 | if (status < 0) | |
4670 | goto error; | |
4671 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618); | |
4672 | if (status < 0) | |
4673 | goto error; | |
4674 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988); | |
4675 | if (status < 0) | |
4676 | goto error; | |
4677 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809); | |
4678 | if (status < 0) | |
4679 | goto error; | |
4680 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809); | |
4681 | if (status < 0) | |
4682 | goto error; | |
4683 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609); | |
4684 | if (status < 0) | |
4685 | goto error; | |
ebc7de22 | 4686 | |
be44eb28 MCC |
4687 | /* Decision Feedback Equalizer */ |
4688 | status = write16(state, QAM_DQ_QUAL_FUN0__A, 4); | |
4689 | if (status < 0) | |
4690 | goto error; | |
4691 | status = write16(state, QAM_DQ_QUAL_FUN1__A, 4); | |
4692 | if (status < 0) | |
4693 | goto error; | |
4694 | status = write16(state, QAM_DQ_QUAL_FUN2__A, 4); | |
4695 | if (status < 0) | |
4696 | goto error; | |
4697 | status = write16(state, QAM_DQ_QUAL_FUN3__A, 4); | |
4698 | if (status < 0) | |
4699 | goto error; | |
4700 | status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); | |
4701 | if (status < 0) | |
4702 | goto error; | |
4703 | status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); | |
4704 | if (status < 0) | |
4705 | goto error; | |
ebc7de22 | 4706 | |
be44eb28 MCC |
4707 | status = write16(state, QAM_SY_SYNC_HWM__A, 5); |
4708 | if (status < 0) | |
4709 | goto error; | |
4710 | status = write16(state, QAM_SY_SYNC_AWM__A, 4); | |
4711 | if (status < 0) | |
4712 | goto error; | |
4713 | status = write16(state, QAM_SY_SYNC_LWM__A, 3); | |
4714 | if (status < 0) | |
4715 | goto error; | |
ebc7de22 | 4716 | |
be44eb28 | 4717 | /* QAM Slicer Settings */ |
ab5060cd MCC |
4718 | status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, |
4719 | DRXK_QAM_SL_SIG_POWER_QAM64); | |
be44eb28 MCC |
4720 | if (status < 0) |
4721 | goto error; | |
ebc7de22 OE |
4722 | |
4723 | ||
be44eb28 | 4724 | /* QAM Loop Controller Coeficients */ |
ebc7de22 | 4725 | |
be44eb28 MCC |
4726 | status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); |
4727 | if (status < 0) | |
4728 | goto error; | |
4729 | status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); | |
4730 | if (status < 0) | |
4731 | goto error; | |
4732 | status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); | |
4733 | if (status < 0) | |
4734 | goto error; | |
4735 | status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); | |
4736 | if (status < 0) | |
4737 | goto error; | |
4738 | status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); | |
4739 | if (status < 0) | |
4740 | goto error; | |
4741 | status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); | |
4742 | if (status < 0) | |
4743 | goto error; | |
4744 | status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); | |
4745 | if (status < 0) | |
4746 | goto error; | |
4747 | status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); | |
4748 | if (status < 0) | |
4749 | goto error; | |
ea90f011 | 4750 | |
be44eb28 MCC |
4751 | status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); |
4752 | if (status < 0) | |
4753 | goto error; | |
4754 | status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); | |
4755 | if (status < 0) | |
4756 | goto error; | |
4757 | status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100); | |
4758 | if (status < 0) | |
4759 | goto error; | |
4760 | status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); | |
4761 | if (status < 0) | |
4762 | goto error; | |
4763 | status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30); | |
4764 | if (status < 0) | |
4765 | goto error; | |
4766 | status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); | |
4767 | if (status < 0) | |
4768 | goto error; | |
4769 | status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); | |
4770 | if (status < 0) | |
4771 | goto error; | |
4772 | status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); | |
4773 | if (status < 0) | |
4774 | goto error; | |
4775 | status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); | |
4776 | if (status < 0) | |
4777 | goto error; | |
4778 | status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); | |
4779 | if (status < 0) | |
4780 | goto error; | |
4781 | status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); | |
4782 | if (status < 0) | |
4783 | goto error; | |
4784 | status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); | |
4785 | if (status < 0) | |
4786 | goto error; | |
ebc7de22 OE |
4787 | |
4788 | ||
be44eb28 | 4789 | /* QAM State Machine (FSM) Thresholds */ |
ebc7de22 | 4790 | |
be44eb28 MCC |
4791 | status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100); |
4792 | if (status < 0) | |
4793 | goto error; | |
4794 | status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); | |
4795 | if (status < 0) | |
4796 | goto error; | |
4797 | status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); | |
4798 | if (status < 0) | |
4799 | goto error; | |
4800 | status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110); | |
4801 | if (status < 0) | |
4802 | goto error; | |
4803 | status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200); | |
4804 | if (status < 0) | |
4805 | goto error; | |
4806 | status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95); | |
4807 | if (status < 0) | |
4808 | goto error; | |
ebc7de22 | 4809 | |
be44eb28 MCC |
4810 | status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); |
4811 | if (status < 0) | |
4812 | goto error; | |
4813 | status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); | |
4814 | if (status < 0) | |
4815 | goto error; | |
4816 | status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15); | |
4817 | if (status < 0) | |
4818 | goto error; | |
ebc7de22 OE |
4819 | |
4820 | ||
be44eb28 | 4821 | /* QAM FSM Tracking Parameters */ |
ebc7de22 | 4822 | |
be44eb28 MCC |
4823 | status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); |
4824 | if (status < 0) | |
4825 | goto error; | |
4826 | status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141); | |
4827 | if (status < 0) | |
4828 | goto error; | |
4829 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7); | |
4830 | if (status < 0) | |
4831 | goto error; | |
4832 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0); | |
4833 | if (status < 0) | |
4834 | goto error; | |
4835 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); | |
4836 | if (status < 0) | |
4837 | goto error; | |
4838 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); | |
4839 | if (status < 0) | |
4840 | goto error; | |
4841 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); | |
4842 | error: | |
4843 | if (status < 0) | |
3a4398f5 | 4844 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 OE |
4845 | |
4846 | return status; | |
43dd07f7 RM |
4847 | } |
4848 | ||
4849 | /*============================================================================*/ | |
4850 | ||
4851 | /** | |
4852 | * \brief QAM128 specific setup | |
4853 | * \param demod: instance of demod. | |
4854 | * \return DRXStatus_t. | |
4855 | */ | |
cd7a67a4 | 4856 | static int set_qam128(struct drxk_state *state) |
43dd07f7 | 4857 | { |
ebc7de22 OE |
4858 | int status = 0; |
4859 | ||
2da67501 | 4860 | dprintk(1, "\n"); |
be44eb28 MCC |
4861 | /* QAM Equalizer Setup */ |
4862 | /* Equalizer */ | |
4863 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564); | |
4864 | if (status < 0) | |
4865 | goto error; | |
4866 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598); | |
4867 | if (status < 0) | |
4868 | goto error; | |
4869 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394); | |
4870 | if (status < 0) | |
4871 | goto error; | |
4872 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409); | |
4873 | if (status < 0) | |
4874 | goto error; | |
4875 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656); | |
4876 | if (status < 0) | |
4877 | goto error; | |
4878 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238); | |
4879 | if (status < 0) | |
4880 | goto error; | |
ebc7de22 | 4881 | |
be44eb28 MCC |
4882 | /* Decision Feedback Equalizer */ |
4883 | status = write16(state, QAM_DQ_QUAL_FUN0__A, 6); | |
4884 | if (status < 0) | |
4885 | goto error; | |
4886 | status = write16(state, QAM_DQ_QUAL_FUN1__A, 6); | |
4887 | if (status < 0) | |
4888 | goto error; | |
4889 | status = write16(state, QAM_DQ_QUAL_FUN2__A, 6); | |
4890 | if (status < 0) | |
4891 | goto error; | |
4892 | status = write16(state, QAM_DQ_QUAL_FUN3__A, 6); | |
4893 | if (status < 0) | |
4894 | goto error; | |
4895 | status = write16(state, QAM_DQ_QUAL_FUN4__A, 5); | |
4896 | if (status < 0) | |
4897 | goto error; | |
4898 | status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); | |
4899 | if (status < 0) | |
4900 | goto error; | |
ebc7de22 | 4901 | |
be44eb28 MCC |
4902 | status = write16(state, QAM_SY_SYNC_HWM__A, 6); |
4903 | if (status < 0) | |
4904 | goto error; | |
4905 | status = write16(state, QAM_SY_SYNC_AWM__A, 5); | |
4906 | if (status < 0) | |
4907 | goto error; | |
4908 | status = write16(state, QAM_SY_SYNC_LWM__A, 3); | |
4909 | if (status < 0) | |
4910 | goto error; | |
ebc7de22 | 4911 | |
ebc7de22 | 4912 | |
be44eb28 | 4913 | /* QAM Slicer Settings */ |
ebc7de22 | 4914 | |
ab5060cd MCC |
4915 | status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, |
4916 | DRXK_QAM_SL_SIG_POWER_QAM128); | |
be44eb28 MCC |
4917 | if (status < 0) |
4918 | goto error; | |
ebc7de22 | 4919 | |
ebc7de22 | 4920 | |
be44eb28 | 4921 | /* QAM Loop Controller Coeficients */ |
ea90f011 | 4922 | |
be44eb28 MCC |
4923 | status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); |
4924 | if (status < 0) | |
4925 | goto error; | |
4926 | status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); | |
4927 | if (status < 0) | |
4928 | goto error; | |
4929 | status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); | |
4930 | if (status < 0) | |
4931 | goto error; | |
4932 | status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); | |
4933 | if (status < 0) | |
4934 | goto error; | |
4935 | status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); | |
4936 | if (status < 0) | |
4937 | goto error; | |
4938 | status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); | |
4939 | if (status < 0) | |
4940 | goto error; | |
4941 | status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); | |
4942 | if (status < 0) | |
4943 | goto error; | |
4944 | status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); | |
4945 | if (status < 0) | |
4946 | goto error; | |
4947 | ||
4948 | status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); | |
4949 | if (status < 0) | |
4950 | goto error; | |
4951 | status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); | |
4952 | if (status < 0) | |
4953 | goto error; | |
4954 | status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120); | |
4955 | if (status < 0) | |
4956 | goto error; | |
4957 | status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); | |
4958 | if (status < 0) | |
4959 | goto error; | |
4960 | status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40); | |
4961 | if (status < 0) | |
4962 | goto error; | |
4963 | status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60); | |
4964 | if (status < 0) | |
4965 | goto error; | |
4966 | status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); | |
4967 | if (status < 0) | |
4968 | goto error; | |
4969 | status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); | |
4970 | if (status < 0) | |
4971 | goto error; | |
4972 | status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64); | |
4973 | if (status < 0) | |
4974 | goto error; | |
4975 | status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); | |
4976 | if (status < 0) | |
4977 | goto error; | |
4978 | status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); | |
4979 | if (status < 0) | |
4980 | goto error; | |
4981 | status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); | |
4982 | if (status < 0) | |
4983 | goto error; | |
ebc7de22 OE |
4984 | |
4985 | ||
be44eb28 | 4986 | /* QAM State Machine (FSM) Thresholds */ |
ebc7de22 | 4987 | |
be44eb28 MCC |
4988 | status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); |
4989 | if (status < 0) | |
4990 | goto error; | |
4991 | status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); | |
4992 | if (status < 0) | |
4993 | goto error; | |
4994 | status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); | |
4995 | if (status < 0) | |
4996 | goto error; | |
4997 | status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); | |
4998 | if (status < 0) | |
4999 | goto error; | |
5000 | status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140); | |
5001 | if (status < 0) | |
5002 | goto error; | |
5003 | status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); | |
5004 | if (status < 0) | |
5005 | goto error; | |
ebc7de22 | 5006 | |
be44eb28 MCC |
5007 | status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); |
5008 | if (status < 0) | |
5009 | goto error; | |
5010 | status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5); | |
5011 | if (status < 0) | |
5012 | goto error; | |
ebc7de22 | 5013 | |
be44eb28 MCC |
5014 | status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); |
5015 | if (status < 0) | |
5016 | goto error; | |
ebc7de22 | 5017 | |
be44eb28 | 5018 | /* QAM FSM Tracking Parameters */ |
ebc7de22 | 5019 | |
be44eb28 MCC |
5020 | status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); |
5021 | if (status < 0) | |
5022 | goto error; | |
5023 | status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65); | |
5024 | if (status < 0) | |
5025 | goto error; | |
5026 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5); | |
5027 | if (status < 0) | |
5028 | goto error; | |
5029 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3); | |
5030 | if (status < 0) | |
5031 | goto error; | |
5032 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); | |
5033 | if (status < 0) | |
5034 | goto error; | |
5035 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); | |
5036 | if (status < 0) | |
5037 | goto error; | |
5038 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); | |
5039 | error: | |
5040 | if (status < 0) | |
3a4398f5 | 5041 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 OE |
5042 | |
5043 | return status; | |
43dd07f7 RM |
5044 | } |
5045 | ||
5046 | /*============================================================================*/ | |
5047 | ||
5048 | /** | |
5049 | * \brief QAM256 specific setup | |
5050 | * \param demod: instance of demod. | |
5051 | * \return DRXStatus_t. | |
5052 | */ | |
cd7a67a4 | 5053 | static int set_qam256(struct drxk_state *state) |
43dd07f7 | 5054 | { |
ebc7de22 OE |
5055 | int status = 0; |
5056 | ||
2da67501 | 5057 | dprintk(1, "\n"); |
be44eb28 MCC |
5058 | /* QAM Equalizer Setup */ |
5059 | /* Equalizer */ | |
5060 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502); | |
5061 | if (status < 0) | |
5062 | goto error; | |
5063 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084); | |
5064 | if (status < 0) | |
5065 | goto error; | |
5066 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543); | |
5067 | if (status < 0) | |
5068 | goto error; | |
5069 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931); | |
5070 | if (status < 0) | |
5071 | goto error; | |
5072 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629); | |
5073 | if (status < 0) | |
5074 | goto error; | |
5075 | status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385); | |
5076 | if (status < 0) | |
5077 | goto error; | |
ebc7de22 | 5078 | |
be44eb28 MCC |
5079 | /* Decision Feedback Equalizer */ |
5080 | status = write16(state, QAM_DQ_QUAL_FUN0__A, 8); | |
5081 | if (status < 0) | |
5082 | goto error; | |
5083 | status = write16(state, QAM_DQ_QUAL_FUN1__A, 8); | |
5084 | if (status < 0) | |
5085 | goto error; | |
5086 | status = write16(state, QAM_DQ_QUAL_FUN2__A, 8); | |
5087 | if (status < 0) | |
5088 | goto error; | |
5089 | status = write16(state, QAM_DQ_QUAL_FUN3__A, 8); | |
5090 | if (status < 0) | |
5091 | goto error; | |
5092 | status = write16(state, QAM_DQ_QUAL_FUN4__A, 6); | |
5093 | if (status < 0) | |
5094 | goto error; | |
5095 | status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); | |
5096 | if (status < 0) | |
5097 | goto error; | |
ebc7de22 | 5098 | |
be44eb28 MCC |
5099 | status = write16(state, QAM_SY_SYNC_HWM__A, 5); |
5100 | if (status < 0) | |
5101 | goto error; | |
5102 | status = write16(state, QAM_SY_SYNC_AWM__A, 4); | |
5103 | if (status < 0) | |
5104 | goto error; | |
5105 | status = write16(state, QAM_SY_SYNC_LWM__A, 3); | |
5106 | if (status < 0) | |
5107 | goto error; | |
ebc7de22 | 5108 | |
be44eb28 | 5109 | /* QAM Slicer Settings */ |
ebc7de22 | 5110 | |
ab5060cd MCC |
5111 | status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, |
5112 | DRXK_QAM_SL_SIG_POWER_QAM256); | |
be44eb28 MCC |
5113 | if (status < 0) |
5114 | goto error; | |
ebc7de22 | 5115 | |
ebc7de22 | 5116 | |
be44eb28 | 5117 | /* QAM Loop Controller Coeficients */ |
ea90f011 | 5118 | |
be44eb28 MCC |
5119 | status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); |
5120 | if (status < 0) | |
5121 | goto error; | |
5122 | status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); | |
5123 | if (status < 0) | |
5124 | goto error; | |
5125 | status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); | |
5126 | if (status < 0) | |
5127 | goto error; | |
5128 | status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); | |
5129 | if (status < 0) | |
5130 | goto error; | |
5131 | status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); | |
5132 | if (status < 0) | |
5133 | goto error; | |
5134 | status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); | |
5135 | if (status < 0) | |
5136 | goto error; | |
5137 | status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); | |
5138 | if (status < 0) | |
5139 | goto error; | |
5140 | status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); | |
5141 | if (status < 0) | |
5142 | goto error; | |
ebc7de22 | 5143 | |
be44eb28 MCC |
5144 | status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); |
5145 | if (status < 0) | |
5146 | goto error; | |
5147 | status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); | |
5148 | if (status < 0) | |
5149 | goto error; | |
5150 | status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250); | |
5151 | if (status < 0) | |
5152 | goto error; | |
5153 | status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); | |
5154 | if (status < 0) | |
5155 | goto error; | |
5156 | status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50); | |
5157 | if (status < 0) | |
5158 | goto error; | |
5159 | status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125); | |
5160 | if (status < 0) | |
5161 | goto error; | |
5162 | status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); | |
5163 | if (status < 0) | |
5164 | goto error; | |
5165 | status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); | |
5166 | if (status < 0) | |
5167 | goto error; | |
5168 | status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); | |
5169 | if (status < 0) | |
5170 | goto error; | |
5171 | status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); | |
5172 | if (status < 0) | |
5173 | goto error; | |
5174 | status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); | |
5175 | if (status < 0) | |
5176 | goto error; | |
5177 | status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); | |
5178 | if (status < 0) | |
5179 | goto error; | |
ebc7de22 | 5180 | |
ebc7de22 | 5181 | |
be44eb28 | 5182 | /* QAM State Machine (FSM) Thresholds */ |
ebc7de22 | 5183 | |
be44eb28 MCC |
5184 | status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); |
5185 | if (status < 0) | |
5186 | goto error; | |
5187 | status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); | |
5188 | if (status < 0) | |
5189 | goto error; | |
5190 | status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); | |
5191 | if (status < 0) | |
5192 | goto error; | |
5193 | status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); | |
5194 | if (status < 0) | |
5195 | goto error; | |
5196 | status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150); | |
5197 | if (status < 0) | |
5198 | goto error; | |
5199 | status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110); | |
5200 | if (status < 0) | |
5201 | goto error; | |
ebc7de22 | 5202 | |
be44eb28 MCC |
5203 | status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); |
5204 | if (status < 0) | |
5205 | goto error; | |
5206 | status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); | |
5207 | if (status < 0) | |
5208 | goto error; | |
5209 | status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); | |
5210 | if (status < 0) | |
5211 | goto error; | |
ebc7de22 | 5212 | |
ebc7de22 | 5213 | |
be44eb28 | 5214 | /* QAM FSM Tracking Parameters */ |
ebc7de22 | 5215 | |
be44eb28 MCC |
5216 | status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); |
5217 | if (status < 0) | |
5218 | goto error; | |
5219 | status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74); | |
5220 | if (status < 0) | |
5221 | goto error; | |
5222 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18); | |
5223 | if (status < 0) | |
5224 | goto error; | |
5225 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13); | |
5226 | if (status < 0) | |
5227 | goto error; | |
5228 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7); | |
5229 | if (status < 0) | |
5230 | goto error; | |
5231 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0); | |
5232 | if (status < 0) | |
5233 | goto error; | |
5234 | status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); | |
5235 | error: | |
5236 | if (status < 0) | |
3a4398f5 | 5237 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 5238 | return status; |
43dd07f7 RM |
5239 | } |
5240 | ||
5241 | ||
5242 | /*============================================================================*/ | |
5243 | /** | |
5244 | * \brief Reset QAM block. | |
5245 | * \param demod: instance of demod. | |
5246 | * \param channel: pointer to channel data. | |
5247 | * \return DRXStatus_t. | |
5248 | */ | |
cd7a67a4 | 5249 | static int qam_reset_qam(struct drxk_state *state) |
43dd07f7 | 5250 | { |
ebc7de22 | 5251 | int status; |
cd7a67a4 | 5252 | u16 cmd_result; |
43dd07f7 | 5253 | |
2da67501 | 5254 | dprintk(1, "\n"); |
be44eb28 MCC |
5255 | /* Stop QAM comstate->m_exec */ |
5256 | status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); | |
5257 | if (status < 0) | |
5258 | goto error; | |
43dd07f7 | 5259 | |
ab5060cd MCC |
5260 | status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM |
5261 | | SCU_RAM_COMMAND_CMD_DEMOD_RESET, | |
5262 | 0, NULL, 1, &cmd_result); | |
be44eb28 MCC |
5263 | error: |
5264 | if (status < 0) | |
3a4398f5 | 5265 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 5266 | return status; |
43dd07f7 RM |
5267 | } |
5268 | ||
5269 | /*============================================================================*/ | |
5270 | ||
5271 | /** | |
5272 | * \brief Set QAM symbolrate. | |
5273 | * \param demod: instance of demod. | |
5274 | * \param channel: pointer to channel data. | |
5275 | * \return DRXStatus_t. | |
5276 | */ | |
cd7a67a4 | 5277 | static int qam_set_symbolrate(struct drxk_state *state) |
43dd07f7 | 5278 | { |
cd7a67a4 MCC |
5279 | u32 adc_frequency = 0; |
5280 | u32 symb_freq = 0; | |
5281 | u32 iqm_rc_rate = 0; | |
ebc7de22 | 5282 | u16 ratesel = 0; |
cd7a67a4 | 5283 | u32 lc_symb_rate = 0; |
ebc7de22 OE |
5284 | int status; |
5285 | ||
2da67501 | 5286 | dprintk(1, "\n"); |
be44eb28 | 5287 | /* Select & calculate correct IQM rate */ |
cd7a67a4 | 5288 | adc_frequency = (state->m_sys_clock_freq * 1000) / 3; |
be44eb28 | 5289 | ratesel = 0; |
ed5452a2 MCC |
5290 | /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */ |
5291 | if (state->props.symbol_rate <= 1188750) | |
be44eb28 | 5292 | ratesel = 3; |
ed5452a2 | 5293 | else if (state->props.symbol_rate <= 2377500) |
be44eb28 | 5294 | ratesel = 2; |
ed5452a2 | 5295 | else if (state->props.symbol_rate <= 4755000) |
be44eb28 MCC |
5296 | ratesel = 1; |
5297 | status = write16(state, IQM_FD_RATESEL__A, ratesel); | |
5298 | if (status < 0) | |
5299 | goto error; | |
ebc7de22 | 5300 | |
be44eb28 MCC |
5301 | /* |
5302 | IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23) | |
5303 | */ | |
cd7a67a4 MCC |
5304 | symb_freq = state->props.symbol_rate * (1 << ratesel); |
5305 | if (symb_freq == 0) { | |
be44eb28 MCC |
5306 | /* Divide by zero */ |
5307 | status = -EINVAL; | |
5308 | goto error; | |
5309 | } | |
cd7a67a4 MCC |
5310 | iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) + |
5311 | (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) - | |
be44eb28 | 5312 | (1 << 23); |
cd7a67a4 | 5313 | status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate); |
be44eb28 MCC |
5314 | if (status < 0) |
5315 | goto error; | |
cd7a67a4 | 5316 | state->m_iqm_rc_rate = iqm_rc_rate; |
be44eb28 | 5317 | /* |
cd7a67a4 | 5318 | LcSymbFreq = round (.125 * symbolrate / adc_freq * (1<<15)) |
be44eb28 | 5319 | */ |
cd7a67a4 MCC |
5320 | symb_freq = state->props.symbol_rate; |
5321 | if (adc_frequency == 0) { | |
be44eb28 MCC |
5322 | /* Divide by zero */ |
5323 | status = -EINVAL; | |
5324 | goto error; | |
5325 | } | |
cd7a67a4 MCC |
5326 | lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) + |
5327 | (Frac28a((symb_freq % adc_frequency), adc_frequency) >> | |
be44eb28 | 5328 | 16); |
cd7a67a4 MCC |
5329 | if (lc_symb_rate > 511) |
5330 | lc_symb_rate = 511; | |
5331 | status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate); | |
be44eb28 MCC |
5332 | |
5333 | error: | |
5334 | if (status < 0) | |
3a4398f5 | 5335 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 5336 | return status; |
43dd07f7 RM |
5337 | } |
5338 | ||
5339 | /*============================================================================*/ | |
5340 | ||
5341 | /** | |
5342 | * \brief Get QAM lock status. | |
5343 | * \param demod: instance of demod. | |
5344 | * \param channel: pointer to channel data. | |
5345 | * \return DRXStatus_t. | |
5346 | */ | |
5347 | ||
cd7a67a4 | 5348 | static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status) |
43dd07f7 RM |
5349 | { |
5350 | int status; | |
cd7a67a4 | 5351 | u16 result[2] = { 0, 0 }; |
43dd07f7 | 5352 | |
2da67501 | 5353 | dprintk(1, "\n"); |
cd7a67a4 | 5354 | *p_lock_status = NOT_LOCKED; |
be44eb28 | 5355 | status = scu_command(state, |
ebc7de22 OE |
5356 | SCU_RAM_COMMAND_STANDARD_QAM | |
5357 | SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, | |
cd7a67a4 | 5358 | result); |
ebc7de22 | 5359 | if (status < 0) |
3a4398f5 | 5360 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 5361 | |
cd7a67a4 | 5362 | if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) { |
43dd07f7 | 5363 | /* 0x0000 NOT LOCKED */ |
cd7a67a4 | 5364 | } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) { |
43dd07f7 | 5365 | /* 0x4000 DEMOD LOCKED */ |
cd7a67a4 MCC |
5366 | *p_lock_status = DEMOD_LOCK; |
5367 | } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) { | |
43dd07f7 | 5368 | /* 0x8000 DEMOD + FEC LOCKED (system lock) */ |
cd7a67a4 | 5369 | *p_lock_status = MPEG_LOCK; |
ebc7de22 | 5370 | } else { |
43dd07f7 RM |
5371 | /* 0xC000 NEVER LOCKED */ |
5372 | /* (system will never be able to lock to the signal) */ | |
ab5060cd MCC |
5373 | /* |
5374 | * TODO: check this, intermediate & standard specific lock | |
5375 | * states are not taken into account here | |
5376 | */ | |
cd7a67a4 | 5377 | *p_lock_status = NEVER_LOCK; |
43dd07f7 RM |
5378 | } |
5379 | return status; | |
5380 | } | |
5381 | ||
5382 | #define QAM_MIRROR__M 0x03 | |
5383 | #define QAM_MIRROR_NORMAL 0x00 | |
5384 | #define QAM_MIRRORED 0x01 | |
5385 | #define QAM_MIRROR_AUTO_ON 0x02 | |
5386 | #define QAM_LOCKRANGE__M 0x10 | |
5387 | #define QAM_LOCKRANGE_NORMAL 0x10 | |
5388 | ||
cd7a67a4 MCC |
5389 | static int qam_demodulator_command(struct drxk_state *state, |
5390 | int number_of_parameters) | |
9e23f50a MB |
5391 | { |
5392 | int status; | |
cd7a67a4 MCC |
5393 | u16 cmd_result; |
5394 | u16 set_param_parameters[4] = { 0, 0, 0, 0 }; | |
9e23f50a | 5395 | |
cd7a67a4 MCC |
5396 | set_param_parameters[0] = state->m_constellation; /* modulation */ |
5397 | set_param_parameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ | |
9e23f50a | 5398 | |
cd7a67a4 MCC |
5399 | if (number_of_parameters == 2) { |
5400 | u16 set_env_parameters[1] = { 0 }; | |
9e23f50a | 5401 | |
cd7a67a4 MCC |
5402 | if (state->m_operation_mode == OM_QAM_ITU_C) |
5403 | set_env_parameters[0] = QAM_TOP_ANNEX_C; | |
9e23f50a | 5404 | else |
cd7a67a4 | 5405 | set_env_parameters[0] = QAM_TOP_ANNEX_A; |
9e23f50a MB |
5406 | |
5407 | status = scu_command(state, | |
ab5060cd MCC |
5408 | SCU_RAM_COMMAND_STANDARD_QAM |
5409 | | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, | |
cd7a67a4 | 5410 | 1, set_env_parameters, 1, &cmd_result); |
9e23f50a MB |
5411 | if (status < 0) |
5412 | goto error; | |
5413 | ||
5414 | status = scu_command(state, | |
ab5060cd MCC |
5415 | SCU_RAM_COMMAND_STANDARD_QAM |
5416 | | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, | |
cd7a67a4 MCC |
5417 | number_of_parameters, set_param_parameters, |
5418 | 1, &cmd_result); | |
5419 | } else if (number_of_parameters == 4) { | |
5420 | if (state->m_operation_mode == OM_QAM_ITU_C) | |
5421 | set_param_parameters[2] = QAM_TOP_ANNEX_C; | |
9e23f50a | 5422 | else |
cd7a67a4 | 5423 | set_param_parameters[2] = QAM_TOP_ANNEX_A; |
9e23f50a | 5424 | |
cd7a67a4 | 5425 | set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON); |
9e23f50a MB |
5426 | /* Env parameters */ |
5427 | /* check for LOCKRANGE Extented */ | |
cd7a67a4 | 5428 | /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */ |
9e23f50a MB |
5429 | |
5430 | status = scu_command(state, | |
ab5060cd MCC |
5431 | SCU_RAM_COMMAND_STANDARD_QAM |
5432 | | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, | |
cd7a67a4 MCC |
5433 | number_of_parameters, set_param_parameters, |
5434 | 1, &cmd_result); | |
9e23f50a | 5435 | } else { |
3a4398f5 MCC |
5436 | pr_warn("Unknown QAM demodulator parameter count %d\n", |
5437 | number_of_parameters); | |
94af1b63 | 5438 | status = -EINVAL; |
9e23f50a MB |
5439 | } |
5440 | ||
5441 | error: | |
5442 | if (status < 0) | |
3a4398f5 | 5443 | pr_warn("Warning %d on %s\n", status, __func__); |
9e23f50a MB |
5444 | return status; |
5445 | } | |
5446 | ||
cd7a67a4 MCC |
5447 | static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, |
5448 | s32 tuner_freq_offset) | |
43dd07f7 | 5449 | { |
be44eb28 | 5450 | int status; |
cd7a67a4 MCC |
5451 | u16 cmd_result; |
5452 | int qam_demod_param_count = state->qam_demod_parameter_count; | |
43dd07f7 | 5453 | |
2da67501 | 5454 | dprintk(1, "\n"); |
be44eb28 | 5455 | /* |
119faf90 MCC |
5456 | * STEP 1: reset demodulator |
5457 | * resets FEC DI and FEC RS | |
5458 | * resets QAM block | |
5459 | * resets SCU variables | |
5460 | */ | |
be44eb28 MCC |
5461 | status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP); |
5462 | if (status < 0) | |
5463 | goto error; | |
5464 | status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); | |
5465 | if (status < 0) | |
5466 | goto error; | |
cd7a67a4 | 5467 | status = qam_reset_qam(state); |
be44eb28 MCC |
5468 | if (status < 0) |
5469 | goto error; | |
43dd07f7 | 5470 | |
be44eb28 | 5471 | /* |
119faf90 MCC |
5472 | * STEP 2: configure demodulator |
5473 | * -set params; resets IQM,QAM,FEC HW; initializes some | |
5474 | * SCU variables | |
5475 | */ | |
cd7a67a4 | 5476 | status = qam_set_symbolrate(state); |
be44eb28 MCC |
5477 | if (status < 0) |
5478 | goto error; | |
5479 | ||
be44eb28 | 5480 | /* Set params */ |
ed5452a2 | 5481 | switch (state->props.modulation) { |
be44eb28 | 5482 | case QAM_256: |
cd7a67a4 | 5483 | state->m_constellation = DRX_CONSTELLATION_QAM256; |
be44eb28 MCC |
5484 | break; |
5485 | case QAM_AUTO: | |
5486 | case QAM_64: | |
cd7a67a4 | 5487 | state->m_constellation = DRX_CONSTELLATION_QAM64; |
be44eb28 MCC |
5488 | break; |
5489 | case QAM_16: | |
cd7a67a4 | 5490 | state->m_constellation = DRX_CONSTELLATION_QAM16; |
be44eb28 MCC |
5491 | break; |
5492 | case QAM_32: | |
cd7a67a4 | 5493 | state->m_constellation = DRX_CONSTELLATION_QAM32; |
be44eb28 MCC |
5494 | break; |
5495 | case QAM_128: | |
cd7a67a4 | 5496 | state->m_constellation = DRX_CONSTELLATION_QAM128; |
be44eb28 MCC |
5497 | break; |
5498 | default: | |
5499 | status = -EINVAL; | |
5500 | break; | |
5501 | } | |
5502 | if (status < 0) | |
5503 | goto error; | |
43dd07f7 | 5504 | |
9e23f50a MB |
5505 | /* Use the 4-parameter if it's requested or we're probing for |
5506 | * the correct command. */ | |
5507 | if (state->qam_demod_parameter_count == 4 | |
5508 | || !state->qam_demod_parameter_count) { | |
cd7a67a4 MCC |
5509 | qam_demod_param_count = 4; |
5510 | status = qam_demodulator_command(state, qam_demod_param_count); | |
9e23f50a | 5511 | } |
43dd07f7 | 5512 | |
9e23f50a MB |
5513 | /* Use the 2-parameter command if it was requested or if we're |
5514 | * probing for the correct command and the 4-parameter command | |
5515 | * failed. */ | |
5516 | if (state->qam_demod_parameter_count == 2 | |
5517 | || (!state->qam_demod_parameter_count && status < 0)) { | |
cd7a67a4 MCC |
5518 | qam_demod_param_count = 2; |
5519 | status = qam_demodulator_command(state, qam_demod_param_count); | |
5eee2bb2 | 5520 | } |
9e23f50a MB |
5521 | |
5522 | if (status < 0) { | |
0fb220f2 MCC |
5523 | dprintk(1, "Could not set demodulator parameters.\n"); |
5524 | dprintk(1, | |
5525 | "Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n", | |
9e23f50a MB |
5526 | state->qam_demod_parameter_count, |
5527 | state->microcode_name); | |
5eee2bb2 | 5528 | goto error; |
9e23f50a | 5529 | } else if (!state->qam_demod_parameter_count) { |
0fb220f2 MCC |
5530 | dprintk(1, |
5531 | "Auto-probing the QAM command parameters was successful - using %d parameters.\n", | |
cd7a67a4 | 5532 | qam_demod_param_count); |
9e23f50a | 5533 | |
7eaf7188 MCC |
5534 | /* |
5535 | * One of our commands was successful. We don't need to | |
5536 | * auto-probe anymore, now that we got the correct command. | |
5537 | */ | |
cd7a67a4 | 5538 | state->qam_demod_parameter_count = qam_demod_param_count; |
9e23f50a | 5539 | } |
43dd07f7 | 5540 | |
119faf90 MCC |
5541 | /* |
5542 | * STEP 3: enable the system in a mode where the ADC provides valid | |
ed5452a2 | 5543 | * signal setup modulation independent registers |
119faf90 | 5544 | */ |
ea90f011 | 5545 | #if 0 |
cd7a67a4 | 5546 | status = set_frequency(channel, tuner_freq_offset)); |
be44eb28 MCC |
5547 | if (status < 0) |
5548 | goto error; | |
ea90f011 | 5549 | #endif |
ab5060cd MCC |
5550 | status = set_frequency_shifter(state, intermediate_freqk_hz, |
5551 | tuner_freq_offset, true); | |
be44eb28 MCC |
5552 | if (status < 0) |
5553 | goto error; | |
43dd07f7 | 5554 | |
be44eb28 | 5555 | /* Setup BER measurement */ |
ab5060cd MCC |
5556 | status = set_qam_measurement(state, state->m_constellation, |
5557 | state->props.symbol_rate); | |
be44eb28 MCC |
5558 | if (status < 0) |
5559 | goto error; | |
ebc7de22 | 5560 | |
be44eb28 MCC |
5561 | /* Reset default values */ |
5562 | status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); | |
5563 | if (status < 0) | |
5564 | goto error; | |
5565 | status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); | |
5566 | if (status < 0) | |
5567 | goto error; | |
ea90f011 | 5568 | |
be44eb28 MCC |
5569 | /* Reset default LC values */ |
5570 | status = write16(state, QAM_LC_RATE_LIMIT__A, 3); | |
5571 | if (status < 0) | |
5572 | goto error; | |
5573 | status = write16(state, QAM_LC_LPF_FACTORP__A, 4); | |
5574 | if (status < 0) | |
5575 | goto error; | |
5576 | status = write16(state, QAM_LC_LPF_FACTORI__A, 4); | |
5577 | if (status < 0) | |
5578 | goto error; | |
5579 | status = write16(state, QAM_LC_MODE__A, 7); | |
5580 | if (status < 0) | |
5581 | goto error; | |
ebc7de22 | 5582 | |
be44eb28 MCC |
5583 | status = write16(state, QAM_LC_QUAL_TAB0__A, 1); |
5584 | if (status < 0) | |
5585 | goto error; | |
5586 | status = write16(state, QAM_LC_QUAL_TAB1__A, 1); | |
5587 | if (status < 0) | |
5588 | goto error; | |
5589 | status = write16(state, QAM_LC_QUAL_TAB2__A, 1); | |
5590 | if (status < 0) | |
5591 | goto error; | |
5592 | status = write16(state, QAM_LC_QUAL_TAB3__A, 1); | |
5593 | if (status < 0) | |
5594 | goto error; | |
5595 | status = write16(state, QAM_LC_QUAL_TAB4__A, 2); | |
5596 | if (status < 0) | |
5597 | goto error; | |
5598 | status = write16(state, QAM_LC_QUAL_TAB5__A, 2); | |
5599 | if (status < 0) | |
5600 | goto error; | |
5601 | status = write16(state, QAM_LC_QUAL_TAB6__A, 2); | |
5602 | if (status < 0) | |
5603 | goto error; | |
5604 | status = write16(state, QAM_LC_QUAL_TAB8__A, 2); | |
5605 | if (status < 0) | |
5606 | goto error; | |
5607 | status = write16(state, QAM_LC_QUAL_TAB9__A, 2); | |
5608 | if (status < 0) | |
5609 | goto error; | |
5610 | status = write16(state, QAM_LC_QUAL_TAB10__A, 2); | |
5611 | if (status < 0) | |
5612 | goto error; | |
5613 | status = write16(state, QAM_LC_QUAL_TAB12__A, 2); | |
5614 | if (status < 0) | |
5615 | goto error; | |
5616 | status = write16(state, QAM_LC_QUAL_TAB15__A, 3); | |
5617 | if (status < 0) | |
5618 | goto error; | |
5619 | status = write16(state, QAM_LC_QUAL_TAB16__A, 3); | |
5620 | if (status < 0) | |
5621 | goto error; | |
5622 | status = write16(state, QAM_LC_QUAL_TAB20__A, 4); | |
5623 | if (status < 0) | |
5624 | goto error; | |
5625 | status = write16(state, QAM_LC_QUAL_TAB25__A, 4); | |
5626 | if (status < 0) | |
5627 | goto error; | |
ebc7de22 | 5628 | |
be44eb28 | 5629 | /* Mirroring, QAM-block starting point not inverted */ |
ab5060cd MCC |
5630 | status = write16(state, QAM_SY_SP_INV__A, |
5631 | QAM_SY_SP_INV_SPECTRUM_INV_DIS); | |
be44eb28 MCC |
5632 | if (status < 0) |
5633 | goto error; | |
ebc7de22 | 5634 | |
be44eb28 MCC |
5635 | /* Halt SCU to enable safe non-atomic accesses */ |
5636 | status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); | |
5637 | if (status < 0) | |
5638 | goto error; | |
ebc7de22 | 5639 | |
ed5452a2 MCC |
5640 | /* STEP 4: modulation specific setup */ |
5641 | switch (state->props.modulation) { | |
be44eb28 | 5642 | case QAM_16: |
cd7a67a4 | 5643 | status = set_qam16(state); |
be44eb28 MCC |
5644 | break; |
5645 | case QAM_32: | |
cd7a67a4 | 5646 | status = set_qam32(state); |
be44eb28 MCC |
5647 | break; |
5648 | case QAM_AUTO: | |
5649 | case QAM_64: | |
cd7a67a4 | 5650 | status = set_qam64(state); |
be44eb28 MCC |
5651 | break; |
5652 | case QAM_128: | |
cd7a67a4 | 5653 | status = set_qam128(state); |
be44eb28 MCC |
5654 | break; |
5655 | case QAM_256: | |
cd7a67a4 | 5656 | status = set_qam256(state); |
be44eb28 MCC |
5657 | break; |
5658 | default: | |
5659 | status = -EINVAL; | |
5660 | break; | |
5661 | } | |
5662 | if (status < 0) | |
5663 | goto error; | |
ebc7de22 | 5664 | |
be44eb28 MCC |
5665 | /* Activate SCU to enable SCU commands */ |
5666 | status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); | |
5667 | if (status < 0) | |
5668 | goto error; | |
ebc7de22 | 5669 | |
be44eb28 | 5670 | /* Re-configure MPEG output, requires knowledge of channel bitrate */ |
ed5452a2 | 5671 | /* extAttr->currentChannel.modulation = channel->modulation; */ |
be44eb28 | 5672 | /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ |
cd7a67a4 | 5673 | status = mpegts_dto_setup(state, state->m_operation_mode); |
be44eb28 MCC |
5674 | if (status < 0) |
5675 | goto error; | |
ebc7de22 | 5676 | |
cd7a67a4 MCC |
5677 | /* start processes */ |
5678 | status = mpegts_start(state); | |
be44eb28 MCC |
5679 | if (status < 0) |
5680 | goto error; | |
5681 | status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); | |
5682 | if (status < 0) | |
5683 | goto error; | |
5684 | status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); | |
5685 | if (status < 0) | |
5686 | goto error; | |
5687 | status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); | |
5688 | if (status < 0) | |
5689 | goto error; | |
ebc7de22 | 5690 | |
be44eb28 | 5691 | /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ |
ab5060cd MCC |
5692 | status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM |
5693 | | SCU_RAM_COMMAND_CMD_DEMOD_START, | |
5694 | 0, NULL, 1, &cmd_result); | |
be44eb28 MCC |
5695 | if (status < 0) |
5696 | goto error; | |
ebc7de22 | 5697 | |
be44eb28 MCC |
5698 | /* update global DRXK data container */ |
5699 | /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */ | |
ebc7de22 | 5700 | |
be44eb28 | 5701 | error: |
ebc7de22 | 5702 | if (status < 0) |
3a4398f5 | 5703 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 5704 | return status; |
43dd07f7 RM |
5705 | } |
5706 | ||
cd7a67a4 MCC |
5707 | static int set_qam_standard(struct drxk_state *state, |
5708 | enum operation_mode o_mode) | |
43dd07f7 | 5709 | { |
be44eb28 | 5710 | int status; |
43dd07f7 RM |
5711 | #ifdef DRXK_QAM_TAPS |
5712 | #define DRXK_QAMA_TAPS_SELECT | |
5713 | #include "drxk_filters.h" | |
5714 | #undef DRXK_QAMA_TAPS_SELECT | |
43dd07f7 RM |
5715 | #endif |
5716 | ||
f1b82970 MCC |
5717 | dprintk(1, "\n"); |
5718 | ||
be44eb28 | 5719 | /* added antenna switch */ |
cd7a67a4 | 5720 | switch_antenna_to_qam(state); |
ebc7de22 | 5721 | |
be44eb28 | 5722 | /* Ensure correct power-up mode */ |
cd7a67a4 | 5723 | status = power_up_qam(state); |
be44eb28 MCC |
5724 | if (status < 0) |
5725 | goto error; | |
5726 | /* Reset QAM block */ | |
cd7a67a4 | 5727 | status = qam_reset_qam(state); |
be44eb28 MCC |
5728 | if (status < 0) |
5729 | goto error; | |
ebc7de22 | 5730 | |
be44eb28 | 5731 | /* Setup IQM */ |
ebc7de22 | 5732 | |
be44eb28 MCC |
5733 | status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); |
5734 | if (status < 0) | |
5735 | goto error; | |
5736 | status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); | |
5737 | if (status < 0) | |
5738 | goto error; | |
ebc7de22 | 5739 | |
be44eb28 MCC |
5740 | /* Upload IQM Channel Filter settings by |
5741 | boot loader from ROM table */ | |
cd7a67a4 | 5742 | switch (o_mode) { |
be44eb28 | 5743 | case OM_QAM_ITU_A: |
ab5060cd MCC |
5744 | status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, |
5745 | DRXK_BLCC_NR_ELEMENTS_TAPS, | |
5746 | DRXK_BLC_TIMEOUT); | |
be44eb28 MCC |
5747 | break; |
5748 | case OM_QAM_ITU_C: | |
ab5060cd MCC |
5749 | status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A, |
5750 | DRXK_BL_ROM_OFFSET_TAPS_ITU_C, | |
5751 | DRXK_BLDC_NR_ELEMENTS_TAPS, | |
5752 | DRXK_BLC_TIMEOUT); | |
ea90f011 | 5753 | if (status < 0) |
be44eb28 | 5754 | goto error; |
ab5060cd MCC |
5755 | status = bl_direct_cmd(state, |
5756 | IQM_CF_TAP_IM0__A, | |
5757 | DRXK_BL_ROM_OFFSET_TAPS_ITU_C, | |
5758 | DRXK_BLDC_NR_ELEMENTS_TAPS, | |
5759 | DRXK_BLC_TIMEOUT); | |
be44eb28 MCC |
5760 | break; |
5761 | default: | |
5762 | status = -EINVAL; | |
5763 | } | |
5764 | if (status < 0) | |
5765 | goto error; | |
ea90f011 | 5766 | |
ab5060cd | 5767 | status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B); |
be44eb28 MCC |
5768 | if (status < 0) |
5769 | goto error; | |
5770 | status = write16(state, IQM_CF_SYMMETRIC__A, 0); | |
5771 | if (status < 0) | |
5772 | goto error; | |
ab5060cd MCC |
5773 | status = write16(state, IQM_CF_MIDTAP__A, |
5774 | ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B))); | |
be44eb28 MCC |
5775 | if (status < 0) |
5776 | goto error; | |
ea90f011 | 5777 | |
be44eb28 MCC |
5778 | status = write16(state, IQM_RC_STRETCH__A, 21); |
5779 | if (status < 0) | |
5780 | goto error; | |
5781 | status = write16(state, IQM_AF_CLP_LEN__A, 0); | |
5782 | if (status < 0) | |
5783 | goto error; | |
5784 | status = write16(state, IQM_AF_CLP_TH__A, 448); | |
5785 | if (status < 0) | |
5786 | goto error; | |
5787 | status = write16(state, IQM_AF_SNS_LEN__A, 0); | |
5788 | if (status < 0) | |
5789 | goto error; | |
5790 | status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0); | |
5791 | if (status < 0) | |
5792 | goto error; | |
ea90f011 | 5793 | |
be44eb28 MCC |
5794 | status = write16(state, IQM_FS_ADJ_SEL__A, 1); |
5795 | if (status < 0) | |
5796 | goto error; | |
5797 | status = write16(state, IQM_RC_ADJ_SEL__A, 1); | |
5798 | if (status < 0) | |
5799 | goto error; | |
5800 | status = write16(state, IQM_CF_ADJ_SEL__A, 1); | |
5801 | if (status < 0) | |
5802 | goto error; | |
5803 | status = write16(state, IQM_AF_UPD_SEL__A, 0); | |
5804 | if (status < 0) | |
5805 | goto error; | |
ebc7de22 | 5806 | |
be44eb28 MCC |
5807 | /* IQM Impulse Noise Processing Unit */ |
5808 | status = write16(state, IQM_CF_CLP_VAL__A, 500); | |
5809 | if (status < 0) | |
5810 | goto error; | |
5811 | status = write16(state, IQM_CF_DATATH__A, 1000); | |
5812 | if (status < 0) | |
5813 | goto error; | |
5814 | status = write16(state, IQM_CF_BYPASSDET__A, 1); | |
5815 | if (status < 0) | |
5816 | goto error; | |
5817 | status = write16(state, IQM_CF_DET_LCT__A, 0); | |
5818 | if (status < 0) | |
5819 | goto error; | |
5820 | status = write16(state, IQM_CF_WND_LEN__A, 1); | |
5821 | if (status < 0) | |
5822 | goto error; | |
5823 | status = write16(state, IQM_CF_PKDTH__A, 1); | |
5824 | if (status < 0) | |
5825 | goto error; | |
5826 | status = write16(state, IQM_AF_INC_BYPASS__A, 1); | |
5827 | if (status < 0) | |
5828 | goto error; | |
ebc7de22 | 5829 | |
be44eb28 | 5830 | /* turn on IQMAF. Must be done before setAgc**() */ |
cd7a67a4 | 5831 | status = set_iqm_af(state, true); |
be44eb28 MCC |
5832 | if (status < 0) |
5833 | goto error; | |
5834 | status = write16(state, IQM_AF_START_LOCK__A, 0x01); | |
5835 | if (status < 0) | |
5836 | goto error; | |
ebc7de22 | 5837 | |
be44eb28 | 5838 | /* IQM will not be reset from here, sync ADC and update/init AGC */ |
cd7a67a4 | 5839 | status = adc_synchronization(state); |
be44eb28 MCC |
5840 | if (status < 0) |
5841 | goto error; | |
ebc7de22 | 5842 | |
be44eb28 MCC |
5843 | /* Set the FSM step period */ |
5844 | status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000); | |
5845 | if (status < 0) | |
5846 | goto error; | |
ebc7de22 | 5847 | |
be44eb28 MCC |
5848 | /* Halt SCU to enable safe non-atomic accesses */ |
5849 | status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); | |
5850 | if (status < 0) | |
5851 | goto error; | |
ebc7de22 | 5852 | |
be44eb28 MCC |
5853 | /* No more resets of the IQM, current standard correctly set => |
5854 | now AGCs can be configured. */ | |
ebc7de22 | 5855 | |
cd7a67a4 | 5856 | status = init_agc(state, true); |
be44eb28 MCC |
5857 | if (status < 0) |
5858 | goto error; | |
cd7a67a4 | 5859 | status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg)); |
be44eb28 MCC |
5860 | if (status < 0) |
5861 | goto error; | |
ebc7de22 | 5862 | |
be44eb28 | 5863 | /* Configure AGC's */ |
cd7a67a4 | 5864 | status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true); |
be44eb28 MCC |
5865 | if (status < 0) |
5866 | goto error; | |
cd7a67a4 | 5867 | status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true); |
be44eb28 MCC |
5868 | if (status < 0) |
5869 | goto error; | |
ebc7de22 | 5870 | |
be44eb28 MCC |
5871 | /* Activate SCU to enable SCU commands */ |
5872 | status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); | |
5873 | error: | |
5874 | if (status < 0) | |
3a4398f5 | 5875 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 5876 | return status; |
43dd07f7 RM |
5877 | } |
5878 | ||
cd7a67a4 | 5879 | static int write_gpio(struct drxk_state *state) |
43dd07f7 | 5880 | { |
ebc7de22 OE |
5881 | int status; |
5882 | u16 value = 0; | |
5883 | ||
2da67501 | 5884 | dprintk(1, "\n"); |
be44eb28 | 5885 | /* stop lock indicator process */ |
ab5060cd MCC |
5886 | status = write16(state, SCU_RAM_GPIO__A, |
5887 | SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); | |
be44eb28 MCC |
5888 | if (status < 0) |
5889 | goto error; | |
ebc7de22 | 5890 | |
be44eb28 MCC |
5891 | /* Write magic word to enable pdr reg write */ |
5892 | status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); | |
5893 | if (status < 0) | |
5894 | goto error; | |
ebc7de22 | 5895 | |
cd7a67a4 MCC |
5896 | if (state->m_has_sawsw) { |
5897 | if (state->uio_mask & 0x0001) { /* UIO-1 */ | |
90796aca | 5898 | /* write to io pad configuration register - output mode */ |
ab5060cd MCC |
5899 | status = write16(state, SIO_PDR_SMA_TX_CFG__A, |
5900 | state->m_gpio_cfg); | |
90796aca MCC |
5901 | if (status < 0) |
5902 | goto error; | |
ebc7de22 | 5903 | |
90796aca MCC |
5904 | /* use corresponding bit in io data output registar */ |
5905 | status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); | |
5906 | if (status < 0) | |
5907 | goto error; | |
cd7a67a4 | 5908 | if ((state->m_gpio & 0x0001) == 0) |
90796aca MCC |
5909 | value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ |
5910 | else | |
5911 | value |= 0x8000; /* write one to 15th bit - 1st UIO */ | |
5912 | /* write back to io data output register */ | |
5913 | status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); | |
5914 | if (status < 0) | |
5915 | goto error; | |
5916 | } | |
cd7a67a4 | 5917 | if (state->uio_mask & 0x0002) { /* UIO-2 */ |
90796aca | 5918 | /* write to io pad configuration register - output mode */ |
ab5060cd MCC |
5919 | status = write16(state, SIO_PDR_SMA_RX_CFG__A, |
5920 | state->m_gpio_cfg); | |
90796aca MCC |
5921 | if (status < 0) |
5922 | goto error; | |
be44eb28 | 5923 | |
90796aca MCC |
5924 | /* use corresponding bit in io data output registar */ |
5925 | status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); | |
5926 | if (status < 0) | |
5927 | goto error; | |
cd7a67a4 | 5928 | if ((state->m_gpio & 0x0002) == 0) |
90796aca MCC |
5929 | value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */ |
5930 | else | |
5931 | value |= 0x4000; /* write one to 14th bit - 2st UIO */ | |
5932 | /* write back to io data output register */ | |
5933 | status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); | |
5934 | if (status < 0) | |
5935 | goto error; | |
5936 | } | |
cd7a67a4 | 5937 | if (state->uio_mask & 0x0004) { /* UIO-3 */ |
90796aca | 5938 | /* write to io pad configuration register - output mode */ |
ab5060cd MCC |
5939 | status = write16(state, SIO_PDR_GPIO_CFG__A, |
5940 | state->m_gpio_cfg); | |
90796aca MCC |
5941 | if (status < 0) |
5942 | goto error; | |
5943 | ||
5944 | /* use corresponding bit in io data output registar */ | |
5945 | status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); | |
5946 | if (status < 0) | |
5947 | goto error; | |
cd7a67a4 | 5948 | if ((state->m_gpio & 0x0004) == 0) |
90796aca MCC |
5949 | value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ |
5950 | else | |
5951 | value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ | |
5952 | /* write back to io data output register */ | |
5953 | status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); | |
5954 | if (status < 0) | |
5955 | goto error; | |
5956 | } | |
be44eb28 MCC |
5957 | } |
5958 | /* Write magic word to disable pdr reg write */ | |
5959 | status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); | |
5960 | error: | |
5961 | if (status < 0) | |
3a4398f5 | 5962 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 5963 | return status; |
43dd07f7 RM |
5964 | } |
5965 | ||
cd7a67a4 | 5966 | static int switch_antenna_to_qam(struct drxk_state *state) |
43dd07f7 | 5967 | { |
147e110b | 5968 | int status = 0; |
90796aca | 5969 | bool gpio_state; |
ebc7de22 | 5970 | |
2da67501 | 5971 | dprintk(1, "\n"); |
147e110b | 5972 | |
90796aca MCC |
5973 | if (!state->antenna_gpio) |
5974 | return 0; | |
5975 | ||
cd7a67a4 | 5976 | gpio_state = state->m_gpio & state->antenna_gpio; |
90796aca MCC |
5977 | |
5978 | if (state->antenna_dvbt ^ gpio_state) { | |
5979 | /* Antenna is on DVB-T mode. Switch */ | |
5980 | if (state->antenna_dvbt) | |
cd7a67a4 | 5981 | state->m_gpio &= ~state->antenna_gpio; |
90796aca | 5982 | else |
cd7a67a4 MCC |
5983 | state->m_gpio |= state->antenna_gpio; |
5984 | status = write_gpio(state); | |
ebc7de22 | 5985 | } |
be44eb28 | 5986 | if (status < 0) |
3a4398f5 | 5987 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 5988 | return status; |
43dd07f7 RM |
5989 | } |
5990 | ||
cd7a67a4 | 5991 | static int switch_antenna_to_dvbt(struct drxk_state *state) |
43dd07f7 | 5992 | { |
147e110b | 5993 | int status = 0; |
90796aca | 5994 | bool gpio_state; |
ebc7de22 | 5995 | |
2da67501 | 5996 | dprintk(1, "\n"); |
90796aca MCC |
5997 | |
5998 | if (!state->antenna_gpio) | |
5999 | return 0; | |
6000 | ||
cd7a67a4 | 6001 | gpio_state = state->m_gpio & state->antenna_gpio; |
90796aca MCC |
6002 | |
6003 | if (!(state->antenna_dvbt ^ gpio_state)) { | |
6004 | /* Antenna is on DVB-C mode. Switch */ | |
6005 | if (state->antenna_dvbt) | |
cd7a67a4 | 6006 | state->m_gpio |= state->antenna_gpio; |
90796aca | 6007 | else |
cd7a67a4 MCC |
6008 | state->m_gpio &= ~state->antenna_gpio; |
6009 | status = write_gpio(state); | |
43dd07f7 | 6010 | } |
be44eb28 | 6011 | if (status < 0) |
3a4398f5 | 6012 | pr_err("Error %d on %s\n", status, __func__); |
43dd07f7 RM |
6013 | return status; |
6014 | } | |
6015 | ||
6016 | ||
cd7a67a4 | 6017 | static int power_down_device(struct drxk_state *state) |
43dd07f7 RM |
6018 | { |
6019 | /* Power down to requested mode */ | |
6020 | /* Backup some register settings */ | |
6021 | /* Set pins with possible pull-ups connected to them in input mode */ | |
6022 | /* Analog power down */ | |
6023 | /* ADC power down */ | |
6024 | /* Power down device */ | |
6025 | int status; | |
2da67501 MCC |
6026 | |
6027 | dprintk(1, "\n"); | |
cd7a67a4 | 6028 | if (state->m_b_p_down_open_bridge) { |
be44eb28 MCC |
6029 | /* Open I2C bridge before power down of DRXK */ |
6030 | status = ConfigureI2CBridge(state, true); | |
ea90f011 | 6031 | if (status < 0) |
be44eb28 MCC |
6032 | goto error; |
6033 | } | |
6034 | /* driver 0.9.0 */ | |
cd7a67a4 | 6035 | status = dvbt_enable_ofdm_token_ring(state, false); |
be44eb28 MCC |
6036 | if (status < 0) |
6037 | goto error; | |
43dd07f7 | 6038 | |
ab5060cd MCC |
6039 | status = write16(state, SIO_CC_PWD_MODE__A, |
6040 | SIO_CC_PWD_MODE_LEVEL_CLOCK); | |
ebc7de22 | 6041 | if (status < 0) |
be44eb28 MCC |
6042 | goto error; |
6043 | status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); | |
6044 | if (status < 0) | |
6045 | goto error; | |
cd7a67a4 MCC |
6046 | state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; |
6047 | status = hi_cfg_command(state); | |
be44eb28 MCC |
6048 | error: |
6049 | if (status < 0) | |
3a4398f5 | 6050 | pr_err("Error %d on %s\n", status, __func__); |
ebc7de22 | 6051 | |
be44eb28 | 6052 | return status; |
43dd07f7 RM |
6053 | } |
6054 | ||
43dd07f7 RM |
6055 | static int init_drxk(struct drxk_state *state) |
6056 | { | |
177bc7da | 6057 | int status = 0, n = 0; |
cd7a67a4 MCC |
6058 | enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; |
6059 | u16 driver_version; | |
43dd07f7 | 6060 | |
2da67501 | 6061 | dprintk(1, "\n"); |
cd7a67a4 | 6062 | if ((state->m_drxk_state == DRXK_UNINITIALIZED)) { |
20bfe7ae | 6063 | drxk_i2c_lock(state); |
cd7a67a4 | 6064 | status = power_up_device(state); |
be44eb28 MCC |
6065 | if (status < 0) |
6066 | goto error; | |
cd7a67a4 | 6067 | status = drxx_open(state); |
be44eb28 MCC |
6068 | if (status < 0) |
6069 | goto error; | |
6070 | /* Soft reset of OFDM-, sys- and osc-clockdomain */ | |
ab5060cd MCC |
6071 | status = write16(state, SIO_CC_SOFT_RST__A, |
6072 | SIO_CC_SOFT_RST_OFDM__M | |
6073 | | SIO_CC_SOFT_RST_SYS__M | |
6074 | | SIO_CC_SOFT_RST_OSC__M); | |
be44eb28 MCC |
6075 | if (status < 0) |
6076 | goto error; | |
6077 | status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); | |
6078 | if (status < 0) | |
6079 | goto error; | |
ab5060cd MCC |
6080 | /* |
6081 | * TODO is this needed? If yes, how much delay in | |
6082 | * worst case scenario | |
6083 | */ | |
b72852ba | 6084 | usleep_range(1000, 2000); |
cd7a67a4 MCC |
6085 | state->m_drxk_a3_patch_code = true; |
6086 | status = get_device_capabilities(state); | |
be44eb28 MCC |
6087 | if (status < 0) |
6088 | goto error; | |
6089 | ||
6090 | /* Bridge delay, uses oscilator clock */ | |
6091 | /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ | |
6092 | /* SDA brdige delay */ | |
cd7a67a4 MCC |
6093 | state->m_hi_cfg_bridge_delay = |
6094 | (u16) ((state->m_osc_clock_freq / 1000) * | |
be44eb28 MCC |
6095 | HI_I2C_BRIDGE_DELAY) / 1000; |
6096 | /* Clipping */ | |
cd7a67a4 | 6097 | if (state->m_hi_cfg_bridge_delay > |
be44eb28 | 6098 | SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { |
cd7a67a4 | 6099 | state->m_hi_cfg_bridge_delay = |
be44eb28 MCC |
6100 | SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; |
6101 | } | |
6102 | /* SCL bridge delay, same as SDA for now */ | |
cd7a67a4 MCC |
6103 | state->m_hi_cfg_bridge_delay += |
6104 | state->m_hi_cfg_bridge_delay << | |
be44eb28 MCC |
6105 | SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; |
6106 | ||
cd7a67a4 | 6107 | status = init_hi(state); |
be44eb28 MCC |
6108 | if (status < 0) |
6109 | goto error; | |
6110 | /* disable various processes */ | |
43dd07f7 | 6111 | #if NOA1ROM |
be44eb28 MCC |
6112 | if (!(state->m_DRXK_A1_ROM_CODE) |
6113 | && !(state->m_DRXK_A2_ROM_CODE)) | |
43dd07f7 | 6114 | #endif |
be44eb28 | 6115 | { |
ab5060cd MCC |
6116 | status = write16(state, SCU_RAM_GPIO__A, |
6117 | SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); | |
ea90f011 | 6118 | if (status < 0) |
be44eb28 MCC |
6119 | goto error; |
6120 | } | |
43dd07f7 | 6121 | |
be44eb28 | 6122 | /* disable MPEG port */ |
cd7a67a4 | 6123 | status = mpegts_disable(state); |
be44eb28 MCC |
6124 | if (status < 0) |
6125 | goto error; | |
43dd07f7 | 6126 | |
be44eb28 MCC |
6127 | /* Stop AUD and SCU */ |
6128 | status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); | |
6129 | if (status < 0) | |
6130 | goto error; | |
6131 | status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); | |
6132 | if (status < 0) | |
6133 | goto error; | |
e4f4f875 | 6134 | |
be44eb28 | 6135 | /* enable token-ring bus through OFDM block for possible ucode upload */ |
ab5060cd MCC |
6136 | status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, |
6137 | SIO_OFDM_SH_OFDM_RING_ENABLE_ON); | |
be44eb28 MCC |
6138 | if (status < 0) |
6139 | goto error; | |
43dd07f7 | 6140 | |
be44eb28 | 6141 | /* include boot loader section */ |
ab5060cd MCC |
6142 | status = write16(state, SIO_BL_COMM_EXEC__A, |
6143 | SIO_BL_COMM_EXEC_ACTIVE); | |
be44eb28 MCC |
6144 | if (status < 0) |
6145 | goto error; | |
cd7a67a4 | 6146 | status = bl_chain_cmd(state, 0, 6, 100); |
be44eb28 MCC |
6147 | if (status < 0) |
6148 | goto error; | |
43dd07f7 | 6149 | |
177bc7da | 6150 | if (state->fw) { |
cd7a67a4 | 6151 | status = download_microcode(state, state->fw->data, |
177bc7da MCC |
6152 | state->fw->size); |
6153 | if (status < 0) | |
6154 | goto error; | |
6155 | } | |
43dd07f7 | 6156 | |
be44eb28 | 6157 | /* disable token-ring bus through OFDM block for possible ucode upload */ |
ab5060cd MCC |
6158 | status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, |
6159 | SIO_OFDM_SH_OFDM_RING_ENABLE_OFF); | |
be44eb28 MCC |
6160 | if (status < 0) |
6161 | goto error; | |
ebc7de22 | 6162 | |
be44eb28 MCC |
6163 | /* Run SCU for a little while to initialize microcode version numbers */ |
6164 | status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); | |
6165 | if (status < 0) | |
6166 | goto error; | |
cd7a67a4 | 6167 | status = drxx_open(state); |
be44eb28 MCC |
6168 | if (status < 0) |
6169 | goto error; | |
6170 | /* added for test */ | |
6171 | msleep(30); | |
43dd07f7 | 6172 | |
cd7a67a4 MCC |
6173 | power_mode = DRXK_POWER_DOWN_OFDM; |
6174 | status = ctrl_power_mode(state, &power_mode); | |
be44eb28 MCC |
6175 | if (status < 0) |
6176 | goto error; | |
6177 | ||
6178 | /* Stamp driver version number in SCU data RAM in BCD code | |
39c1cb2b | 6179 | Done to enable field application engineers to retrieve drxdriver version |
be44eb28 MCC |
6180 | via I2C from SCU RAM. |
6181 | Not using SCU command interface for SCU register access since no | |
6182 | microcode may be present. | |
6183 | */ | |
cd7a67a4 | 6184 | driver_version = |
be44eb28 MCC |
6185 | (((DRXK_VERSION_MAJOR / 100) % 10) << 12) + |
6186 | (((DRXK_VERSION_MAJOR / 10) % 10) << 8) + | |
6187 | ((DRXK_VERSION_MAJOR % 10) << 4) + | |
6188 | (DRXK_VERSION_MINOR % 10); | |
ab5060cd MCC |
6189 | status = write16(state, SCU_RAM_DRIVER_VER_HI__A, |
6190 | driver_version); | |
be44eb28 MCC |
6191 | if (status < 0) |
6192 | goto error; | |
cd7a67a4 | 6193 | driver_version = |
be44eb28 MCC |
6194 | (((DRXK_VERSION_PATCH / 1000) % 10) << 12) + |
6195 | (((DRXK_VERSION_PATCH / 100) % 10) << 8) + | |
6196 | (((DRXK_VERSION_PATCH / 10) % 10) << 4) + | |
6197 | (DRXK_VERSION_PATCH % 10); | |
ab5060cd MCC |
6198 | status = write16(state, SCU_RAM_DRIVER_VER_LO__A, |
6199 | driver_version); | |
be44eb28 MCC |
6200 | if (status < 0) |
6201 | goto error; | |
6202 | ||
3a4398f5 | 6203 | pr_info("DRXK driver version %d.%d.%d\n", |
be44eb28 MCC |
6204 | DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR, |
6205 | DRXK_VERSION_PATCH); | |
6206 | ||
ab5060cd MCC |
6207 | /* |
6208 | * Dirty fix of default values for ROM/PATCH microcode | |
6209 | * Dirty because this fix makes it impossible to setup | |
6210 | * suitable values before calling DRX_Open. This solution | |
6211 | * requires changes to RF AGC speed to be done via the CTRL | |
6212 | * function after calling DRX_Open | |
6213 | */ | |
be44eb28 | 6214 | |
cd7a67a4 | 6215 | /* m_dvbt_rf_agc_cfg.speed = 3; */ |
be44eb28 MCC |
6216 | |
6217 | /* Reset driver debug flags to 0 */ | |
6218 | status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); | |
6219 | if (status < 0) | |
6220 | goto error; | |
6221 | /* driver 0.9.0 */ | |
6222 | /* Setup FEC OC: | |
6223 | NOTE: No more full FEC resets allowed afterwards!! */ | |
6224 | status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); | |
6225 | if (status < 0) | |
6226 | goto error; | |
6227 | /* MPEGTS functions are still the same */ | |
cd7a67a4 | 6228 | status = mpegts_dto_init(state); |
be44eb28 MCC |
6229 | if (status < 0) |
6230 | goto error; | |
cd7a67a4 | 6231 | status = mpegts_stop(state); |
be44eb28 MCC |
6232 | if (status < 0) |
6233 | goto error; | |
cd7a67a4 | 6234 | status = mpegts_configure_polarity(state); |
be44eb28 MCC |
6235 | if (status < 0) |
6236 | goto error; | |
cd7a67a4 | 6237 | status = mpegts_configure_pins(state, state->m_enable_mpeg_output); |
be44eb28 MCC |
6238 | if (status < 0) |
6239 | goto error; | |
6240 | /* added: configure GPIO */ | |
cd7a67a4 | 6241 | status = write_gpio(state); |
be44eb28 MCC |
6242 | if (status < 0) |
6243 | goto error; | |
43dd07f7 | 6244 | |
cd7a67a4 | 6245 | state->m_drxk_state = DRXK_STOPPED; |
43dd07f7 | 6246 | |
cd7a67a4 MCC |
6247 | if (state->m_b_power_down) { |
6248 | status = power_down_device(state); | |
ea90f011 | 6249 | if (status < 0) |
be44eb28 | 6250 | goto error; |
cd7a67a4 | 6251 | state->m_drxk_state = DRXK_POWERED_DOWN; |
be44eb28 | 6252 | } else |
cd7a67a4 | 6253 | state->m_drxk_state = DRXK_STOPPED; |
177bc7da MCC |
6254 | |
6255 | /* Initialize the supported delivery systems */ | |
6256 | n = 0; | |
cd7a67a4 | 6257 | if (state->m_has_dvbc) { |
177bc7da MCC |
6258 | state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; |
6259 | state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; | |
6260 | strlcat(state->frontend.ops.info.name, " DVB-C", | |
6261 | sizeof(state->frontend.ops.info.name)); | |
6262 | } | |
cd7a67a4 | 6263 | if (state->m_has_dvbt) { |
177bc7da MCC |
6264 | state->frontend.ops.delsys[n++] = SYS_DVBT; |
6265 | strlcat(state->frontend.ops.info.name, " DVB-T", | |
6266 | sizeof(state->frontend.ops.info.name)); | |
6267 | } | |
20bfe7ae | 6268 | drxk_i2c_unlock(state); |
43dd07f7 | 6269 | } |
be44eb28 | 6270 | error: |
20bfe7ae | 6271 | if (status < 0) { |
cd7a67a4 | 6272 | state->m_drxk_state = DRXK_NO_DEV; |
20bfe7ae | 6273 | drxk_i2c_unlock(state); |
3a4398f5 | 6274 | pr_err("Error %d on %s\n", status, __func__); |
20bfe7ae | 6275 | } |
43dd07f7 | 6276 | |
e716adac | 6277 | return status; |
43dd07f7 RM |
6278 | } |
6279 | ||
177bc7da MCC |
6280 | static void load_firmware_cb(const struct firmware *fw, |
6281 | void *context) | |
6282 | { | |
6283 | struct drxk_state *state = context; | |
6284 | ||
704a28e8 | 6285 | dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded"); |
177bc7da | 6286 | if (!fw) { |
3a4398f5 | 6287 | pr_err("Could not load firmware file %s.\n", |
177bc7da | 6288 | state->microcode_name); |
3a4398f5 | 6289 | pr_info("Copy %s to your hotplug directory!\n", |
177bc7da MCC |
6290 | state->microcode_name); |
6291 | state->microcode_name = NULL; | |
6292 | ||
6293 | /* | |
6294 | * As firmware is now load asynchronous, it is not possible | |
6295 | * anymore to fail at frontend attach. We might silently | |
6296 | * return here, and hope that the driver won't crash. | |
6297 | * We might also change all DVB callbacks to return -ENODEV | |
6298 | * if the device is not initialized. | |
6299 | * As the DRX-K devices have their own internal firmware, | |
6300 | * let's just hope that it will match a firmware revision | |
6301 | * compatible with this driver and proceed. | |
6302 | */ | |
6303 | } | |
6304 | state->fw = fw; | |
6305 | ||
6306 | init_drxk(state); | |
6307 | } | |
6308 | ||
fa4b2a17 | 6309 | static void drxk_release(struct dvb_frontend *fe) |
43dd07f7 | 6310 | { |
ebc7de22 OE |
6311 | struct drxk_state *state = fe->demodulator_priv; |
6312 | ||
2da67501 | 6313 | dprintk(1, "\n"); |
9bc2dd7e | 6314 | release_firmware(state->fw); |
177bc7da | 6315 | |
43dd07f7 RM |
6316 | kfree(state); |
6317 | } | |
6318 | ||
fa4b2a17 | 6319 | static int drxk_sleep(struct dvb_frontend *fe) |
43dd07f7 | 6320 | { |
ebc7de22 | 6321 | struct drxk_state *state = fe->demodulator_priv; |
43dd07f7 | 6322 | |
2da67501 | 6323 | dprintk(1, "\n"); |
704a28e8 | 6324 | |
cd7a67a4 | 6325 | if (state->m_drxk_state == DRXK_NO_DEV) |
704a28e8 | 6326 | return -ENODEV; |
cd7a67a4 | 6327 | if (state->m_drxk_state == DRXK_UNINITIALIZED) |
704a28e8 MCC |
6328 | return 0; |
6329 | ||
cd7a67a4 | 6330 | shut_down(state); |
43dd07f7 RM |
6331 | return 0; |
6332 | } | |
6333 | ||
ebc7de22 | 6334 | static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) |
43dd07f7 RM |
6335 | { |
6336 | struct drxk_state *state = fe->demodulator_priv; | |
6337 | ||
257ee97e | 6338 | dprintk(1, ": %s\n", enable ? "enable" : "disable"); |
704a28e8 | 6339 | |
cd7a67a4 | 6340 | if (state->m_drxk_state == DRXK_NO_DEV) |
704a28e8 MCC |
6341 | return -ENODEV; |
6342 | ||
43dd07f7 RM |
6343 | return ConfigureI2CBridge(state, enable ? true : false); |
6344 | } | |
6345 | ||
ed5452a2 | 6346 | static int drxk_set_parameters(struct dvb_frontend *fe) |
43dd07f7 | 6347 | { |
ed5452a2 | 6348 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
6cb393c8 | 6349 | u32 delsys = p->delivery_system, old_delsys; |
43dd07f7 RM |
6350 | struct drxk_state *state = fe->demodulator_priv; |
6351 | u32 IF; | |
6352 | ||
2da67501 | 6353 | dprintk(1, "\n"); |
8513e144 | 6354 | |
cd7a67a4 | 6355 | if (state->m_drxk_state == DRXK_NO_DEV) |
704a28e8 MCC |
6356 | return -ENODEV; |
6357 | ||
cd7a67a4 | 6358 | if (state->m_drxk_state == DRXK_UNINITIALIZED) |
704a28e8 MCC |
6359 | return -EAGAIN; |
6360 | ||
8513e144 | 6361 | if (!fe->ops.tuner_ops.get_if_frequency) { |
3a4398f5 | 6362 | pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n"); |
8513e144 MCC |
6363 | return -EINVAL; |
6364 | } | |
6365 | ||
fa4b2a17 MCC |
6366 | if (fe->ops.i2c_gate_ctrl) |
6367 | fe->ops.i2c_gate_ctrl(fe, 1); | |
6368 | if (fe->ops.tuner_ops.set_params) | |
6369 | fe->ops.tuner_ops.set_params(fe); | |
6370 | if (fe->ops.i2c_gate_ctrl) | |
6371 | fe->ops.i2c_gate_ctrl(fe, 0); | |
6cb393c8 MCC |
6372 | |
6373 | old_delsys = state->props.delivery_system; | |
fa4b2a17 MCC |
6374 | state->props = *p; |
6375 | ||
6cb393c8 | 6376 | if (old_delsys != delsys) { |
cd7a67a4 | 6377 | shut_down(state); |
6cb393c8 MCC |
6378 | switch (delsys) { |
6379 | case SYS_DVBC_ANNEX_A: | |
6380 | case SYS_DVBC_ANNEX_C: | |
cd7a67a4 | 6381 | if (!state->m_has_dvbc) |
6cb393c8 | 6382 | return -EINVAL; |
ab5060cd MCC |
6383 | state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? |
6384 | true : false; | |
6cb393c8 | 6385 | if (state->m_itut_annex_c) |
cd7a67a4 | 6386 | setoperation_mode(state, OM_QAM_ITU_C); |
6cb393c8 | 6387 | else |
cd7a67a4 | 6388 | setoperation_mode(state, OM_QAM_ITU_A); |
fa4b2a17 | 6389 | break; |
6cb393c8 | 6390 | case SYS_DVBT: |
cd7a67a4 | 6391 | if (!state->m_has_dvbt) |
6cb393c8 | 6392 | return -EINVAL; |
cd7a67a4 | 6393 | setoperation_mode(state, OM_DVBT); |
6cb393c8 MCC |
6394 | break; |
6395 | default: | |
fa4b2a17 | 6396 | return -EINVAL; |
6cb393c8 | 6397 | } |
2440f7af | 6398 | } |
8513e144 | 6399 | |
8513e144 | 6400 | fe->ops.tuner_ops.get_if_frequency(fe, &IF); |
cd7a67a4 | 6401 | start(state, 0, IF); |
43dd07f7 | 6402 | |
39c1cb2b | 6403 | /* After set_frontend, stats aren't available */ |
8f3741e0 MCC |
6404 | p->strength.stat[0].scale = FE_SCALE_RELATIVE; |
6405 | p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6406 | p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6407 | p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6408 | p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6409 | p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6410 | p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6411 | p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6412 | ||
e0e6ecaf | 6413 | /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */ |
ebc7de22 | 6414 | |
43dd07f7 RM |
6415 | return 0; |
6416 | } | |
6417 | ||
59a7a23c MCC |
6418 | static int get_strength(struct drxk_state *state, u64 *strength) |
6419 | { | |
6420 | int status; | |
cd7a67a4 MCC |
6421 | struct s_cfg_agc rf_agc, if_agc; |
6422 | u32 total_gain = 0; | |
59a7a23c | 6423 | u32 atten = 0; |
cd7a67a4 | 6424 | u32 agc_range = 0; |
59a7a23c MCC |
6425 | u16 scu_lvl = 0; |
6426 | u16 scu_coc = 0; | |
6427 | /* FIXME: those are part of the tuner presets */ | |
cd7a67a4 MCC |
6428 | u16 tuner_rf_gain = 50; /* Default value on az6007 driver */ |
6429 | u16 tuner_if_gain = 40; /* Default value on az6007 driver */ | |
59a7a23c MCC |
6430 | |
6431 | *strength = 0; | |
6432 | ||
cd7a67a4 MCC |
6433 | if (is_dvbt(state)) { |
6434 | rf_agc = state->m_dvbt_rf_agc_cfg; | |
6435 | if_agc = state->m_dvbt_if_agc_cfg; | |
6436 | } else if (is_qam(state)) { | |
6437 | rf_agc = state->m_qam_rf_agc_cfg; | |
6438 | if_agc = state->m_qam_if_agc_cfg; | |
59a7a23c | 6439 | } else { |
cd7a67a4 MCC |
6440 | rf_agc = state->m_atv_rf_agc_cfg; |
6441 | if_agc = state->m_atv_if_agc_cfg; | |
59a7a23c MCC |
6442 | } |
6443 | ||
cd7a67a4 MCC |
6444 | if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) { |
6445 | /* SCU output_level */ | |
59a7a23c MCC |
6446 | status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl); |
6447 | if (status < 0) | |
6448 | return status; | |
6449 | ||
6450 | /* SCU c.o.c. */ | |
6451 | read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc); | |
6452 | if (status < 0) | |
6453 | return status; | |
6454 | ||
6455 | if (((u32) scu_lvl + (u32) scu_coc) < 0xffff) | |
cd7a67a4 | 6456 | rf_agc.output_level = scu_lvl + scu_coc; |
59a7a23c | 6457 | else |
cd7a67a4 | 6458 | rf_agc.output_level = 0xffff; |
59a7a23c MCC |
6459 | |
6460 | /* Take RF gain into account */ | |
cd7a67a4 | 6461 | total_gain += tuner_rf_gain; |
59a7a23c MCC |
6462 | |
6463 | /* clip output value */ | |
cd7a67a4 MCC |
6464 | if (rf_agc.output_level < rf_agc.min_output_level) |
6465 | rf_agc.output_level = rf_agc.min_output_level; | |
6466 | if (rf_agc.output_level > rf_agc.max_output_level) | |
6467 | rf_agc.output_level = rf_agc.max_output_level; | |
59a7a23c | 6468 | |
cd7a67a4 MCC |
6469 | agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level); |
6470 | if (agc_range > 0) { | |
59a7a23c | 6471 | atten += 100UL * |
cd7a67a4 MCC |
6472 | ((u32)(tuner_rf_gain)) * |
6473 | ((u32)(rf_agc.output_level - rf_agc.min_output_level)) | |
6474 | / agc_range; | |
59a7a23c MCC |
6475 | } |
6476 | } | |
6477 | ||
cd7a67a4 | 6478 | if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) { |
59a7a23c | 6479 | status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A, |
cd7a67a4 | 6480 | &if_agc.output_level); |
59a7a23c MCC |
6481 | if (status < 0) |
6482 | return status; | |
6483 | ||
6484 | status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, | |
cd7a67a4 | 6485 | &if_agc.top); |
59a7a23c MCC |
6486 | if (status < 0) |
6487 | return status; | |
6488 | ||
6489 | /* Take IF gain into account */ | |
cd7a67a4 | 6490 | total_gain += (u32) tuner_if_gain; |
59a7a23c MCC |
6491 | |
6492 | /* clip output value */ | |
cd7a67a4 MCC |
6493 | if (if_agc.output_level < if_agc.min_output_level) |
6494 | if_agc.output_level = if_agc.min_output_level; | |
6495 | if (if_agc.output_level > if_agc.max_output_level) | |
6496 | if_agc.output_level = if_agc.max_output_level; | |
59a7a23c | 6497 | |
ab5060cd | 6498 | agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level); |
cd7a67a4 | 6499 | if (agc_range > 0) { |
59a7a23c | 6500 | atten += 100UL * |
cd7a67a4 MCC |
6501 | ((u32)(tuner_if_gain)) * |
6502 | ((u32)(if_agc.output_level - if_agc.min_output_level)) | |
6503 | / agc_range; | |
59a7a23c MCC |
6504 | } |
6505 | } | |
6506 | ||
6507 | /* | |
6508 | * Convert to 0..65535 scale. | |
6509 | * If it can't be measured (AGC is disabled), just show 100%. | |
6510 | */ | |
cd7a67a4 MCC |
6511 | if (total_gain > 0) |
6512 | *strength = (65535UL * atten / total_gain / 100); | |
59a7a23c MCC |
6513 | else |
6514 | *strength = 65535; | |
6515 | ||
6516 | return 0; | |
6517 | } | |
6518 | ||
8f3741e0 | 6519 | static int drxk_get_stats(struct dvb_frontend *fe) |
43dd07f7 | 6520 | { |
8f3741e0 | 6521 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
43dd07f7 | 6522 | struct drxk_state *state = fe->demodulator_priv; |
8f3741e0 | 6523 | int status; |
43dd07f7 | 6524 | u32 stat; |
8f3741e0 MCC |
6525 | u16 reg16; |
6526 | u32 post_bit_count; | |
6527 | u32 post_bit_err_count; | |
6528 | u32 post_bit_error_scale; | |
6529 | u32 pre_bit_err_count; | |
6530 | u32 pre_bit_count; | |
6531 | u32 pkt_count; | |
6532 | u32 pkt_error_count; | |
59a7a23c | 6533 | s32 cnr; |
704a28e8 | 6534 | |
cd7a67a4 | 6535 | if (state->m_drxk_state == DRXK_NO_DEV) |
704a28e8 | 6536 | return -ENODEV; |
cd7a67a4 | 6537 | if (state->m_drxk_state == DRXK_UNINITIALIZED) |
704a28e8 MCC |
6538 | return -EAGAIN; |
6539 | ||
8f3741e0 MCC |
6540 | /* get status */ |
6541 | state->fe_status = 0; | |
cd7a67a4 | 6542 | get_lock_status(state, &stat); |
ebc7de22 | 6543 | if (stat == MPEG_LOCK) |
8f3741e0 | 6544 | state->fe_status |= 0x1f; |
ebc7de22 | 6545 | if (stat == FEC_LOCK) |
8f3741e0 | 6546 | state->fe_status |= 0x0f; |
ebc7de22 | 6547 | if (stat == DEMOD_LOCK) |
8f3741e0 MCC |
6548 | state->fe_status |= 0x07; |
6549 | ||
59a7a23c MCC |
6550 | /* |
6551 | * Estimate signal strength from AGC | |
6552 | */ | |
6553 | get_strength(state, &c->strength.stat[0].uvalue); | |
6554 | c->strength.stat[0].scale = FE_SCALE_RELATIVE; | |
6555 | ||
6556 | ||
8f3741e0 | 6557 | if (stat >= DEMOD_LOCK) { |
cd7a67a4 | 6558 | get_signal_to_noise(state, &cnr); |
8f3741e0 MCC |
6559 | c->cnr.stat[0].svalue = cnr * 100; |
6560 | c->cnr.stat[0].scale = FE_SCALE_DECIBEL; | |
6561 | } else { | |
6562 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6563 | } | |
6564 | ||
6565 | if (stat < FEC_LOCK) { | |
6566 | c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6567 | c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6568 | c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6569 | c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6570 | c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6571 | c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6572 | return 0; | |
6573 | } | |
6574 | ||
6575 | /* Get post BER */ | |
6576 | ||
6577 | /* BER measurement is valid if at least FEC lock is achieved */ | |
6578 | ||
ab5060cd MCC |
6579 | /* |
6580 | * OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be | |
6581 | * written to set nr of symbols or bits over which to measure | |
6582 | * EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg(). | |
6583 | */ | |
8f3741e0 MCC |
6584 | |
6585 | /* Read registers for post/preViterbi BER calculation */ | |
6586 | status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16); | |
6587 | if (status < 0) | |
6588 | goto error; | |
6589 | pre_bit_err_count = reg16; | |
6590 | ||
6591 | status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16); | |
6592 | if (status < 0) | |
6593 | goto error; | |
6594 | pre_bit_count = reg16; | |
6595 | ||
6596 | /* Number of bit-errors */ | |
6597 | status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16); | |
6598 | if (status < 0) | |
6599 | goto error; | |
6600 | post_bit_err_count = reg16; | |
6601 | ||
6602 | status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16); | |
6603 | if (status < 0) | |
6604 | goto error; | |
6605 | post_bit_error_scale = reg16; | |
6606 | ||
6607 | status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16); | |
6608 | if (status < 0) | |
6609 | goto error; | |
6610 | pkt_count = reg16; | |
6611 | ||
6612 | status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16); | |
6613 | if (status < 0) | |
6614 | goto error; | |
6615 | pkt_error_count = reg16; | |
6616 | write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); | |
6617 | ||
6618 | post_bit_err_count *= post_bit_error_scale; | |
6619 | ||
6620 | post_bit_count = pkt_count * 204 * 8; | |
6621 | ||
6622 | /* Store the results */ | |
6623 | c->block_error.stat[0].scale = FE_SCALE_COUNTER; | |
6624 | c->block_error.stat[0].uvalue += pkt_error_count; | |
6625 | c->block_count.stat[0].scale = FE_SCALE_COUNTER; | |
6626 | c->block_count.stat[0].uvalue += pkt_count; | |
6627 | ||
6628 | c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; | |
6629 | c->pre_bit_error.stat[0].uvalue += pre_bit_err_count; | |
6630 | c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; | |
6631 | c->pre_bit_count.stat[0].uvalue += pre_bit_count; | |
6632 | ||
6633 | c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; | |
6634 | c->post_bit_error.stat[0].uvalue += post_bit_err_count; | |
6635 | c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; | |
6636 | c->post_bit_count.stat[0].uvalue += post_bit_count; | |
6637 | ||
8f3741e0 MCC |
6638 | error: |
6639 | return status; | |
6640 | } | |
6641 | ||
6642 | ||
0df289a2 | 6643 | static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status) |
8f3741e0 MCC |
6644 | { |
6645 | struct drxk_state *state = fe->demodulator_priv; | |
6646 | int rc; | |
6647 | ||
6648 | dprintk(1, "\n"); | |
6649 | ||
6650 | rc = drxk_get_stats(fe); | |
6651 | if (rc < 0) | |
6652 | return rc; | |
6653 | ||
6654 | *status = state->fe_status; | |
6655 | ||
43dd07f7 RM |
6656 | return 0; |
6657 | } | |
6658 | ||
ebc7de22 OE |
6659 | static int drxk_read_signal_strength(struct dvb_frontend *fe, |
6660 | u16 *strength) | |
43dd07f7 RM |
6661 | { |
6662 | struct drxk_state *state = fe->demodulator_priv; | |
340e7696 | 6663 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
43dd07f7 | 6664 | |
2da67501 | 6665 | dprintk(1, "\n"); |
704a28e8 | 6666 | |
cd7a67a4 | 6667 | if (state->m_drxk_state == DRXK_NO_DEV) |
704a28e8 | 6668 | return -ENODEV; |
cd7a67a4 | 6669 | if (state->m_drxk_state == DRXK_UNINITIALIZED) |
704a28e8 MCC |
6670 | return -EAGAIN; |
6671 | ||
340e7696 | 6672 | *strength = c->strength.stat[0].uvalue; |
43dd07f7 RM |
6673 | return 0; |
6674 | } | |
6675 | ||
6676 | static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) | |
6677 | { | |
6678 | struct drxk_state *state = fe->demodulator_priv; | |
6679 | s32 snr2; | |
6680 | ||
2da67501 | 6681 | dprintk(1, "\n"); |
704a28e8 | 6682 | |
cd7a67a4 | 6683 | if (state->m_drxk_state == DRXK_NO_DEV) |
704a28e8 | 6684 | return -ENODEV; |
cd7a67a4 | 6685 | if (state->m_drxk_state == DRXK_UNINITIALIZED) |
704a28e8 MCC |
6686 | return -EAGAIN; |
6687 | ||
cd7a67a4 | 6688 | get_signal_to_noise(state, &snr2); |
8f3741e0 MCC |
6689 | |
6690 | /* No negative SNR, clip to zero */ | |
6691 | if (snr2 < 0) | |
6692 | snr2 = 0; | |
ebc7de22 | 6693 | *snr = snr2 & 0xffff; |
43dd07f7 RM |
6694 | return 0; |
6695 | } | |
6696 | ||
6697 | static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) | |
6698 | { | |
6699 | struct drxk_state *state = fe->demodulator_priv; | |
6700 | u16 err; | |
6701 | ||
2da67501 | 6702 | dprintk(1, "\n"); |
704a28e8 | 6703 | |
cd7a67a4 | 6704 | if (state->m_drxk_state == DRXK_NO_DEV) |
704a28e8 | 6705 | return -ENODEV; |
cd7a67a4 | 6706 | if (state->m_drxk_state == DRXK_UNINITIALIZED) |
704a28e8 MCC |
6707 | return -EAGAIN; |
6708 | ||
cd7a67a4 | 6709 | dvbtqam_get_acc_pkt_err(state, &err); |
43dd07f7 RM |
6710 | *ucblocks = (u32) err; |
6711 | return 0; | |
6712 | } | |
6713 | ||
ab5060cd MCC |
6714 | static int drxk_get_tune_settings(struct dvb_frontend *fe, |
6715 | struct dvb_frontend_tune_settings *sets) | |
43dd07f7 | 6716 | { |
704a28e8 | 6717 | struct drxk_state *state = fe->demodulator_priv; |
fa4b2a17 | 6718 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
2da67501 MCC |
6719 | |
6720 | dprintk(1, "\n"); | |
704a28e8 | 6721 | |
cd7a67a4 | 6722 | if (state->m_drxk_state == DRXK_NO_DEV) |
704a28e8 | 6723 | return -ENODEV; |
cd7a67a4 | 6724 | if (state->m_drxk_state == DRXK_UNINITIALIZED) |
704a28e8 MCC |
6725 | return -EAGAIN; |
6726 | ||
fa4b2a17 MCC |
6727 | switch (p->delivery_system) { |
6728 | case SYS_DVBC_ANNEX_A: | |
6729 | case SYS_DVBC_ANNEX_C: | |
dc66d7f4 | 6730 | case SYS_DVBT: |
fa4b2a17 MCC |
6731 | sets->min_delay_ms = 3000; |
6732 | sets->max_drift = 0; | |
6733 | sets->step_size = 0; | |
6734 | return 0; | |
6735 | default: | |
fa4b2a17 MCC |
6736 | return -EINVAL; |
6737 | } | |
43dd07f7 RM |
6738 | } |
6739 | ||
fa4b2a17 MCC |
6740 | static struct dvb_frontend_ops drxk_ops = { |
6741 | /* .delsys will be filled dynamically */ | |
43dd07f7 | 6742 | .info = { |
fa4b2a17 MCC |
6743 | .name = "DRXK", |
6744 | .frequency_min = 47000000, | |
6745 | .frequency_max = 865000000, | |
6746 | /* For DVB-C */ | |
6747 | .symbol_rate_min = 870000, | |
6748 | .symbol_rate_max = 11700000, | |
6749 | /* For DVB-T */ | |
6750 | .frequency_stepsize = 166667, | |
6751 | ||
6752 | .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | | |
6753 | FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO | | |
6754 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
6755 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS | | |
6756 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER | | |
6757 | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | |
6758 | }, | |
6759 | ||
6760 | .release = drxk_release, | |
6761 | .sleep = drxk_sleep, | |
43dd07f7 RM |
6762 | .i2c_gate_ctrl = drxk_gate_ctrl, |
6763 | ||
ed5452a2 | 6764 | .set_frontend = drxk_set_parameters, |
fa4b2a17 | 6765 | .get_tune_settings = drxk_get_tune_settings, |
43dd07f7 RM |
6766 | |
6767 | .read_status = drxk_read_status, | |
43dd07f7 RM |
6768 | .read_signal_strength = drxk_read_signal_strength, |
6769 | .read_snr = drxk_read_snr, | |
6770 | .read_ucblocks = drxk_read_ucblocks, | |
6771 | }; | |
6772 | ||
0fc55e81 | 6773 | struct dvb_frontend *drxk_attach(const struct drxk_config *config, |
fa4b2a17 | 6774 | struct i2c_adapter *i2c) |
43dd07f7 | 6775 | { |
8f3741e0 | 6776 | struct dtv_frontend_properties *p; |
43dd07f7 | 6777 | struct drxk_state *state = NULL; |
0fc55e81 | 6778 | u8 adr = config->adr; |
177bc7da | 6779 | int status; |
43dd07f7 | 6780 | |
2da67501 | 6781 | dprintk(1, "\n"); |
ebc7de22 | 6782 | state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL); |
43dd07f7 RM |
6783 | if (!state) |
6784 | return NULL; | |
6785 | ||
ebc7de22 OE |
6786 | state->i2c = i2c; |
6787 | state->demod_address = adr; | |
e076c92e | 6788 | state->single_master = config->single_master; |
e4f4f875 | 6789 | state->microcode_name = config->microcode_name; |
9e23f50a | 6790 | state->qam_demod_parameter_count = config->qam_demod_parameter_count; |
f1fe1b75 | 6791 | state->no_i2c_bridge = config->no_i2c_bridge; |
90796aca MCC |
6792 | state->antenna_gpio = config->antenna_gpio; |
6793 | state->antenna_dvbt = config->antenna_dvbt; | |
cd7a67a4 | 6794 | state->m_chunk_size = config->chunk_size; |
d5856813 | 6795 | state->enable_merr_cfg = config->enable_merr_cfg; |
90796aca | 6796 | |
67f04617 | 6797 | if (config->dynamic_clk) { |
5a7f7b79 MCC |
6798 | state->m_dvbt_static_clk = false; |
6799 | state->m_dvbc_static_clk = false; | |
67f04617 | 6800 | } else { |
5a7f7b79 MCC |
6801 | state->m_dvbt_static_clk = true; |
6802 | state->m_dvbc_static_clk = true; | |
67f04617 MCC |
6803 | } |
6804 | ||
6fb65a66 MCC |
6805 | |
6806 | if (config->mpeg_out_clk_strength) | |
cd7a67a4 | 6807 | state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07; |
6fb65a66 | 6808 | else |
cd7a67a4 | 6809 | state->m_ts_clockk_strength = 0x06; |
6fb65a66 | 6810 | |
534e0481 | 6811 | if (config->parallel_ts) |
cd7a67a4 | 6812 | state->m_enable_parallel = true; |
534e0481 | 6813 | else |
cd7a67a4 | 6814 | state->m_enable_parallel = false; |
534e0481 | 6815 | |
90796aca | 6816 | /* NOTE: as more UIO bits will be used, add them to the mask */ |
cd7a67a4 | 6817 | state->uio_mask = config->antenna_gpio; |
90796aca MCC |
6818 | |
6819 | /* Default gpio to DVB-C */ | |
6820 | if (!state->antenna_dvbt && state->antenna_gpio) | |
cd7a67a4 | 6821 | state->m_gpio |= state->antenna_gpio; |
90796aca | 6822 | else |
cd7a67a4 | 6823 | state->m_gpio &= ~state->antenna_gpio; |
43dd07f7 RM |
6824 | |
6825 | mutex_init(&state->mutex); | |
43dd07f7 | 6826 | |
fa4b2a17 MCC |
6827 | memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); |
6828 | state->frontend.demodulator_priv = state; | |
43dd07f7 RM |
6829 | |
6830 | init_state(state); | |
cf694b14 | 6831 | |
177bc7da MCC |
6832 | /* Load firmware and initialize DRX-K */ |
6833 | if (state->microcode_name) { | |
4b819724 | 6834 | const struct firmware *fw = NULL; |
8e30783b | 6835 | |
4b819724 MCC |
6836 | status = request_firmware(&fw, state->microcode_name, |
6837 | state->i2c->dev.parent); | |
6838 | if (status < 0) | |
6839 | fw = NULL; | |
6840 | load_firmware_cb(fw, state); | |
177bc7da MCC |
6841 | } else if (init_drxk(state) < 0) |
6842 | goto error; | |
0d3e6fe7 | 6843 | |
8f3741e0 MCC |
6844 | |
6845 | /* Initialize stats */ | |
6846 | p = &state->frontend.dtv_property_cache; | |
6847 | p->strength.len = 1; | |
6848 | p->cnr.len = 1; | |
6849 | p->block_error.len = 1; | |
6850 | p->block_count.len = 1; | |
6851 | p->pre_bit_error.len = 1; | |
6852 | p->pre_bit_count.len = 1; | |
6853 | p->post_bit_error.len = 1; | |
6854 | p->post_bit_count.len = 1; | |
6855 | ||
6856 | p->strength.stat[0].scale = FE_SCALE_RELATIVE; | |
6857 | p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6858 | p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6859 | p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6860 | p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6861 | p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6862 | p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6863 | p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
6864 | ||
3a4398f5 | 6865 | pr_info("frontend initialized.\n"); |
fa4b2a17 | 6866 | return &state->frontend; |
43dd07f7 RM |
6867 | |
6868 | error: | |
3a4398f5 | 6869 | pr_err("not found\n"); |
43dd07f7 RM |
6870 | kfree(state); |
6871 | return NULL; | |
6872 | } | |
ebc7de22 | 6873 | EXPORT_SYMBOL(drxk_attach); |
43dd07f7 RM |
6874 | |
6875 | MODULE_DESCRIPTION("DRX-K driver"); | |
6876 | MODULE_AUTHOR("Ralph Metzler"); | |
6877 | MODULE_LICENSE("GPL"); |