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ca19aaa5 PB |
1 | /* |
2 | * Driver for the Integrant ITD1000 "Zero-IF Tuner IC for Direct Broadcast Satellite" | |
3 | * | |
4 | * Copyright (c) 2007-8 Patrick Boettcher <pb@linuxtv.org> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/dvb/frontend.h> | |
26 | #include <linux/i2c.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
ca19aaa5 PB |
28 | |
29 | #include "dvb_frontend.h" | |
30 | ||
31 | #include "itd1000.h" | |
32 | #include "itd1000_priv.h" | |
33 | ||
8393796d MCC |
34 | /* Max transfer size done by I2C transfer functions */ |
35 | #define MAX_XFER_SIZE 64 | |
36 | ||
ca19aaa5 PB |
37 | static int debug; |
38 | module_param(debug, int, 0644); | |
39 | MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off)."); | |
40 | ||
a5bef1d2 | 41 | #define itd_dbg(args...) do { \ |
ca19aaa5 PB |
42 | if (debug) { \ |
43 | printk(KERN_DEBUG "ITD1000: " args);\ | |
ca19aaa5 PB |
44 | } \ |
45 | } while (0) | |
46 | ||
a5bef1d2 | 47 | #define itd_warn(args...) do { \ |
ca19aaa5 | 48 | printk(KERN_WARNING "ITD1000: " args); \ |
ca19aaa5 PB |
49 | } while (0) |
50 | ||
a5bef1d2 | 51 | #define itd_info(args...) do { \ |
ca19aaa5 | 52 | printk(KERN_INFO "ITD1000: " args); \ |
ca19aaa5 PB |
53 | } while (0) |
54 | ||
55 | /* don't write more than one byte with flexcop behind */ | |
56 | static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len) | |
57 | { | |
8393796d | 58 | u8 buf[MAX_XFER_SIZE]; |
ca19aaa5 PB |
59 | struct i2c_msg msg = { |
60 | .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1 | |
61 | }; | |
8393796d MCC |
62 | |
63 | if (1 + len > sizeof(buf)) { | |
64 | printk(KERN_WARNING | |
65 | "itd1000: i2c wr reg=%04x: len=%d is too big!\n", | |
66 | reg, len); | |
67 | return -EINVAL; | |
68 | } | |
69 | ||
ca19aaa5 PB |
70 | buf[0] = reg; |
71 | memcpy(&buf[1], v, len); | |
72 | ||
a5bef1d2 | 73 | /* itd_dbg("wr %02x: %02x\n", reg, v[0]); */ |
ca19aaa5 PB |
74 | |
75 | if (i2c_transfer(state->i2c, &msg, 1) != 1) { | |
76 | printk(KERN_WARNING "itd1000 I2C write failed\n"); | |
77 | return -EREMOTEIO; | |
78 | } | |
79 | return 0; | |
80 | } | |
81 | ||
82 | static int itd1000_read_reg(struct itd1000_state *state, u8 reg) | |
83 | { | |
84 | u8 val; | |
85 | struct i2c_msg msg[2] = { | |
86 | { .addr = state->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 }, | |
87 | { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 }, | |
88 | }; | |
89 | ||
90 | /* ugly flexcop workaround */ | |
91 | itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1); | |
92 | ||
93 | if (i2c_transfer(state->i2c, msg, 2) != 2) { | |
a5bef1d2 | 94 | itd_warn("itd1000 I2C read failed\n"); |
ca19aaa5 PB |
95 | return -EREMOTEIO; |
96 | } | |
97 | return val; | |
98 | } | |
99 | ||
100 | static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v) | |
101 | { | |
102 | int ret = itd1000_write_regs(state, r, &v, 1); | |
103 | state->shadow[r] = v; | |
104 | return ret; | |
105 | } | |
106 | ||
107 | ||
108 | static struct { | |
109 | u32 symbol_rate; | |
110 | u8 pgaext : 4; /* PLLFH */ | |
111 | u8 bbgvmin : 4; /* BBGVMIN */ | |
112 | } itd1000_lpf_pga[] = { | |
113 | { 0, 0x8, 0x3 }, | |
114 | { 5200000, 0x8, 0x3 }, | |
115 | { 12200000, 0x4, 0x3 }, | |
116 | { 15400000, 0x2, 0x3 }, | |
117 | { 19800000, 0x2, 0x3 }, | |
118 | { 21500000, 0x2, 0x3 }, | |
119 | { 24500000, 0x2, 0x3 }, | |
120 | { 28400000, 0x2, 0x3 }, | |
121 | { 33400000, 0x2, 0x3 }, | |
122 | { 34400000, 0x1, 0x4 }, | |
123 | { 34400000, 0x1, 0x4 }, | |
124 | { 38400000, 0x1, 0x4 }, | |
125 | { 38400000, 0x1, 0x4 }, | |
126 | { 40400000, 0x1, 0x4 }, | |
127 | { 45400000, 0x1, 0x4 }, | |
128 | }; | |
129 | ||
130 | static void itd1000_set_lpf_bw(struct itd1000_state *state, u32 symbol_rate) | |
131 | { | |
132 | u8 i; | |
133 | u8 con1 = itd1000_read_reg(state, CON1) & 0xfd; | |
134 | u8 pllfh = itd1000_read_reg(state, PLLFH) & 0x0f; | |
135 | u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0; | |
136 | u8 bw = itd1000_read_reg(state, BW) & 0xf0; | |
137 | ||
a5bef1d2 | 138 | itd_dbg("symbol_rate = %d\n", symbol_rate); |
ca19aaa5 PB |
139 | |
140 | /* not sure what is that ? - starting to download the table */ | |
141 | itd1000_write_reg(state, CON1, con1 | (1 << 1)); | |
142 | ||
143 | for (i = 0; i < ARRAY_SIZE(itd1000_lpf_pga); i++) | |
144 | if (symbol_rate < itd1000_lpf_pga[i].symbol_rate) { | |
a5bef1d2 | 145 | itd_dbg("symrate: index: %d pgaext: %x, bbgvmin: %x\n", i, itd1000_lpf_pga[i].pgaext, itd1000_lpf_pga[i].bbgvmin); |
ca19aaa5 PB |
146 | itd1000_write_reg(state, PLLFH, pllfh | (itd1000_lpf_pga[i].pgaext << 4)); |
147 | itd1000_write_reg(state, BBGVMIN, bbgvmin | (itd1000_lpf_pga[i].bbgvmin)); | |
148 | itd1000_write_reg(state, BW, bw | (i & 0x0f)); | |
149 | break; | |
150 | } | |
151 | ||
152 | itd1000_write_reg(state, CON1, con1 | (0 << 1)); | |
153 | } | |
154 | ||
155 | static struct { | |
156 | u8 vcorg; | |
157 | u32 fmax_rg; | |
158 | } itd1000_vcorg[] = { | |
159 | { 1, 920000 }, | |
160 | { 2, 971000 }, | |
161 | { 3, 1031000 }, | |
162 | { 4, 1091000 }, | |
163 | { 5, 1171000 }, | |
164 | { 6, 1281000 }, | |
165 | { 7, 1381000 }, | |
166 | { 8, 500000 }, /* this is intentional. */ | |
167 | { 9, 1451000 }, | |
168 | { 10, 1531000 }, | |
169 | { 11, 1631000 }, | |
170 | { 12, 1741000 }, | |
171 | { 13, 1891000 }, | |
172 | { 14, 2071000 }, | |
173 | { 15, 2250000 }, | |
174 | }; | |
175 | ||
176 | static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz) | |
177 | { | |
178 | u8 i; | |
179 | u8 gvbb_i2c = itd1000_read_reg(state, GVBB_I2C) & 0xbf; | |
180 | u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f; | |
181 | u8 adcout; | |
182 | ||
183 | /* reserved bit again (reset ?) */ | |
184 | itd1000_write_reg(state, GVBB_I2C, gvbb_i2c | (1 << 6)); | |
185 | ||
186 | for (i = 0; i < ARRAY_SIZE(itd1000_vcorg); i++) { | |
187 | if (freq_khz < itd1000_vcorg[i].fmax_rg) { | |
188 | itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | (itd1000_vcorg[i].vcorg << 4)); | |
189 | msleep(1); | |
190 | ||
191 | adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f; | |
192 | ||
a5bef1d2 | 193 | itd_dbg("VCO: %dkHz: %d -> ADCOUT: %d %02x\n", freq_khz, itd1000_vcorg[i].vcorg, adcout, vco_chp1_i2c); |
ca19aaa5 PB |
194 | |
195 | if (adcout > 13) { | |
196 | if (!(itd1000_vcorg[i].vcorg == 7 || itd1000_vcorg[i].vcorg == 15)) | |
197 | itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg + 1) << 4)); | |
198 | } else if (adcout < 2) { | |
199 | if (!(itd1000_vcorg[i].vcorg == 1 || itd1000_vcorg[i].vcorg == 9)) | |
200 | itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg - 1) << 4)); | |
201 | } | |
202 | break; | |
203 | } | |
204 | } | |
205 | } | |
206 | ||
4ed83b51 | 207 | static const struct { |
ca19aaa5 PB |
208 | u32 freq; |
209 | u8 values[10]; /* RFTR, RFST1 - RFST9 */ | |
210 | } itd1000_fre_values[] = { | |
211 | { 1075000, { 0x59, 0x1d, 0x1c, 0x17, 0x16, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, | |
212 | { 1250000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, | |
213 | { 1450000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, | |
214 | { 1650000, { 0x69, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, | |
215 | { 1750000, { 0x69, 0x1e, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, | |
216 | { 1850000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } }, | |
217 | { 1900000, { 0x69, 0x1d, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } }, | |
218 | { 1950000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0d, 0x0b, 0x0a } }, | |
219 | { 2050000, { 0x69, 0x1e, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0b, 0x0a } }, | |
220 | { 2150000, { 0x69, 0x1d, 0x1c, 0x17, 0x15, 0x14, 0x13, 0x0f, 0x0e, 0x0b } } | |
221 | }; | |
222 | ||
223 | ||
224 | #define FREF 16 | |
225 | ||
226 | static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz) | |
227 | { | |
228 | int i, j; | |
229 | u32 plln, pllf; | |
230 | u64 tmp; | |
231 | ||
232 | plln = (freq_khz * 1000) / 2 / FREF; | |
233 | ||
234 | /* Compute the factional part times 1000 */ | |
235 | tmp = plln % 1000000; | |
236 | plln /= 1000000; | |
237 | ||
238 | tmp *= 1048576; | |
239 | do_div(tmp, 1000000); | |
240 | pllf = (u32) tmp; | |
241 | ||
242 | state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF; | |
a5bef1d2 | 243 | itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln); |
ca19aaa5 | 244 | |
1c4bbfd1 | 245 | itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */ |
ca19aaa5 PB |
246 | itd1000_write_reg(state, PLLNL, plln & 0xff); |
247 | itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f)); | |
248 | itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff); | |
249 | itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff); | |
250 | ||
251 | for (i = 0; i < ARRAY_SIZE(itd1000_fre_values); i++) { | |
252 | if (freq_khz <= itd1000_fre_values[i].freq) { | |
a5bef1d2 | 253 | itd_dbg("fre_values: %d\n", i); |
ca19aaa5 PB |
254 | itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]); |
255 | for (j = 0; j < 9; j++) | |
256 | itd1000_write_reg(state, RFST1+j, itd1000_fre_values[i].values[j+1]); | |
257 | break; | |
258 | } | |
259 | } | |
260 | ||
261 | itd1000_set_vco(state, freq_khz); | |
262 | } | |
263 | ||
14d24d14 | 264 | static int itd1000_set_parameters(struct dvb_frontend *fe) |
ca19aaa5 | 265 | { |
ab3eee07 | 266 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
ca19aaa5 PB |
267 | struct itd1000_state *state = fe->tuner_priv; |
268 | u8 pllcon1; | |
269 | ||
ab3eee07 MCC |
270 | itd1000_set_lo(state, c->frequency); |
271 | itd1000_set_lpf_bw(state, c->symbol_rate); | |
ca19aaa5 PB |
272 | |
273 | pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f; | |
274 | itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7)); | |
275 | itd1000_write_reg(state, PLLCON1, pllcon1); | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
280 | static int itd1000_get_frequency(struct dvb_frontend *fe, u32 *frequency) | |
281 | { | |
282 | struct itd1000_state *state = fe->tuner_priv; | |
283 | *frequency = state->frequency; | |
284 | return 0; | |
285 | } | |
286 | ||
287 | static int itd1000_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) | |
288 | { | |
289 | return 0; | |
290 | } | |
291 | ||
292 | static u8 itd1000_init_tab[][2] = { | |
293 | { PLLCON1, 0x65 }, /* Register does not change */ | |
294 | { PLLNH, 0x80 }, /* Bits [7:6] do not change */ | |
295 | { RESERVED_0X6D, 0x3b }, | |
296 | { VCO_CHP2_I2C, 0x12 }, | |
297 | { 0x72, 0xf9 }, /* No such regsister defined */ | |
298 | { RESERVED_0X73, 0xff }, | |
299 | { RESERVED_0X74, 0xb2 }, | |
300 | { RESERVED_0X75, 0xc7 }, | |
301 | { EXTGVBBRF, 0xf0 }, | |
302 | { DIVAGCCK, 0x80 }, | |
303 | { BBTR, 0xa0 }, | |
304 | { RESERVED_0X7E, 0x4f }, | |
305 | { 0x82, 0x88 }, /* No such regsister defined */ | |
306 | { 0x83, 0x80 }, /* No such regsister defined */ | |
307 | { 0x84, 0x80 }, /* No such regsister defined */ | |
308 | { RESERVED_0X85, 0x74 }, | |
309 | { RESERVED_0X86, 0xff }, | |
310 | { RESERVED_0X88, 0x02 }, | |
311 | { RESERVED_0X89, 0x16 }, | |
312 | { RFST0, 0x1f }, | |
313 | { RESERVED_0X94, 0x66 }, | |
314 | { RESERVED_0X95, 0x66 }, | |
315 | { RESERVED_0X96, 0x77 }, | |
316 | { RESERVED_0X97, 0x99 }, | |
317 | { RESERVED_0X98, 0xff }, | |
318 | { RESERVED_0X99, 0xfc }, | |
319 | { RESERVED_0X9A, 0xba }, | |
320 | { RESERVED_0X9B, 0xaa }, | |
321 | }; | |
322 | ||
323 | static u8 itd1000_reinit_tab[][2] = { | |
324 | { VCO_CHP1_I2C, 0x8a }, | |
325 | { BW, 0x87 }, | |
326 | { GVBB_I2C, 0x03 }, | |
327 | { BBGVMIN, 0x03 }, | |
328 | { CON1, 0x2e }, | |
329 | }; | |
330 | ||
331 | ||
332 | static int itd1000_init(struct dvb_frontend *fe) | |
333 | { | |
334 | struct itd1000_state *state = fe->tuner_priv; | |
335 | int i; | |
336 | ||
337 | for (i = 0; i < ARRAY_SIZE(itd1000_init_tab); i++) | |
338 | itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]); | |
339 | ||
340 | for (i = 0; i < ARRAY_SIZE(itd1000_reinit_tab); i++) | |
341 | itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]); | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
346 | static int itd1000_sleep(struct dvb_frontend *fe) | |
347 | { | |
348 | return 0; | |
349 | } | |
350 | ||
351 | static int itd1000_release(struct dvb_frontend *fe) | |
352 | { | |
353 | kfree(fe->tuner_priv); | |
354 | fe->tuner_priv = NULL; | |
355 | return 0; | |
356 | } | |
357 | ||
358 | static const struct dvb_tuner_ops itd1000_tuner_ops = { | |
359 | .info = { | |
360 | .name = "Integrant ITD1000", | |
361 | .frequency_min = 950000, | |
362 | .frequency_max = 2150000, | |
363 | .frequency_step = 125, /* kHz for QPSK frontends */ | |
364 | }, | |
365 | ||
366 | .release = itd1000_release, | |
367 | ||
368 | .init = itd1000_init, | |
369 | .sleep = itd1000_sleep, | |
370 | ||
371 | .set_params = itd1000_set_parameters, | |
372 | .get_frequency = itd1000_get_frequency, | |
373 | .get_bandwidth = itd1000_get_bandwidth | |
374 | }; | |
375 | ||
376 | ||
377 | struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg) | |
378 | { | |
379 | struct itd1000_state *state = NULL; | |
380 | u8 i = 0; | |
381 | ||
382 | state = kzalloc(sizeof(struct itd1000_state), GFP_KERNEL); | |
383 | if (state == NULL) | |
384 | return NULL; | |
385 | ||
386 | state->cfg = cfg; | |
387 | state->i2c = i2c; | |
388 | ||
389 | i = itd1000_read_reg(state, 0); | |
390 | if (i != 0) { | |
391 | kfree(state); | |
392 | return NULL; | |
393 | } | |
a5bef1d2 | 394 | itd_info("successfully identified (ID: %d)\n", i); |
ca19aaa5 PB |
395 | |
396 | memset(state->shadow, 0xff, sizeof(state->shadow)); | |
397 | for (i = 0x65; i < 0x9c; i++) | |
398 | state->shadow[i] = itd1000_read_reg(state, i); | |
399 | ||
400 | memcpy(&fe->ops.tuner_ops, &itd1000_tuner_ops, sizeof(struct dvb_tuner_ops)); | |
401 | ||
402 | fe->tuner_priv = state; | |
403 | ||
404 | return fe; | |
405 | } | |
406 | EXPORT_SYMBOL(itd1000_attach); | |
407 | ||
408 | MODULE_AUTHOR("Patrick Boettcher <pb@linuxtv.org>"); | |
409 | MODULE_DESCRIPTION("Integrant ITD1000 driver"); | |
410 | MODULE_LICENSE("GPL"); |