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b63b36fa FR |
1 | /* |
2 | * Support for LGDT3306A - 8VSB/QAM-B | |
3 | * | |
4 | * Copyright (C) 2013 Fred Richter <frichter@hauppauge.com> | |
5 | * - driver structure based on lgdt3305.[ch] by Michael Krufky | |
6 | * - code based on LG3306_V0.35 API by LG Electronics Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <asm/div64.h> | |
25 | #include <linux/dvb/frontend.h> | |
26 | #include "dvb_math.h" | |
27 | #include "lgdt3306a.h" | |
28 | ||
29 | ||
30 | static int debug; | |
31 | module_param(debug, int, 0644); | |
32 | MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))"); | |
33 | ||
34 | #define DBG_INFO 1 | |
35 | #define DBG_REG 2 | |
8e8cd34e | 36 | #define DBG_DUMP 4 /* FGR - comment out to remove dump code */ |
b63b36fa FR |
37 | |
38 | #define lg_printk(kern, fmt, arg...) \ | |
39 | printk(kern "%s(): " fmt, __func__, ##arg) | |
40 | ||
41 | #define lg_info(fmt, arg...) printk(KERN_INFO "lgdt3306a: " fmt, ##arg) | |
42 | #define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg) | |
43 | #define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg) | |
44 | #define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \ | |
45 | lg_printk(KERN_DEBUG, fmt, ##arg) | |
46 | #define lg_reg(fmt, arg...) if (debug & DBG_REG) \ | |
47 | lg_printk(KERN_DEBUG, fmt, ##arg) | |
48 | ||
49 | #define lg_chkerr(ret) \ | |
50 | ({ \ | |
51 | int __ret; \ | |
52 | __ret = (ret < 0); \ | |
53 | if (__ret) \ | |
54 | lg_err("error %d on line %d\n", ret, __LINE__); \ | |
55 | __ret; \ | |
56 | }) | |
57 | ||
58 | struct lgdt3306a_state { | |
59 | struct i2c_adapter *i2c_adap; | |
60 | const struct lgdt3306a_config *cfg; | |
61 | ||
62 | struct dvb_frontend frontend; | |
63 | ||
64 | fe_modulation_t current_modulation; | |
65 | u32 current_frequency; | |
66 | u32 snr; | |
67 | }; | |
68 | ||
69 | /* ----------------------------------------------- | |
70 | LG3306A Register Usage | |
71 | (LG does not really name the registers, so this code does not either) | |
72 | 0000 -> 00FF Common control and status | |
73 | 1000 -> 10FF Synchronizer control and status | |
74 | 1F00 -> 1FFF Smart Antenna control and status | |
75 | 2100 -> 21FF VSB Equalizer control and status | |
76 | 2800 -> 28FF QAM Equalizer control and status | |
77 | 3000 -> 30FF FEC control and status | |
78 | ---------------------------------------------- */ | |
79 | ||
80 | typedef enum{ | |
81 | LG3306_UNLOCK = 0x00, | |
82 | LG3306_LOCK = 0x01, | |
83 | LG3306_UNKNOWN_LOCK = 0xFF | |
84 | }LG3306_LOCK_STATUS; | |
85 | ||
86 | typedef enum{ | |
87 | LG3306_NL_INIT = 0x00, | |
88 | LG3306_NL_PROCESS = 0x01, | |
89 | LG3306_NL_LOCK = 0x02, | |
90 | LG3306_NL_FAIL = 0x03, | |
91 | LG3306_NL_UNKNOWN = 0xFF | |
92 | }LG3306_NEVERLOCK_STATUS; | |
93 | ||
94 | typedef enum{ | |
95 | LG3306_VSB = 0x00, | |
96 | LG3306_QAM64 = 0x01, | |
97 | LG3306_QAM256 = 0x02, | |
98 | LG3306_UNKNOWN_MODE = 0xFF | |
99 | }LG3306_MODULATION; | |
100 | ||
101 | typedef enum | |
102 | { | |
103 | LG3306_SYNC_LOCK, | |
104 | LG3306_FEC_LOCK, | |
105 | LG3306_TR_LOCK, | |
106 | LG3306_AGC_LOCK, | |
107 | } LG3306_LOCK_CHECK; | |
108 | ||
109 | ||
110 | #ifdef DBG_DUMP | |
111 | static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state); | |
112 | static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state); | |
113 | #endif | |
114 | ||
115 | ||
116 | static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val) | |
117 | { | |
118 | int ret; | |
119 | u8 buf[] = { reg >> 8, reg & 0xff, val }; | |
120 | struct i2c_msg msg = { | |
121 | .addr = state->cfg->i2c_addr, .flags = 0, | |
122 | .buf = buf, .len = 3, | |
123 | }; | |
124 | ||
125 | lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); | |
126 | ||
127 | ret = i2c_transfer(state->i2c_adap, &msg, 1); | |
128 | ||
129 | if (ret != 1) { | |
130 | lg_err("error (addr %02x %02x <- %02x, err = %i)\n", | |
131 | msg.buf[0], msg.buf[1], msg.buf[2], ret); | |
132 | if (ret < 0) | |
133 | return ret; | |
134 | else | |
135 | return -EREMOTEIO; | |
136 | } | |
137 | return 0; | |
138 | } | |
139 | ||
140 | static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val) | |
141 | { | |
142 | int ret; | |
143 | u8 reg_buf[] = { reg >> 8, reg & 0xff }; | |
144 | struct i2c_msg msg[] = { | |
145 | { .addr = state->cfg->i2c_addr, | |
146 | .flags = 0, .buf = reg_buf, .len = 2 }, | |
147 | { .addr = state->cfg->i2c_addr, | |
148 | .flags = I2C_M_RD, .buf = val, .len = 1 }, | |
149 | }; | |
150 | ||
151 | ret = i2c_transfer(state->i2c_adap, msg, 2); | |
152 | ||
153 | if (ret != 2) { | |
154 | lg_err("error (addr %02x reg %04x error (ret == %i)\n", | |
155 | state->cfg->i2c_addr, reg, ret); | |
156 | if (ret < 0) | |
157 | return ret; | |
158 | else | |
159 | return -EREMOTEIO; | |
160 | } | |
161 | lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val); | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
166 | #define read_reg(state, reg) \ | |
167 | ({ \ | |
168 | u8 __val; \ | |
169 | int ret = lgdt3306a_read_reg(state, reg, &__val); \ | |
170 | if (lg_chkerr(ret)) \ | |
171 | __val = 0; \ | |
172 | __val; \ | |
173 | }) | |
174 | ||
175 | static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state, | |
176 | u16 reg, int bit, int onoff) | |
177 | { | |
178 | u8 val; | |
179 | int ret; | |
180 | ||
181 | lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff); | |
182 | ||
183 | ret = lgdt3306a_read_reg(state, reg, &val); | |
184 | if (lg_chkerr(ret)) | |
185 | goto fail; | |
186 | ||
187 | val &= ~(1 << bit); | |
188 | val |= (onoff & 1) << bit; | |
189 | ||
190 | ret = lgdt3306a_write_reg(state, reg, val); | |
191 | lg_chkerr(ret); | |
192 | fail: | |
193 | return ret; | |
194 | } | |
195 | ||
196 | /* ------------------------------------------------------------------------ */ | |
197 | ||
198 | static int lgdt3306a_soft_reset(struct lgdt3306a_state *state) | |
199 | { | |
200 | int ret; | |
201 | ||
202 | lg_dbg("\n"); | |
203 | ||
204 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); | |
205 | if (lg_chkerr(ret)) | |
206 | goto fail; | |
207 | ||
208 | msleep(20); | |
209 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); | |
210 | lg_chkerr(ret); | |
211 | ||
212 | fail: | |
213 | return ret; | |
214 | } | |
215 | ||
216 | static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state, | |
217 | enum lgdt3306a_mpeg_mode mode) | |
218 | { | |
219 | u8 val; | |
220 | int ret; | |
221 | ||
222 | lg_dbg("(%d)\n", mode); | |
8e8cd34e MIK |
223 | /* transport packet format */ |
224 | ret = lgdt3306a_set_reg_bit(state, 0x0071, 7, mode == LGDT3306A_MPEG_PARALLEL?1:0); /* TPSENB=0x80 */ | |
b63b36fa FR |
225 | if (lg_chkerr(ret)) |
226 | goto fail; | |
227 | ||
8e8cd34e MIK |
228 | /* start of packet signal duration */ |
229 | ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0); /* TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration */ | |
b63b36fa FR |
230 | if (lg_chkerr(ret)) |
231 | goto fail; | |
232 | ||
233 | ret = lgdt3306a_read_reg(state, 0x0070, &val); | |
234 | if (lg_chkerr(ret)) | |
235 | goto fail; | |
236 | ||
8e8cd34e | 237 | val |= 0x10; /* TPCLKSUPB=0x10 */ |
b63b36fa | 238 | |
8e8cd34e | 239 | if (mode == LGDT3306A_MPEG_PARALLEL) |
b63b36fa FR |
240 | val &= ~0x10; |
241 | ||
242 | ret = lgdt3306a_write_reg(state, 0x0070, val); | |
243 | lg_chkerr(ret); | |
244 | ||
245 | fail: | |
246 | return ret; | |
247 | } | |
248 | ||
249 | static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state, | |
250 | enum lgdt3306a_tp_clock_edge edge, | |
251 | enum lgdt3306a_tp_valid_polarity valid) | |
252 | { | |
253 | u8 val; | |
254 | int ret; | |
255 | ||
256 | lg_dbg("edge=%d, valid=%d\n", edge, valid); | |
257 | ||
258 | ret = lgdt3306a_read_reg(state, 0x0070, &val); | |
259 | if (lg_chkerr(ret)) | |
260 | goto fail; | |
261 | ||
8e8cd34e | 262 | val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */ |
b63b36fa | 263 | |
8e8cd34e | 264 | if (edge == LGDT3306A_TPCLK_RISING_EDGE) |
b63b36fa | 265 | val |= 0x04; |
8e8cd34e | 266 | if (valid == LGDT3306A_TP_VALID_HIGH) |
b63b36fa FR |
267 | val |= 0x02; |
268 | ||
269 | ret = lgdt3306a_write_reg(state, 0x0070, val); | |
270 | lg_chkerr(ret); | |
271 | ||
272 | fail: | |
273 | return ret; | |
274 | } | |
275 | ||
276 | static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state, | |
277 | int mode) | |
278 | { | |
279 | u8 val; | |
280 | int ret; | |
281 | ||
282 | lg_dbg("(%d)\n", mode); | |
283 | ||
8e8cd34e | 284 | if (mode) { |
b63b36fa FR |
285 | ret = lgdt3306a_read_reg(state, 0x0070, &val); |
286 | if (lg_chkerr(ret)) | |
287 | goto fail; | |
8e8cd34e | 288 | val &= ~0xA8; /* Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20, TPDATAOUTEN=0x08 */ |
b63b36fa FR |
289 | ret = lgdt3306a_write_reg(state, 0x0070, val); |
290 | if (lg_chkerr(ret)) | |
291 | goto fail; | |
292 | ||
8e8cd34e | 293 | ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1); /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */ |
b63b36fa FR |
294 | if (lg_chkerr(ret)) |
295 | goto fail; | |
296 | ||
297 | } else { | |
8e8cd34e | 298 | ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0); /* enable IFAGC pin */ |
b63b36fa FR |
299 | if (lg_chkerr(ret)) |
300 | goto fail; | |
301 | ||
302 | ret = lgdt3306a_read_reg(state, 0x0070, &val); | |
303 | if (lg_chkerr(ret)) | |
304 | goto fail; | |
305 | ||
8e8cd34e | 306 | val |= 0xA8; /* enable bus */ |
b63b36fa FR |
307 | ret = lgdt3306a_write_reg(state, 0x0070, val); |
308 | if (lg_chkerr(ret)) | |
309 | goto fail; | |
310 | } | |
311 | ||
312 | fail: | |
313 | return ret; | |
314 | } | |
315 | ||
8e8cd34e | 316 | static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire) |
b63b36fa FR |
317 | { |
318 | struct lgdt3306a_state *state = fe->demodulator_priv; | |
319 | ||
320 | lg_dbg("acquire=%d\n", acquire); | |
321 | ||
322 | return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1); | |
323 | ||
324 | } | |
325 | ||
326 | static int lgdt3306a_power(struct lgdt3306a_state *state, | |
327 | int mode) | |
328 | { | |
329 | int ret; | |
330 | ||
331 | lg_dbg("(%d)\n", mode); | |
332 | ||
8e8cd34e MIK |
333 | if (mode == 0) { |
334 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); /* into reset */ | |
b63b36fa FR |
335 | if (lg_chkerr(ret)) |
336 | goto fail; | |
337 | ||
8e8cd34e | 338 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0); /* power down */ |
b63b36fa FR |
339 | if (lg_chkerr(ret)) |
340 | goto fail; | |
341 | ||
342 | } else { | |
8e8cd34e | 343 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); /* out of reset */ |
b63b36fa FR |
344 | if (lg_chkerr(ret)) |
345 | goto fail; | |
346 | ||
8e8cd34e | 347 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1); /* power up */ |
b63b36fa FR |
348 | if (lg_chkerr(ret)) |
349 | goto fail; | |
350 | } | |
351 | ||
352 | #ifdef DBG_DUMP | |
353 | lgdt3306a_DumpAllRegs(state); | |
354 | #endif | |
355 | fail: | |
356 | return ret; | |
357 | } | |
358 | ||
359 | ||
360 | static int lgdt3306a_set_vsb(struct lgdt3306a_state *state) | |
361 | { | |
362 | u8 val; | |
363 | int ret; | |
364 | ||
365 | lg_dbg("\n"); | |
366 | ||
8e8cd34e | 367 | /* 0. Spectrum inversion detection manual; spectrum inverted */ |
b63b36fa | 368 | ret = lgdt3306a_read_reg(state, 0x0002, &val); |
8e8cd34e MIK |
369 | val &= 0xF7; /* SPECINVAUTO Off */ |
370 | val |= 0x04; /* SPECINV On */ | |
b63b36fa FR |
371 | ret = lgdt3306a_write_reg(state, 0x0002, val); |
372 | if (lg_chkerr(ret)) | |
373 | goto fail; | |
374 | ||
8e8cd34e | 375 | /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */ |
b63b36fa FR |
376 | ret = lgdt3306a_write_reg(state, 0x0008, 0x80); |
377 | if (lg_chkerr(ret)) | |
378 | goto fail; | |
379 | ||
8e8cd34e | 380 | /* 2. Bandwidth mode for VSB(6MHz) */ |
b63b36fa FR |
381 | ret = lgdt3306a_read_reg(state, 0x0009, &val); |
382 | val &= 0xE3; | |
8e8cd34e | 383 | val |= 0x0C; /* STDOPDETTMODE[2:0]=3 */ |
b63b36fa FR |
384 | ret = lgdt3306a_write_reg(state, 0x0009, val); |
385 | if (lg_chkerr(ret)) | |
386 | goto fail; | |
387 | ||
8e8cd34e | 388 | /* 3. QAM mode detection mode(None) */ |
b63b36fa | 389 | ret = lgdt3306a_read_reg(state, 0x0009, &val); |
8e8cd34e | 390 | val &= 0xFC; /* STDOPDETCMODE[1:0]=0 */ |
b63b36fa FR |
391 | ret = lgdt3306a_write_reg(state, 0x0009, val); |
392 | if (lg_chkerr(ret)) | |
393 | goto fail; | |
394 | ||
8e8cd34e | 395 | /* 4. ADC sampling frequency rate(2x sampling) */ |
b63b36fa | 396 | ret = lgdt3306a_read_reg(state, 0x000D, &val); |
8e8cd34e | 397 | val &= 0xBF; /* SAMPLING4XFEN=0 */ |
b63b36fa FR |
398 | ret = lgdt3306a_write_reg(state, 0x000D, val); |
399 | if (lg_chkerr(ret)) | |
400 | goto fail; | |
401 | ||
8e8cd34e MIK |
402 | #if 0 |
403 | /* FGR - disable any AICC filtering, testing only */ | |
404 | ||
b63b36fa FR |
405 | ret = lgdt3306a_write_reg(state, 0x0024, 0x00); |
406 | if (lg_chkerr(ret)) | |
407 | goto fail; | |
408 | ||
8e8cd34e | 409 | /* AICCFIXFREQ0 NT N-1(Video rejection) */ |
b63b36fa FR |
410 | ret = lgdt3306a_write_reg(state, 0x002E, 0x00); |
411 | ret = lgdt3306a_write_reg(state, 0x002F, 0x00); | |
412 | ret = lgdt3306a_write_reg(state, 0x0030, 0x00); | |
413 | ||
8e8cd34e | 414 | /* AICCFIXFREQ1 NT N-1(Audio rejection) */ |
b63b36fa FR |
415 | ret = lgdt3306a_write_reg(state, 0x002B, 0x00); |
416 | ret = lgdt3306a_write_reg(state, 0x002C, 0x00); | |
417 | ret = lgdt3306a_write_reg(state, 0x002D, 0x00); | |
418 | ||
8e8cd34e | 419 | /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */ |
b63b36fa FR |
420 | ret = lgdt3306a_write_reg(state, 0x0028, 0x00); |
421 | ret = lgdt3306a_write_reg(state, 0x0029, 0x00); | |
422 | ret = lgdt3306a_write_reg(state, 0x002A, 0x00); | |
423 | ||
8e8cd34e | 424 | /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */ |
b63b36fa FR |
425 | ret = lgdt3306a_write_reg(state, 0x0025, 0x00); |
426 | ret = lgdt3306a_write_reg(state, 0x0026, 0x00); | |
427 | ret = lgdt3306a_write_reg(state, 0x0027, 0x00); | |
428 | ||
8e8cd34e MIK |
429 | #else |
430 | /* FGR - this works well for HVR-1955,1975 */ | |
431 | ||
432 | /* 5. AICCOPMODE NT N-1 Adj. */ | |
b63b36fa FR |
433 | ret = lgdt3306a_write_reg(state, 0x0024, 0x5A); |
434 | if (lg_chkerr(ret)) | |
435 | goto fail; | |
436 | ||
8e8cd34e | 437 | /* AICCFIXFREQ0 NT N-1(Video rejection) */ |
b63b36fa FR |
438 | ret = lgdt3306a_write_reg(state, 0x002E, 0x5A); |
439 | ret = lgdt3306a_write_reg(state, 0x002F, 0x00); | |
440 | ret = lgdt3306a_write_reg(state, 0x0030, 0x00); | |
441 | ||
8e8cd34e | 442 | /* AICCFIXFREQ1 NT N-1(Audio rejection) */ |
b63b36fa FR |
443 | ret = lgdt3306a_write_reg(state, 0x002B, 0x36); |
444 | ret = lgdt3306a_write_reg(state, 0x002C, 0x00); | |
445 | ret = lgdt3306a_write_reg(state, 0x002D, 0x00); | |
446 | ||
8e8cd34e | 447 | /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */ |
b63b36fa FR |
448 | ret = lgdt3306a_write_reg(state, 0x0028, 0x2A); |
449 | ret = lgdt3306a_write_reg(state, 0x0029, 0x00); | |
450 | ret = lgdt3306a_write_reg(state, 0x002A, 0x00); | |
451 | ||
8e8cd34e | 452 | /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */ |
b63b36fa FR |
453 | ret = lgdt3306a_write_reg(state, 0x0025, 0x06); |
454 | ret = lgdt3306a_write_reg(state, 0x0026, 0x00); | |
455 | ret = lgdt3306a_write_reg(state, 0x0027, 0x00); | |
456 | #endif | |
457 | ||
458 | ret = lgdt3306a_read_reg(state, 0x001E, &val); | |
459 | val &= 0x0F; | |
460 | val |= 0xA0; | |
461 | ret = lgdt3306a_write_reg(state, 0x001E, val); | |
462 | ||
463 | ret = lgdt3306a_write_reg(state, 0x0022, 0x08); | |
464 | ||
465 | ret = lgdt3306a_write_reg(state, 0x0023, 0xFF); | |
466 | ||
467 | ret = lgdt3306a_read_reg(state, 0x211F, &val); | |
468 | val &= 0xEF; | |
469 | ret = lgdt3306a_write_reg(state, 0x211F, val); | |
470 | ||
471 | ret = lgdt3306a_write_reg(state, 0x2173, 0x01); | |
472 | ||
473 | ret = lgdt3306a_read_reg(state, 0x1061, &val); | |
474 | val &= 0xF8; | |
475 | val |= 0x04; | |
476 | ret = lgdt3306a_write_reg(state, 0x1061, val); | |
477 | ||
478 | ret = lgdt3306a_read_reg(state, 0x103D, &val); | |
479 | val &= 0xCF; | |
480 | ret = lgdt3306a_write_reg(state, 0x103D, val); | |
481 | ||
482 | ret = lgdt3306a_write_reg(state, 0x2122, 0x40); | |
483 | ||
484 | ret = lgdt3306a_read_reg(state, 0x2141, &val); | |
485 | val &= 0x3F; | |
486 | ret = lgdt3306a_write_reg(state, 0x2141, val); | |
487 | ||
488 | ret = lgdt3306a_read_reg(state, 0x2135, &val); | |
489 | val &= 0x0F; | |
490 | val |= 0x70; | |
491 | ret = lgdt3306a_write_reg(state, 0x2135, val); | |
492 | ||
493 | ret = lgdt3306a_read_reg(state, 0x0003, &val); | |
494 | val &= 0xF7; | |
495 | ret = lgdt3306a_write_reg(state, 0x0003, val); | |
496 | ||
497 | ret = lgdt3306a_read_reg(state, 0x001C, &val); | |
498 | val &= 0x7F; | |
499 | ret = lgdt3306a_write_reg(state, 0x001C, val); | |
500 | ||
8e8cd34e | 501 | /* 6. EQ step size */ |
b63b36fa FR |
502 | ret = lgdt3306a_read_reg(state, 0x2179, &val); |
503 | val &= 0xF8; | |
504 | ret = lgdt3306a_write_reg(state, 0x2179, val); | |
505 | ||
506 | ret = lgdt3306a_read_reg(state, 0x217A, &val); | |
507 | val &= 0xF8; | |
508 | ret = lgdt3306a_write_reg(state, 0x217A, val); | |
509 | ||
8e8cd34e | 510 | /* 7. Reset */ |
b63b36fa FR |
511 | ret = lgdt3306a_soft_reset(state); |
512 | if (lg_chkerr(ret)) | |
513 | goto fail; | |
514 | ||
515 | lg_dbg("complete\n"); | |
516 | fail: | |
517 | return ret; | |
518 | } | |
519 | ||
520 | static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation) | |
521 | { | |
522 | u8 val; | |
523 | int ret; | |
524 | ||
525 | lg_dbg("modulation=%d\n", modulation); | |
526 | ||
8e8cd34e | 527 | /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */ |
b63b36fa FR |
528 | ret = lgdt3306a_write_reg(state, 0x0008, 0x08); |
529 | if (lg_chkerr(ret)) | |
530 | goto fail; | |
531 | ||
8e8cd34e | 532 | /* 1a. Spectrum inversion detection to Auto */ |
b63b36fa | 533 | ret = lgdt3306a_read_reg(state, 0x0002, &val); |
8e8cd34e MIK |
534 | val &= 0xFB; /* SPECINV Off */ |
535 | val |= 0x08; /* SPECINVAUTO On */ | |
b63b36fa FR |
536 | ret = lgdt3306a_write_reg(state, 0x0002, val); |
537 | if (lg_chkerr(ret)) | |
538 | goto fail; | |
539 | ||
8e8cd34e | 540 | /* 2. Bandwidth mode for QAM */ |
b63b36fa | 541 | ret = lgdt3306a_read_reg(state, 0x0009, &val); |
8e8cd34e | 542 | val &= 0xE3; /* STDOPDETTMODE[2:0]=0 VSB Off */ |
b63b36fa FR |
543 | ret = lgdt3306a_write_reg(state, 0x0009, val); |
544 | if (lg_chkerr(ret)) | |
545 | goto fail; | |
546 | ||
8e8cd34e | 547 | /* 3. : 64QAM/256QAM detection(manual, auto) */ |
b63b36fa FR |
548 | ret = lgdt3306a_read_reg(state, 0x0009, &val); |
549 | val &= 0xFC; | |
8e8cd34e | 550 | val |= 0x02; /* STDOPDETCMODE[1:0]=1=Manual 2=Auto */ |
b63b36fa FR |
551 | ret = lgdt3306a_write_reg(state, 0x0009, val); |
552 | if (lg_chkerr(ret)) | |
553 | goto fail; | |
554 | ||
8e8cd34e | 555 | /* 3a. : 64QAM/256QAM selection for manual */ |
b63b36fa FR |
556 | ret = lgdt3306a_read_reg(state, 0x101a, &val); |
557 | val &= 0xF8; | |
8e8cd34e MIK |
558 | if (modulation == QAM_64) |
559 | val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */ | |
560 | else | |
561 | val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */ | |
562 | ||
b63b36fa FR |
563 | ret = lgdt3306a_write_reg(state, 0x101a, val); |
564 | if (lg_chkerr(ret)) | |
565 | goto fail; | |
566 | ||
8e8cd34e | 567 | /* 4. ADC sampling frequency rate(4x sampling) */ |
b63b36fa FR |
568 | ret = lgdt3306a_read_reg(state, 0x000D, &val); |
569 | val &= 0xBF; | |
8e8cd34e | 570 | val |= 0x40; /* SAMPLING4XFEN=1 */ |
b63b36fa FR |
571 | ret = lgdt3306a_write_reg(state, 0x000D, val); |
572 | if (lg_chkerr(ret)) | |
573 | goto fail; | |
574 | ||
8e8cd34e | 575 | /* 5. No AICC operation in QAM mode */ |
b63b36fa FR |
576 | ret = lgdt3306a_read_reg(state, 0x0024, &val); |
577 | val &= 0x00; | |
578 | ret = lgdt3306a_write_reg(state, 0x0024, val); | |
579 | if (lg_chkerr(ret)) | |
580 | goto fail; | |
581 | ||
8e8cd34e | 582 | /* 6. Reset */ |
b63b36fa FR |
583 | ret = lgdt3306a_soft_reset(state); |
584 | if (lg_chkerr(ret)) | |
585 | goto fail; | |
586 | ||
587 | lg_dbg("complete\n"); | |
588 | fail: | |
589 | return ret; | |
590 | } | |
591 | ||
592 | static int lgdt3306a_set_modulation(struct lgdt3306a_state *state, | |
593 | struct dtv_frontend_properties *p) | |
594 | { | |
595 | int ret; | |
596 | ||
597 | lg_dbg("\n"); | |
598 | ||
599 | switch (p->modulation) { | |
600 | case VSB_8: | |
601 | ret = lgdt3306a_set_vsb(state); | |
602 | break; | |
603 | case QAM_64: | |
604 | ret = lgdt3306a_set_qam(state, QAM_64); | |
605 | break; | |
606 | case QAM_256: | |
607 | ret = lgdt3306a_set_qam(state, QAM_256); | |
608 | break; | |
609 | default: | |
610 | return -EINVAL; | |
611 | } | |
612 | if (lg_chkerr(ret)) | |
613 | goto fail; | |
614 | ||
615 | state->current_modulation = p->modulation; | |
616 | ||
617 | fail: | |
618 | return ret; | |
619 | } | |
620 | ||
621 | /* ------------------------------------------------------------------------ */ | |
622 | ||
623 | static int lgdt3306a_agc_setup(struct lgdt3306a_state *state, | |
624 | struct dtv_frontend_properties *p) | |
625 | { | |
8e8cd34e | 626 | /* TODO: anything we want to do here??? */ |
b63b36fa FR |
627 | lg_dbg("\n"); |
628 | ||
629 | switch (p->modulation) { | |
630 | case VSB_8: | |
631 | break; | |
632 | case QAM_64: | |
633 | case QAM_256: | |
634 | break; | |
635 | default: | |
636 | return -EINVAL; | |
637 | } | |
638 | return 0; | |
639 | } | |
640 | ||
641 | /* ------------------------------------------------------------------------ */ | |
642 | ||
643 | static int lgdt3306a_set_inversion(struct lgdt3306a_state *state, | |
644 | int inversion) | |
645 | { | |
646 | int ret; | |
647 | ||
648 | lg_dbg("(%d)\n", inversion); | |
649 | ||
8e8cd34e | 650 | ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0); |
b63b36fa FR |
651 | return ret; |
652 | } | |
653 | ||
654 | static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state, | |
655 | int enabled) | |
656 | { | |
657 | int ret; | |
658 | ||
659 | lg_dbg("(%d)\n", enabled); | |
660 | ||
8e8cd34e MIK |
661 | /* 0=Manual 1=Auto(QAM only) */ |
662 | ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);/* SPECINVAUTO=0x04 */ | |
b63b36fa FR |
663 | return ret; |
664 | } | |
665 | ||
666 | static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state, | |
667 | struct dtv_frontend_properties *p, | |
668 | int inversion) | |
669 | { | |
670 | int ret = 0; | |
671 | ||
672 | lg_dbg("(%d)\n", inversion); | |
8e8cd34e MIK |
673 | #if 0 |
674 | /* FGR - spectral_inversion defaults already set for VSB and QAM; can enable later if desired */ | |
b63b36fa FR |
675 | |
676 | ret = lgdt3306a_set_inversion(state, inversion); | |
677 | ||
678 | switch (p->modulation) { | |
679 | case VSB_8: | |
8e8cd34e | 680 | ret = lgdt3306a_set_inversion_auto(state, 0); /* Manual only for VSB */ |
b63b36fa FR |
681 | break; |
682 | case QAM_64: | |
683 | case QAM_256: | |
8e8cd34e | 684 | ret = lgdt3306a_set_inversion_auto(state, 1); /* Auto ok for QAM */ |
b63b36fa FR |
685 | break; |
686 | default: | |
687 | ret = -EINVAL; | |
688 | } | |
689 | #endif | |
690 | return ret; | |
691 | } | |
692 | ||
693 | static int lgdt3306a_set_if(struct lgdt3306a_state *state, | |
694 | struct dtv_frontend_properties *p) | |
695 | { | |
696 | int ret; | |
697 | u16 if_freq_khz; | |
698 | u8 nco1, nco2; | |
699 | ||
700 | switch (p->modulation) { | |
701 | case VSB_8: | |
702 | if_freq_khz = state->cfg->vsb_if_khz; | |
703 | break; | |
704 | case QAM_64: | |
705 | case QAM_256: | |
706 | if_freq_khz = state->cfg->qam_if_khz; | |
707 | break; | |
708 | default: | |
709 | return -EINVAL; | |
710 | } | |
711 | ||
8e8cd34e | 712 | switch (if_freq_khz) { |
b63b36fa FR |
713 | default: |
714 | lg_warn("IF=%d KHz is not supportted, 3250 assumed\n", if_freq_khz); | |
8e8cd34e MIK |
715 | /* fallthrough */ |
716 | case 3250: /* 3.25Mhz */ | |
b63b36fa FR |
717 | nco1 = 0x34; |
718 | nco2 = 0x00; | |
719 | break; | |
8e8cd34e | 720 | case 3500: /* 3.50Mhz */ |
b63b36fa FR |
721 | nco1 = 0x38; |
722 | nco2 = 0x00; | |
723 | break; | |
8e8cd34e | 724 | case 4000: /* 4.00Mhz */ |
b63b36fa FR |
725 | nco1 = 0x40; |
726 | nco2 = 0x00; | |
727 | break; | |
8e8cd34e | 728 | case 5000: /* 5.00Mhz */ |
b63b36fa FR |
729 | nco1 = 0x50; |
730 | nco2 = 0x00; | |
731 | break; | |
8e8cd34e | 732 | case 5380: /* 5.38Mhz */ |
b63b36fa FR |
733 | nco1 = 0x56; |
734 | nco2 = 0x14; | |
735 | break; | |
736 | } | |
737 | ret = lgdt3306a_write_reg(state, 0x0010, nco1); | |
738 | ret = lgdt3306a_write_reg(state, 0x0011, nco2); | |
739 | ||
740 | lg_dbg("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2); | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
745 | /* ------------------------------------------------------------------------ */ | |
746 | ||
747 | static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) | |
748 | { | |
749 | struct lgdt3306a_state *state = fe->demodulator_priv; | |
750 | ||
8e8cd34e | 751 | if (state->cfg->deny_i2c_rptr) { |
b63b36fa FR |
752 | lg_dbg("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr); |
753 | return 0; | |
754 | } | |
755 | lg_dbg("(%d)\n", enable); | |
756 | ||
8e8cd34e | 757 | return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1); /* NI2CRPTEN=0x80 */ |
b63b36fa FR |
758 | } |
759 | ||
760 | static int lgdt3306a_sleep(struct lgdt3306a_state *state) | |
761 | { | |
762 | int ret; | |
763 | ||
764 | lg_dbg("\n"); | |
8e8cd34e | 765 | state->current_frequency = -1; /* force re-tune, when we wake */ |
b63b36fa | 766 | |
8e8cd34e | 767 | ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */ |
b63b36fa FR |
768 | if (lg_chkerr(ret)) |
769 | goto fail; | |
770 | ||
8e8cd34e | 771 | ret = lgdt3306a_power(state, 0); /* power down */ |
b63b36fa FR |
772 | lg_chkerr(ret); |
773 | ||
774 | fail: | |
775 | return 0; | |
776 | } | |
777 | ||
778 | static int lgdt3306a_fe_sleep(struct dvb_frontend *fe) | |
779 | { | |
780 | struct lgdt3306a_state *state = fe->demodulator_priv; | |
781 | ||
782 | return lgdt3306a_sleep(state); | |
783 | } | |
784 | ||
785 | static int lgdt3306a_init(struct dvb_frontend *fe) | |
786 | { | |
787 | struct lgdt3306a_state *state = fe->demodulator_priv; | |
788 | u8 val; | |
789 | int ret; | |
790 | ||
791 | lg_dbg("\n"); | |
792 | ||
8e8cd34e MIK |
793 | /* 1. Normal operation mode */ |
794 | ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */ | |
b63b36fa FR |
795 | if (lg_chkerr(ret)) |
796 | goto fail; | |
797 | ||
8e8cd34e | 798 | /* 2. Spectrum inversion auto detection (Not valid for VSB) */ |
b63b36fa FR |
799 | ret = lgdt3306a_set_inversion_auto(state, 0); |
800 | if (lg_chkerr(ret)) | |
801 | goto fail; | |
802 | ||
8e8cd34e | 803 | /* 3. Spectrum inversion(According to the tuner configuration) */ |
b63b36fa FR |
804 | ret = lgdt3306a_set_inversion(state, 1); |
805 | if (lg_chkerr(ret)) | |
806 | goto fail; | |
807 | ||
8e8cd34e MIK |
808 | /* 4. Peak-to-peak voltage of ADC input signal */ |
809 | ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1); /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */ | |
b63b36fa FR |
810 | if (lg_chkerr(ret)) |
811 | goto fail; | |
812 | ||
8e8cd34e MIK |
813 | /* 5. ADC output data capture clock phase */ |
814 | ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0); /* 0=same phase as ADC clock */ | |
b63b36fa FR |
815 | if (lg_chkerr(ret)) |
816 | goto fail; | |
817 | ||
8e8cd34e MIK |
818 | /* 5a. ADC sampling clock source */ |
819 | ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0); /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */ | |
b63b36fa FR |
820 | if (lg_chkerr(ret)) |
821 | goto fail; | |
822 | ||
8e8cd34e MIK |
823 | /* 6. Automatic PLL set */ |
824 | ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0); /* PLLSETAUTO=0x40; 0=off */ | |
b63b36fa FR |
825 | if (lg_chkerr(ret)) |
826 | goto fail; | |
827 | ||
8e8cd34e MIK |
828 | if (state->cfg->xtalMHz == 24) { /* 24MHz */ |
829 | /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */ | |
b63b36fa FR |
830 | ret = lgdt3306a_read_reg(state, 0x0005, &val); |
831 | if (lg_chkerr(ret)) | |
832 | goto fail; | |
833 | val &= 0xC0; | |
834 | val |= 0x25; | |
835 | ret = lgdt3306a_write_reg(state, 0x0005, val); | |
836 | if (lg_chkerr(ret)) | |
837 | goto fail; | |
838 | ret = lgdt3306a_write_reg(state, 0x0006, 0x64); | |
839 | if (lg_chkerr(ret)) | |
840 | goto fail; | |
841 | ||
8e8cd34e | 842 | /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */ |
b63b36fa FR |
843 | ret = lgdt3306a_read_reg(state, 0x000D, &val); |
844 | if (lg_chkerr(ret)) | |
845 | goto fail; | |
846 | val &= 0xC0; | |
847 | val |= 0x18; | |
848 | ret = lgdt3306a_write_reg(state, 0x000D, val); | |
849 | if (lg_chkerr(ret)) | |
850 | goto fail; | |
851 | ||
8e8cd34e MIK |
852 | } else if (state->cfg->xtalMHz == 25) { /* 25MHz */ |
853 | /* 7. Frequency for PLL output */ | |
b63b36fa FR |
854 | ret = lgdt3306a_read_reg(state, 0x0005, &val); |
855 | if (lg_chkerr(ret)) | |
856 | goto fail; | |
857 | val &= 0xC0; | |
858 | val |= 0x25; | |
859 | ret = lgdt3306a_write_reg(state, 0x0005, val); | |
860 | if (lg_chkerr(ret)) | |
861 | goto fail; | |
862 | ret = lgdt3306a_write_reg(state, 0x0006, 0x64); | |
863 | if (lg_chkerr(ret)) | |
864 | goto fail; | |
865 | ||
8e8cd34e | 866 | /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */ |
b63b36fa FR |
867 | ret = lgdt3306a_read_reg(state, 0x000D, &val); |
868 | if (lg_chkerr(ret)) | |
869 | goto fail; | |
870 | val &= 0xC0; | |
871 | val |= 0x19; | |
872 | ret = lgdt3306a_write_reg(state, 0x000D, val); | |
873 | if (lg_chkerr(ret)) | |
874 | goto fail; | |
875 | } else { | |
876 | lg_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz); | |
877 | } | |
8e8cd34e MIK |
878 | #if 0 |
879 | ret = lgdt3306a_write_reg(state, 0x000E, 0x00); | |
880 | ret = lgdt3306a_write_reg(state, 0x000F, 0x00); | |
881 | #endif | |
b63b36fa | 882 | |
8e8cd34e MIK |
883 | /* 9. Center frequency of input signal of ADC */ |
884 | ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */ | |
885 | ret = lgdt3306a_write_reg(state, 0x0011, 0x00); | |
b63b36fa | 886 | |
8e8cd34e MIK |
887 | /* 10. Fixed gain error value */ |
888 | ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */ | |
b63b36fa | 889 | |
8e8cd34e | 890 | /* 10a. VSB TR BW gear shift initial step */ |
b63b36fa FR |
891 | ret = lgdt3306a_read_reg(state, 0x103C, &val); |
892 | val &= 0x0F; | |
8e8cd34e | 893 | val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */ |
b63b36fa FR |
894 | ret = lgdt3306a_write_reg(state, 0x103C, val); |
895 | ||
8e8cd34e | 896 | /* 10b. Timing offset calibration in low temperature for VSB */ |
b63b36fa FR |
897 | ret = lgdt3306a_read_reg(state, 0x103D, &val); |
898 | val &= 0xFC; | |
899 | val |= 0x03; | |
900 | ret = lgdt3306a_write_reg(state, 0x103D, val); | |
901 | ||
8e8cd34e | 902 | /* 10c. Timing offset calibration in low temperature for QAM */ |
b63b36fa FR |
903 | ret = lgdt3306a_read_reg(state, 0x1036, &val); |
904 | val &= 0xF0; | |
905 | val |= 0x0C; | |
906 | ret = lgdt3306a_write_reg(state, 0x1036, val); | |
907 | ||
8e8cd34e | 908 | /* 11. Using the imaginary part of CIR in CIR loading */ |
b63b36fa | 909 | ret = lgdt3306a_read_reg(state, 0x211F, &val); |
8e8cd34e | 910 | val &= 0xEF; /* do not use imaginary of CIR */ |
b63b36fa FR |
911 | ret = lgdt3306a_write_reg(state, 0x211F, val); |
912 | ||
8e8cd34e | 913 | /* 12. Control of no signal detector function */ |
b63b36fa | 914 | ret = lgdt3306a_read_reg(state, 0x2849, &val); |
8e8cd34e | 915 | val &= 0xEF; /* NOUSENOSIGDET=0, enable no signal detector */ |
b63b36fa FR |
916 | ret = lgdt3306a_write_reg(state, 0x2849, val); |
917 | ||
8e8cd34e | 918 | /* FGR - put demod in some known mode */ |
b63b36fa FR |
919 | ret = lgdt3306a_set_vsb(state); |
920 | ||
8e8cd34e | 921 | /* 13. TP stream format */ |
b63b36fa FR |
922 | ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode); |
923 | ||
8e8cd34e | 924 | /* 14. disable output buses */ |
b63b36fa FR |
925 | ret = lgdt3306a_mpeg_tristate(state, 1); |
926 | ||
8e8cd34e | 927 | /* 15. Sleep (in reset) */ |
b63b36fa FR |
928 | ret = lgdt3306a_sleep(state); |
929 | lg_chkerr(ret); | |
930 | ||
931 | fail: | |
932 | return ret; | |
933 | } | |
934 | ||
935 | static int lgdt3306a_set_parameters(struct dvb_frontend *fe) | |
936 | { | |
937 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; | |
938 | struct lgdt3306a_state *state = fe->demodulator_priv; | |
939 | int ret; | |
940 | ||
941 | lg_dbg("(%d, %d)\n", p->frequency, p->modulation); | |
942 | ||
8e8cd34e MIK |
943 | if (state->current_frequency == p->frequency && |
944 | state->current_modulation == p->modulation) { | |
b63b36fa FR |
945 | lg_dbg(" (already set, skipping ...)\n"); |
946 | return 0; | |
947 | } | |
948 | state->current_frequency = -1; | |
949 | state->current_modulation = -1; | |
950 | ||
8e8cd34e | 951 | ret = lgdt3306a_power(state, 1); /* power up */ |
b63b36fa FR |
952 | if (lg_chkerr(ret)) |
953 | goto fail; | |
954 | ||
955 | if (fe->ops.tuner_ops.set_params) { | |
956 | ret = fe->ops.tuner_ops.set_params(fe); | |
957 | if (fe->ops.i2c_gate_ctrl) | |
958 | fe->ops.i2c_gate_ctrl(fe, 0); | |
8e8cd34e MIK |
959 | #if 0 |
960 | if (lg_chkerr(ret)) | |
961 | goto fail; | |
962 | state->current_frequency = p->frequency; | |
963 | #endif | |
b63b36fa FR |
964 | } |
965 | ||
966 | ret = lgdt3306a_set_modulation(state, p); | |
967 | if (lg_chkerr(ret)) | |
968 | goto fail; | |
969 | ||
970 | ret = lgdt3306a_agc_setup(state, p); | |
971 | if (lg_chkerr(ret)) | |
972 | goto fail; | |
973 | ||
974 | ret = lgdt3306a_set_if(state, p); | |
975 | if (lg_chkerr(ret)) | |
976 | goto fail; | |
977 | ||
978 | ret = lgdt3306a_spectral_inversion(state, p, | |
8e8cd34e | 979 | state->cfg->spectral_inversion ? 1 : 0); |
b63b36fa FR |
980 | if (lg_chkerr(ret)) |
981 | goto fail; | |
982 | ||
983 | ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode); | |
984 | if (lg_chkerr(ret)) | |
985 | goto fail; | |
986 | ||
987 | ret = lgdt3306a_mpeg_mode_polarity(state, | |
988 | state->cfg->tpclk_edge, | |
989 | state->cfg->tpvalid_polarity); | |
990 | if (lg_chkerr(ret)) | |
991 | goto fail; | |
992 | ||
8e8cd34e | 993 | ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */ |
b63b36fa FR |
994 | if (lg_chkerr(ret)) |
995 | goto fail; | |
996 | ||
997 | ret = lgdt3306a_soft_reset(state); | |
998 | if (lg_chkerr(ret)) | |
999 | goto fail; | |
1000 | ||
1001 | #ifdef DBG_DUMP | |
1002 | lgdt3306a_DumpAllRegs(state); | |
1003 | #endif | |
1004 | state->current_frequency = p->frequency; | |
1005 | fail: | |
1006 | return ret; | |
1007 | } | |
1008 | ||
1009 | static int lgdt3306a_get_frontend(struct dvb_frontend *fe) | |
1010 | { | |
1011 | struct lgdt3306a_state *state = fe->demodulator_priv; | |
1012 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; | |
1013 | ||
1014 | lg_dbg("(%u, %d)\n", state->current_frequency, state->current_modulation); | |
1015 | ||
1016 | p->modulation = state->current_modulation; | |
1017 | p->frequency = state->current_frequency; | |
1018 | return 0; | |
1019 | } | |
1020 | ||
1021 | static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe) | |
1022 | { | |
1023 | #if 1 | |
1024 | return DVBFE_ALGO_CUSTOM; | |
1025 | #else | |
1026 | return DVBFE_ALGO_HW; | |
1027 | #endif | |
1028 | } | |
1029 | ||
1030 | /* ------------------------------------------------------------------------ */ | |
1031 | static void lgdt3306a_monitor_vsb(struct lgdt3306a_state *state) | |
1032 | { | |
1033 | u8 val; | |
1034 | int ret; | |
8e8cd34e MIK |
1035 | u8 snrRef, maxPowerMan, nCombDet; |
1036 | u16 fbDlyCir; | |
b63b36fa FR |
1037 | |
1038 | ret = lgdt3306a_read_reg(state, 0x21A1, &val); | |
1039 | snrRef = val & 0x3F; | |
1040 | ||
1041 | ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan); | |
1042 | ||
1043 | ret = lgdt3306a_read_reg(state, 0x2191, &val); | |
1044 | nCombDet = (val & 0x80) >> 7; | |
1045 | ||
1046 | ret = lgdt3306a_read_reg(state, 0x2180, &val); | |
1047 | fbDlyCir = (val & 0x03) << 8; | |
1048 | ret = lgdt3306a_read_reg(state, 0x2181, &val); | |
1049 | fbDlyCir |= val; | |
1050 | ||
1051 | lg_dbg("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n", | |
1052 | snrRef, maxPowerMan, nCombDet, fbDlyCir); | |
1053 | ||
8e8cd34e | 1054 | /* Carrier offset sub loop bandwidth */ |
b63b36fa FR |
1055 | ret = lgdt3306a_read_reg(state, 0x1061, &val); |
1056 | val &= 0xF8; | |
1057 | if ((snrRef > 18) && (maxPowerMan > 0x68) && (nCombDet == 0x01) && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) { | |
8e8cd34e MIK |
1058 | /* SNR is over 18dB and no ghosting */ |
1059 | val |= 0x00; /* final bandwidth = 0 */ | |
b63b36fa | 1060 | } else { |
8e8cd34e | 1061 | val |= 0x04; /* final bandwidth = 4 */ |
b63b36fa FR |
1062 | } |
1063 | ret = lgdt3306a_write_reg(state, 0x1061, val); | |
1064 | ||
8e8cd34e | 1065 | /* Adjust Notch Filter */ |
b63b36fa FR |
1066 | ret = lgdt3306a_read_reg(state, 0x0024, &val); |
1067 | val &= 0x0F; | |
8e8cd34e | 1068 | if (nCombDet == 0) { /* Turn on the Notch Filter */ |
b63b36fa FR |
1069 | val |= 0x50; |
1070 | } | |
1071 | ret = lgdt3306a_write_reg(state, 0x0024, val); | |
1072 | ||
8e8cd34e | 1073 | /* VSB Timing Recovery output normalization */ |
b63b36fa FR |
1074 | ret = lgdt3306a_read_reg(state, 0x103D, &val); |
1075 | val &= 0xCF; | |
1076 | val |= 0x20; | |
1077 | ret = lgdt3306a_write_reg(state, 0x103D, val); | |
1078 | } | |
1079 | ||
1080 | static LG3306_MODULATION lgdt3306a_check_oper_mode(struct lgdt3306a_state *state) | |
1081 | { | |
1082 | u8 val = 0; | |
1083 | int ret; | |
1084 | ||
1085 | ret = lgdt3306a_read_reg(state, 0x0081, &val); | |
1086 | ||
1087 | if (val & 0x80) { | |
1088 | lg_dbg("VSB\n"); | |
8e8cd34e | 1089 | return LG3306_VSB; |
b63b36fa FR |
1090 | } |
1091 | else if (val & 0x08) { | |
1092 | ret = lgdt3306a_read_reg(state, 0x00A6, &val); | |
1093 | val = val >> 2; | |
1094 | if (val & 0x01) { | |
1095 | lg_dbg("QAM256\n"); | |
8e8cd34e | 1096 | return LG3306_QAM256; |
b63b36fa FR |
1097 | } else { |
1098 | lg_dbg("QAM64\n"); | |
8e8cd34e | 1099 | return LG3306_QAM64; |
b63b36fa FR |
1100 | } |
1101 | } | |
1102 | lg_warn("UNKNOWN\n"); | |
8e8cd34e | 1103 | return LG3306_UNKNOWN_MODE; |
b63b36fa FR |
1104 | } |
1105 | ||
1106 | static LG3306_LOCK_STATUS lgdt3306a_check_lock_status(struct lgdt3306a_state *state, | |
1107 | LG3306_LOCK_CHECK whatLock) | |
1108 | { | |
1109 | u8 val = 0; | |
1110 | int ret; | |
1111 | LG3306_MODULATION modeOper; | |
1112 | LG3306_LOCK_STATUS lockStatus; | |
1113 | ||
1114 | modeOper = LG3306_UNKNOWN_MODE; | |
1115 | ||
8e8cd34e MIK |
1116 | switch (whatLock) { |
1117 | case LG3306_SYNC_LOCK: | |
1118 | { | |
1119 | ret = lgdt3306a_read_reg(state, 0x00A6, &val); | |
1120 | ||
1121 | if ((val & 0x80) == 0x80) | |
1122 | lockStatus = LG3306_LOCK; | |
1123 | else | |
1124 | lockStatus = LG3306_UNLOCK; | |
1125 | ||
1126 | lg_dbg("SYNC_LOCK=%x\n", lockStatus); | |
1127 | break; | |
1128 | } | |
1129 | case LG3306_AGC_LOCK: | |
1130 | { | |
1131 | ret = lgdt3306a_read_reg(state, 0x0080, &val); | |
1132 | ||
1133 | if ((val & 0x40) == 0x40) | |
1134 | lockStatus = LG3306_LOCK; | |
1135 | else | |
1136 | lockStatus = LG3306_UNLOCK; | |
1137 | ||
1138 | lg_dbg("AGC_LOCK=%x\n", lockStatus); | |
1139 | break; | |
1140 | } | |
1141 | case LG3306_TR_LOCK: | |
b63b36fa | 1142 | { |
8e8cd34e MIK |
1143 | modeOper = lgdt3306a_check_oper_mode(state); |
1144 | if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) { | |
1145 | ret = lgdt3306a_read_reg(state, 0x1094, &val); | |
b63b36fa FR |
1146 | |
1147 | if ((val & 0x80) == 0x80) | |
1148 | lockStatus = LG3306_LOCK; | |
1149 | else | |
1150 | lockStatus = LG3306_UNLOCK; | |
8e8cd34e MIK |
1151 | } else |
1152 | lockStatus = LG3306_UNKNOWN_LOCK; | |
b63b36fa | 1153 | |
8e8cd34e MIK |
1154 | lg_dbg("TR_LOCK=%x\n", lockStatus); |
1155 | break; | |
1156 | } | |
1157 | case LG3306_FEC_LOCK: | |
1158 | { | |
1159 | modeOper = lgdt3306a_check_oper_mode(state); | |
1160 | if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) { | |
b63b36fa FR |
1161 | ret = lgdt3306a_read_reg(state, 0x0080, &val); |
1162 | ||
8e8cd34e | 1163 | if ((val & 0x10) == 0x10) |
b63b36fa FR |
1164 | lockStatus = LG3306_LOCK; |
1165 | else | |
1166 | lockStatus = LG3306_UNLOCK; | |
8e8cd34e MIK |
1167 | } else |
1168 | lockStatus = LG3306_UNKNOWN_LOCK; | |
b63b36fa | 1169 | |
8e8cd34e MIK |
1170 | lg_dbg("FEC_LOCK=%x\n", lockStatus); |
1171 | break; | |
1172 | } | |
b63b36fa | 1173 | |
8e8cd34e MIK |
1174 | default: |
1175 | lockStatus = LG3306_UNKNOWN_LOCK; | |
1176 | lg_warn("UNKNOWN whatLock=%d\n", whatLock); | |
1177 | break; | |
b63b36fa FR |
1178 | } |
1179 | ||
8e8cd34e | 1180 | return lockStatus; |
b63b36fa FR |
1181 | } |
1182 | ||
1183 | static LG3306_NEVERLOCK_STATUS lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state) | |
1184 | { | |
1185 | u8 val = 0; | |
1186 | int ret; | |
1187 | LG3306_NEVERLOCK_STATUS lockStatus; | |
1188 | ||
1189 | ret = lgdt3306a_read_reg(state, 0x0080, &val); | |
1190 | lockStatus = (LG3306_NEVERLOCK_STATUS)(val & 0x03); | |
1191 | ||
1192 | lg_dbg("NeverLock=%d", lockStatus); | |
1193 | ||
8e8cd34e | 1194 | return lockStatus; |
b63b36fa FR |
1195 | } |
1196 | ||
1197 | static void lgdt3306a_pre_monitoring(struct lgdt3306a_state *state) | |
1198 | { | |
1199 | u8 val = 0; | |
1200 | int ret; | |
1201 | u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus; | |
1202 | ||
8e8cd34e | 1203 | /* Channel variation */ |
b63b36fa FR |
1204 | ret = lgdt3306a_read_reg(state, 0x21BC, &currChDiffACQ); |
1205 | ||
8e8cd34e | 1206 | /* SNR of Frame sync */ |
b63b36fa FR |
1207 | ret = lgdt3306a_read_reg(state, 0x21A1, &val); |
1208 | snrRef = val & 0x3F; | |
1209 | ||
8e8cd34e | 1210 | /* Strong Main CIR */ |
b63b36fa FR |
1211 | ret = lgdt3306a_read_reg(state, 0x2199, &val); |
1212 | mainStrong = (val & 0x40) >> 6; | |
1213 | ||
1214 | ret = lgdt3306a_read_reg(state, 0x0090, &val); | |
1215 | aiccrejStatus = (val & 0xF0) >> 4; | |
1216 | ||
1217 | lg_dbg("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n", | |
1218 | snrRef, mainStrong, aiccrejStatus, currChDiffACQ); | |
1219 | ||
8e8cd34e MIK |
1220 | #if 0 |
1221 | if ((mainStrong == 0) && (currChDiffACQ > 0x70)) /* Dynamic ghost exists */ | |
1222 | #endif | |
1223 | if (mainStrong == 0) { | |
b63b36fa FR |
1224 | ret = lgdt3306a_read_reg(state, 0x2135, &val); |
1225 | val &= 0x0F; | |
1226 | val |= 0xA0; | |
1227 | ret = lgdt3306a_write_reg(state, 0x2135, val); | |
1228 | ||
1229 | ret = lgdt3306a_read_reg(state, 0x2141, &val); | |
1230 | val &= 0x3F; | |
1231 | val |= 0x80; | |
1232 | ret = lgdt3306a_write_reg(state, 0x2141, val); | |
1233 | ||
1234 | ret = lgdt3306a_write_reg(state, 0x2122, 0x70); | |
8e8cd34e | 1235 | } else { /* Weak ghost or static channel */ |
b63b36fa FR |
1236 | ret = lgdt3306a_read_reg(state, 0x2135, &val); |
1237 | val &= 0x0F; | |
1238 | val |= 0x70; | |
1239 | ret = lgdt3306a_write_reg(state, 0x2135, val); | |
1240 | ||
1241 | ret = lgdt3306a_read_reg(state, 0x2141, &val); | |
1242 | val &= 0x3F; | |
1243 | val |= 0x40; | |
1244 | ret = lgdt3306a_write_reg(state, 0x2141, val); | |
1245 | ||
1246 | ret = lgdt3306a_write_reg(state, 0x2122, 0x40); | |
1247 | } | |
1248 | ||
1249 | } | |
1250 | ||
1251 | static LG3306_LOCK_STATUS lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state) | |
1252 | { | |
8e8cd34e | 1253 | LG3306_LOCK_STATUS syncLockStatus = LG3306_UNLOCK; |
b63b36fa FR |
1254 | int i; |
1255 | ||
1256 | for (i = 0; i < 2; i++) { | |
1257 | msleep(30); | |
1258 | ||
1259 | syncLockStatus = lgdt3306a_check_lock_status(state, LG3306_SYNC_LOCK); | |
1260 | ||
1261 | if (syncLockStatus == LG3306_LOCK) { | |
1262 | lg_dbg("locked(%d)\n", i); | |
8e8cd34e | 1263 | return LG3306_LOCK; |
b63b36fa FR |
1264 | } |
1265 | } | |
1266 | lg_dbg("not locked\n"); | |
8e8cd34e | 1267 | return LG3306_UNLOCK; |
b63b36fa FR |
1268 | } |
1269 | ||
1270 | static LG3306_LOCK_STATUS lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state) | |
1271 | { | |
1272 | LG3306_LOCK_STATUS FECLockStatus = LG3306_UNLOCK; | |
1273 | int i; | |
1274 | ||
1275 | for (i = 0; i < 2; i++) { | |
1276 | msleep(30); | |
1277 | ||
1278 | FECLockStatus = lgdt3306a_check_lock_status(state, LG3306_FEC_LOCK); | |
1279 | ||
1280 | if (FECLockStatus == LG3306_LOCK) { | |
1281 | lg_dbg("locked(%d)\n", i); | |
8e8cd34e | 1282 | return FECLockStatus; |
b63b36fa FR |
1283 | } |
1284 | } | |
1285 | lg_dbg("not locked\n"); | |
8e8cd34e | 1286 | return FECLockStatus; |
b63b36fa FR |
1287 | } |
1288 | ||
1289 | static LG3306_NEVERLOCK_STATUS lgdt3306a_neverlock_poll(struct lgdt3306a_state *state) | |
1290 | { | |
1291 | LG3306_NEVERLOCK_STATUS NLLockStatus = LG3306_NL_FAIL; | |
1292 | int i; | |
1293 | ||
8e8cd34e | 1294 | for (i = 0; i < 5; i++) { |
b63b36fa FR |
1295 | msleep(30); |
1296 | ||
1297 | NLLockStatus = lgdt3306a_check_neverlock_status(state); | |
1298 | ||
1299 | if (NLLockStatus == LG3306_NL_LOCK) { | |
1300 | lg_dbg("NL_LOCK(%d)\n", i); | |
8e8cd34e | 1301 | return NLLockStatus; |
b63b36fa FR |
1302 | } |
1303 | } | |
1304 | lg_dbg("NLLockStatus=%d\n", NLLockStatus); | |
8e8cd34e | 1305 | return NLLockStatus; |
b63b36fa FR |
1306 | } |
1307 | ||
1308 | static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state) | |
1309 | { | |
1310 | u8 val; | |
1311 | int ret; | |
1312 | ||
1313 | ret = lgdt3306a_read_reg(state, 0x00FA, &val); | |
1314 | ||
8e8cd34e | 1315 | return val; |
b63b36fa FR |
1316 | } |
1317 | ||
1318 | static u32 log10_x1000(u32 x) | |
1319 | { | |
8e8cd34e MIK |
1320 | static u32 valx_x10[] = { 10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100 }; |
1321 | static u32 log10x_x1000[] = { 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000 }; | |
1322 | static u32 nelems = sizeof(valx_x10)/sizeof(valx_x10[0]); | |
b63b36fa | 1323 | u32 log_val = 0; |
8e8cd34e | 1324 | u32 i; |
b63b36fa | 1325 | |
8e8cd34e MIK |
1326 | if (x <= 0) |
1327 | return -1000000; /* signal error */ | |
b63b36fa | 1328 | |
8e8cd34e MIK |
1329 | if (x < 10) { |
1330 | while (x < 10) { | |
1331 | x = x * 10; | |
b63b36fa FR |
1332 | log_val--; |
1333 | } | |
8e8cd34e MIK |
1334 | } else if (x == 10) { |
1335 | return 0; /* log(1)=0 */ | |
b63b36fa | 1336 | } else { |
8e8cd34e MIK |
1337 | while (x >= 100) { |
1338 | x = x / 10; | |
b63b36fa FR |
1339 | log_val++; |
1340 | } | |
8e8cd34e | 1341 | } |
b63b36fa FR |
1342 | log_val *= 1000; |
1343 | ||
8e8cd34e MIK |
1344 | if (x == 10) /* was our input an exact multiple of 10 */ |
1345 | return log_val; /* don't need to interpolate */ | |
b63b36fa | 1346 | |
8e8cd34e MIK |
1347 | /* find our place on the log curve */ |
1348 | for (i = 1; i < nelems; i++) { | |
1349 | if (valx_x10[i] >= x) | |
1350 | break; | |
b63b36fa FR |
1351 | } |
1352 | ||
1353 | { | |
1354 | u32 diff_val = x - valx_x10[i-1]; | |
1355 | u32 step_val = valx_x10[i] - valx_x10[i-1]; | |
1356 | u32 step_log10 = log10x_x1000[i] - log10x_x1000[i-1]; | |
8e8cd34e MIK |
1357 | /* do a linear interpolation to get in-between values */ |
1358 | return log_val + log10x_x1000[i-1] + | |
1359 | ((diff_val*step_log10) / step_val); | |
b63b36fa FR |
1360 | } |
1361 | } | |
1362 | ||
1363 | static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state) | |
1364 | { | |
1365 | u32 mse; /* Mean-Square Error */ | |
1366 | u32 pwr; /* Constelation power */ | |
1367 | u32 snr_x100; | |
1368 | ||
1369 | mse = (read_reg(state, 0x00EC) << 8) | | |
1370 | (read_reg(state, 0x00ED)); | |
1371 | pwr = (read_reg(state, 0x00E8) << 8) | | |
1372 | (read_reg(state, 0x00E9)); | |
1373 | ||
1374 | if (mse == 0) /* no signal */ | |
1375 | return 0; | |
1376 | ||
8e8cd34e | 1377 | snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000; |
b63b36fa FR |
1378 | lg_dbg("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100); |
1379 | ||
1380 | return snr_x100; | |
1381 | } | |
1382 | ||
1383 | static LG3306_LOCK_STATUS lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state) | |
1384 | { | |
8e8cd34e MIK |
1385 | u8 cnt = 0; |
1386 | u8 packet_error; | |
1387 | u32 snr; | |
b63b36fa | 1388 | |
8e8cd34e | 1389 | while (1) { |
b63b36fa FR |
1390 | if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) { |
1391 | lg_dbg("no sync lock!\n"); | |
8e8cd34e | 1392 | return LG3306_UNLOCK; |
b63b36fa FR |
1393 | } else { |
1394 | msleep(20); | |
1395 | lgdt3306a_pre_monitoring(state); | |
1396 | ||
1397 | packet_error = lgdt3306a_get_packet_error(state); | |
1398 | snr = lgdt3306a_calculate_snr_x100(state); | |
8e8cd34e MIK |
1399 | lg_dbg("cnt=%d errors=%d snr=%d\n", |
1400 | cnt, packet_error, snr); | |
b63b36fa | 1401 | |
8e8cd34e | 1402 | if ((snr < 1500) || (packet_error >= 0xff)) |
b63b36fa | 1403 | cnt++; |
8e8cd34e MIK |
1404 | else |
1405 | return LG3306_LOCK; | |
b63b36fa | 1406 | |
8e8cd34e | 1407 | if (cnt >= 10) { |
b63b36fa | 1408 | lg_dbg("not locked!\n"); |
8e8cd34e | 1409 | return LG3306_UNLOCK; |
b63b36fa FR |
1410 | } |
1411 | } | |
1412 | } | |
8e8cd34e | 1413 | return LG3306_UNLOCK; |
b63b36fa FR |
1414 | } |
1415 | ||
1416 | static LG3306_LOCK_STATUS lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state) | |
1417 | { | |
1418 | u8 cnt = 0; | |
1419 | u8 packet_error; | |
1420 | u32 snr; | |
1421 | ||
8e8cd34e MIK |
1422 | while (1) { |
1423 | if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) { | |
b63b36fa | 1424 | lg_dbg("no fec lock!\n"); |
8e8cd34e | 1425 | return LG3306_UNLOCK; |
b63b36fa FR |
1426 | } else { |
1427 | msleep(20); | |
1428 | ||
1429 | packet_error = lgdt3306a_get_packet_error(state); | |
1430 | snr = lgdt3306a_calculate_snr_x100(state); | |
8e8cd34e MIK |
1431 | lg_dbg("cnt=%d errors=%d snr=%d\n", |
1432 | cnt, packet_error, snr); | |
b63b36fa | 1433 | |
8e8cd34e | 1434 | if ((snr < 1500) || (packet_error >= 0xff)) |
b63b36fa | 1435 | cnt++; |
8e8cd34e MIK |
1436 | else |
1437 | return LG3306_LOCK; | |
b63b36fa | 1438 | |
8e8cd34e | 1439 | if (cnt >= 10) { |
b63b36fa | 1440 | lg_dbg("not locked!\n"); |
8e8cd34e | 1441 | return LG3306_UNLOCK; |
b63b36fa FR |
1442 | } |
1443 | } | |
1444 | } | |
8e8cd34e | 1445 | return LG3306_UNLOCK; |
b63b36fa FR |
1446 | } |
1447 | ||
1448 | static int lgdt3306a_read_status(struct dvb_frontend *fe, fe_status_t *status) | |
1449 | { | |
b63b36fa | 1450 | struct lgdt3306a_state *state = fe->demodulator_priv; |
b63b36fa | 1451 | u16 strength = 0; |
8e8cd34e MIK |
1452 | int ret = 0; |
1453 | ||
b63b36fa FR |
1454 | if (fe->ops.tuner_ops.get_rf_strength) { |
1455 | ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength); | |
8e8cd34e | 1456 | if (ret == 0) { |
b63b36fa FR |
1457 | lg_dbg("strength=%d\n", strength); |
1458 | } else { | |
1459 | lg_dbg("fe->ops.tuner_ops.get_rf_strength() failed\n"); | |
1460 | } | |
1461 | } | |
1462 | ||
1463 | *status = 0; | |
8e8cd34e | 1464 | if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) { |
b63b36fa FR |
1465 | *status |= FE_HAS_SIGNAL; |
1466 | *status |= FE_HAS_CARRIER; | |
1467 | ||
1468 | switch (state->current_modulation) { | |
1469 | case QAM_256: | |
1470 | case QAM_64: | |
8e8cd34e | 1471 | if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) { |
b63b36fa FR |
1472 | *status |= FE_HAS_VITERBI; |
1473 | *status |= FE_HAS_SYNC; | |
1474 | ||
1475 | *status |= FE_HAS_LOCK; | |
1476 | } | |
1477 | break; | |
1478 | case VSB_8: | |
8e8cd34e | 1479 | if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) { |
b63b36fa FR |
1480 | *status |= FE_HAS_VITERBI; |
1481 | *status |= FE_HAS_SYNC; | |
1482 | ||
1483 | *status |= FE_HAS_LOCK; | |
1484 | ||
1485 | lgdt3306a_monitor_vsb(state); | |
1486 | } | |
1487 | break; | |
1488 | default: | |
1489 | ret = -EINVAL; | |
1490 | } | |
1491 | } | |
1492 | return ret; | |
1493 | } | |
1494 | ||
1495 | ||
1496 | static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr) | |
1497 | { | |
1498 | struct lgdt3306a_state *state = fe->demodulator_priv; | |
1499 | ||
1500 | state->snr = lgdt3306a_calculate_snr_x100(state); | |
1501 | /* report SNR in dB * 10 */ | |
1502 | *snr = state->snr/10; | |
1503 | ||
1504 | return 0; | |
1505 | } | |
1506 | ||
1507 | static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe, | |
1508 | u16 *strength) | |
1509 | { | |
1510 | /* | |
1511 | * Calculate some sort of "strength" from SNR | |
1512 | */ | |
1513 | struct lgdt3306a_state *state = fe->demodulator_priv; | |
8e8cd34e | 1514 | u16 snr; /* snr_x10 */ |
b63b36fa | 1515 | int ret; |
8e8cd34e | 1516 | u32 ref_snr; /* snr*100 */ |
b63b36fa FR |
1517 | u32 str; |
1518 | ||
1519 | *strength = 0; | |
1520 | ||
1521 | switch (state->current_modulation) { | |
1522 | case VSB_8: | |
8e8cd34e | 1523 | ref_snr = 1600; /* 16dB */ |
b63b36fa FR |
1524 | break; |
1525 | case QAM_64: | |
8e8cd34e | 1526 | ref_snr = 2200; /* 22dB */ |
b63b36fa FR |
1527 | break; |
1528 | case QAM_256: | |
8e8cd34e | 1529 | ref_snr = 2800; /* 28dB */ |
b63b36fa FR |
1530 | break; |
1531 | default: | |
1532 | return -EINVAL; | |
1533 | } | |
1534 | ||
1535 | ret = fe->ops.read_snr(fe, &snr); | |
1536 | if (lg_chkerr(ret)) | |
1537 | goto fail; | |
1538 | ||
8e8cd34e | 1539 | if (state->snr <= (ref_snr - 100)) |
b63b36fa | 1540 | str = 0; |
8e8cd34e MIK |
1541 | else if (state->snr <= ref_snr) |
1542 | str = (0xffff * 65) / 100; /* 65% */ | |
b63b36fa FR |
1543 | else { |
1544 | str = state->snr - ref_snr; | |
1545 | str /= 50; | |
8e8cd34e MIK |
1546 | str += 78; /* 78%-100% */ |
1547 | if (str > 100) | |
b63b36fa FR |
1548 | str = 100; |
1549 | str = (0xffff * str) / 100; | |
1550 | } | |
1551 | *strength = (u16)str; | |
1552 | lg_dbg("strength=%u\n", *strength); | |
1553 | ||
1554 | fail: | |
1555 | return ret; | |
1556 | } | |
1557 | ||
1558 | /* ------------------------------------------------------------------------ */ | |
1559 | ||
1560 | static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber) | |
1561 | { | |
1562 | struct lgdt3306a_state *state = fe->demodulator_priv; | |
1563 | u32 tmp; | |
1564 | ||
1565 | *ber = 0; | |
1566 | #if 1 | |
8e8cd34e MIK |
1567 | /* FGR - BUGBUG - I don't know what value is expected by dvb_core |
1568 | * what is the scale of the value?? */ | |
1569 | tmp = read_reg(state, 0x00FC); /* NBERVALUE[24-31] */ | |
1570 | tmp = (tmp << 8) | read_reg(state, 0x00FD); /* NBERVALUE[16-23] */ | |
1571 | tmp = (tmp << 8) | read_reg(state, 0x00FE); /* NBERVALUE[8-15] */ | |
1572 | tmp = (tmp << 8) | read_reg(state, 0x00FF); /* NBERVALUE[0-7] */ | |
b63b36fa FR |
1573 | *ber = tmp; |
1574 | lg_dbg("ber=%u\n", tmp); | |
1575 | #endif | |
1576 | return 0; | |
1577 | } | |
1578 | ||
1579 | static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) | |
1580 | { | |
1581 | struct lgdt3306a_state *state = fe->demodulator_priv; | |
1582 | ||
8e8cd34e | 1583 | *ucblocks = 0; |
b63b36fa | 1584 | #if 1 |
8e8cd34e MIK |
1585 | /* FGR - BUGBUG - I don't know what value is expected by dvb_core |
1586 | * what happens when value wraps? */ | |
1587 | *ucblocks = read_reg(state, 0x00F4); /* TPIFTPERRCNT[0-7] */ | |
b63b36fa FR |
1588 | lg_dbg("ucblocks=%u\n", *ucblocks); |
1589 | #endif | |
1590 | ||
1591 | return 0; | |
1592 | } | |
1593 | ||
1594 | static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune, unsigned int mode_flags, unsigned int *delay, fe_status_t *status) | |
1595 | { | |
1596 | int ret = 0; | |
1597 | struct lgdt3306a_state *state = fe->demodulator_priv; | |
1598 | ||
1599 | lg_dbg("re_tune=%u\n", re_tune); | |
1600 | ||
1601 | if (re_tune) { | |
8e8cd34e MIK |
1602 | state->current_frequency = -1; /* force re-tune */ |
1603 | if ((ret = lgdt3306a_set_parameters(fe)) != 0) | |
b63b36fa | 1604 | return ret; |
b63b36fa FR |
1605 | } |
1606 | *delay = 125; | |
1607 | ret = lgdt3306a_read_status(fe, status); | |
1608 | ||
1609 | return ret; | |
1610 | } | |
1611 | ||
1612 | static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe, | |
8e8cd34e MIK |
1613 | struct dvb_frontend_tune_settings |
1614 | *fe_tune_settings) | |
b63b36fa FR |
1615 | { |
1616 | fe_tune_settings->min_delay_ms = 100; | |
1617 | lg_dbg("\n"); | |
1618 | return 0; | |
1619 | } | |
1620 | ||
1621 | static int lgdt3306a_search(struct dvb_frontend *fe) | |
1622 | { | |
1623 | fe_status_t status = 0; | |
1624 | int i, ret; | |
1625 | ||
1626 | /* set frontend */ | |
1627 | ret = lgdt3306a_set_parameters(fe); | |
1628 | if (ret) | |
1629 | goto error; | |
1630 | ||
1631 | /* wait frontend lock */ | |
1632 | for (i = 20; i > 0; i--) { | |
1633 | lg_dbg(": loop=%d\n", i); | |
1634 | msleep(50); | |
1635 | ret = lgdt3306a_read_status(fe, &status); | |
1636 | if (ret) | |
1637 | goto error; | |
1638 | ||
1639 | if (status & FE_HAS_LOCK) | |
1640 | break; | |
1641 | } | |
1642 | ||
1643 | /* check if we have a valid signal */ | |
8e8cd34e | 1644 | if (status & FE_HAS_LOCK) |
b63b36fa | 1645 | return DVBFE_ALGO_SEARCH_SUCCESS; |
8e8cd34e | 1646 | else |
b63b36fa | 1647 | return DVBFE_ALGO_SEARCH_AGAIN; |
b63b36fa FR |
1648 | |
1649 | error: | |
1650 | lg_dbg("failed (%d)\n", ret); | |
1651 | return DVBFE_ALGO_SEARCH_ERROR; | |
1652 | } | |
1653 | ||
1654 | static void lgdt3306a_release(struct dvb_frontend *fe) | |
1655 | { | |
1656 | struct lgdt3306a_state *state = fe->demodulator_priv; | |
8e8cd34e | 1657 | |
b63b36fa FR |
1658 | lg_dbg("\n"); |
1659 | kfree(state); | |
1660 | } | |
1661 | ||
1662 | static struct dvb_frontend_ops lgdt3306a_ops; | |
1663 | ||
1664 | struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config, | |
1665 | struct i2c_adapter *i2c_adap) | |
1666 | { | |
1667 | struct lgdt3306a_state *state = NULL; | |
1668 | int ret; | |
1669 | u8 val; | |
1670 | ||
1671 | lg_dbg("(%d-%04x)\n", | |
1672 | i2c_adap ? i2c_adapter_id(i2c_adap) : 0, | |
1673 | config ? config->i2c_addr : 0); | |
1674 | ||
1675 | state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL); | |
1676 | if (state == NULL) | |
1677 | goto fail; | |
1678 | ||
1679 | state->cfg = config; | |
1680 | state->i2c_adap = i2c_adap; | |
1681 | ||
1682 | memcpy(&state->frontend.ops, &lgdt3306a_ops, | |
1683 | sizeof(struct dvb_frontend_ops)); | |
1684 | state->frontend.demodulator_priv = state; | |
1685 | ||
1686 | /* verify that we're talking to a lg3306a */ | |
8e8cd34e MIK |
1687 | /* FGR - NOTE - there is no obvious ChipId to check; we check |
1688 | * some "known" bits after reset, but it's still just a guess */ | |
b63b36fa FR |
1689 | ret = lgdt3306a_read_reg(state, 0x0000, &val); |
1690 | if (lg_chkerr(ret)) | |
1691 | goto fail; | |
8e8cd34e | 1692 | if ((val & 0x74) != 0x74) { |
b63b36fa | 1693 | lg_warn("expected 0x74, got 0x%x\n", (val & 0x74)); |
8e8cd34e MIK |
1694 | #if 0 |
1695 | goto fail; /* BUGBUG - re-enable when we know this is right */ | |
1696 | #endif | |
b63b36fa FR |
1697 | } |
1698 | ret = lgdt3306a_read_reg(state, 0x0001, &val); | |
1699 | if (lg_chkerr(ret)) | |
1700 | goto fail; | |
8e8cd34e | 1701 | if ((val & 0xF6) != 0xC6) { |
b63b36fa | 1702 | lg_warn("expected 0xC6, got 0x%x\n", (val & 0xF6)); |
8e8cd34e MIK |
1703 | #if 0 |
1704 | goto fail; /* BUGBUG - re-enable when we know this is right */ | |
1705 | #endif | |
b63b36fa FR |
1706 | } |
1707 | ret = lgdt3306a_read_reg(state, 0x0002, &val); | |
1708 | if (lg_chkerr(ret)) | |
1709 | goto fail; | |
8e8cd34e | 1710 | if ((val & 0x73) != 0x03) { |
b63b36fa | 1711 | lg_warn("expected 0x03, got 0x%x\n", (val & 0x73)); |
8e8cd34e MIK |
1712 | #if 0 |
1713 | goto fail; /* BUGBUG - re-enable when we know this is right */ | |
1714 | #endif | |
b63b36fa FR |
1715 | } |
1716 | ||
1717 | state->current_frequency = -1; | |
1718 | state->current_modulation = -1; | |
1719 | ||
1720 | lgdt3306a_sleep(state); | |
1721 | ||
1722 | return &state->frontend; | |
1723 | ||
1724 | fail: | |
1725 | lg_warn("unable to detect LGDT3306A hardware\n"); | |
1726 | kfree(state); | |
1727 | return NULL; | |
1728 | } | |
1729 | ||
1730 | #ifdef DBG_DUMP | |
1731 | ||
1732 | static const short regtab[] = { | |
1733 | 0x0000, //SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 | |
1734 | 0x0001, //1'b1 1'b1 1'b0 1'b0 AUTORPTRS | |
1735 | 0x0002, //NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT | |
1736 | 0x0003, //AGCRFOUT | |
1737 | 0x0004, //ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL | |
1738 | 0x0005, //PLLINDIVSE | |
1739 | 0x0006, //PLLCTRL[7:0] 11100001 | |
1740 | 0x0007, //SYSINITWAITTIME[7:0] (msec) 00001000 | |
1741 | 0x0008, //STDOPMODE[7:0] 10000000 | |
1742 | 0x0009, //1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 | |
1743 | 0x000A, //DAFTEN 1'b1 x x SCSYSLOCK | |
1744 | 0x000B, //SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 | |
1745 | 0x000D, //x SAMPLING4 | |
1746 | 0x000E, //SAMFREQ[15:8] 00000000 | |
1747 | 0x000F, //SAMFREQ[7:0] 00000000 | |
1748 | 0x0010, //IFFREQ[15:8] 01100000 | |
1749 | 0x0011, //IFFREQ[7:0] 00000000 | |
1750 | 0x0012, //AGCEN AGCREFMO | |
1751 | 0x0013, //AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 | |
1752 | 0x0014, //AGCFIXVALUE[7:0] 01111111 | |
1753 | 0x0015, //AGCREF[15:8] 00001010 | |
1754 | 0x0016, //AGCREF[7:0] 11100100 | |
1755 | 0x0017, //AGCDELAY[7:0] 00100000 | |
1756 | 0x0018, //AGCRFBW[3:0] AGCIFBW[3:0] 10001000 | |
1757 | 0x0019, //AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL | |
1758 | 0x001C, //1'b1 PFEN MFEN AICCVSYNC | |
1759 | 0x001D, //1'b0 1'b1 1'b0 1'b1 AICCVSYNC | |
1760 | 0x001E, //AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 | |
1761 | 0x001F, //AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 | |
1762 | 0x0020, //AICCDETTH[15:8] 01111100 | |
1763 | 0x0021, //AICCDETTH[7:0] 00000000 | |
1764 | 0x0022, //AICCOFFTH[15:8] 00000101 | |
1765 | 0x0023, //AICCOFFTH[7:0] 11100000 | |
1766 | 0x0024, //AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 | |
1767 | 0x0025, //AICCFIXFREQ3[23:16] 00000000 | |
1768 | 0x0026, //AICCFIXFREQ3[15:8] 00000000 | |
1769 | 0x0027, //AICCFIXFREQ3[7:0] 00000000 | |
1770 | 0x0028, //AICCFIXFREQ2[23:16] 00000000 | |
1771 | 0x0029, //AICCFIXFREQ2[15:8] 00000000 | |
1772 | 0x002A, //AICCFIXFREQ2[7:0] 00000000 | |
1773 | 0x002B, //AICCFIXFREQ1[23:16] 00000000 | |
1774 | 0x002C, //AICCFIXFREQ1[15:8] 00000000 | |
1775 | 0x002D, //AICCFIXFREQ1[7:0] 00000000 | |
1776 | 0x002E, //AICCFIXFREQ0[23:16] 00000000 | |
1777 | 0x002F, //AICCFIXFREQ0[15:8] 00000000 | |
1778 | 0x0030, //AICCFIXFREQ0[7:0] 00000000 | |
1779 | 0x0031, //1'b0 1'b1 1'b0 1'b0 x DAGC1STER | |
1780 | 0x0032, //DAGC1STEN DAGC1STER | |
1781 | 0x0033, //DAGC1STREF[15:8] 00001010 | |
1782 | 0x0034, //DAGC1STREF[7:0] 11100100 | |
1783 | 0x0035, //DAGC2NDE | |
1784 | 0x0036, //DAGC2NDREF[15:8] 00001010 | |
1785 | 0x0037, //DAGC2NDREF[7:0] 10000000 | |
1786 | 0x0038, //DAGC2NDLOCKDETRNGSEL[1:0] | |
1787 | 0x003D, //1'b1 SAMGEARS | |
1788 | 0x0040, //SAMLFGMA | |
1789 | 0x0041, //SAMLFBWM | |
1790 | 0x0044, //1'b1 CRGEARSHE | |
1791 | 0x0045, //CRLFGMAN | |
1792 | 0x0046, //CFLFBWMA | |
1793 | 0x0047, //CRLFGMAN | |
1794 | 0x0048, //x x x x CRLFGSTEP_VS[3:0] xxxx1001 | |
1795 | 0x0049, //CRLFBWMA | |
1796 | 0x004A, //CRLFBWMA | |
1797 | 0x0050, //1'b0 1'b1 1'b1 1'b0 MSECALCDA | |
1798 | 0x0070, //TPOUTEN TPIFEN TPCLKOUTE | |
1799 | 0x0071, //TPSENB TPSSOPBITE | |
1800 | 0x0073, //TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 | |
1801 | 0x0075, //x x x x x IQSWAPCTRL[2:0] xxxxx000 | |
1802 | 0x0076, //NBERCON NBERST NBERPOL NBERWSYN | |
1803 | 0x0077, //x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 | |
1804 | 0x0078, //NBERPOLY[31:24] 00000000 | |
1805 | 0x0079, //NBERPOLY[23:16] 00000000 | |
1806 | 0x007A, //NBERPOLY[15:8] 00000000 | |
1807 | 0x007B, //NBERPOLY[7:0] 00000000 | |
1808 | 0x007C, //NBERPED[31:24] 00000000 | |
1809 | 0x007D, //NBERPED[23:16] 00000000 | |
1810 | 0x007E, //NBERPED[15:8] 00000000 | |
1811 | 0x007F, //NBERPED[7:0] 00000000 | |
1812 | 0x0080, //x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] | |
1813 | 0x0085, //SPECINVST | |
1814 | 0x0088, //SYSLOCKTIME[15:8] | |
1815 | 0x0089, //SYSLOCKTIME[7:0] | |
1816 | 0x008C, //FECLOCKTIME[15:8] | |
1817 | 0x008D, //FECLOCKTIME[7:0] | |
1818 | 0x008E, //AGCACCOUT[15:8] | |
1819 | 0x008F, //AGCACCOUT[7:0] | |
1820 | 0x0090, //AICCREJSTATUS[3:0] AICCREJBUSY[3:0] | |
1821 | 0x0091, //AICCVSYNC | |
1822 | 0x009C, //CARRFREQOFFSET[15:8] | |
1823 | 0x009D, //CARRFREQOFFSET[7:0] | |
1824 | 0x00A1, //SAMFREQOFFSET[23:16] | |
1825 | 0x00A2, //SAMFREQOFFSET[15:8] | |
1826 | 0x00A3, //SAMFREQOFFSET[7:0] | |
1827 | 0x00A6, //SYNCLOCK SYNCLOCKH | |
1828 | #if 0//covered elsewhere | |
1829 | 0x00E8, //CONSTPWR[15:8] | |
1830 | 0x00E9, //CONSTPWR[7:0] | |
1831 | 0x00EA, //BMSE[15:8] | |
1832 | 0x00EB, //BMSE[7:0] | |
1833 | 0x00EC, //MSE[15:8] | |
1834 | 0x00ED, //MSE[7:0] | |
1835 | 0x00EE, //CONSTI[7:0] | |
1836 | 0x00EF, //CONSTQ[7:0] | |
1837 | #endif | |
1838 | 0x00F4, //TPIFTPERRCNT[7:0] | |
1839 | 0x00F5, //TPCORREC | |
1840 | 0x00F6, //VBBER[15:8] | |
1841 | 0x00F7, //VBBER[7:0] | |
1842 | 0x00F8, //VABER[15:8] | |
1843 | 0x00F9, //VABER[7:0] | |
1844 | 0x00FA, //TPERRCNT[7:0] | |
1845 | 0x00FB, //NBERLOCK x x x x x x x | |
1846 | 0x00FC, //NBERVALUE[31:24] | |
1847 | 0x00FD, //NBERVALUE[23:16] | |
1848 | 0x00FE, //NBERVALUE[15:8] | |
1849 | 0x00FF, //NBERVALUE[7:0] | |
1850 | 0x1000, //1'b0 WODAGCOU | |
1851 | 0x1005, //x x 1'b1 1'b1 x SRD_Q_QM | |
1852 | 0x1009, //SRDWAITTIME[7:0] (10msec) 00100011 | |
1853 | 0x100A, //SRDWAITTIME_CQS[7:0] (msec) 01100100 | |
1854 | 0x101A, //x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 | |
1855 | 0x1036, //1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 | |
1856 | 0x103C, //SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 | |
1857 | 0x103D, //1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 | |
1858 | 0x103F, //SAMZTEDSE | |
1859 | 0x105D, //EQSTATUSE | |
1860 | 0x105F, //x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 | |
1861 | 0x1060, //1'b1 EQSTATUSE | |
1862 | 0x1061, //CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 | |
1863 | 0x1065, //1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x | |
1864 | 0x1066, //1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE | |
1865 | 0x1068, //CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 | |
1866 | 0x106E, //x x x x x CREPHNEN_ | |
1867 | 0x106F, //CREPHNTH_V[7:0] 00010101 | |
1868 | 0x1072, //CRSWEEPN | |
1869 | 0x1073, //CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 | |
1870 | 0x1074, //CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 | |
1871 | 0x1080, //DAFTSTATUS[1:0] x x x x x x | |
1872 | 0x1081, //SRDSTATUS[1:0] x x x x x SRDLOCK | |
1873 | 0x10A9, //EQSTATUS_CQS[1:0] x x x x x x | |
1874 | 0x10B7, //EQSTATUS_V[1:0] x x x x x x | |
1875 | #if 0//SMART_ANT | |
1876 | 0x1F00, //MODEDETE | |
1877 | 0x1F01, //x x x x x x x SFNRST xxxxxxx0 | |
1878 | 0x1F03, //NUMOFANT[7:0] 10000000 | |
1879 | 0x1F04, //x SELMASK[6:0] x0000000 | |
1880 | 0x1F05, //x SETMASK[6:0] x0000000 | |
1881 | 0x1F06, //x TXDATA[6:0] x0000000 | |
1882 | 0x1F07, //x CHNUMBER[6:0] x0000000 | |
1883 | 0x1F09, //AGCTIME[23:16] 10011000 | |
1884 | 0x1F0A, //AGCTIME[15:8] 10010110 | |
1885 | 0x1F0B, //AGCTIME[7:0] 10000000 | |
1886 | 0x1F0C, //ANTTIME[31:24] 00000000 | |
1887 | 0x1F0D, //ANTTIME[23:16] 00000011 | |
1888 | 0x1F0E, //ANTTIME[15:8] 10010000 | |
1889 | 0x1F0F, //ANTTIME[7:0] 10010000 | |
1890 | 0x1F11, //SYNCTIME[23:16] 10011000 | |
1891 | 0x1F12, //SYNCTIME[15:8] 10010110 | |
1892 | 0x1F13, //SYNCTIME[7:0] 10000000 | |
1893 | 0x1F14, //SNRTIME[31:24] 00000001 | |
1894 | 0x1F15, //SNRTIME[23:16] 01111101 | |
1895 | 0x1F16, //SNRTIME[15:8] 01111000 | |
1896 | 0x1F17, //SNRTIME[7:0] 01000000 | |
1897 | 0x1F19, //FECTIME[23:16] 00000000 | |
1898 | 0x1F1A, //FECTIME[15:8] 01110010 | |
1899 | 0x1F1B, //FECTIME[7:0] 01110000 | |
1900 | 0x1F1D, //FECTHD[7:0] 00000011 | |
1901 | 0x1F1F, //SNRTHD[23:16] 00001000 | |
1902 | 0x1F20, //SNRTHD[15:8] 01111111 | |
1903 | 0x1F21, //SNRTHD[7:0] 10000101 | |
1904 | 0x1F80, //IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG | |
1905 | 0x1F81, //x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO | |
1906 | 0x1F82, //x x x SCANOPCD[4:0] | |
1907 | 0x1F83, //x x x x MAINOPCD[3:0] | |
1908 | 0x1F84, //x x RXDATA[13:8] | |
1909 | 0x1F85, //RXDATA[7:0] | |
1910 | 0x1F86, //x x SDTDATA[13:8] | |
1911 | 0x1F87, //SDTDATA[7:0] | |
1912 | 0x1F89, //ANTSNR[23:16] | |
1913 | 0x1F8A, //ANTSNR[15:8] | |
1914 | 0x1F8B, //ANTSNR[7:0] | |
1915 | 0x1F8C, //x x x x ANTFEC[13:8] | |
1916 | 0x1F8D, //ANTFEC[7:0] | |
1917 | 0x1F8E, //MAXCNT[7:0] | |
1918 | 0x1F8F, //SCANCNT[7:0] | |
1919 | 0x1F91, //MAXPW[23:16] | |
1920 | 0x1F92, //MAXPW[15:8] | |
1921 | 0x1F93, //MAXPW[7:0] | |
1922 | 0x1F95, //CURPWMSE[23:16] | |
1923 | 0x1F96, //CURPWMSE[15:8] | |
1924 | 0x1F97, //CURPWMSE[7:0] | |
1925 | #endif//SMART_ANT | |
1926 | 0x211F, //1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 | |
1927 | 0x212A, //EQAUTOST | |
1928 | 0x2122, //CHFAST[7:0] 01100000 | |
1929 | 0x212B, //FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 | |
1930 | 0x212C, //PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 | |
1931 | 0x212D, //1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS | |
1932 | 0x2135, //DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 | |
1933 | 0x2141, //TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 | |
1934 | 0x2162, //AICCCTRLE | |
1935 | 0x2173, //PHNCNFCNT[7:0] 00000100 | |
1936 | 0x2179, //1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 | |
1937 | 0x217A, //1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 | |
1938 | 0x217E, //CNFCNTTPIF[7:0] 00001000 | |
1939 | 0x217F, //TPERRCNTTPIF[7:0] 00000001 | |
1940 | 0x2180, //x x x x x x FBDLYCIR[9:8] | |
1941 | 0x2181, //FBDLYCIR[7:0] | |
1942 | 0x2185, //MAXPWRMAIN[7:0] | |
1943 | 0x2191, //NCOMBDET x x x x x x x | |
1944 | 0x2199, //x MAINSTRON | |
1945 | 0x219A, //FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] | |
1946 | 0x21A1, //x x SNRREF[5:0] | |
1947 | 0x2845, //1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 | |
1948 | 0x2846, //1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 | |
1949 | 0x2847, //ENNOSIGDE | |
1950 | 0x2849, //1'b1 1'b1 NOUSENOSI | |
1951 | 0x284A, //EQINITWAITTIME[7:0] 01100100 | |
1952 | 0x3000, //1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM | |
1953 | 0x3001, //RPTRSTWAITTIME[7:0] (100msec) 00110010 | |
1954 | 0x3031, //FRAMELOC | |
1955 | 0x3032, //1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 | |
1956 | 0x30A9, //VDLOCK_Q FRAMELOCK | |
1957 | 0x30AA, //MPEGLOCK | |
1958 | }; | |
1959 | ||
1960 | #define numDumpRegs (sizeof(regtab)/sizeof(regtab[0])) | |
1961 | static u8 regval1[numDumpRegs] = {0, }; | |
1962 | static u8 regval2[numDumpRegs] = {0, }; | |
1963 | ||
1964 | static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state) | |
1965 | { | |
1966 | memset(regval2, 0xff, sizeof(regval2)); | |
1967 | lgdt3306a_DumpRegs(state); | |
1968 | } | |
1969 | ||
1970 | static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state) | |
1971 | { | |
1972 | int i; | |
1973 | int sav_debug = debug; | |
8e8cd34e | 1974 | |
b63b36fa FR |
1975 | if ((debug & DBG_DUMP) == 0) |
1976 | return; | |
8e8cd34e | 1977 | debug &= ~DBG_REG; /* supress DBG_REG during reg dump */ |
b63b36fa FR |
1978 | |
1979 | lg_info("\n"); | |
1980 | ||
8e8cd34e | 1981 | for (i = 0; i < numDumpRegs; i++) { |
b63b36fa | 1982 | lgdt3306a_read_reg(state, regtab[i], ®val1[i]); |
8e8cd34e MIK |
1983 | if (regval1[i] != regval2[i]) { |
1984 | lg_info(" %04X = %02X\n", regtab[i], regval1[i]); | |
1985 | regval2[i] = regval1[i]; | |
b63b36fa FR |
1986 | } |
1987 | } | |
1988 | debug = sav_debug; | |
1989 | } | |
8e8cd34e | 1990 | #endif /* DBG_DUMP */ |
b63b36fa FR |
1991 | |
1992 | ||
1993 | ||
1994 | EXPORT_SYMBOL(lgdt3306a_attach); | |
1995 | ||
1996 | static struct dvb_frontend_ops lgdt3306a_ops = { | |
1997 | .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, | |
1998 | .info = { | |
1999 | .name = "LG Electronics LGDT3306A VSB/QAM Frontend", | |
8e8cd34e MIK |
2000 | #if 0 |
2001 | .type = FE_ATSC, | |
2002 | #endif | |
b63b36fa | 2003 | .frequency_min = 54000000, |
8e8cd34e | 2004 | .frequency_max = 858000000, |
b63b36fa FR |
2005 | .frequency_stepsize = 62500, |
2006 | .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB | |
2007 | }, | |
2008 | .i2c_gate_ctrl = lgdt3306a_i2c_gate_ctrl, | |
2009 | .init = lgdt3306a_init, | |
2010 | .sleep = lgdt3306a_fe_sleep, | |
2011 | /* if this is set, it overrides the default swzigzag */ | |
2012 | .tune = lgdt3306a_tune, | |
2013 | .set_frontend = lgdt3306a_set_parameters, | |
2014 | .get_frontend = lgdt3306a_get_frontend, | |
2015 | .get_frontend_algo = lgdt3306a_get_frontend_algo, | |
2016 | .get_tune_settings = lgdt3306a_get_tune_settings, | |
2017 | .read_status = lgdt3306a_read_status, | |
2018 | .read_ber = lgdt3306a_read_ber, | |
2019 | .read_signal_strength = lgdt3306a_read_signal_strength, | |
2020 | .read_snr = lgdt3306a_read_snr, | |
2021 | .read_ucblocks = lgdt3306a_read_ucblocks, | |
2022 | .release = lgdt3306a_release, | |
2023 | .ts_bus_ctrl = lgdt3306a_ts_bus_ctrl, | |
2024 | .search = lgdt3306a_search, | |
2025 | }; | |
2026 | ||
2027 | MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver"); | |
2028 | MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>"); | |
2029 | MODULE_LICENSE("GPL"); | |
2030 | MODULE_VERSION("0.2"); | |
2031 | ||
2032 | /* | |
2033 | * Local variables: | |
2034 | * c-basic-offset: 8 | |
2035 | * End: | |
2036 | */ |