Commit | Line | Data |
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b9ede79a MCC |
1 | /* |
2 | * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver | |
3 | * | |
a77cfcac | 4 | * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com> |
b9ede79a MCC |
5 | * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com> |
6 | * | |
b9ede79a MCC |
7 | * This program is free software; you can redistribute it and/or |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <asm/div64.h> | |
19 | ||
20 | #include "dvb_frontend.h" | |
21 | #include "mb86a20s.h" | |
22 | ||
23 | static int debug = 1; | |
24 | module_param(debug, int, 0644); | |
25 | MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); | |
26 | ||
b9ede79a MCC |
27 | struct mb86a20s_state { |
28 | struct i2c_adapter *i2c; | |
29 | const struct mb86a20s_config *config; | |
09b6d21e | 30 | u32 last_frequency; |
b9ede79a MCC |
31 | |
32 | struct dvb_frontend frontend; | |
c736a5f2 MCC |
33 | |
34 | bool need_init; | |
b9ede79a MCC |
35 | }; |
36 | ||
37 | struct regdata { | |
38 | u8 reg; | |
39 | u8 data; | |
40 | }; | |
41 | ||
42 | /* | |
43 | * Initialization sequence: Use whatevere default values that PV SBTVD | |
44 | * does on its initialisation, obtained via USB snoop | |
45 | */ | |
46 | static struct regdata mb86a20s_init[] = { | |
47 | { 0x70, 0x0f }, | |
48 | { 0x70, 0xff }, | |
49 | { 0x08, 0x01 }, | |
50 | { 0x09, 0x3e }, | |
a7025edf | 51 | { 0x50, 0xd1 }, { 0x51, 0x22 }, |
b9ede79a MCC |
52 | { 0x39, 0x01 }, |
53 | { 0x71, 0x00 }, | |
a7025edf MCC |
54 | { 0x28, 0x2a }, { 0x29, 0x00 }, { 0x2a, 0xff }, { 0x2b, 0x80 }, |
55 | { 0x28, 0x20 }, { 0x29, 0x33 }, { 0x2a, 0xdf }, { 0x2b, 0xa9 }, | |
ebe96749 | 56 | { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 }, |
b9ede79a MCC |
57 | { 0x3b, 0x21 }, |
58 | { 0x3c, 0x3a }, | |
59 | { 0x01, 0x0d }, | |
a7025edf MCC |
60 | { 0x04, 0x08 }, { 0x05, 0x05 }, |
61 | { 0x04, 0x0e }, { 0x05, 0x00 }, | |
62 | { 0x04, 0x0f }, { 0x05, 0x14 }, | |
63 | { 0x04, 0x0b }, { 0x05, 0x8c }, | |
64 | { 0x04, 0x00 }, { 0x05, 0x00 }, | |
65 | { 0x04, 0x01 }, { 0x05, 0x07 }, | |
66 | { 0x04, 0x02 }, { 0x05, 0x0f }, | |
67 | { 0x04, 0x03 }, { 0x05, 0xa0 }, | |
68 | { 0x04, 0x09 }, { 0x05, 0x00 }, | |
69 | { 0x04, 0x0a }, { 0x05, 0xff }, | |
70 | { 0x04, 0x27 }, { 0x05, 0x64 }, | |
71 | { 0x04, 0x28 }, { 0x05, 0x00 }, | |
72 | { 0x04, 0x1e }, { 0x05, 0xff }, | |
73 | { 0x04, 0x29 }, { 0x05, 0x0a }, | |
74 | { 0x04, 0x32 }, { 0x05, 0x0a }, | |
75 | { 0x04, 0x14 }, { 0x05, 0x02 }, | |
76 | { 0x04, 0x04 }, { 0x05, 0x00 }, | |
77 | { 0x04, 0x05 }, { 0x05, 0x22 }, | |
78 | { 0x04, 0x06 }, { 0x05, 0x0e }, | |
79 | { 0x04, 0x07 }, { 0x05, 0xd8 }, | |
80 | { 0x04, 0x12 }, { 0x05, 0x00 }, | |
81 | { 0x04, 0x13 }, { 0x05, 0xff }, | |
ebe96749 MCC |
82 | { 0x04, 0x15 }, { 0x05, 0x4e }, |
83 | { 0x04, 0x16 }, { 0x05, 0x20 }, | |
09b6d21e MCC |
84 | |
85 | /* | |
86 | * On this demod, when the bit count reaches the count below, | |
87 | * it collects the bit error count. The bit counters are initialized | |
88 | * to 65535 here. This warrants that all of them will be quickly | |
89 | * calculated when device gets locked. As TMCC is parsed, the values | |
90 | * can be adjusted later in the driver's code. | |
91 | */ | |
92 | { 0x52, 0x01 }, /* Turn on BER before Viterbi */ | |
93 | { 0x50, 0xa7 }, { 0x51, 0x00 }, | |
a7025edf MCC |
94 | { 0x50, 0xa8 }, { 0x51, 0xff }, |
95 | { 0x50, 0xa9 }, { 0x51, 0xff }, | |
09b6d21e | 96 | { 0x50, 0xaa }, { 0x51, 0x00 }, |
a7025edf MCC |
97 | { 0x50, 0xab }, { 0x51, 0xff }, |
98 | { 0x50, 0xac }, { 0x51, 0xff }, | |
09b6d21e | 99 | { 0x50, 0xad }, { 0x51, 0x00 }, |
a7025edf MCC |
100 | { 0x50, 0xae }, { 0x51, 0xff }, |
101 | { 0x50, 0xaf }, { 0x51, 0xff }, | |
09b6d21e MCC |
102 | |
103 | { 0x5e, 0x00 }, /* Turn off BER after Viterbi */ | |
a7025edf MCC |
104 | { 0x50, 0xdc }, { 0x51, 0x01 }, |
105 | { 0x50, 0xdd }, { 0x51, 0xf4 }, | |
106 | { 0x50, 0xde }, { 0x51, 0x01 }, | |
107 | { 0x50, 0xdf }, { 0x51, 0xf4 }, | |
108 | { 0x50, 0xe0 }, { 0x51, 0x01 }, | |
109 | { 0x50, 0xe1 }, { 0x51, 0xf4 }, | |
110 | { 0x50, 0xb0 }, { 0x51, 0x07 }, | |
111 | { 0x50, 0xb2 }, { 0x51, 0xff }, | |
112 | { 0x50, 0xb3 }, { 0x51, 0xff }, | |
113 | { 0x50, 0xb4 }, { 0x51, 0xff }, | |
114 | { 0x50, 0xb5 }, { 0x51, 0xff }, | |
115 | { 0x50, 0xb6 }, { 0x51, 0xff }, | |
116 | { 0x50, 0xb7 }, { 0x51, 0xff }, | |
117 | { 0x50, 0x50 }, { 0x51, 0x02 }, | |
09b6d21e MCC |
118 | { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */ |
119 | { 0x45, 0x04 }, /* CN symbol 4 */ | |
b9ede79a | 120 | { 0x48, 0x04 }, |
a7025edf MCC |
121 | { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */ |
122 | { 0x50, 0xd6 }, { 0x51, 0x1f }, | |
123 | { 0x50, 0xd2 }, { 0x51, 0x03 }, | |
124 | { 0x50, 0xd7 }, { 0x51, 0x3f }, | |
ebe96749 MCC |
125 | { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x28, 0x74 }, { 0x29, 0x40 }, |
126 | { 0x28, 0x46 }, { 0x29, 0x2c }, { 0x28, 0x46 }, { 0x29, 0x0c }, | |
ce77d120 MCC |
127 | |
128 | { 0x04, 0x40 }, { 0x05, 0x00 }, | |
ebe96749 MCC |
129 | { 0x28, 0x00 }, { 0x29, 0x10 }, |
130 | { 0x28, 0x05 }, { 0x29, 0x02 }, | |
b9ede79a | 131 | { 0x1c, 0x01 }, |
a7025edf MCC |
132 | { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 }, |
133 | { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d }, | |
134 | { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 }, | |
135 | { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 }, | |
136 | { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 }, | |
137 | { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 }, | |
138 | { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 }, | |
139 | { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 }, | |
140 | { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e }, | |
141 | { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e }, | |
142 | { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 }, | |
143 | { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f }, | |
144 | { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 }, | |
145 | { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 }, | |
146 | { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe }, | |
147 | { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 }, | |
148 | { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee }, | |
149 | { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 }, | |
150 | { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f }, | |
151 | { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 }, | |
152 | { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 }, | |
153 | { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a }, | |
154 | { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc }, | |
155 | { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba }, | |
156 | { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 }, | |
157 | { 0x50, 0x1e }, { 0x51, 0x5d }, | |
158 | { 0x50, 0x22 }, { 0x51, 0x00 }, | |
159 | { 0x50, 0x23 }, { 0x51, 0xc8 }, | |
160 | { 0x50, 0x24 }, { 0x51, 0x00 }, | |
161 | { 0x50, 0x25 }, { 0x51, 0xf0 }, | |
162 | { 0x50, 0x26 }, { 0x51, 0x00 }, | |
163 | { 0x50, 0x27 }, { 0x51, 0xc3 }, | |
164 | { 0x50, 0x39 }, { 0x51, 0x02 }, | |
ebe96749 | 165 | { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 }, |
b9ede79a MCC |
166 | { 0xd0, 0x00 }, |
167 | }; | |
168 | ||
169 | static struct regdata mb86a20s_reset_reception[] = { | |
170 | { 0x70, 0xf0 }, | |
171 | { 0x70, 0xff }, | |
172 | { 0x08, 0x01 }, | |
173 | { 0x08, 0x00 }, | |
174 | }; | |
175 | ||
09b6d21e MCC |
176 | static struct regdata mb86a20s_vber_reset[] = { |
177 | { 0x53, 0x00 }, /* VBER Counter reset */ | |
178 | { 0x53, 0x07 }, | |
179 | }; | |
180 | ||
181 | static struct regdata mb86a20s_per_reset[] = { | |
182 | { 0x50, 0xb1 }, /* PER Counter reset */ | |
183 | { 0x51, 0x07 }, | |
184 | { 0x51, 0x00 }, | |
185 | }; | |
186 | ||
dd4493ef MCC |
187 | /* |
188 | * I2C read/write functions and macros | |
189 | */ | |
190 | ||
b9ede79a | 191 | static int mb86a20s_i2c_writereg(struct mb86a20s_state *state, |
09b6d21e | 192 | u8 i2c_addr, u8 reg, u8 data) |
b9ede79a MCC |
193 | { |
194 | u8 buf[] = { reg, data }; | |
195 | struct i2c_msg msg = { | |
196 | .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 | |
197 | }; | |
198 | int rc; | |
199 | ||
200 | rc = i2c_transfer(state->i2c, &msg, 1); | |
201 | if (rc != 1) { | |
f66d81b5 MCC |
202 | dev_err(&state->i2c->dev, |
203 | "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n", | |
204 | __func__, rc, reg, data); | |
b9ede79a MCC |
205 | return rc; |
206 | } | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
211 | static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state, | |
212 | u8 i2c_addr, struct regdata *rd, int size) | |
213 | { | |
214 | int i, rc; | |
215 | ||
216 | for (i = 0; i < size; i++) { | |
217 | rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg, | |
218 | rd[i].data); | |
219 | if (rc < 0) | |
220 | return rc; | |
221 | } | |
222 | return 0; | |
223 | } | |
224 | ||
225 | static int mb86a20s_i2c_readreg(struct mb86a20s_state *state, | |
226 | u8 i2c_addr, u8 reg) | |
227 | { | |
228 | u8 val; | |
229 | int rc; | |
230 | struct i2c_msg msg[] = { | |
231 | { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, | |
232 | { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 } | |
233 | }; | |
234 | ||
235 | rc = i2c_transfer(state->i2c, msg, 2); | |
236 | ||
237 | if (rc != 2) { | |
f66d81b5 MCC |
238 | dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n", |
239 | __func__, reg, rc); | |
240 | return (rc < 0) ? rc : -EIO; | |
b9ede79a MCC |
241 | } |
242 | ||
243 | return val; | |
244 | } | |
245 | ||
246 | #define mb86a20s_readreg(state, reg) \ | |
247 | mb86a20s_i2c_readreg(state, state->config->demod_address, reg) | |
248 | #define mb86a20s_writereg(state, reg, val) \ | |
249 | mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val) | |
250 | #define mb86a20s_writeregdata(state, regdata) \ | |
251 | mb86a20s_i2c_writeregdata(state, state->config->demod_address, \ | |
252 | regdata, ARRAY_SIZE(regdata)) | |
253 | ||
09b6d21e MCC |
254 | /* |
255 | * Ancillary internal routines (likely compiled inlined) | |
256 | * | |
257 | * The functions below assume that gateway lock has already obtained | |
258 | */ | |
259 | ||
dd4493ef | 260 | static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status) |
b9ede79a MCC |
261 | { |
262 | struct mb86a20s_state *state = fe->demodulator_priv; | |
dd4493ef | 263 | int val; |
b9ede79a | 264 | |
dd4493ef | 265 | *status = 0; |
b9ede79a | 266 | |
dd4493ef MCC |
267 | val = mb86a20s_readreg(state, 0x0a) & 0xf; |
268 | if (val < 0) | |
269 | return val; | |
68541cda | 270 | |
dd4493ef MCC |
271 | if (val >= 2) |
272 | *status |= FE_HAS_SIGNAL; | |
b9ede79a | 273 | |
dd4493ef MCC |
274 | if (val >= 4) |
275 | *status |= FE_HAS_CARRIER; | |
7572f9c5 | 276 | |
dd4493ef MCC |
277 | if (val >= 5) |
278 | *status |= FE_HAS_VITERBI; | |
7572f9c5 | 279 | |
dd4493ef MCC |
280 | if (val >= 7) |
281 | *status |= FE_HAS_SYNC; | |
68541cda | 282 | |
dd4493ef MCC |
283 | if (val >= 8) /* Maybe 9? */ |
284 | *status |= FE_HAS_LOCK; | |
285 | ||
f66d81b5 MCC |
286 | dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n", |
287 | __func__, *status, val); | |
dd4493ef MCC |
288 | |
289 | return 0; | |
b9ede79a MCC |
290 | } |
291 | ||
09b6d21e | 292 | static int mb86a20s_read_signal_strength(struct dvb_frontend *fe) |
b9ede79a MCC |
293 | { |
294 | struct mb86a20s_state *state = fe->demodulator_priv; | |
09b6d21e | 295 | int rc; |
b9ede79a | 296 | unsigned rf_max, rf_min, rf; |
68541cda | 297 | |
b9ede79a MCC |
298 | /* Does a binary search to get RF strength */ |
299 | rf_max = 0xfff; | |
300 | rf_min = 0; | |
301 | do { | |
302 | rf = (rf_max + rf_min) / 2; | |
09b6d21e MCC |
303 | rc = mb86a20s_writereg(state, 0x04, 0x1f); |
304 | if (rc < 0) | |
305 | return rc; | |
306 | rc = mb86a20s_writereg(state, 0x05, rf >> 8); | |
307 | if (rc < 0) | |
308 | return rc; | |
309 | rc = mb86a20s_writereg(state, 0x04, 0x20); | |
310 | if (rc < 0) | |
311 | return rc; | |
312 | rc = mb86a20s_writereg(state, 0x04, rf); | |
313 | if (rc < 0) | |
314 | return rc; | |
b9ede79a | 315 | |
09b6d21e MCC |
316 | rc = mb86a20s_readreg(state, 0x02); |
317 | if (rc < 0) | |
318 | return rc; | |
319 | if (rc & 0x08) | |
b9ede79a MCC |
320 | rf_min = (rf_max + rf_min) / 2; |
321 | else | |
322 | rf_max = (rf_max + rf_min) / 2; | |
323 | if (rf_max - rf_min < 4) { | |
09b6d21e MCC |
324 | rf = (rf_max + rf_min) / 2; |
325 | ||
326 | /* Rescale it from 2^12 (4096) to 2^16 */ | |
327 | rf <<= (16 - 12); | |
f66d81b5 MCC |
328 | dev_dbg(&state->i2c->dev, |
329 | "%s: signal strength = %d (%d < RF=%d < %d)\n", | |
330 | __func__, rf, rf_min, rf >> 4, rf_max); | |
09b6d21e | 331 | return rf; |
b9ede79a MCC |
332 | } |
333 | } while (1); | |
334 | ||
b9ede79a MCC |
335 | return 0; |
336 | } | |
337 | ||
959a119f MCC |
338 | static int mb86a20s_get_modulation(struct mb86a20s_state *state, |
339 | unsigned layer) | |
340 | { | |
341 | int rc; | |
342 | static unsigned char reg[] = { | |
343 | [0] = 0x86, /* Layer A */ | |
344 | [1] = 0x8a, /* Layer B */ | |
345 | [2] = 0x8e, /* Layer C */ | |
346 | }; | |
347 | ||
82033bc5 | 348 | if (layer >= ARRAY_SIZE(reg)) |
959a119f MCC |
349 | return -EINVAL; |
350 | rc = mb86a20s_writereg(state, 0x6d, reg[layer]); | |
351 | if (rc < 0) | |
352 | return rc; | |
353 | rc = mb86a20s_readreg(state, 0x6e); | |
354 | if (rc < 0) | |
355 | return rc; | |
04585921 | 356 | switch ((rc >> 4) & 0x07) { |
959a119f MCC |
357 | case 0: |
358 | return DQPSK; | |
359 | case 1: | |
360 | return QPSK; | |
361 | case 2: | |
362 | return QAM_16; | |
363 | case 3: | |
364 | return QAM_64; | |
365 | default: | |
366 | return QAM_AUTO; | |
367 | } | |
368 | } | |
369 | ||
370 | static int mb86a20s_get_fec(struct mb86a20s_state *state, | |
371 | unsigned layer) | |
372 | { | |
373 | int rc; | |
374 | ||
375 | static unsigned char reg[] = { | |
376 | [0] = 0x87, /* Layer A */ | |
377 | [1] = 0x8b, /* Layer B */ | |
378 | [2] = 0x8f, /* Layer C */ | |
379 | }; | |
380 | ||
82033bc5 | 381 | if (layer >= ARRAY_SIZE(reg)) |
959a119f MCC |
382 | return -EINVAL; |
383 | rc = mb86a20s_writereg(state, 0x6d, reg[layer]); | |
384 | if (rc < 0) | |
385 | return rc; | |
386 | rc = mb86a20s_readreg(state, 0x6e); | |
387 | if (rc < 0) | |
388 | return rc; | |
04585921 | 389 | switch ((rc >> 4) & 0x07) { |
959a119f MCC |
390 | case 0: |
391 | return FEC_1_2; | |
392 | case 1: | |
393 | return FEC_2_3; | |
394 | case 2: | |
395 | return FEC_3_4; | |
396 | case 3: | |
397 | return FEC_5_6; | |
398 | case 4: | |
399 | return FEC_7_8; | |
400 | default: | |
401 | return FEC_AUTO; | |
402 | } | |
403 | } | |
404 | ||
405 | static int mb86a20s_get_interleaving(struct mb86a20s_state *state, | |
406 | unsigned layer) | |
407 | { | |
408 | int rc; | |
409 | ||
410 | static unsigned char reg[] = { | |
411 | [0] = 0x88, /* Layer A */ | |
412 | [1] = 0x8c, /* Layer B */ | |
413 | [2] = 0x90, /* Layer C */ | |
414 | }; | |
415 | ||
82033bc5 | 416 | if (layer >= ARRAY_SIZE(reg)) |
959a119f MCC |
417 | return -EINVAL; |
418 | rc = mb86a20s_writereg(state, 0x6d, reg[layer]); | |
419 | if (rc < 0) | |
420 | return rc; | |
421 | rc = mb86a20s_readreg(state, 0x6e); | |
422 | if (rc < 0) | |
423 | return rc; | |
04585921 MCC |
424 | |
425 | switch ((rc >> 4) & 0x07) { | |
426 | case 1: | |
427 | return GUARD_INTERVAL_1_4; | |
428 | case 2: | |
429 | return GUARD_INTERVAL_1_8; | |
430 | case 3: | |
431 | return GUARD_INTERVAL_1_16; | |
432 | case 4: | |
433 | return GUARD_INTERVAL_1_32; | |
434 | ||
435 | default: | |
436 | case 0: | |
437 | return GUARD_INTERVAL_AUTO; | |
438 | } | |
959a119f MCC |
439 | } |
440 | ||
441 | static int mb86a20s_get_segment_count(struct mb86a20s_state *state, | |
442 | unsigned layer) | |
443 | { | |
444 | int rc, count; | |
959a119f MCC |
445 | static unsigned char reg[] = { |
446 | [0] = 0x89, /* Layer A */ | |
447 | [1] = 0x8d, /* Layer B */ | |
448 | [2] = 0x91, /* Layer C */ | |
449 | }; | |
450 | ||
f66d81b5 MCC |
451 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
452 | ||
82033bc5 | 453 | if (layer >= ARRAY_SIZE(reg)) |
959a119f | 454 | return -EINVAL; |
f66d81b5 | 455 | |
959a119f MCC |
456 | rc = mb86a20s_writereg(state, 0x6d, reg[layer]); |
457 | if (rc < 0) | |
458 | return rc; | |
459 | rc = mb86a20s_readreg(state, 0x6e); | |
460 | if (rc < 0) | |
461 | return rc; | |
462 | count = (rc >> 4) & 0x0f; | |
463 | ||
f66d81b5 MCC |
464 | dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count); |
465 | ||
959a119f MCC |
466 | return count; |
467 | } | |
468 | ||
a77cfcac MCC |
469 | static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe) |
470 | { | |
f66d81b5 | 471 | struct mb86a20s_state *state = fe->demodulator_priv; |
a77cfcac MCC |
472 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
473 | ||
f66d81b5 MCC |
474 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
475 | ||
a77cfcac MCC |
476 | /* Fixed parameters */ |
477 | c->delivery_system = SYS_ISDBT; | |
478 | c->bandwidth_hz = 6000000; | |
479 | ||
480 | /* Initialize values that will be later autodetected */ | |
481 | c->isdbt_layer_enabled = 0; | |
482 | c->transmission_mode = TRANSMISSION_MODE_AUTO; | |
483 | c->guard_interval = GUARD_INTERVAL_AUTO; | |
484 | c->isdbt_sb_mode = 0; | |
485 | c->isdbt_sb_segment_count = 0; | |
486 | } | |
487 | ||
7c61d80a | 488 | static int mb86a20s_get_frontend(struct dvb_frontend *fe) |
b9ede79a | 489 | { |
959a119f | 490 | struct mb86a20s_state *state = fe->demodulator_priv; |
a77cfcac | 491 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
959a119f | 492 | int i, rc; |
b9ede79a | 493 | |
f66d81b5 MCC |
494 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
495 | ||
a77cfcac MCC |
496 | /* Reset frontend cache to default values */ |
497 | mb86a20s_reset_frontend_cache(fe); | |
959a119f | 498 | |
959a119f MCC |
499 | /* Check for partial reception */ |
500 | rc = mb86a20s_writereg(state, 0x6d, 0x85); | |
a77cfcac MCC |
501 | if (rc < 0) |
502 | return rc; | |
503 | rc = mb86a20s_readreg(state, 0x6e); | |
504 | if (rc < 0) | |
505 | return rc; | |
506 | c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0; | |
959a119f MCC |
507 | |
508 | /* Get per-layer data */ | |
a77cfcac | 509 | |
959a119f | 510 | for (i = 0; i < 3; i++) { |
f66d81b5 MCC |
511 | dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n", |
512 | __func__, 'A' + i); | |
513 | ||
959a119f | 514 | rc = mb86a20s_get_segment_count(state, i); |
a77cfcac | 515 | if (rc < 0) |
f66d81b5 | 516 | goto noperlayer_error; |
a77cfcac MCC |
517 | if (rc >= 0 && rc < 14) |
518 | c->layer[i].segment_count = rc; | |
519 | else { | |
520 | c->layer[i].segment_count = 0; | |
959a119f | 521 | continue; |
a77cfcac MCC |
522 | } |
523 | c->isdbt_layer_enabled |= 1 << i; | |
959a119f | 524 | rc = mb86a20s_get_modulation(state, i); |
a77cfcac | 525 | if (rc < 0) |
f66d81b5 MCC |
526 | goto noperlayer_error; |
527 | dev_dbg(&state->i2c->dev, "%s: modulation %d.\n", | |
528 | __func__, rc); | |
a77cfcac | 529 | c->layer[i].modulation = rc; |
959a119f | 530 | rc = mb86a20s_get_fec(state, i); |
a77cfcac | 531 | if (rc < 0) |
f66d81b5 MCC |
532 | goto noperlayer_error; |
533 | dev_dbg(&state->i2c->dev, "%s: FEC %d.\n", | |
534 | __func__, rc); | |
a77cfcac | 535 | c->layer[i].fec = rc; |
959a119f | 536 | rc = mb86a20s_get_interleaving(state, i); |
a77cfcac | 537 | if (rc < 0) |
f66d81b5 MCC |
538 | goto noperlayer_error; |
539 | dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n", | |
540 | __func__, rc); | |
a77cfcac | 541 | c->layer[i].interleaving = rc; |
959a119f MCC |
542 | } |
543 | ||
959a119f | 544 | rc = mb86a20s_writereg(state, 0x6d, 0x84); |
a77cfcac MCC |
545 | if (rc < 0) |
546 | return rc; | |
547 | if ((rc & 0x60) == 0x20) { | |
548 | c->isdbt_sb_mode = 1; | |
959a119f | 549 | /* At least, one segment should exist */ |
a77cfcac MCC |
550 | if (!c->isdbt_sb_segment_count) |
551 | c->isdbt_sb_segment_count = 1; | |
552 | } | |
959a119f MCC |
553 | |
554 | /* Get transmission mode and guard interval */ | |
959a119f | 555 | rc = mb86a20s_readreg(state, 0x07); |
a77cfcac MCC |
556 | if (rc < 0) |
557 | return rc; | |
558 | if ((rc & 0x60) == 0x20) { | |
559 | switch (rc & 0x0c >> 2) { | |
560 | case 0: | |
561 | c->transmission_mode = TRANSMISSION_MODE_2K; | |
562 | break; | |
563 | case 1: | |
564 | c->transmission_mode = TRANSMISSION_MODE_4K; | |
565 | break; | |
566 | case 2: | |
567 | c->transmission_mode = TRANSMISSION_MODE_8K; | |
568 | break; | |
959a119f | 569 | } |
a77cfcac MCC |
570 | } |
571 | if (!(rc & 0x10)) { | |
572 | switch (rc & 0x3) { | |
573 | case 0: | |
574 | c->guard_interval = GUARD_INTERVAL_1_4; | |
575 | break; | |
576 | case 1: | |
577 | c->guard_interval = GUARD_INTERVAL_1_8; | |
578 | break; | |
579 | case 2: | |
580 | c->guard_interval = GUARD_INTERVAL_1_16; | |
581 | break; | |
959a119f MCC |
582 | } |
583 | } | |
09b6d21e | 584 | return 0; |
959a119f | 585 | |
f66d81b5 | 586 | noperlayer_error: |
b9ede79a | 587 | |
09b6d21e MCC |
588 | /* per-layer info is incomplete; discard all per-layer */ |
589 | c->isdbt_layer_enabled = 0; | |
590 | ||
591 | return rc; | |
592 | } | |
593 | ||
594 | static int mb86a20s_reset_counters(struct dvb_frontend *fe) | |
595 | { | |
596 | struct mb86a20s_state *state = fe->demodulator_priv; | |
597 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
598 | int rc, val; | |
599 | ||
600 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); | |
601 | ||
602 | /* Reset the counters, if the channel changed */ | |
603 | if (state->last_frequency != c->frequency) { | |
604 | memset(&c->strength, 0, sizeof(c->strength)); | |
605 | memset(&c->cnr, 0, sizeof(c->cnr)); | |
606 | memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error)); | |
607 | memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count)); | |
608 | memset(&c->block_error, 0, sizeof(c->block_error)); | |
609 | memset(&c->block_count, 0, sizeof(c->block_count)); | |
610 | ||
611 | state->last_frequency = c->frequency; | |
612 | } | |
613 | ||
614 | /* Clear status for most stats */ | |
615 | ||
616 | /* BER counter reset */ | |
617 | rc = mb86a20s_writeregdata(state, mb86a20s_vber_reset); | |
618 | if (rc < 0) | |
619 | goto err; | |
620 | ||
621 | /* MER, PER counter reset */ | |
622 | rc = mb86a20s_writeregdata(state, mb86a20s_per_reset); | |
623 | if (rc < 0) | |
624 | goto err; | |
625 | ||
626 | /* CNR counter reset */ | |
627 | rc = mb86a20s_readreg(state, 0x45); | |
628 | if (rc < 0) | |
629 | goto err; | |
630 | val = rc; | |
631 | rc = mb86a20s_writereg(state, 0x45, val | 0x10); | |
632 | if (rc < 0) | |
633 | goto err; | |
634 | rc = mb86a20s_writereg(state, 0x45, val & 0x6f); | |
635 | if (rc < 0) | |
636 | goto err; | |
637 | ||
638 | /* MER counter reset */ | |
639 | rc = mb86a20s_writereg(state, 0x50, 0x50); | |
640 | if (rc < 0) | |
641 | goto err; | |
642 | rc = mb86a20s_readreg(state, 0x51); | |
643 | if (rc < 0) | |
644 | goto err; | |
645 | val = rc; | |
646 | rc = mb86a20s_writereg(state, 0x51, val | 0x01); | |
647 | if (rc < 0) | |
648 | goto err; | |
649 | rc = mb86a20s_writereg(state, 0x51, val & 0x06); | |
650 | if (rc < 0) | |
651 | goto err; | |
652 | ||
149d518a | 653 | goto ok; |
09b6d21e | 654 | err: |
149d518a MCC |
655 | dev_err(&state->i2c->dev, |
656 | "%s: Can't reset FE statistics (error %d).\n", | |
657 | __func__, rc); | |
658 | ok: | |
a77cfcac | 659 | return rc; |
09b6d21e MCC |
660 | } |
661 | ||
149d518a MCC |
662 | static int mb86a20s_get_ber_before_vterbi(struct dvb_frontend *fe, |
663 | unsigned layer, | |
664 | u32 *error, u32 *count) | |
665 | { | |
666 | struct mb86a20s_state *state = fe->demodulator_priv; | |
667 | int rc; | |
668 | ||
669 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); | |
670 | ||
671 | if (layer >= 3) | |
672 | return -EINVAL; | |
673 | ||
674 | /* Check if the BER measures are already available */ | |
675 | rc = mb86a20s_readreg(state, 0x54); | |
676 | if (rc < 0) | |
677 | return rc; | |
678 | ||
679 | /* Check if data is available for that layer */ | |
680 | if (!(rc & (1 << layer))) { | |
681 | dev_dbg(&state->i2c->dev, | |
682 | "%s: BER for layer %c is not available yet.\n", | |
683 | __func__, 'A' + layer); | |
684 | return -EBUSY; | |
685 | } | |
686 | ||
687 | /* Read Bit Error Count */ | |
688 | rc = mb86a20s_readreg(state, 0x55 + layer * 3); | |
689 | if (rc < 0) | |
690 | return rc; | |
691 | *error = rc << 16; | |
692 | rc = mb86a20s_readreg(state, 0x56 + layer * 3); | |
693 | if (rc < 0) | |
694 | return rc; | |
695 | *error |= rc << 8; | |
696 | rc = mb86a20s_readreg(state, 0x57 + layer * 3); | |
697 | if (rc < 0) | |
698 | return rc; | |
699 | *error |= rc; | |
700 | ||
701 | dev_dbg(&state->i2c->dev, | |
702 | "%s: bit error before Viterbi for layer %c: %d.\n", | |
703 | __func__, 'A' + layer, *error); | |
704 | ||
705 | /* Read Bit Count */ | |
706 | rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); | |
707 | if (rc < 0) | |
708 | return rc; | |
709 | rc = mb86a20s_readreg(state, 0x51); | |
710 | if (rc < 0) | |
711 | return rc; | |
712 | *count = rc << 16; | |
713 | rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); | |
714 | if (rc < 0) | |
715 | return rc; | |
716 | rc = mb86a20s_readreg(state, 0x51); | |
717 | if (rc < 0) | |
718 | return rc; | |
719 | *count |= rc << 8; | |
720 | rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); | |
721 | if (rc < 0) | |
722 | return rc; | |
723 | rc = mb86a20s_readreg(state, 0x51); | |
724 | if (rc < 0) | |
725 | return rc; | |
726 | *count |= rc; | |
727 | ||
728 | dev_dbg(&state->i2c->dev, | |
729 | "%s: bit count before Viterbi for layer %c: %d.\n", | |
730 | __func__, 'A' + layer, *count); | |
731 | ||
732 | ||
733 | /* Reset counter to collect new data */ | |
734 | rc = mb86a20s_writereg(state, 0x53, 0x07 & ~(1 << layer)); | |
735 | if (rc < 0) | |
736 | return rc; | |
737 | rc = mb86a20s_writereg(state, 0x53, 0x07); | |
738 | ||
739 | return 0; | |
740 | } | |
741 | ||
09b6d21e MCC |
742 | static void mb86a20s_stats_not_ready(struct dvb_frontend *fe) |
743 | { | |
744 | struct mb86a20s_state *state = fe->demodulator_priv; | |
745 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
746 | int i; | |
747 | ||
748 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); | |
a77cfcac | 749 | |
09b6d21e MCC |
750 | /* Fill the length of each status counter */ |
751 | ||
752 | /* Only global stats */ | |
753 | c->strength.len = 1; | |
754 | ||
755 | /* Per-layer stats - 3 layers + global */ | |
756 | c->cnr.len = 4; | |
757 | c->pre_bit_error.len = 4; | |
758 | c->pre_bit_count.len = 4; | |
759 | c->block_error.len = 4; | |
760 | c->block_count.len = 4; | |
761 | ||
762 | /* Signal is always available */ | |
763 | c->strength.stat[0].scale = FE_SCALE_RELATIVE; | |
764 | c->strength.stat[0].uvalue = 0; | |
765 | ||
766 | /* Put all of them at FE_SCALE_NOT_AVAILABLE */ | |
767 | for (i = 0; i < 4; i++) { | |
768 | c->cnr.stat[i].scale = FE_SCALE_NOT_AVAILABLE; | |
769 | c->pre_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE; | |
770 | c->pre_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE; | |
771 | c->block_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE; | |
772 | c->block_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE; | |
773 | } | |
b9ede79a MCC |
774 | } |
775 | ||
149d518a MCC |
776 | static int mb86a20s_get_stats(struct dvb_frontend *fe) |
777 | { | |
778 | struct mb86a20s_state *state = fe->demodulator_priv; | |
779 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
780 | int rc = 0, i; | |
781 | u32 bit_error = 0, bit_count = 0; | |
782 | u32 t_pre_bit_error = 0, t_pre_bit_count = 0; | |
783 | int active_layers = 0, ber_layers = 0; | |
784 | ||
785 | /* Get per-layer stats */ | |
786 | for (i = 0; i < 3; i++) { | |
787 | if (c->isdbt_layer_enabled & (1 << i)) { | |
788 | /* Layer is active and has rc segments */ | |
789 | active_layers++; | |
790 | ||
791 | /* Read per-layer BER */ | |
792 | /* Handle BER before vterbi */ | |
793 | rc = mb86a20s_get_ber_before_vterbi(fe, i, | |
794 | &bit_error, | |
795 | &bit_count); | |
796 | if (rc >= 0) { | |
797 | c->pre_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER; | |
798 | c->pre_bit_error.stat[1 + i].uvalue += bit_error; | |
799 | c->pre_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER; | |
800 | c->pre_bit_count.stat[1 + i].uvalue += bit_count; | |
801 | } else if (rc != -EBUSY) { | |
802 | /* | |
803 | * If an I/O error happened, | |
804 | * measures are now unavailable | |
805 | */ | |
806 | c->pre_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; | |
807 | c->pre_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; | |
808 | dev_err(&state->i2c->dev, | |
809 | "%s: Can't get BER for layer %c (error %d).\n", | |
810 | __func__, 'A' + i, rc); | |
811 | } | |
812 | ||
813 | if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE) | |
814 | ber_layers++; | |
815 | ||
816 | /* Update total BER */ | |
817 | t_pre_bit_error += c->pre_bit_error.stat[1 + i].uvalue; | |
818 | t_pre_bit_count += c->pre_bit_count.stat[1 + i].uvalue; | |
819 | } | |
820 | } | |
821 | ||
822 | /* | |
823 | * Start showing global count if at least one error count is | |
824 | * available. | |
825 | */ | |
826 | if (ber_layers) { | |
827 | /* | |
828 | * At least one per-layer BER measure was read. We can now | |
829 | * calculate the total BER | |
830 | * | |
831 | * Total Bit Error/Count is calculated as the sum of the | |
832 | * bit errors on all active layers. | |
833 | */ | |
834 | c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; | |
835 | c->pre_bit_error.stat[0].uvalue = t_pre_bit_error; | |
836 | c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; | |
837 | c->pre_bit_count.stat[0].uvalue = t_pre_bit_count; | |
838 | } | |
839 | ||
840 | return rc; | |
841 | } | |
09b6d21e MCC |
842 | |
843 | /* | |
844 | * The functions below are called via DVB callbacks, so they need to | |
845 | * properly use the I2C gate control | |
846 | */ | |
847 | ||
dd4493ef MCC |
848 | static int mb86a20s_initfe(struct dvb_frontend *fe) |
849 | { | |
850 | struct mb86a20s_state *state = fe->demodulator_priv; | |
851 | int rc; | |
852 | u8 regD5 = 1; | |
853 | ||
f66d81b5 | 854 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
dd4493ef MCC |
855 | |
856 | if (fe->ops.i2c_gate_ctrl) | |
857 | fe->ops.i2c_gate_ctrl(fe, 0); | |
858 | ||
859 | /* Initialize the frontend */ | |
860 | rc = mb86a20s_writeregdata(state, mb86a20s_init); | |
861 | if (rc < 0) | |
862 | goto err; | |
863 | ||
864 | if (!state->config->is_serial) { | |
865 | regD5 &= ~1; | |
866 | ||
867 | rc = mb86a20s_writereg(state, 0x50, 0xd5); | |
868 | if (rc < 0) | |
869 | goto err; | |
870 | rc = mb86a20s_writereg(state, 0x51, regD5); | |
871 | if (rc < 0) | |
872 | goto err; | |
873 | } | |
874 | ||
875 | err: | |
876 | if (fe->ops.i2c_gate_ctrl) | |
877 | fe->ops.i2c_gate_ctrl(fe, 1); | |
878 | ||
879 | if (rc < 0) { | |
880 | state->need_init = true; | |
f66d81b5 MCC |
881 | dev_info(&state->i2c->dev, |
882 | "mb86a20s: Init failed. Will try again later\n"); | |
dd4493ef MCC |
883 | } else { |
884 | state->need_init = false; | |
f66d81b5 | 885 | dev_dbg(&state->i2c->dev, "Initialization succeeded.\n"); |
dd4493ef MCC |
886 | } |
887 | return rc; | |
888 | } | |
889 | ||
890 | static int mb86a20s_set_frontend(struct dvb_frontend *fe) | |
891 | { | |
892 | struct mb86a20s_state *state = fe->demodulator_priv; | |
893 | int rc; | |
894 | #if 0 | |
895 | /* | |
896 | * FIXME: Properly implement the set frontend properties | |
897 | */ | |
898 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
899 | #endif | |
f66d81b5 | 900 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
dd4493ef MCC |
901 | |
902 | /* | |
903 | * Gate should already be opened, but it doesn't hurt to | |
904 | * double-check | |
905 | */ | |
906 | if (fe->ops.i2c_gate_ctrl) | |
907 | fe->ops.i2c_gate_ctrl(fe, 1); | |
dd4493ef MCC |
908 | fe->ops.tuner_ops.set_params(fe); |
909 | ||
910 | /* | |
911 | * Make it more reliable: if, for some reason, the initial | |
912 | * device initialization doesn't happen, initialize it when | |
913 | * a SBTVD parameters are adjusted. | |
914 | * | |
915 | * Unfortunately, due to a hard to track bug at tda829x/tda18271, | |
916 | * the agc callback logic is not called during DVB attach time, | |
917 | * causing mb86a20s to not be initialized with Kworld SBTVD. | |
918 | * So, this hack is needed, in order to make Kworld SBTVD to work. | |
919 | */ | |
920 | if (state->need_init) | |
921 | mb86a20s_initfe(fe); | |
922 | ||
923 | if (fe->ops.i2c_gate_ctrl) | |
924 | fe->ops.i2c_gate_ctrl(fe, 0); | |
925 | rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception); | |
09b6d21e | 926 | mb86a20s_reset_counters(fe); |
dd4493ef MCC |
927 | if (fe->ops.i2c_gate_ctrl) |
928 | fe->ops.i2c_gate_ctrl(fe, 1); | |
929 | ||
930 | return rc; | |
931 | } | |
932 | ||
09b6d21e MCC |
933 | static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe, |
934 | fe_status_t *status) | |
d36e418a | 935 | { |
09b6d21e MCC |
936 | struct mb86a20s_state *state = fe->demodulator_priv; |
937 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
938 | int rc; | |
d36e418a | 939 | |
09b6d21e | 940 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
d36e418a MCC |
941 | |
942 | if (fe->ops.i2c_gate_ctrl) | |
943 | fe->ops.i2c_gate_ctrl(fe, 0); | |
944 | ||
09b6d21e MCC |
945 | /* Get lock */ |
946 | rc = mb86a20s_read_status(fe, status); | |
947 | if (!(*status & FE_HAS_LOCK)) { | |
948 | mb86a20s_stats_not_ready(fe); | |
949 | mb86a20s_reset_frontend_cache(fe); | |
950 | } | |
149d518a MCC |
951 | if (rc < 0) { |
952 | dev_err(&state->i2c->dev, | |
953 | "%s: Can't read frontend lock status\n", __func__); | |
09b6d21e | 954 | goto error; |
149d518a | 955 | } |
09b6d21e MCC |
956 | |
957 | /* Get signal strength */ | |
958 | rc = mb86a20s_read_signal_strength(fe); | |
959 | if (rc < 0) { | |
149d518a MCC |
960 | dev_err(&state->i2c->dev, |
961 | "%s: Can't reset VBER registers.\n", __func__); | |
09b6d21e MCC |
962 | mb86a20s_stats_not_ready(fe); |
963 | mb86a20s_reset_frontend_cache(fe); | |
149d518a MCC |
964 | |
965 | rc = 0; /* Status is OK */ | |
09b6d21e MCC |
966 | goto error; |
967 | } | |
968 | /* Fill signal strength */ | |
969 | c->strength.stat[0].uvalue = rc; | |
970 | ||
971 | if (*status & FE_HAS_LOCK) { | |
972 | /* Get TMCC info*/ | |
973 | rc = mb86a20s_get_frontend(fe); | |
149d518a MCC |
974 | if (rc < 0) { |
975 | dev_err(&state->i2c->dev, | |
976 | "%s: Can't get FE TMCC data.\n", __func__); | |
977 | rc = 0; /* Status is OK */ | |
978 | goto error; | |
979 | } | |
980 | ||
981 | /* Get statistics */ | |
982 | rc = mb86a20s_get_stats(fe); | |
983 | if (rc < 0 && rc != -EBUSY) { | |
984 | dev_err(&state->i2c->dev, | |
985 | "%s: Can't get FE statistics.\n", __func__); | |
986 | rc = 0; | |
09b6d21e | 987 | goto error; |
149d518a MCC |
988 | } |
989 | rc = 0; /* Don't return EBUSY to userspace */ | |
09b6d21e | 990 | } |
149d518a | 991 | goto ok; |
09b6d21e | 992 | |
149d518a | 993 | error: |
09b6d21e | 994 | mb86a20s_stats_not_ready(fe); |
d36e418a | 995 | |
149d518a | 996 | ok: |
d36e418a MCC |
997 | if (fe->ops.i2c_gate_ctrl) |
998 | fe->ops.i2c_gate_ctrl(fe, 1); | |
149d518a | 999 | |
09b6d21e MCC |
1000 | return rc; |
1001 | } | |
1002 | ||
1003 | static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe, | |
1004 | u16 *strength) | |
1005 | { | |
1006 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
1007 | ||
1008 | ||
1009 | *strength = c->strength.stat[0].uvalue; | |
d36e418a | 1010 | |
09b6d21e | 1011 | return 0; |
d36e418a MCC |
1012 | } |
1013 | ||
09b6d21e MCC |
1014 | static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe) |
1015 | { | |
1016 | /* | |
1017 | * get_frontend is now handled together with other stats | |
1018 | * retrival, when read_status() is called, as some statistics | |
1019 | * will depend on the layers detection. | |
1020 | */ | |
1021 | return 0; | |
1022 | }; | |
1023 | ||
b9ede79a | 1024 | static int mb86a20s_tune(struct dvb_frontend *fe, |
7e072221 | 1025 | bool re_tune, |
b9ede79a MCC |
1026 | unsigned int mode_flags, |
1027 | unsigned int *delay, | |
1028 | fe_status_t *status) | |
1029 | { | |
f66d81b5 | 1030 | struct mb86a20s_state *state = fe->demodulator_priv; |
b9ede79a MCC |
1031 | int rc = 0; |
1032 | ||
f66d81b5 | 1033 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
b9ede79a | 1034 | |
7e072221 | 1035 | if (re_tune) |
2d76e22b | 1036 | rc = mb86a20s_set_frontend(fe); |
b9ede79a MCC |
1037 | |
1038 | if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) | |
09b6d21e | 1039 | mb86a20s_read_status_and_stats(fe, status); |
b9ede79a MCC |
1040 | |
1041 | return rc; | |
1042 | } | |
1043 | ||
1044 | static void mb86a20s_release(struct dvb_frontend *fe) | |
1045 | { | |
1046 | struct mb86a20s_state *state = fe->demodulator_priv; | |
1047 | ||
f66d81b5 | 1048 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
b9ede79a MCC |
1049 | |
1050 | kfree(state); | |
1051 | } | |
1052 | ||
1053 | static struct dvb_frontend_ops mb86a20s_ops; | |
1054 | ||
1055 | struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config, | |
1056 | struct i2c_adapter *i2c) | |
1057 | { | |
f66d81b5 | 1058 | struct mb86a20s_state *state; |
b9ede79a MCC |
1059 | u8 rev; |
1060 | ||
f167e302 MCC |
1061 | dev_dbg(&i2c->dev, "%s called.\n", __func__); |
1062 | ||
b9ede79a | 1063 | /* allocate memory for the internal state */ |
f66d81b5 | 1064 | state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL); |
b9ede79a | 1065 | if (state == NULL) { |
f167e302 | 1066 | dev_err(&i2c->dev, |
f66d81b5 | 1067 | "%s: unable to allocate memory for state\n", __func__); |
b9ede79a MCC |
1068 | goto error; |
1069 | } | |
1070 | ||
1071 | /* setup the state */ | |
1072 | state->config = config; | |
1073 | state->i2c = i2c; | |
1074 | ||
1075 | /* create dvb_frontend */ | |
1076 | memcpy(&state->frontend.ops, &mb86a20s_ops, | |
1077 | sizeof(struct dvb_frontend_ops)); | |
1078 | state->frontend.demodulator_priv = state; | |
1079 | ||
1080 | /* Check if it is a mb86a20s frontend */ | |
1081 | rev = mb86a20s_readreg(state, 0); | |
1082 | ||
1083 | if (rev == 0x13) { | |
f167e302 | 1084 | dev_info(&i2c->dev, |
f66d81b5 | 1085 | "Detected a Fujitsu mb86a20s frontend\n"); |
b9ede79a | 1086 | } else { |
f167e302 | 1087 | dev_dbg(&i2c->dev, |
f66d81b5 | 1088 | "Frontend revision %d is unknown - aborting.\n", |
b9ede79a MCC |
1089 | rev); |
1090 | goto error; | |
1091 | } | |
1092 | ||
1093 | return &state->frontend; | |
1094 | ||
1095 | error: | |
1096 | kfree(state); | |
1097 | return NULL; | |
1098 | } | |
1099 | EXPORT_SYMBOL(mb86a20s_attach); | |
1100 | ||
1101 | static struct dvb_frontend_ops mb86a20s_ops = { | |
2d76e22b | 1102 | .delsys = { SYS_ISDBT }, |
b9ede79a MCC |
1103 | /* Use dib8000 values per default */ |
1104 | .info = { | |
1105 | .name = "Fujitsu mb86A20s", | |
b9ede79a MCC |
1106 | .caps = FE_CAN_INVERSION_AUTO | FE_CAN_RECOVER | |
1107 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
1108 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
1109 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | | |
1110 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO | | |
1111 | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, | |
1112 | /* Actually, those values depend on the used tuner */ | |
1113 | .frequency_min = 45000000, | |
1114 | .frequency_max = 864000000, | |
1115 | .frequency_stepsize = 62500, | |
1116 | }, | |
1117 | ||
1118 | .release = mb86a20s_release, | |
1119 | ||
1120 | .init = mb86a20s_initfe, | |
2d76e22b | 1121 | .set_frontend = mb86a20s_set_frontend, |
09b6d21e MCC |
1122 | .get_frontend = mb86a20s_get_frontend_dummy, |
1123 | .read_status = mb86a20s_read_status_and_stats, | |
1124 | .read_signal_strength = mb86a20s_read_signal_strength_from_cache, | |
b9ede79a MCC |
1125 | .tune = mb86a20s_tune, |
1126 | }; | |
1127 | ||
1128 | MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware"); | |
1129 | MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); | |
1130 | MODULE_LICENSE("GPL"); |