Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
6a5cbd59 | 2 | Driver for Zarlink VP310/MT312/ZL10313 Satellite Channel Decoder |
1da177e4 LT |
3 | |
4 | Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org> | |
6a5cbd59 | 5 | Copyright (C) 2008 Matthias Schwarzott <zzam@gentoo.org> |
1da177e4 LT |
6 | |
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ||
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | ||
22 | References: | |
23 | http://products.zarlink.com/product_profiles/MT312.htm | |
24 | http://products.zarlink.com/product_profiles/SL1935.htm | |
25 | */ | |
26 | ||
27 | #include <linux/delay.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
4e57b681 TS |
32 | #include <linux/string.h> |
33 | #include <linux/slab.h> | |
1da177e4 LT |
34 | |
35 | #include "dvb_frontend.h" | |
36 | #include "mt312_priv.h" | |
37 | #include "mt312.h" | |
38 | ||
8393796d MCC |
39 | /* Max transfer size done by I2C transfer functions */ |
40 | #define MAX_XFER_SIZE 64 | |
1da177e4 LT |
41 | |
42 | struct mt312_state { | |
89f64758 | 43 | struct i2c_adapter *i2c; |
1da177e4 | 44 | /* configuration settings */ |
89f64758 | 45 | const struct mt312_config *config; |
1da177e4 LT |
46 | struct dvb_frontend frontend; |
47 | ||
48 | u8 id; | |
111221fb MS |
49 | unsigned long xtal; |
50 | u8 freq_mult; | |
1da177e4 LT |
51 | }; |
52 | ||
53 | static int debug; | |
54 | #define dprintk(args...) \ | |
55 | do { \ | |
89f64758 MS |
56 | if (debug) \ |
57 | printk(KERN_DEBUG "mt312: " args); \ | |
1da177e4 LT |
58 | } while (0) |
59 | ||
1da177e4 | 60 | #define MT312_PLL_CLK 10000000UL /* 10 MHz */ |
6a5cbd59 | 61 | #define MT312_PLL_CLK_10_111 10111000UL /* 10.111 MHz */ |
1da177e4 | 62 | |
89f64758 | 63 | static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg, |
1881ee89 | 64 | u8 *buf, const size_t count) |
1da177e4 LT |
65 | { |
66 | int ret; | |
67 | struct i2c_msg msg[2]; | |
68 | u8 regbuf[1] = { reg }; | |
69 | ||
70 | msg[0].addr = state->config->demod_address; | |
71 | msg[0].flags = 0; | |
72 | msg[0].buf = regbuf; | |
73 | msg[0].len = 1; | |
74 | msg[1].addr = state->config->demod_address; | |
75 | msg[1].flags = I2C_M_RD; | |
76 | msg[1].buf = buf; | |
77 | msg[1].len = count; | |
78 | ||
79 | ret = i2c_transfer(state->i2c, msg, 2); | |
80 | ||
81 | if (ret != 2) { | |
302e8acc | 82 | printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret); |
1da177e4 LT |
83 | return -EREMOTEIO; |
84 | } | |
85 | ||
89f64758 | 86 | if (debug) { |
1da177e4 LT |
87 | int i; |
88 | dprintk("R(%d):", reg & 0x7f); | |
89 | for (i = 0; i < count; i++) | |
0389b34e | 90 | printk(KERN_CONT " %02x", buf[i]); |
1da177e4 LT |
91 | printk("\n"); |
92 | } | |
93 | ||
94 | return 0; | |
95 | } | |
96 | ||
89f64758 | 97 | static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg, |
1881ee89 | 98 | const u8 *src, const size_t count) |
1da177e4 LT |
99 | { |
100 | int ret; | |
8393796d | 101 | u8 buf[MAX_XFER_SIZE]; |
1da177e4 LT |
102 | struct i2c_msg msg; |
103 | ||
8393796d MCC |
104 | if (1 + count > sizeof(buf)) { |
105 | printk(KERN_WARNING | |
35f30f36 | 106 | "mt312: write: len=%zu is too big!\n", count); |
8393796d MCC |
107 | return -EINVAL; |
108 | } | |
109 | ||
89f64758 | 110 | if (debug) { |
1da177e4 LT |
111 | int i; |
112 | dprintk("W(%d):", reg & 0x7f); | |
113 | for (i = 0; i < count; i++) | |
0389b34e | 114 | printk(KERN_CONT " %02x", src[i]); |
1da177e4 LT |
115 | printk("\n"); |
116 | } | |
117 | ||
118 | buf[0] = reg; | |
119 | memcpy(&buf[1], src, count); | |
120 | ||
121 | msg.addr = state->config->demod_address; | |
122 | msg.flags = 0; | |
123 | msg.buf = buf; | |
124 | msg.len = count + 1; | |
125 | ||
126 | ret = i2c_transfer(state->i2c, &msg, 1); | |
127 | ||
128 | if (ret != 1) { | |
271ddbf7 | 129 | dprintk("%s: ret == %d\n", __func__, ret); |
1da177e4 LT |
130 | return -EREMOTEIO; |
131 | } | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
89f64758 | 136 | static inline int mt312_readreg(struct mt312_state *state, |
1da177e4 LT |
137 | const enum mt312_reg_addr reg, u8 *val) |
138 | { | |
139 | return mt312_read(state, reg, val, 1); | |
140 | } | |
141 | ||
89f64758 | 142 | static inline int mt312_writereg(struct mt312_state *state, |
1da177e4 LT |
143 | const enum mt312_reg_addr reg, const u8 val) |
144 | { | |
145 | return mt312_write(state, reg, &val, 1); | |
146 | } | |
147 | ||
148 | static inline u32 mt312_div(u32 a, u32 b) | |
149 | { | |
150 | return (a + (b / 2)) / b; | |
151 | } | |
152 | ||
89f64758 | 153 | static int mt312_reset(struct mt312_state *state, const u8 full) |
1da177e4 LT |
154 | { |
155 | return mt312_writereg(state, RESET, full ? 0x80 : 0x40); | |
156 | } | |
157 | ||
89f64758 | 158 | static int mt312_get_inversion(struct mt312_state *state, |
0df289a2 | 159 | enum fe_spectral_inversion *i) |
1da177e4 LT |
160 | { |
161 | int ret; | |
162 | u8 vit_mode; | |
163 | ||
994fc28b MS |
164 | ret = mt312_readreg(state, VIT_MODE, &vit_mode); |
165 | if (ret < 0) | |
1da177e4 LT |
166 | return ret; |
167 | ||
168 | if (vit_mode & 0x80) /* auto inversion was used */ | |
169 | *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF; | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
89f64758 | 174 | static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr) |
1da177e4 LT |
175 | { |
176 | int ret; | |
177 | u8 sym_rate_h; | |
178 | u8 dec_ratio; | |
179 | u16 sym_rat_op; | |
180 | u16 monitor; | |
181 | u8 buf[2]; | |
182 | ||
994fc28b MS |
183 | ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h); |
184 | if (ret < 0) | |
1da177e4 LT |
185 | return ret; |
186 | ||
89f64758 MS |
187 | if (sym_rate_h & 0x80) { |
188 | /* symbol rate search was used */ | |
994fc28b MS |
189 | ret = mt312_writereg(state, MON_CTRL, 0x03); |
190 | if (ret < 0) | |
1da177e4 LT |
191 | return ret; |
192 | ||
994fc28b MS |
193 | ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); |
194 | if (ret < 0) | |
1da177e4 LT |
195 | return ret; |
196 | ||
197 | monitor = (buf[0] << 8) | buf[1]; | |
198 | ||
0b6a3342 | 199 | dprintk("sr(auto) = %u\n", |
1da177e4 LT |
200 | mt312_div(monitor * 15625, 4)); |
201 | } else { | |
994fc28b MS |
202 | ret = mt312_writereg(state, MON_CTRL, 0x05); |
203 | if (ret < 0) | |
1da177e4 LT |
204 | return ret; |
205 | ||
994fc28b MS |
206 | ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); |
207 | if (ret < 0) | |
1da177e4 LT |
208 | return ret; |
209 | ||
210 | dec_ratio = ((buf[0] >> 5) & 0x07) * 32; | |
211 | ||
994fc28b MS |
212 | ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf)); |
213 | if (ret < 0) | |
1da177e4 LT |
214 | return ret; |
215 | ||
216 | sym_rat_op = (buf[0] << 8) | buf[1]; | |
217 | ||
0b6a3342 | 218 | dprintk("sym_rat_op=%d dec_ratio=%d\n", |
1da177e4 | 219 | sym_rat_op, dec_ratio); |
0b6a3342 | 220 | dprintk("*sr(manual) = %lu\n", |
111221fb | 221 | (((state->xtal * 8192) / (sym_rat_op + 8192)) * |
1da177e4 LT |
222 | 2) - dec_ratio); |
223 | } | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
0df289a2 | 228 | static int mt312_get_code_rate(struct mt312_state *state, enum fe_code_rate *cr) |
1da177e4 | 229 | { |
0df289a2 | 230 | const enum fe_code_rate fec_tab[8] = |
1da177e4 LT |
231 | { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8, |
232 | FEC_AUTO, FEC_AUTO }; | |
233 | ||
234 | int ret; | |
235 | u8 fec_status; | |
236 | ||
994fc28b MS |
237 | ret = mt312_readreg(state, FEC_STATUS, &fec_status); |
238 | if (ret < 0) | |
1da177e4 LT |
239 | return ret; |
240 | ||
241 | *cr = fec_tab[(fec_status >> 4) & 0x07]; | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
89f64758 | 246 | static int mt312_initfe(struct dvb_frontend *fe) |
1da177e4 | 247 | { |
b8742700 | 248 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
249 | int ret; |
250 | u8 buf[2]; | |
251 | ||
252 | /* wake up */ | |
994fc28b | 253 | ret = mt312_writereg(state, CONFIG, |
111221fb | 254 | (state->freq_mult == 6 ? 0x88 : 0x8c)); |
994fc28b | 255 | if (ret < 0) |
1da177e4 LT |
256 | return ret; |
257 | ||
258 | /* wait at least 150 usec */ | |
259 | udelay(150); | |
260 | ||
261 | /* full reset */ | |
994fc28b MS |
262 | ret = mt312_reset(state, 1); |
263 | if (ret < 0) | |
1da177e4 LT |
264 | return ret; |
265 | ||
89f64758 MS |
266 | /* Per datasheet, write correct values. 09/28/03 ACCJr. |
267 | * If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */ | |
1da177e4 | 268 | { |
89f64758 MS |
269 | u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02, |
270 | 0x01, 0x00, 0x00, 0x00 }; | |
1da177e4 | 271 | |
994fc28b MS |
272 | ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def)); |
273 | if (ret < 0) | |
1da177e4 LT |
274 | return ret; |
275 | } | |
276 | ||
6a5cbd59 MS |
277 | switch (state->id) { |
278 | case ID_ZL10313: | |
279 | /* enable ADC */ | |
280 | ret = mt312_writereg(state, GPP_CTRL, 0x80); | |
281 | if (ret < 0) | |
282 | return ret; | |
283 | ||
284 | /* configure ZL10313 for optimal ADC performance */ | |
285 | buf[0] = 0x80; | |
286 | buf[1] = 0xB0; | |
287 | ret = mt312_write(state, HW_CTRL, buf, 2); | |
288 | if (ret < 0) | |
289 | return ret; | |
290 | ||
291 | /* enable MPEG output and ADCs */ | |
292 | ret = mt312_writereg(state, HW_CTRL, 0x00); | |
293 | if (ret < 0) | |
294 | return ret; | |
295 | ||
296 | ret = mt312_writereg(state, MPEG_CTRL, 0x00); | |
297 | if (ret < 0) | |
298 | return ret; | |
299 | ||
300 | break; | |
301 | } | |
302 | ||
1da177e4 | 303 | /* SYS_CLK */ |
111221fb | 304 | buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000); |
1da177e4 LT |
305 | |
306 | /* DISEQC_RATIO */ | |
111221fb | 307 | buf[1] = mt312_div(state->xtal, 22000 * 4); |
1da177e4 | 308 | |
994fc28b MS |
309 | ret = mt312_write(state, SYS_CLK, buf, sizeof(buf)); |
310 | if (ret < 0) | |
1da177e4 LT |
311 | return ret; |
312 | ||
994fc28b MS |
313 | ret = mt312_writereg(state, SNR_THS_HIGH, 0x32); |
314 | if (ret < 0) | |
1da177e4 LT |
315 | return ret; |
316 | ||
6a5cbd59 MS |
317 | /* different MOCLK polarity */ |
318 | switch (state->id) { | |
319 | case ID_ZL10313: | |
320 | buf[0] = 0x33; | |
321 | break; | |
322 | default: | |
323 | buf[0] = 0x53; | |
324 | break; | |
325 | } | |
326 | ||
327 | ret = mt312_writereg(state, OP_CTRL, buf[0]); | |
994fc28b | 328 | if (ret < 0) |
1da177e4 LT |
329 | return ret; |
330 | ||
331 | /* TS_SW_LIM */ | |
332 | buf[0] = 0x8c; | |
333 | buf[1] = 0x98; | |
334 | ||
994fc28b MS |
335 | ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf)); |
336 | if (ret < 0) | |
1da177e4 LT |
337 | return ret; |
338 | ||
994fc28b MS |
339 | ret = mt312_writereg(state, CS_SW_LIM, 0x69); |
340 | if (ret < 0) | |
1da177e4 LT |
341 | return ret; |
342 | ||
1da177e4 LT |
343 | return 0; |
344 | } | |
345 | ||
89f64758 | 346 | static int mt312_send_master_cmd(struct dvb_frontend *fe, |
1da177e4 LT |
347 | struct dvb_diseqc_master_cmd *c) |
348 | { | |
b8742700 | 349 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
350 | int ret; |
351 | u8 diseqc_mode; | |
352 | ||
353 | if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg))) | |
354 | return -EINVAL; | |
355 | ||
994fc28b MS |
356 | ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); |
357 | if (ret < 0) | |
1da177e4 LT |
358 | return ret; |
359 | ||
994fc28b MS |
360 | ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len); |
361 | if (ret < 0) | |
1da177e4 LT |
362 | return ret; |
363 | ||
994fc28b MS |
364 | ret = mt312_writereg(state, DISEQC_MODE, |
365 | (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3) | |
366 | | 0x04); | |
367 | if (ret < 0) | |
1da177e4 LT |
368 | return ret; |
369 | ||
82cd2dff MS |
370 | /* is there a better way to wait for message to be transmitted */ |
371 | msleep(100); | |
372 | ||
1da177e4 | 373 | /* set DISEQC_MODE[2:0] to zero if a return message is expected */ |
994fc28b MS |
374 | if (c->msg[0] & 0x02) { |
375 | ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40)); | |
376 | if (ret < 0) | |
1da177e4 | 377 | return ret; |
994fc28b | 378 | } |
1da177e4 LT |
379 | |
380 | return 0; | |
381 | } | |
382 | ||
0df289a2 MCC |
383 | static int mt312_send_burst(struct dvb_frontend *fe, |
384 | const enum fe_sec_mini_cmd c) | |
1da177e4 | 385 | { |
b8742700 | 386 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
387 | const u8 mini_tab[2] = { 0x02, 0x03 }; |
388 | ||
389 | int ret; | |
390 | u8 diseqc_mode; | |
391 | ||
392 | if (c > SEC_MINI_B) | |
393 | return -EINVAL; | |
394 | ||
994fc28b MS |
395 | ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); |
396 | if (ret < 0) | |
1da177e4 LT |
397 | return ret; |
398 | ||
994fc28b MS |
399 | ret = mt312_writereg(state, DISEQC_MODE, |
400 | (diseqc_mode & 0x40) | mini_tab[c]); | |
401 | if (ret < 0) | |
1da177e4 LT |
402 | return ret; |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
0df289a2 MCC |
407 | static int mt312_set_tone(struct dvb_frontend *fe, |
408 | const enum fe_sec_tone_mode t) | |
1da177e4 | 409 | { |
b8742700 | 410 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
411 | const u8 tone_tab[2] = { 0x01, 0x00 }; |
412 | ||
413 | int ret; | |
414 | u8 diseqc_mode; | |
415 | ||
416 | if (t > SEC_TONE_OFF) | |
417 | return -EINVAL; | |
418 | ||
994fc28b MS |
419 | ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); |
420 | if (ret < 0) | |
1da177e4 LT |
421 | return ret; |
422 | ||
994fc28b MS |
423 | ret = mt312_writereg(state, DISEQC_MODE, |
424 | (diseqc_mode & 0x40) | tone_tab[t]); | |
425 | if (ret < 0) | |
1da177e4 LT |
426 | return ret; |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
0df289a2 MCC |
431 | static int mt312_set_voltage(struct dvb_frontend *fe, |
432 | const enum fe_sec_voltage v) | |
1da177e4 | 433 | { |
b8742700 | 434 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 | 435 | const u8 volt_tab[3] = { 0x00, 0x40, 0x00 }; |
11d3f323 | 436 | u8 val; |
1da177e4 LT |
437 | |
438 | if (v > SEC_VOLTAGE_OFF) | |
439 | return -EINVAL; | |
440 | ||
11d3f323 MS |
441 | val = volt_tab[v]; |
442 | if (state->config->voltage_inverted) | |
443 | val ^= 0x40; | |
444 | ||
445 | return mt312_writereg(state, DISEQC_MODE, val); | |
1da177e4 LT |
446 | } |
447 | ||
0df289a2 | 448 | static int mt312_read_status(struct dvb_frontend *fe, enum fe_status *s) |
1da177e4 | 449 | { |
b8742700 | 450 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
451 | int ret; |
452 | u8 status[3]; | |
453 | ||
454 | *s = 0; | |
455 | ||
994fc28b MS |
456 | ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status)); |
457 | if (ret < 0) | |
1da177e4 LT |
458 | return ret; |
459 | ||
0b6a3342 | 460 | dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x," |
89f64758 | 461 | " FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]); |
1da177e4 LT |
462 | |
463 | if (status[0] & 0xc0) | |
464 | *s |= FE_HAS_SIGNAL; /* signal noise ratio */ | |
465 | if (status[0] & 0x04) | |
466 | *s |= FE_HAS_CARRIER; /* qpsk carrier lock */ | |
467 | if (status[2] & 0x02) | |
468 | *s |= FE_HAS_VITERBI; /* viterbi lock */ | |
469 | if (status[2] & 0x04) | |
470 | *s |= FE_HAS_SYNC; /* byte align lock */ | |
471 | if (status[0] & 0x01) | |
472 | *s |= FE_HAS_LOCK; /* qpsk lock */ | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
89f64758 | 477 | static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber) |
1da177e4 | 478 | { |
b8742700 | 479 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
480 | int ret; |
481 | u8 buf[3]; | |
482 | ||
994fc28b MS |
483 | ret = mt312_read(state, RS_BERCNT_H, buf, 3); |
484 | if (ret < 0) | |
1da177e4 LT |
485 | return ret; |
486 | ||
487 | *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64; | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
89f64758 MS |
492 | static int mt312_read_signal_strength(struct dvb_frontend *fe, |
493 | u16 *signal_strength) | |
1da177e4 | 494 | { |
b8742700 | 495 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
496 | int ret; |
497 | u8 buf[3]; | |
498 | u16 agc; | |
499 | s16 err_db; | |
500 | ||
994fc28b MS |
501 | ret = mt312_read(state, AGC_H, buf, sizeof(buf)); |
502 | if (ret < 0) | |
1da177e4 LT |
503 | return ret; |
504 | ||
505 | agc = (buf[0] << 6) | (buf[1] >> 2); | |
506 | err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6; | |
507 | ||
508 | *signal_strength = agc; | |
509 | ||
0b6a3342 | 510 | dprintk("agc=%08x err_db=%hd\n", agc, err_db); |
1da177e4 LT |
511 | |
512 | return 0; | |
513 | } | |
514 | ||
89f64758 | 515 | static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr) |
1da177e4 | 516 | { |
b8742700 | 517 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
518 | int ret; |
519 | u8 buf[2]; | |
520 | ||
1881ee89 | 521 | ret = mt312_read(state, M_SNR_H, buf, sizeof(buf)); |
994fc28b | 522 | if (ret < 0) |
1da177e4 LT |
523 | return ret; |
524 | ||
525 | *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1); | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
89f64758 | 530 | static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc) |
1da177e4 | 531 | { |
b8742700 | 532 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
533 | int ret; |
534 | u8 buf[2]; | |
535 | ||
1881ee89 | 536 | ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf)); |
994fc28b | 537 | if (ret < 0) |
1da177e4 LT |
538 | return ret; |
539 | ||
540 | *ubc = (buf[0] << 8) | buf[1]; | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
827b5f3e | 545 | static int mt312_set_frontend(struct dvb_frontend *fe) |
1da177e4 | 546 | { |
827b5f3e | 547 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
b8742700 | 548 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
549 | int ret; |
550 | u8 buf[5], config_val; | |
551 | u16 sr; | |
552 | ||
553 | const u8 fec_tab[10] = | |
554 | { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f }; | |
555 | const u8 inv_tab[3] = { 0x00, 0x40, 0x80 }; | |
556 | ||
271ddbf7 | 557 | dprintk("%s: Freq %d\n", __func__, p->frequency); |
1da177e4 | 558 | |
dea74869 PB |
559 | if ((p->frequency < fe->ops.info.frequency_min) |
560 | || (p->frequency > fe->ops.info.frequency_max)) | |
1da177e4 LT |
561 | return -EINVAL; |
562 | ||
830e4b55 | 563 | if (((int)p->inversion < INVERSION_OFF) |
1da177e4 LT |
564 | || (p->inversion > INVERSION_ON)) |
565 | return -EINVAL; | |
566 | ||
827b5f3e MCC |
567 | if ((p->symbol_rate < fe->ops.info.symbol_rate_min) |
568 | || (p->symbol_rate > fe->ops.info.symbol_rate_max)) | |
1da177e4 LT |
569 | return -EINVAL; |
570 | ||
830e4b55 | 571 | if (((int)p->fec_inner < FEC_NONE) |
827b5f3e | 572 | || (p->fec_inner > FEC_AUTO)) |
1da177e4 LT |
573 | return -EINVAL; |
574 | ||
827b5f3e MCC |
575 | if ((p->fec_inner == FEC_4_5) |
576 | || (p->fec_inner == FEC_8_9)) | |
1da177e4 LT |
577 | return -EINVAL; |
578 | ||
579 | switch (state->id) { | |
580 | case ID_VP310: | |
89f64758 MS |
581 | /* For now we will do this only for the VP310. |
582 | * It should be better for the mt312 as well, | |
583 | * but tuning will be slower. ACCJr 09/29/03 | |
584 | */ | |
682e852e AD |
585 | ret = mt312_readreg(state, CONFIG, &config_val); |
586 | if (ret < 0) | |
1da177e4 | 587 | return ret; |
827b5f3e | 588 | if (p->symbol_rate >= 30000000) { |
89f64758 | 589 | /* Note that 30MS/s should use 90MHz */ |
111221fb | 590 | if (state->freq_mult == 6) { |
89f64758 | 591 | /* We are running 60MHz */ |
111221fb | 592 | state->freq_mult = 9; |
994fc28b MS |
593 | ret = mt312_initfe(fe); |
594 | if (ret < 0) | |
1da177e4 LT |
595 | return ret; |
596 | } | |
89f64758 | 597 | } else { |
111221fb | 598 | if (state->freq_mult == 9) { |
89f64758 | 599 | /* We are running 90MHz */ |
111221fb | 600 | state->freq_mult = 6; |
994fc28b MS |
601 | ret = mt312_initfe(fe); |
602 | if (ret < 0) | |
1da177e4 LT |
603 | return ret; |
604 | } | |
605 | } | |
606 | break; | |
607 | ||
608 | case ID_MT312: | |
6a5cbd59 | 609 | case ID_ZL10313: |
1da177e4 LT |
610 | break; |
611 | ||
612 | default: | |
613 | return -EINVAL; | |
614 | } | |
615 | ||
dea74869 | 616 | if (fe->ops.tuner_ops.set_params) { |
14d24d14 | 617 | fe->ops.tuner_ops.set_params(fe); |
89f64758 MS |
618 | if (fe->ops.i2c_gate_ctrl) |
619 | fe->ops.i2c_gate_ctrl(fe, 0); | |
a81870e0 | 620 | } |
1da177e4 LT |
621 | |
622 | /* sr = (u16)(sr * 256.0 / 1000000.0) */ | |
827b5f3e | 623 | sr = mt312_div(p->symbol_rate * 4, 15625); |
1da177e4 LT |
624 | |
625 | /* SYM_RATE */ | |
626 | buf[0] = (sr >> 8) & 0x3f; | |
627 | buf[1] = (sr >> 0) & 0xff; | |
628 | ||
629 | /* VIT_MODE */ | |
827b5f3e | 630 | buf[2] = inv_tab[p->inversion] | fec_tab[p->fec_inner]; |
1da177e4 LT |
631 | |
632 | /* QPSK_CTRL */ | |
633 | buf[3] = 0x40; /* swap I and Q before QPSK demodulation */ | |
634 | ||
827b5f3e | 635 | if (p->symbol_rate < 10000000) |
1da177e4 LT |
636 | buf[3] |= 0x04; /* use afc mode */ |
637 | ||
638 | /* GO */ | |
639 | buf[4] = 0x01; | |
640 | ||
994fc28b MS |
641 | ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf)); |
642 | if (ret < 0) | |
1da177e4 LT |
643 | return ret; |
644 | ||
9101e622 | 645 | mt312_reset(state, 0); |
1da177e4 LT |
646 | |
647 | return 0; | |
648 | } | |
649 | ||
7c61d80a | 650 | static int mt312_get_frontend(struct dvb_frontend *fe) |
1da177e4 | 651 | { |
7c61d80a | 652 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
b8742700 | 653 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
654 | int ret; |
655 | ||
994fc28b MS |
656 | ret = mt312_get_inversion(state, &p->inversion); |
657 | if (ret < 0) | |
1da177e4 LT |
658 | return ret; |
659 | ||
827b5f3e | 660 | ret = mt312_get_symbol_rate(state, &p->symbol_rate); |
994fc28b | 661 | if (ret < 0) |
1da177e4 LT |
662 | return ret; |
663 | ||
827b5f3e | 664 | ret = mt312_get_code_rate(state, &p->fec_inner); |
994fc28b | 665 | if (ret < 0) |
1da177e4 LT |
666 | return ret; |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
89f64758 | 671 | static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) |
a81870e0 | 672 | { |
89f64758 | 673 | struct mt312_state *state = fe->demodulator_priv; |
a81870e0 | 674 | |
6a5cbd59 MS |
675 | u8 val = 0x00; |
676 | int ret; | |
677 | ||
678 | switch (state->id) { | |
679 | case ID_ZL10313: | |
680 | ret = mt312_readreg(state, GPP_CTRL, &val); | |
681 | if (ret < 0) | |
682 | goto error; | |
683 | ||
25985edc | 684 | /* preserve this bit to not accidentally shutdown ADC */ |
6a5cbd59 MS |
685 | val &= 0x80; |
686 | break; | |
a81870e0 | 687 | } |
6a5cbd59 MS |
688 | |
689 | if (enable) | |
690 | val |= 0x40; | |
691 | else | |
692 | val &= ~0x40; | |
693 | ||
694 | ret = mt312_writereg(state, GPP_CTRL, val); | |
695 | ||
696 | error: | |
697 | return ret; | |
a81870e0 AQ |
698 | } |
699 | ||
89f64758 | 700 | static int mt312_sleep(struct dvb_frontend *fe) |
1da177e4 | 701 | { |
b8742700 | 702 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
703 | int ret; |
704 | u8 config; | |
705 | ||
706 | /* reset all registers to defaults */ | |
994fc28b MS |
707 | ret = mt312_reset(state, 1); |
708 | if (ret < 0) | |
1da177e4 LT |
709 | return ret; |
710 | ||
6a5cbd59 MS |
711 | if (state->id == ID_ZL10313) { |
712 | /* reset ADC */ | |
713 | ret = mt312_writereg(state, GPP_CTRL, 0x00); | |
714 | if (ret < 0) | |
715 | return ret; | |
716 | ||
717 | /* full shutdown of ADCs, mpeg bus tristated */ | |
718 | ret = mt312_writereg(state, HW_CTRL, 0x0d); | |
719 | if (ret < 0) | |
720 | return ret; | |
721 | } | |
722 | ||
994fc28b MS |
723 | ret = mt312_readreg(state, CONFIG, &config); |
724 | if (ret < 0) | |
1da177e4 LT |
725 | return ret; |
726 | ||
727 | /* enter standby */ | |
994fc28b MS |
728 | ret = mt312_writereg(state, CONFIG, config & 0x7f); |
729 | if (ret < 0) | |
1da177e4 LT |
730 | return ret; |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
89f64758 MS |
735 | static int mt312_get_tune_settings(struct dvb_frontend *fe, |
736 | struct dvb_frontend_tune_settings *fesettings) | |
1da177e4 LT |
737 | { |
738 | fesettings->min_delay_ms = 50; | |
739 | fesettings->step_size = 0; | |
740 | fesettings->max_drift = 0; | |
741 | return 0; | |
742 | } | |
743 | ||
89f64758 | 744 | static void mt312_release(struct dvb_frontend *fe) |
1da177e4 | 745 | { |
89f64758 | 746 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
747 | kfree(state); |
748 | } | |
749 | ||
111221fb | 750 | #define MT312_SYS_CLK 90000000UL /* 90 MHz */ |
e4671b6b | 751 | static struct dvb_frontend_ops mt312_ops = { |
827b5f3e | 752 | .delsys = { SYS_DVBS }, |
1da177e4 LT |
753 | .info = { |
754 | .name = "Zarlink ???? DVB-S", | |
1da177e4 LT |
755 | .frequency_min = 950000, |
756 | .frequency_max = 2150000, | |
0389b34e MS |
757 | /* FIXME: adjust freq to real used xtal */ |
758 | .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128, | |
111221fb | 759 | .symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */ |
1da177e4 LT |
760 | .symbol_rate_max = MT312_SYS_CLK / 2, |
761 | .caps = | |
762 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | | |
763 | FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | | |
764 | FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS | | |
9101e622 | 765 | FE_CAN_RECOVER |
1da177e4 LT |
766 | }, |
767 | ||
768 | .release = mt312_release, | |
769 | ||
770 | .init = mt312_initfe, | |
771 | .sleep = mt312_sleep, | |
a81870e0 | 772 | .i2c_gate_ctrl = mt312_i2c_gate_ctrl, |
1da177e4 | 773 | |
827b5f3e MCC |
774 | .set_frontend = mt312_set_frontend, |
775 | .get_frontend = mt312_get_frontend, | |
1da177e4 LT |
776 | .get_tune_settings = mt312_get_tune_settings, |
777 | ||
778 | .read_status = mt312_read_status, | |
779 | .read_ber = mt312_read_ber, | |
780 | .read_signal_strength = mt312_read_signal_strength, | |
781 | .read_snr = mt312_read_snr, | |
782 | .read_ucblocks = mt312_read_ucblocks, | |
783 | ||
784 | .diseqc_send_master_cmd = mt312_send_master_cmd, | |
785 | .diseqc_send_burst = mt312_send_burst, | |
786 | .set_tone = mt312_set_tone, | |
787 | .set_voltage = mt312_set_voltage, | |
788 | }; | |
789 | ||
e4671b6b | 790 | struct dvb_frontend *mt312_attach(const struct mt312_config *config, |
89f64758 | 791 | struct i2c_adapter *i2c) |
805e660c | 792 | { |
89f64758 | 793 | struct mt312_state *state = NULL; |
805e660c AB |
794 | |
795 | /* allocate memory for the internal state */ | |
084e24ac | 796 | state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL); |
805e660c AB |
797 | if (state == NULL) |
798 | goto error; | |
799 | ||
800 | /* setup the state */ | |
801 | state->config = config; | |
802 | state->i2c = i2c; | |
805e660c AB |
803 | |
804 | /* check if the demod is there */ | |
805 | if (mt312_readreg(state, ID, &state->id) < 0) | |
806 | goto error; | |
807 | ||
dea74869 | 808 | /* create dvb_frontend */ |
e4671b6b | 809 | memcpy(&state->frontend.ops, &mt312_ops, |
89f64758 | 810 | sizeof(struct dvb_frontend_ops)); |
dea74869 PB |
811 | state->frontend.demodulator_priv = state; |
812 | ||
805e660c AB |
813 | switch (state->id) { |
814 | case ID_VP310: | |
dea74869 | 815 | strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S"); |
111221fb MS |
816 | state->xtal = MT312_PLL_CLK; |
817 | state->freq_mult = 9; | |
805e660c AB |
818 | break; |
819 | case ID_MT312: | |
dea74869 | 820 | strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S"); |
111221fb MS |
821 | state->xtal = MT312_PLL_CLK; |
822 | state->freq_mult = 6; | |
805e660c | 823 | break; |
6a5cbd59 MS |
824 | case ID_ZL10313: |
825 | strcpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S"); | |
826 | state->xtal = MT312_PLL_CLK_10_111; | |
827 | state->freq_mult = 9; | |
828 | break; | |
805e660c | 829 | default: |
6a5cbd59 | 830 | printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313" |
89f64758 | 831 | " are supported chips.\n"); |
805e660c AB |
832 | goto error; |
833 | } | |
834 | ||
805e660c AB |
835 | return &state->frontend; |
836 | ||
837 | error: | |
838 | kfree(state); | |
839 | return NULL; | |
840 | } | |
e4671b6b | 841 | EXPORT_SYMBOL(mt312_attach); |
805e660c | 842 | |
1da177e4 LT |
843 | module_param(debug, int, 0644); |
844 | MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); | |
845 | ||
6a5cbd59 | 846 | MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver"); |
1da177e4 | 847 | MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>"); |
e4671b6b | 848 | MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>"); |
1da177e4 LT |
849 | MODULE_LICENSE("GPL"); |
850 |