[deliverable/linux.git] / drivers / media / dvb-frontends / ts2020.c

/*
    Montage Technology TS2020 - Silicon Tuner driver
    Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>

    Copyright (C) 2009-2012 TurboSight.com

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include "dvb_frontend.h"
#include "ts2020.h"

#define TS2020_XTAL_FREQ   27000 /* in kHz */
#define FREQ_OFFSET_LOW_SYM_RATE 3000

struct ts2020_priv {
	/* i2c details */
	int i2c_address;
	struct i2c_adapter *i2c;
	u8 clk_out_div;
	u32 frequency;
	u32 frequency_div;
};

static int ts2020_release(struct dvb_frontend *fe)
{
	kfree(fe->tuner_priv);
	fe->tuner_priv = NULL;
	return 0;
}

static int ts2020_writereg(struct dvb_frontend *fe, int reg, int data)
{
	struct ts2020_priv *priv = fe->tuner_priv;
	u8 buf[] = { reg, data };
	struct i2c_msg msg[] = {
		{
			.addr = priv->i2c_address,
			.flags = 0,
			.buf = buf,
			.len = 2
		}
	};
	int err;

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 1);

	err = i2c_transfer(priv->i2c, msg, 1);
	if (err != 1) {
		printk(KERN_ERR
		       "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
		       __func__, err, reg, data);
		return -EREMOTEIO;
	}

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 0);

	return 0;
}

static int ts2020_readreg(struct dvb_frontend *fe, u8 reg)
{
	struct ts2020_priv *priv = fe->tuner_priv;
	int ret;
	u8 b0[] = { reg };
	u8 b1[] = { 0 };
	struct i2c_msg msg[] = {
		{
			.addr = priv->i2c_address,
			.flags = 0,
			.buf = b0,
			.len = 1
		}, {
			.addr = priv->i2c_address,
			.flags = I2C_M_RD,
			.buf = b1,
			.len = 1
		}
	};

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 1);

	ret = i2c_transfer(priv->i2c, msg, 2);

	if (ret != 2) {
		printk(KERN_ERR "%s: reg=0x%x(error=%d)\n",
		       __func__, reg, ret);
		return ret;
	}

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 0);

	return b1[0];
}

static int ts2020_sleep(struct dvb_frontend *fe)
{
	struct ts2020_priv *priv = fe->tuner_priv;
	int ret;
	u8 buf[] = { 10, 0 };
	struct i2c_msg msg = {
		.addr = priv->i2c_address,
		.flags = 0,
		.buf = buf,
		.len = 2
	};

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 1);

	ret = i2c_transfer(priv->i2c, &msg, 1);
	if (ret != 1)
		printk(KERN_ERR "%s: i2c error\n", __func__);

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 0);

	return (ret == 1) ? 0 : ret;
}

static int ts2020_init(struct dvb_frontend *fe)
{
	struct ts2020_priv *priv = fe->tuner_priv;

	ts2020_writereg(fe, 0x42, 0x73);
	ts2020_writereg(fe, 0x05, priv->clk_out_div);
	ts2020_writereg(fe, 0x20, 0x27);
	ts2020_writereg(fe, 0x07, 0x02);
	ts2020_writereg(fe, 0x11, 0xff);
	ts2020_writereg(fe, 0x60, 0xf9);
	ts2020_writereg(fe, 0x08, 0x01);
	ts2020_writereg(fe, 0x00, 0x41);

	return 0;
}

static int ts2020_tuner_gate_ctrl(struct dvb_frontend *fe, u8 offset)
{
	int ret;
	ret = ts2020_writereg(fe, 0x51, 0x1f - offset);
	ret |= ts2020_writereg(fe, 0x51, 0x1f);
	ret |= ts2020_writereg(fe, 0x50, offset);
	ret |= ts2020_writereg(fe, 0x50, 0x00);
	msleep(20);
	return ret;
}

static int ts2020_set_tuner_rf(struct dvb_frontend *fe)
{
	int reg;

	reg = ts2020_readreg(fe, 0x3d);
	reg &= 0x7f;
	if (reg < 0x16)
		reg = 0xa1;
	else if (reg == 0x16)
		reg = 0x99;
	else
		reg = 0xf9;

	ts2020_writereg(fe, 0x60, reg);
	reg = ts2020_tuner_gate_ctrl(fe, 0x08);

	return reg;
}

static int ts2020_set_params(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	struct ts2020_priv *priv = fe->tuner_priv;
	int ret;
	u32 frequency = c->frequency;
	s32 offset_khz;
	u32 symbol_rate = (c->symbol_rate / 1000);
	u32 f3db, gdiv28;
	u16 value, ndiv, lpf_coeff;
	u8 lpf_mxdiv, mlpf_max, mlpf_min, nlpf;
	u8 lo = 0x01, div4 = 0x0;

	/* Calculate frequency divider */
	if (frequency < priv->frequency_div) {
		lo |= 0x10;
		div4 = 0x1;
		ndiv = (frequency * 14 * 4) / TS2020_XTAL_FREQ;
	} else
		ndiv = (frequency * 14 * 2) / TS2020_XTAL_FREQ;
	ndiv = ndiv + ndiv % 2;
	ndiv = ndiv - 1024;

	ret = ts2020_writereg(fe, 0x10, 0x80 | lo);

	/* Set frequency divider */
	ret |= ts2020_writereg(fe, 0x01, (ndiv >> 8) & 0xf);
	ret |= ts2020_writereg(fe, 0x02, ndiv & 0xff);

	ret |= ts2020_writereg(fe, 0x03, 0x06);
	ret |= ts2020_tuner_gate_ctrl(fe, 0x10);
	if (ret < 0)
		return -ENODEV;

	/* Tuner Frequency Range */
	ret = ts2020_writereg(fe, 0x10, lo);

	ret |= ts2020_tuner_gate_ctrl(fe, 0x08);

	/* Tuner RF */
	ret |= ts2020_set_tuner_rf(fe);

	gdiv28 = (TS2020_XTAL_FREQ / 1000 * 1694 + 500) / 1000;
	ret |= ts2020_writereg(fe, 0x04, gdiv28 & 0xff);
	ret |= ts2020_tuner_gate_ctrl(fe, 0x04);
	if (ret < 0)
		return -ENODEV;

	value = ts2020_readreg(fe, 0x26);

	f3db = (symbol_rate * 135) / 200 + 2000;
	f3db += FREQ_OFFSET_LOW_SYM_RATE;
	if (f3db < 7000)
		f3db = 7000;
	if (f3db > 40000)
		f3db = 40000;

	gdiv28 = gdiv28 * 207 / (value * 2 + 151);
	mlpf_max = gdiv28 * 135 / 100;
	mlpf_min = gdiv28 * 78 / 100;
	if (mlpf_max > 63)
		mlpf_max = 63;

	lpf_coeff = 2766;

	nlpf = (f3db * gdiv28 * 2 / lpf_coeff /
		(TS2020_XTAL_FREQ / 1000)  + 1) / 2;
	if (nlpf > 23)
		nlpf = 23;
	if (nlpf < 1)
		nlpf = 1;

	lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
		* lpf_coeff * 2  / f3db + 1) / 2;

	if (lpf_mxdiv < mlpf_min) {
		nlpf++;
		lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
			* lpf_coeff * 2  / f3db + 1) / 2;
	}

	if (lpf_mxdiv > mlpf_max)
		lpf_mxdiv = mlpf_max;

	ret = ts2020_writereg(fe, 0x04, lpf_mxdiv);
	ret |= ts2020_writereg(fe, 0x06, nlpf);

	ret |= ts2020_tuner_gate_ctrl(fe, 0x04);

	ret |= ts2020_tuner_gate_ctrl(fe, 0x01);

	msleep(80);
	/* calculate offset assuming 96000kHz*/
	offset_khz = (ndiv - ndiv % 2 + 1024) * TS2020_XTAL_FREQ
		/ (6 + 8) / (div4 + 1) / 2;

	priv->frequency = offset_khz;

	return (ret < 0) ? -EINVAL : 0;
}

static int ts2020_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
	struct ts2020_priv *priv = fe->tuner_priv;
	*frequency = priv->frequency;
	return 0;
}

/* read TS2020 signal strength */
static int ts2020_read_signal_strength(struct dvb_frontend *fe,
						u16 *signal_strength)
{
	u16 sig_reading, sig_strength;
	u8 rfgain, bbgain;

	rfgain = ts2020_readreg(fe, 0x3d) & 0x1f;
	bbgain = ts2020_readreg(fe, 0x21) & 0x1f;

	if (rfgain > 15)
		rfgain = 15;
	if (bbgain > 13)
		bbgain = 13;

	sig_reading = rfgain * 2 + bbgain * 3;

	sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;

	/* cook the value to be suitable for szap-s2 human readable output */
	*signal_strength = sig_strength * 1000;

	return 0;
}

static struct dvb_tuner_ops ts2020_tuner_ops = {
	.info = {
		.name = "TS2020",
		.frequency_min = 950000,
		.frequency_max = 2150000
	},
	.init = ts2020_init,
	.release = ts2020_release,
	.sleep = ts2020_sleep,
	.set_params = ts2020_set_params,
	.get_frequency = ts2020_get_frequency,
	.get_rf_strength = ts2020_read_signal_strength,
};

struct dvb_frontend *ts2020_attach(struct dvb_frontend *fe,
					const struct ts2020_config *config,
					struct i2c_adapter *i2c)
{
	struct ts2020_priv *priv = NULL;
	u8 buf;

	priv = kzalloc(sizeof(struct ts2020_priv), GFP_KERNEL);
	if (priv == NULL)
		return NULL;

	priv->i2c_address = config->tuner_address;
	priv->i2c = i2c;
	priv->clk_out_div = config->clk_out_div;
	priv->frequency_div = config->frequency_div;
	fe->tuner_priv = priv;

	if (!priv->frequency_div)
		priv->frequency_div = 1060000;

	/* Wake Up the tuner */
	if ((0x03 & ts2020_readreg(fe, 0x00)) == 0x00) {
		ts2020_writereg(fe, 0x00, 0x01);
		msleep(2);
	}

	ts2020_writereg(fe, 0x00, 0x03);
	msleep(2);

	/* Check the tuner version */
	buf = ts2020_readreg(fe, 0x00);
	if ((buf == 0x01) || (buf == 0x41) || (buf == 0x81))
		printk(KERN_INFO "%s: Find tuner TS2020!\n", __func__);
	else {
		printk(KERN_ERR "%s: Read tuner reg[0] = %d\n", __func__, buf);
		kfree(priv);
		return NULL;
	}

	memcpy(&fe->ops.tuner_ops, &ts2020_tuner_ops,
				sizeof(struct dvb_tuner_ops));

	return fe;
}
EXPORT_SYMBOL(ts2020_attach);

MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
MODULE_DESCRIPTION("Montage Technology TS2020 - Silicon tuner driver module");
MODULE_LICENSE("GPL");
Commit	Line	Data
6fef4fc7 KD	1	/*
	2	Montage Technology TS2020 - Silicon Tuner driver
	3	Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
	4
	5	Copyright (C) 2009-2012 TurboSight.com
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; if not, write to the Free Software
	19	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	20	*/
	21
	22	#include "dvb_frontend.h"
	23	#include "ts2020.h"
	24
	25	#define TS2020_XTAL_FREQ 27000 /* in kHz */
b858c331	26	#define FREQ_OFFSET_LOW_SYM_RATE 3000
6fef4fc7	27
b858c331 IL	28	struct ts2020_priv {
	29	/* i2c details */
	30	int i2c_address;
6fef4fc7	31	struct i2c_adapter *i2c;
b858c331 IL	32	u8 clk_out_div;
b858c331 IL	33	u32 frequency;
03a67279	34	u32 frequency_div;
6fef4fc7 KD	35	};
6fef4fc7 KD	36
b858c331	37	static int ts2020_release(struct dvb_frontend *fe)
6fef4fc7	38	{
b858c331 IL	39	kfree(fe->tuner_priv);
	40	fe->tuner_priv = NULL;
	41	return 0;
	42	}
	43
	44	static int ts2020_writereg(struct dvb_frontend *fe, int reg, int data)
	45	{
	46	struct ts2020_priv *priv = fe->tuner_priv;
	47	u8 buf[] = { reg, data };
	48	struct i2c_msg msg[] = {
	49	{
	50	.addr = priv->i2c_address,
	51	.flags = 0,
	52	.buf = buf,
	53	.len = 2
	54	}
	55	};
	56	int err;
	57
	58	if (fe->ops.i2c_gate_ctrl)
	59	fe->ops.i2c_gate_ctrl(fe, 1);
	60
	61	err = i2c_transfer(priv->i2c, msg, 1);
	62	if (err != 1) {
	63	printk(KERN_ERR
	64	"%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
	65	__func__, err, reg, data);
	66	return -EREMOTEIO;
	67	}
6fef4fc7	68
b858c331 IL	69	if (fe->ops.i2c_gate_ctrl)
	70	fe->ops.i2c_gate_ctrl(fe, 0);
	71
	72	return 0;
	73	}
	74
	75	static int ts2020_readreg(struct dvb_frontend *fe, u8 reg)
	76	{
	77	struct ts2020_priv *priv = fe->tuner_priv;
6fef4fc7 KD	78	int ret;
	79	u8 b0[] = { reg };
	80	u8 b1[] = { 0 };
	81	struct i2c_msg msg[] = {
	82	{
b858c331	83	.addr = priv->i2c_address,
6fef4fc7 KD	84	.flags = 0,
	85	.buf = b0,
	86	.len = 1
	87	}, {
b858c331	88	.addr = priv->i2c_address,
6fef4fc7 KD	89	.flags = I2C_M_RD,
	90	.buf = b1,
	91	.len = 1
	92	}
	93	};
	94
	95	if (fe->ops.i2c_gate_ctrl)
	96	fe->ops.i2c_gate_ctrl(fe, 1);
	97
b858c331	98	ret = i2c_transfer(priv->i2c, msg, 2);
6fef4fc7 KD	99
6fef4fc7 KD	100	if (ret != 2) {
b858c331 IL	101	printk(KERN_ERR "%s: reg=0x%x(error=%d)\n",
b858c331 IL	102	__func__, reg, ret);
6fef4fc7 KD	103	return ret;
	104	}
	105
b858c331 IL	106	if (fe->ops.i2c_gate_ctrl)
	107	fe->ops.i2c_gate_ctrl(fe, 0);
	108
6fef4fc7 KD	109	return b1[0];
	110	}
	111
b858c331	112	static int ts2020_sleep(struct dvb_frontend *fe)
6fef4fc7	113	{
b858c331 IL	114	struct ts2020_priv *priv = fe->tuner_priv;
	115	int ret;
	116	u8 buf[] = { 10, 0 };
	117	struct i2c_msg msg = {
	118	.addr = priv->i2c_address,
	119	.flags = 0,
	120	.buf = buf,
	121	.len = 2
	122	};
6fef4fc7 KD	123
	124	if (fe->ops.i2c_gate_ctrl)
	125	fe->ops.i2c_gate_ctrl(fe, 1);
	126
b858c331 IL	127	ret = i2c_transfer(priv->i2c, &msg, 1);
	128	if (ret != 1)
	129	printk(KERN_ERR "%s: i2c error\n", __func__);
6fef4fc7 KD	130
	131	if (fe->ops.i2c_gate_ctrl)
	132	fe->ops.i2c_gate_ctrl(fe, 0);
	133
b858c331	134	return (ret == 1) ? 0 : ret;
6fef4fc7 KD	135	}
	136
	137	static int ts2020_init(struct dvb_frontend *fe)
	138	{
b858c331 IL	139	struct ts2020_priv *priv = fe->tuner_priv;
b858c331 IL	140
6fef4fc7	141	ts2020_writereg(fe, 0x42, 0x73);
b858c331 IL	142	ts2020_writereg(fe, 0x05, priv->clk_out_div);
	143	ts2020_writereg(fe, 0x20, 0x27);
	144	ts2020_writereg(fe, 0x07, 0x02);
	145	ts2020_writereg(fe, 0x11, 0xff);
	146	ts2020_writereg(fe, 0x60, 0xf9);
	147	ts2020_writereg(fe, 0x08, 0x01);
	148	ts2020_writereg(fe, 0x00, 0x41);
	149
6fef4fc7 KD	150	return 0;
	151	}
	152
b858c331	153	static int ts2020_tuner_gate_ctrl(struct dvb_frontend *fe, u8 offset)
6fef4fc7	154	{
b858c331 IL	155	int ret;
	156	ret = ts2020_writereg(fe, 0x51, 0x1f - offset);
	157	ret \|= ts2020_writereg(fe, 0x51, 0x1f);
	158	ret \|= ts2020_writereg(fe, 0x50, offset);
	159	ret \|= ts2020_writereg(fe, 0x50, 0x00);
	160	msleep(20);
	161	return ret;
	162	}
6fef4fc7	163
b858c331 IL	164	static int ts2020_set_tuner_rf(struct dvb_frontend *fe)
	165	{
	166	int reg;
6fef4fc7	167
b858c331 IL	168	reg = ts2020_readreg(fe, 0x3d);
	169	reg &= 0x7f;
	170	if (reg < 0x16)
	171	reg = 0xa1;
	172	else if (reg == 0x16)
	173	reg = 0x99;
	174	else
	175	reg = 0xf9;
6fef4fc7	176
b858c331 IL	177	ts2020_writereg(fe, 0x60, reg);
b858c331 IL	178	reg = ts2020_tuner_gate_ctrl(fe, 0x08);
6fef4fc7	179
b858c331	180	return reg;
6fef4fc7 KD	181	}
	182
	183	static int ts2020_set_params(struct dvb_frontend *fe)
	184	{
	185	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
9898df64	186	struct ts2020_priv *priv = fe->tuner_priv;
b858c331 IL	187	int ret;
	188	u32 frequency = c->frequency;
	189	s32 offset_khz;
	190	u32 symbol_rate = (c->symbol_rate / 1000);
	191	u32 f3db, gdiv28;
	192	u16 value, ndiv, lpf_coeff;
	193	u8 lpf_mxdiv, mlpf_max, mlpf_min, nlpf;
	194	u8 lo = 0x01, div4 = 0x0;
	195
	196	/* Calculate frequency divider */
03a67279	197	if (frequency < priv->frequency_div) {
b858c331 IL	198	lo \|= 0x10;
	199	div4 = 0x1;
	200	ndiv = (frequency * 14 * 4) / TS2020_XTAL_FREQ;
	201	} else
	202	ndiv = (frequency * 14 * 2) / TS2020_XTAL_FREQ;
	203	ndiv = ndiv + ndiv % 2;
	204	ndiv = ndiv - 1024;
	205
	206	ret = ts2020_writereg(fe, 0x10, 0x80 \| lo);
	207
	208	/* Set frequency divider */
	209	ret \|= ts2020_writereg(fe, 0x01, (ndiv >> 8) & 0xf);
	210	ret \|= ts2020_writereg(fe, 0x02, ndiv & 0xff);
	211
	212	ret \|= ts2020_writereg(fe, 0x03, 0x06);
	213	ret \|= ts2020_tuner_gate_ctrl(fe, 0x10);
	214	if (ret < 0)
	215	return -ENODEV;
	216
	217	/* Tuner Frequency Range */
	218	ret = ts2020_writereg(fe, 0x10, lo);
	219
	220	ret \|= ts2020_tuner_gate_ctrl(fe, 0x08);
	221
	222	/* Tuner RF */
	223	ret \|= ts2020_set_tuner_rf(fe);
	224
	225	gdiv28 = (TS2020_XTAL_FREQ / 1000 * 1694 + 500) / 1000;
	226	ret \|= ts2020_writereg(fe, 0x04, gdiv28 & 0xff);
	227	ret \|= ts2020_tuner_gate_ctrl(fe, 0x04);
	228	if (ret < 0)
	229	return -ENODEV;
6fef4fc7	230
b858c331	231	value = ts2020_readreg(fe, 0x26);
6fef4fc7	232
b858c331 IL	233	f3db = (symbol_rate * 135) / 200 + 2000;
b858c331 IL	234	f3db += FREQ_OFFSET_LOW_SYM_RATE;
6fef4fc7 KD	235	if (f3db < 7000)
	236	f3db = 7000;
	237	if (f3db > 40000)
	238	f3db = 40000;
	239
b858c331 IL	240	gdiv28 = gdiv28 * 207 / (value * 2 + 151);
	241	mlpf_max = gdiv28 * 135 / 100;
	242	mlpf_min = gdiv28 * 78 / 100;
6fef4fc7 KD	243	if (mlpf_max > 63)
	244	mlpf_max = 63;
	245
b858c331 IL	246	lpf_coeff = 2766;
	247
	248	nlpf = (f3db * gdiv28 * 2 / lpf_coeff /
	249	(TS2020_XTAL_FREQ / 1000) + 1) / 2;
6fef4fc7 KD	250	if (nlpf > 23)
	251	nlpf = 23;
	252	if (nlpf < 1)
	253	nlpf = 1;
	254
b858c331 IL	255	lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
b858c331 IL	256	* lpf_coeff * 2 / f3db + 1) / 2;
6fef4fc7	257
b858c331	258	if (lpf_mxdiv < mlpf_min) {
6fef4fc7	259	nlpf++;
b858c331 IL	260	lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
b858c331 IL	261	* lpf_coeff * 2 / f3db + 1) / 2;
6fef4fc7 KD	262	}
6fef4fc7 KD	263
b858c331 IL	264	if (lpf_mxdiv > mlpf_max)
b858c331 IL	265	lpf_mxdiv = mlpf_max;
6fef4fc7	266
b858c331 IL	267	ret = ts2020_writereg(fe, 0x04, lpf_mxdiv);
b858c331 IL	268	ret \|= ts2020_writereg(fe, 0x06, nlpf);
6fef4fc7	269
b858c331	270	ret \|= ts2020_tuner_gate_ctrl(fe, 0x04);
6fef4fc7	271
b858c331	272	ret \|= ts2020_tuner_gate_ctrl(fe, 0x01);
6fef4fc7	273
b858c331 IL	274	msleep(80);
	275	/* calculate offset assuming 96000kHz*/
	276	offset_khz = (ndiv - ndiv % 2 + 1024) * TS2020_XTAL_FREQ
	277	/ (6 + 8) / (div4 + 1) / 2;
6fef4fc7	278
b858c331 IL	279	priv->frequency = offset_khz;
	280
	281	return (ret < 0) ? -EINVAL : 0;
	282	}
6fef4fc7	283
b858c331 IL	284	static int ts2020_get_frequency(struct dvb_frontend fe, u32 frequency)
	285	{
	286	struct ts2020_priv *priv = fe->tuner_priv;
	287	*frequency = priv->frequency;
6fef4fc7 KD	288	return 0;
	289	}
	290
b858c331 IL	291	/* read TS2020 signal strength */
	292	static int ts2020_read_signal_strength(struct dvb_frontend *fe,
	293	u16 *signal_strength)
6fef4fc7 KD	294	{
	295	u16 sig_reading, sig_strength;
	296	u8 rfgain, bbgain;
	297
	298	rfgain = ts2020_readreg(fe, 0x3d) & 0x1f;
	299	bbgain = ts2020_readreg(fe, 0x21) & 0x1f;
	300
	301	if (rfgain > 15)
	302	rfgain = 15;
	303	if (bbgain > 13)
	304	bbgain = 13;
	305
	306	sig_reading = rfgain * 2 + bbgain * 3;
	307
	308	sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;
	309
	310	/* cook the value to be suitable for szap-s2 human readable output */
	311	signal_strength = sig_strength 1000;
	312
	313	return 0;
	314	}
	315
b858c331	316	static struct dvb_tuner_ops ts2020_tuner_ops = {
6fef4fc7	317	.info = {
b858c331	318	.name = "TS2020",
6fef4fc7	319	.frequency_min = 950000,
b858c331	320	.frequency_max = 2150000
6fef4fc7	321	},
6fef4fc7 KD	322	.init = ts2020_init,
6fef4fc7 KD	323	.release = ts2020_release,
b858c331	324	.sleep = ts2020_sleep,
6fef4fc7 KD	325	.set_params = ts2020_set_params,
6fef4fc7 KD	326	.get_frequency = ts2020_get_frequency,
b858c331	327	.get_rf_strength = ts2020_read_signal_strength,
6fef4fc7 KD	328	};
	329
	330	struct dvb_frontend ts2020_attach(struct dvb_frontend fe,
b858c331 IL	331	const struct ts2020_config *config,
b858c331 IL	332	struct i2c_adapter *i2c)
6fef4fc7	333	{
b858c331 IL	334	struct ts2020_priv *priv = NULL;
	335	u8 buf;
	336
	337	priv = kzalloc(sizeof(struct ts2020_priv), GFP_KERNEL);
	338	if (priv == NULL)
	339	return NULL;
6fef4fc7	340
b858c331 IL	341	priv->i2c_address = config->tuner_address;
	342	priv->i2c = i2c;
	343	priv->clk_out_div = config->clk_out_div;
03a67279	344	priv->frequency_div = config->frequency_div;
b858c331 IL	345	fe->tuner_priv = priv;
b858c331 IL	346
b4559ace MCC	347	if (!priv->frequency_div)
	348	priv->frequency_div = 1060000;
	349
b858c331 IL	350	/* Wake Up the tuner */
	351	if ((0x03 & ts2020_readreg(fe, 0x00)) == 0x00) {
	352	ts2020_writereg(fe, 0x00, 0x01);
	353	msleep(2);
	354	}
	355
	356	ts2020_writereg(fe, 0x00, 0x03);
	357	msleep(2);
	358
	359	/* Check the tuner version */
	360	buf = ts2020_readreg(fe, 0x00);
	361	if ((buf == 0x01) \|\| (buf == 0x41) \|\| (buf == 0x81))
	362	printk(KERN_INFO "%s: Find tuner TS2020!\n", __func__);
	363	else {
	364	printk(KERN_ERR "%s: Read tuner reg[0] = %d\n", __func__, buf);
	365	kfree(priv);
6fef4fc7	366	return NULL;
b858c331	367	}
6fef4fc7	368
b858c331 IL	369	memcpy(&fe->ops.tuner_ops, &ts2020_tuner_ops,
b858c331 IL	370	sizeof(struct dvb_tuner_ops));
6fef4fc7 KD	371
	372	return fe;
	373	}
	374	EXPORT_SYMBOL(ts2020_attach);
	375
	376	MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
	377	MODULE_DESCRIPTION("Montage Technology TS2020 - Silicon tuner driver module");
	378	MODULE_LICENSE("GPL");