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[media] ad9389b: whitespace changes to improve readability
[deliverable/linux.git] / drivers / media / i2c / ad9389b.c
CommitLineData
117a55b6
HV		 1/*
2 * Analog Devices AD9389B/AD9889B video encoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 */
19
20/*
21 * References (c = chapter, p = page):
22 * REF_01 - Analog Devices, Programming Guide, AD9889B/AD9389B,
23 * HDMI Transitter, Rev. A, October 2010
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/slab.h>
29#include <linux/i2c.h>
30#include <linux/delay.h>
31#include <linux/videodev2.h>
32#include <linux/workqueue.h>
33#include <linux/v4l2-dv-timings.h>
34#include <media/v4l2-device.h>
117a55b6 35#include <media/v4l2-common.h>
25764158 36#include <media/v4l2-dv-timings.h>
117a55b6
HV		 37#include <media/v4l2-ctrls.h>
38#include <media/ad9389b.h>
39
40static int debug;
41module_param(debug, int, 0644);
42MODULE_PARM_DESC(debug, "debug level (0-2)");
43
44MODULE_DESCRIPTION("Analog Devices AD9389B/AD9889B video encoder driver");
45MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
46MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
47MODULE_LICENSE("GPL");
48
49#define MASK_AD9389B_EDID_RDY_INT 0x04
50#define MASK_AD9389B_MSEN_INT 0x40
51#define MASK_AD9389B_HPD_INT 0x80
52
53#define MASK_AD9389B_HPD_DETECT 0x40
54#define MASK_AD9389B_MSEN_DETECT 0x20
55#define MASK_AD9389B_EDID_RDY 0x10
56
57#define EDID_MAX_RETRIES (8)
58#define EDID_DELAY 250
59#define EDID_MAX_SEGM 8
60
61/*
62**********************************************************************
63*
64* Arrays with configuration parameters for the AD9389B
65*
66**********************************************************************
67*/
68
69struct i2c_reg_value {
70 u8 reg;
71 u8 value;
72};
73
74struct ad9389b_state_edid {
75 /* total number of blocks */
76 u32 blocks;
77 /* Number of segments read */
78 u32 segments;
79 u8 data[EDID_MAX_SEGM * 256];
80 /* Number of EDID read retries left */
81 unsigned read_retries;
82};
83
84struct ad9389b_state {
85 struct ad9389b_platform_data pdata;
86 struct v4l2_subdev sd;
87 struct media_pad pad;
88 struct v4l2_ctrl_handler hdl;
89 int chip_revision;
90 /* Is the ad9389b powered on? */
91 bool power_on;
92 /* Did we receive hotplug and rx-sense signals? */
93 bool have_monitor;
94 /* timings from s_dv_timings */
95 struct v4l2_dv_timings dv_timings;
96 /* controls */
97 struct v4l2_ctrl *hdmi_mode_ctrl;
98 struct v4l2_ctrl *hotplug_ctrl;
99 struct v4l2_ctrl *rx_sense_ctrl;
100 struct v4l2_ctrl *have_edid0_ctrl;
101 struct v4l2_ctrl *rgb_quantization_range_ctrl;
102 struct i2c_client *edid_i2c_client;
103 struct ad9389b_state_edid edid;
104 /* Running counter of the number of detected EDIDs (for debugging) */
105 unsigned edid_detect_counter;
106 struct workqueue_struct *work_queue;
107 struct delayed_work edid_handler; /* work entry */
108};
109
110static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd);
111static bool ad9389b_check_edid_status(struct v4l2_subdev *sd);
112static void ad9389b_setup(struct v4l2_subdev *sd);
113static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
114static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
115
116static inline struct ad9389b_state *get_ad9389b_state(struct v4l2_subdev *sd)
117{
118 return container_of(sd, struct ad9389b_state, sd);
119}
120
121static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
122{
123 return &container_of(ctrl->handler, struct ad9389b_state, hdl)->sd;
124}
125
126/* ------------------------ I2C ----------------------------------------------- */
127
128static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
129{
130 struct i2c_client *client = v4l2_get_subdevdata(sd);
131
132 return i2c_smbus_read_byte_data(client, reg);
133}
134
135static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
136{
137 struct i2c_client *client = v4l2_get_subdevdata(sd);
138 int ret;
139 int i;
140
141 for (i = 0; i < 3; i++) {
142 ret = i2c_smbus_write_byte_data(client, reg, val);
143 if (ret == 0)
144 return 0;
145 }
146 v4l2_err(sd, "I2C Write Problem\n");
147 return ret;
148}
149
150/* To set specific bits in the register, a clear-mask is given (to be AND-ed),
151 and then the value-mask (to be OR-ed). */
152static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg,
d3ec7de4 153 u8 clr_mask, u8 val_mask)
117a55b6
HV		 154{
155 ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
156}
157
158static void ad9389b_edid_rd(struct v4l2_subdev *sd, u16 len, u8 *buf)
159{
160 struct ad9389b_state *state = get_ad9389b_state(sd);
161 int i;
162
163 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
164
165 for (i = 0; i < len; i++)
166 buf[i] = i2c_smbus_read_byte_data(state->edid_i2c_client, i);
167}
168
169static inline bool ad9389b_have_hotplug(struct v4l2_subdev *sd)
170{
171 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
172}
173
174static inline bool ad9389b_have_rx_sense(struct v4l2_subdev *sd)
175{
176 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
177}
178
179static void ad9389b_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
180{
181 ad9389b_wr_and_or(sd, 0x17, 0xe7, (mode & 0x3)<<3);
182 ad9389b_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
183}
184
185static void ad9389b_csc_coeff(struct v4l2_subdev *sd,
186 u16 A1, u16 A2, u16 A3, u16 A4,
187 u16 B1, u16 B2, u16 B3, u16 B4,
188 u16 C1, u16 C2, u16 C3, u16 C4)
189{
190 /* A */
191 ad9389b_wr_and_or(sd, 0x18, 0xe0, A1>>8);
192 ad9389b_wr(sd, 0x19, A1);
193 ad9389b_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
194 ad9389b_wr(sd, 0x1B, A2);
195 ad9389b_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
196 ad9389b_wr(sd, 0x1d, A3);
197 ad9389b_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
198 ad9389b_wr(sd, 0x1f, A4);
199
200 /* B */
201 ad9389b_wr_and_or(sd, 0x20, 0xe0, B1>>8);
202 ad9389b_wr(sd, 0x21, B1);
203 ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8);
204 ad9389b_wr(sd, 0x23, B2);
205 ad9389b_wr_and_or(sd, 0x24, 0xe0, B3>>8);
206 ad9389b_wr(sd, 0x25, B3);
207 ad9389b_wr_and_or(sd, 0x26, 0xe0, B4>>8);
208 ad9389b_wr(sd, 0x27, B4);
209
210 /* C */
211 ad9389b_wr_and_or(sd, 0x28, 0xe0, C1>>8);
212 ad9389b_wr(sd, 0x29, C1);
213 ad9389b_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
214 ad9389b_wr(sd, 0x2B, C2);
215 ad9389b_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
216 ad9389b_wr(sd, 0x2D, C3);
217 ad9389b_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
218 ad9389b_wr(sd, 0x2F, C4);
219}
220
221static void ad9389b_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
222{
223 if (enable) {
224 u8 csc_mode = 0;
225
226 ad9389b_csc_conversion_mode(sd, csc_mode);
227 ad9389b_csc_coeff(sd,
228 4096-564, 0, 0, 256,
229 0, 4096-564, 0, 256,
230 0, 0, 4096-564, 256);
231 /* enable CSC */
232 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x1);
233 /* AVI infoframe: Limited range RGB (16-235) */
234 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x02);
235 } else {
236 /* disable CSC */
237 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x0);
238 /* AVI infoframe: Full range RGB (0-255) */
239 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x04);
240 }
241}
242
243static void ad9389b_set_IT_content_AVI_InfoFrame(struct v4l2_subdev *sd)
244{
245 struct ad9389b_state *state = get_ad9389b_state(sd);
246
247 if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
248 /* CEA format, not IT */
249 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x00);
250 } else {
251 /* IT format */
252 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x40);
253 }
254}
255
256static int ad9389b_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
257{
258 struct ad9389b_state *state = get_ad9389b_state(sd);
259
260 switch (ctrl->val) {
261 case V4L2_DV_RGB_RANGE_AUTO:
262 /* automatic */
263 if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
264 /* cea format, RGB limited range (16-235) */
265 ad9389b_csc_rgb_full2limit(sd, true);
266 } else {
267 /* not cea format, RGB full range (0-255) */
268 ad9389b_csc_rgb_full2limit(sd, false);
269 }
270 break;
271 case V4L2_DV_RGB_RANGE_LIMITED:
272 /* RGB limited range (16-235) */
273 ad9389b_csc_rgb_full2limit(sd, true);
274 break;
275 case V4L2_DV_RGB_RANGE_FULL:
276 /* RGB full range (0-255) */
277 ad9389b_csc_rgb_full2limit(sd, false);
278 break;
279 default:
280 return -EINVAL;
281 }
282 return 0;
283}
284
285static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)
286{
287 u8 gear;
288
289 /* Workaround for TMDS PLL problem
290 * The TMDS PLL in AD9389b change gear when the chip is heated above a
291 * certain temperature. The output is disabled when the PLL change gear
292 * so the monitor has to lock on the signal again. A workaround for
293 * this is to use the manual PLL gears. This is a solution from Analog
294 * Devices that is not documented in the datasheets.
295 * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear
296 *
297 * The pixel frequency ranges are based on readout of the gear the
298 * automatic gearing selects for different pixel clocks
299 * (read from 0x9e [3:1]).
300 */
301
302 if (pixelclock > 140000000)
303 gear = 0xc0; /* 4th gear */
304 else if (pixelclock > 117000000)
305 gear = 0xb0; /* 3rd gear */
306 else if (pixelclock > 87000000)
307 gear = 0xa0; /* 2nd gear */
308 else if (pixelclock > 60000000)
309 gear = 0x90; /* 1st gear */
310 else
311 gear = 0x80; /* 0th gear */
312
313 ad9389b_wr_and_or(sd, 0x98, 0x0f, gear);
314}
315
316/* ------------------------------ CTRL OPS ------------------------------ */
317
318static int ad9389b_s_ctrl(struct v4l2_ctrl *ctrl)
319{
320 struct v4l2_subdev *sd = to_sd(ctrl);
321 struct ad9389b_state *state = get_ad9389b_state(sd);
322
323 v4l2_dbg(1, debug, sd,
d3ec7de4 324 "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
117a55b6
HV		 325
326 if (state->hdmi_mode_ctrl == ctrl) {
327 /* Set HDMI or DVI-D */
328 ad9389b_wr_and_or(sd, 0xaf, 0xfd,
d3ec7de4 329 ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
117a55b6
HV		 330 return 0;
331 }
332 if (state->rgb_quantization_range_ctrl == ctrl)
333 return ad9389b_set_rgb_quantization_mode(sd, ctrl);
334 return -EINVAL;
335}
336
337static const struct v4l2_ctrl_ops ad9389b_ctrl_ops = {
338 .s_ctrl = ad9389b_s_ctrl,
339};
340
341/* ---------------------------- CORE OPS ------------------------------------------- */
342
343#ifdef CONFIG_VIDEO_ADV_DEBUG
344static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
345{
117a55b6
HV		 346 reg->val = ad9389b_rd(sd, reg->reg & 0xff);
347 reg->size = 1;
348 return 0;
349}
350
977ba3b1 351static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
117a55b6 352{
117a55b6
HV		 353 ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff);
354 return 0;
355}
356#endif
357
117a55b6
HV		 358static int ad9389b_log_status(struct v4l2_subdev *sd)
359{
360 struct ad9389b_state *state = get_ad9389b_state(sd);
361 struct ad9389b_state_edid *edid = &state->edid;
362
363 static const char * const states[] = {
364 "in reset",
365 "reading EDID",
366 "idle",
367 "initializing HDCP",
368 "HDCP enabled",
369 "initializing HDCP repeater",
370 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
371 };
372 static const char * const errors[] = {
373 "no error",
374 "bad receiver BKSV",
375 "Ri mismatch",
376 "Pj mismatch",
377 "i2c error",
378 "timed out",
379 "max repeater cascade exceeded",
380 "hash check failed",
381 "too many devices",
382 "9", "A", "B", "C", "D", "E", "F"
383 };
384
385 u8 manual_gear;
386
387 v4l2_info(sd, "chip revision %d\n", state->chip_revision);
388 v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
389 v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
d3ec7de4
MB		 390 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
391 "detected" : "no",
392 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
393 "detected" : "no",
394 edid->segments ? "found" : "no", edid->blocks);
117a55b6
HV		 395 if (state->have_monitor) {
396 v4l2_info(sd, "%s output %s\n",
d3ec7de4
MB		 397 (ad9389b_rd(sd, 0xaf) & 0x02) ?
398 "HDMI" : "DVI-D",
399 (ad9389b_rd(sd, 0xa1) & 0x3c) ?
400 "disabled" : "enabled");
117a55b6
HV		 401 }
402 v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
d3ec7de4 403 "encrypted" : "no encryption");
117a55b6 404 v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
d3ec7de4
MB		 405 states[ad9389b_rd(sd, 0xc8) & 0xf],
406 errors[ad9389b_rd(sd, 0xc8) >> 4],
407 state->edid_detect_counter,
408 ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
117a55b6
HV		 409 manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
410 v4l2_info(sd, "ad9389b: RGB quantization: %s range\n",
d3ec7de4 411 ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
117a55b6
HV		 412 v4l2_info(sd, "ad9389b: %s gear %d\n",
413 manual_gear ? "manual" : "automatic",
414 manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
d3ec7de4 415 ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
117a55b6
HV		 416 if (state->have_monitor) {
417 if (ad9389b_rd(sd, 0xaf) & 0x02) {
418 /* HDMI only */
419 u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
420 u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
d3ec7de4
MB		 421 ad9389b_rd(sd, 0x02) << 8 |
422 ad9389b_rd(sd, 0x03);
117a55b6
HV		 423 u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
424 u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
425 u32 CTS;
426
427 if (manual_cts)
428 CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
d3ec7de4
MB		 429 ad9389b_rd(sd, 0x08) << 8 |
430 ad9389b_rd(sd, 0x09);
117a55b6
HV		 431 else
432 CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
d3ec7de4
MB		 433 ad9389b_rd(sd, 0x05) << 8 |
434 ad9389b_rd(sd, 0x06);
117a55b6 435 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
d3ec7de4
MB		 436 ad9389b_rd(sd, 0x02) << 8 |
437 ad9389b_rd(sd, 0x03);
117a55b6
HV		 438
439 v4l2_info(sd, "ad9389b: CTS %s mode: N %d, CTS %d\n",
d3ec7de4 440 manual_cts ? "manual" : "automatic", N, CTS);
117a55b6
HV		 441
442 v4l2_info(sd, "ad9389b: VIC: detected %d, sent %d\n",
d3ec7de4 443 vic_detect, vic_sent);
117a55b6
HV		 444 }
445 }
11d034c8
HV		 446 if (state->dv_timings.type == V4L2_DV_BT_656_1120)
447 v4l2_print_dv_timings(sd->name, "timings: ",
448 &state->dv_timings, false);
449 else
117a55b6 450 v4l2_info(sd, "no timings set\n");
117a55b6
HV		 451 return 0;
452}
453
454/* Power up/down ad9389b */
455static int ad9389b_s_power(struct v4l2_subdev *sd, int on)
456{
457 struct ad9389b_state *state = get_ad9389b_state(sd);
458 struct ad9389b_platform_data *pdata = &state->pdata;
459 const int retries = 20;
460 int i;
461
462 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
463
464 state->power_on = on;
465
466 if (!on) {
467 /* Power down */
468 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
469 return true;
470 }
471
472 /* Power up */
473 /* The ad9389b does not always come up immediately.
474 Retry multiple times. */
475 for (i = 0; i < retries; i++) {
476 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x0);
477 if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
478 break;
479 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
480 msleep(10);
481 }
482 if (i == retries) {
483 v4l2_dbg(1, debug, sd, "failed to powerup the ad9389b\n");
484 ad9389b_s_power(sd, 0);
485 return false;
486 }
487 if (i > 1)
488 v4l2_dbg(1, debug, sd,
d3ec7de4 489 "needed %d retries to powerup the ad9389b\n", i);
117a55b6
HV		 490
491 /* Select chip: AD9389B */
492 ad9389b_wr_and_or(sd, 0xba, 0xef, 0x10);
493
494 /* Reserved registers that must be set according to REF_01 p. 11*/
495 ad9389b_wr_and_or(sd, 0x98, 0xf0, 0x07);
496 ad9389b_wr(sd, 0x9c, 0x38);
497 ad9389b_wr_and_or(sd, 0x9d, 0xfc, 0x01);
498
499 /* Differential output drive strength */
500 if (pdata->diff_data_drive_strength > 0)
501 ad9389b_wr(sd, 0xa2, pdata->diff_data_drive_strength);
502 else
503 ad9389b_wr(sd, 0xa2, 0x87);
504
505 if (pdata->diff_clk_drive_strength > 0)
506 ad9389b_wr(sd, 0xa3, pdata->diff_clk_drive_strength);
507 else
508 ad9389b_wr(sd, 0xa3, 0x87);
509
510 ad9389b_wr(sd, 0x0a, 0x01);
511 ad9389b_wr(sd, 0xbb, 0xff);
512
513 /* Set number of attempts to read the EDID */
514 ad9389b_wr(sd, 0xc9, 0xf);
515 return true;
516}
517
518/* Enable interrupts */
519static void ad9389b_set_isr(struct v4l2_subdev *sd, bool enable)
520{
521 u8 irqs = MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT;
522 u8 irqs_rd;
523 int retries = 100;
524
525 /* The datasheet says that the EDID ready interrupt should be
526 disabled if there is no hotplug. */
527 if (!enable)
528 irqs = 0;
529 else if (ad9389b_have_hotplug(sd))
530 irqs |= MASK_AD9389B_EDID_RDY_INT;
531
532 /*
533 * This i2c write can fail (approx. 1 in 1000 writes). But it
534 * is essential that this register is correct, so retry it
535 * multiple times.
536 *
537 * Note that the i2c write does not report an error, but the readback
538 * clearly shows the wrong value.
539 */
540 do {
541 ad9389b_wr(sd, 0x94, irqs);
542 irqs_rd = ad9389b_rd(sd, 0x94);
543 } while (retries-- && irqs_rd != irqs);
544
545 if (irqs_rd != irqs)
546 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
547}
548
549/* Interrupt handler */
550static int ad9389b_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
551{
552 u8 irq_status;
553
554 /* disable interrupts to prevent a race condition */
555 ad9389b_set_isr(sd, false);
556 irq_status = ad9389b_rd(sd, 0x96);
557 /* clear detected interrupts */
558 ad9389b_wr(sd, 0x96, irq_status);
559
560 if (irq_status & (MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT))
561 ad9389b_check_monitor_present_status(sd);
562 if (irq_status & MASK_AD9389B_EDID_RDY_INT)
563 ad9389b_check_edid_status(sd);
564
565 /* enable interrupts */
566 ad9389b_set_isr(sd, true);
567 *handled = true;
568 return 0;
569}
570
571static const struct v4l2_subdev_core_ops ad9389b_core_ops = {
572 .log_status = ad9389b_log_status,
117a55b6
HV		 573#ifdef CONFIG_VIDEO_ADV_DEBUG
574 .g_register = ad9389b_g_register,
575 .s_register = ad9389b_s_register,
576#endif
577 .s_power = ad9389b_s_power,
578 .interrupt_service_routine = ad9389b_isr,
579};
580
581/* ------------------------------ PAD OPS ------------------------------ */
582
583static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
584{
585 struct ad9389b_state *state = get_ad9389b_state(sd);
586
587 if (edid->pad != 0)
588 return -EINVAL;
589 if (edid->blocks == 0 || edid->blocks > 256)
590 return -EINVAL;
591 if (!edid->edid)
592 return -EINVAL;
593 if (!state->edid.segments) {
594 v4l2_dbg(1, debug, sd, "EDID segment 0 not found\n");
595 return -ENODATA;
596 }
597 if (edid->start_block >= state->edid.segments * 2)
598 return -E2BIG;
599 if (edid->blocks + edid->start_block >= state->edid.segments * 2)
600 edid->blocks = state->edid.segments * 2 - edid->start_block;
601 memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
d3ec7de4 602 128 * edid->blocks);
117a55b6
HV		 603 return 0;
604}
605
606static const struct v4l2_subdev_pad_ops ad9389b_pad_ops = {
607 .get_edid = ad9389b_get_edid,
608};
609
610/* ------------------------------ VIDEO OPS ------------------------------ */
611
612/* Enable/disable ad9389b output */
613static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
614{
615 struct ad9389b_state *state = get_ad9389b_state(sd);
616
617 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
618
619 ad9389b_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
620 if (enable) {
621 ad9389b_check_monitor_present_status(sd);
622 } else {
623 ad9389b_s_power(sd, 0);
624 state->have_monitor = false;
625 }
626 return 0;
627}
628
04164904
HV		 629static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
630 .type = V4L2_DV_BT_656_1120,
8f110d68
GG		 631 /* keep this initialization for compatibility with GCC < 4.4.6 */
632 .reserved = { 0 },
633 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
634 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
04164904 635 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
8f110d68
GG		 636 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
637 V4L2_DV_BT_CAP_CUSTOM)
117a55b6
HV		 638};
639
640static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
641 struct v4l2_dv_timings *timings)
642{
643 struct ad9389b_state *state = get_ad9389b_state(sd);
117a55b6
HV		 644
645 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
646
647 /* quick sanity check */
b8f0fff4 648 if (!v4l2_valid_dv_timings(timings, &ad9389b_timings_cap, NULL, NULL))
117a55b6
HV		 649 return -EINVAL;
650
651 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
04164904 652 if the format is one of the CEA or DMT timings. */
b8f0fff4 653 v4l2_find_dv_timings_cap(timings, &ad9389b_timings_cap, 0, NULL, NULL);
117a55b6
HV		 654
655 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
656
657 /* save timings */
658 state->dv_timings = *timings;
659
660 /* update quantization range based on new dv_timings */
661 ad9389b_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
662
663 /* update PLL gear based on new dv_timings */
664 if (state->pdata.tmds_pll_gear == AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC)
665 ad9389b_set_manual_pll_gear(sd, (u32)timings->bt.pixelclock);
666
667 /* update AVI infoframe */
668 ad9389b_set_IT_content_AVI_InfoFrame(sd);
669
670 return 0;
671}
672
673static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
674 struct v4l2_dv_timings *timings)
675{
676 struct ad9389b_state *state = get_ad9389b_state(sd);
677
678 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
679
680 if (!timings)
681 return -EINVAL;
682
683 *timings = state->dv_timings;
684
685 return 0;
686}
687
688static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
d3ec7de4 689 struct v4l2_enum_dv_timings *timings)
117a55b6 690{
b8f0fff4
HV		 691 return v4l2_enum_dv_timings_cap(timings, &ad9389b_timings_cap,
692 NULL, NULL);
117a55b6
HV		 693}
694
695static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
d3ec7de4 696 struct v4l2_dv_timings_cap *cap)
117a55b6 697{
04164904 698 *cap = ad9389b_timings_cap;
117a55b6
HV		 699 return 0;
700}
701
702static const struct v4l2_subdev_video_ops ad9389b_video_ops = {
703 .s_stream = ad9389b_s_stream,
704 .s_dv_timings = ad9389b_s_dv_timings,
705 .g_dv_timings = ad9389b_g_dv_timings,
706 .enum_dv_timings = ad9389b_enum_dv_timings,
707 .dv_timings_cap = ad9389b_dv_timings_cap,
708};
709
710static int ad9389b_s_audio_stream(struct v4l2_subdev *sd, int enable)
711{
712 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
713
714 if (enable)
715 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x80);
716 else
717 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x40);
718
719 return 0;
720}
721
722static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
723{
724 u32 N;
725
726 switch (freq) {
d3ec7de4
MB		 727 case 32000: N = 4096; break;
728 case 44100: N = 6272; break;
729 case 48000: N = 6144; break;
730 case 88200: N = 12544; break;
731 case 96000: N = 12288; break;
117a55b6
HV		 732 case 176400: N = 25088; break;
733 case 192000: N = 24576; break;
734 default:
d3ec7de4 735 return -EINVAL;
117a55b6
HV		 736 }
737
738 /* Set N (used with CTS to regenerate the audio clock) */
739 ad9389b_wr(sd, 0x01, (N >> 16) & 0xf);
740 ad9389b_wr(sd, 0x02, (N >> 8) & 0xff);
741 ad9389b_wr(sd, 0x03, N & 0xff);
742
743 return 0;
744}
745
746static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
747{
748 u32 i2s_sf;
749
750 switch (freq) {
d3ec7de4
MB		 751 case 32000: i2s_sf = 0x30; break;
752 case 44100: i2s_sf = 0x00; break;
753 case 48000: i2s_sf = 0x20; break;
754 case 88200: i2s_sf = 0x80; break;
755 case 96000: i2s_sf = 0xa0; break;
117a55b6
HV		 756 case 176400: i2s_sf = 0xc0; break;
757 case 192000: i2s_sf = 0xe0; break;
758 default:
d3ec7de4 759 return -EINVAL;
117a55b6
HV		 760 }
761
762 /* Set sampling frequency for I2S audio to 48 kHz */
763 ad9389b_wr_and_or(sd, 0x15, 0xf, i2s_sf);
764
765 return 0;
766}
767
768static int ad9389b_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
769{
770 /* TODO based on input/output/config */
771 /* TODO See datasheet "Programmers guide" p. 39-40 */
772
773 /* Only 2 channels in use for application */
774 ad9389b_wr_and_or(sd, 0x50, 0x1f, 0x20);
775 /* Speaker mapping */
776 ad9389b_wr(sd, 0x51, 0x00);
777
778 /* TODO Where should this be placed? */
779 /* 16 bit audio word length */
780 ad9389b_wr_and_or(sd, 0x14, 0xf0, 0x02);
781
782 return 0;
783}
784
785static const struct v4l2_subdev_audio_ops ad9389b_audio_ops = {
786 .s_stream = ad9389b_s_audio_stream,
787 .s_clock_freq = ad9389b_s_clock_freq,
788 .s_i2s_clock_freq = ad9389b_s_i2s_clock_freq,
789 .s_routing = ad9389b_s_routing,
790};
791
792/* --------------------- SUBDEV OPS --------------------------------------- */
793
794static const struct v4l2_subdev_ops ad9389b_ops = {
795 .core = &ad9389b_core_ops,
796 .video = &ad9389b_video_ops,
797 .audio = &ad9389b_audio_ops,
798 .pad = &ad9389b_pad_ops,
799};
800
801/* ----------------------------------------------------------------------- */
802static void ad9389b_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd,
d3ec7de4 803 int segment, u8 *buf)
117a55b6
HV		 804{
805 int i, j;
806
807 if (debug < lvl)
808 return;
809
810 v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
811 for (i = 0; i < 256; i += 16) {
812 u8 b[128];
813 u8 *bp = b;
814
815 if (i == 128)
816 v4l2_dbg(lvl, debug, sd, "\n");
817 for (j = i; j < i + 16; j++) {
818 sprintf(bp, "0x%02x, ", buf[j]);
819 bp += 6;
820 }
821 bp[0] = '\0';
822 v4l2_dbg(lvl, debug, sd, "%s\n", b);
823 }
824}
825
826static void ad9389b_edid_handler(struct work_struct *work)
827{
828 struct delayed_work *dwork = to_delayed_work(work);
d3ec7de4
MB		 829 struct ad9389b_state *state =
830 container_of(dwork, struct ad9389b_state, edid_handler);
117a55b6
HV		 831 struct v4l2_subdev *sd = &state->sd;
832 struct ad9389b_edid_detect ed;
833
834 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
835
836 if (ad9389b_check_edid_status(sd)) {
837 /* Return if we received the EDID. */
838 return;
839 }
840
841 if (ad9389b_have_hotplug(sd)) {
842 /* We must retry reading the EDID several times, it is possible
843 * that initially the EDID couldn't be read due to i2c errors
844 * (DVI connectors are particularly prone to this problem). */
845 if (state->edid.read_retries) {
846 state->edid.read_retries--;
15edc1cc
MB		 847 v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
848 state->have_monitor = false;
849 ad9389b_s_power(sd, false);
850 ad9389b_s_power(sd, true);
117a55b6 851 queue_delayed_work(state->work_queue,
d3ec7de4 852 &state->edid_handler, EDID_DELAY);
117a55b6
HV		 853 return;
854 }
855 }
856
857 /* We failed to read the EDID, so send an event for this. */
858 ed.present = false;
859 ed.segment = ad9389b_rd(sd, 0xc4);
860 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
861 v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
862}
863
864static void ad9389b_audio_setup(struct v4l2_subdev *sd)
865{
866 v4l2_dbg(1, debug, sd, "%s\n", __func__);
867
868 ad9389b_s_i2s_clock_freq(sd, 48000);
869 ad9389b_s_clock_freq(sd, 48000);
870 ad9389b_s_routing(sd, 0, 0, 0);
871}
872
873/* Initial setup of AD9389b */
874
875/* Configure hdmi transmitter. */
876static void ad9389b_setup(struct v4l2_subdev *sd)
877{
878 struct ad9389b_state *state = get_ad9389b_state(sd);
879
880 v4l2_dbg(1, debug, sd, "%s\n", __func__);
881
882 /* Input format: RGB 4:4:4 */
883 ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);
884 /* Output format: RGB 4:4:4 */
885 ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);
f3b33ede
MR		 886 /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion,
887 Aspect ratio: 16:9 */
888 ad9389b_wr_and_or(sd, 0x17, 0xf9, 0x06);
117a55b6
HV		 889 /* Output format: RGB 4:4:4, Active Format Information is valid. */
890 ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);
891 /* Underscanned */
892 ad9389b_wr_and_or(sd, 0x46, 0x3f, 0x80);
893 /* Setup video format */
894 ad9389b_wr(sd, 0x3c, 0x0);
895 /* Active format aspect ratio: same as picure. */
896 ad9389b_wr(sd, 0x47, 0x80);
897 /* No encryption */
898 ad9389b_wr_and_or(sd, 0xaf, 0xef, 0x0);
899 /* Positive clk edge capture for input video clock */
900 ad9389b_wr_and_or(sd, 0xba, 0x1f, 0x60);
901
902 ad9389b_audio_setup(sd);
903
904 v4l2_ctrl_handler_setup(&state->hdl);
905
906 ad9389b_set_IT_content_AVI_InfoFrame(sd);
907}
908
909static void ad9389b_notify_monitor_detect(struct v4l2_subdev *sd)
910{
911 struct ad9389b_monitor_detect mdt;
912 struct ad9389b_state *state = get_ad9389b_state(sd);
913
914 mdt.present = state->have_monitor;
915 v4l2_subdev_notify(sd, AD9389B_MONITOR_DETECT, (void *)&mdt);
916}
917
918static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd)
919{
920 struct ad9389b_state *state = get_ad9389b_state(sd);
921 /* read hotplug and rx-sense state */
922 u8 status = ad9389b_rd(sd, 0x42);
923
924 v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
925 __func__,
926 status,
927 status & MASK_AD9389B_HPD_DETECT ? ", hotplug" : "",
928 status & MASK_AD9389B_MSEN_DETECT ? ", rx-sense" : "");
929
930 if ((status & MASK_AD9389B_HPD_DETECT) &&
931 ((status & MASK_AD9389B_MSEN_DETECT) || state->edid.segments)) {
932 v4l2_dbg(1, debug, sd,
933 "%s: hotplug and (rx-sense or edid)\n", __func__);
934 if (!state->have_monitor) {
935 v4l2_dbg(1, debug, sd, "%s: monitor detected\n", __func__);
936 state->have_monitor = true;
937 ad9389b_set_isr(sd, true);
938 if (!ad9389b_s_power(sd, true)) {
939 v4l2_dbg(1, debug, sd,
940 "%s: monitor detected, powerup failed\n", __func__);
941 return;
942 }
943 ad9389b_setup(sd);
944 ad9389b_notify_monitor_detect(sd);
945 state->edid.read_retries = EDID_MAX_RETRIES;
946 queue_delayed_work(state->work_queue,
947 &state->edid_handler, EDID_DELAY);
948 }
949 } else if (status & MASK_AD9389B_HPD_DETECT) {
950 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
951 state->edid.read_retries = EDID_MAX_RETRIES;
952 queue_delayed_work(state->work_queue,
953 &state->edid_handler, EDID_DELAY);
954 } else if (!(status & MASK_AD9389B_HPD_DETECT)) {
955 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
956 if (state->have_monitor) {
957 v4l2_dbg(1, debug, sd, "%s: monitor not detected\n", __func__);
958 state->have_monitor = false;
959 ad9389b_notify_monitor_detect(sd);
960 }
961 ad9389b_s_power(sd, false);
962 memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
963 }
964
965 /* update read only ctrls */
966 v4l2_ctrl_s_ctrl(state->hotplug_ctrl, ad9389b_have_hotplug(sd) ? 0x1 : 0x0);
967 v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, ad9389b_have_rx_sense(sd) ? 0x1 : 0x0);
968 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
969}
970
971static bool edid_block_verify_crc(u8 *edid_block)
972{
117a55b6 973 u8 sum = 0;
350a1815 974 int i;
117a55b6 975
350a1815
MB		 976 for (i = 0; i < 128; i++)
977 sum += edid_block[i];
978 return sum == 0;
117a55b6
HV		 979}
980
bafd5d79 981static bool edid_verify_crc(struct v4l2_subdev *sd, u32 segment)
117a55b6
HV		 982{
983 struct ad9389b_state *state = get_ad9389b_state(sd);
984 u32 blocks = state->edid.blocks;
985 u8 *data = state->edid.data;
986
987 if (edid_block_verify_crc(&data[segment * 256])) {
988 if ((segment + 1) * 2 <= blocks)
989 return edid_block_verify_crc(&data[segment * 256 + 128]);
990 return true;
991 }
992 return false;
993}
994
bafd5d79
MR		 995static bool edid_verify_header(struct v4l2_subdev *sd, u32 segment)
996{
997 static const u8 hdmi_header[] = {
998 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
999 };
1000 struct ad9389b_state *state = get_ad9389b_state(sd);
1001 u8 *data = state->edid.data;
1002 int i;
1003
1004 if (segment)
1005 return true;
1006
1007 for (i = 0; i < ARRAY_SIZE(hdmi_header); i++)
1008 if (data[i] != hdmi_header[i])
1009 return false;
1010
1011 return true;
1012}
1013
117a55b6
HV		 1014static bool ad9389b_check_edid_status(struct v4l2_subdev *sd)
1015{
1016 struct ad9389b_state *state = get_ad9389b_state(sd);
1017 struct ad9389b_edid_detect ed;
1018 int segment;
1019 u8 edidRdy = ad9389b_rd(sd, 0xc5);
1020
1021 v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
d3ec7de4 1022 __func__, EDID_MAX_RETRIES - state->edid.read_retries);
117a55b6
HV		 1023
1024 if (!(edidRdy & MASK_AD9389B_EDID_RDY))
1025 return false;
1026
1027 segment = ad9389b_rd(sd, 0xc4);
1028 if (segment >= EDID_MAX_SEGM) {
1029 v4l2_err(sd, "edid segment number too big\n");
1030 return false;
1031 }
1032 v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1033 ad9389b_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1034 ad9389b_dbg_dump_edid(2, debug, sd, segment,
d3ec7de4 1035 &state->edid.data[segment * 256]);
117a55b6
HV		 1036 if (segment == 0) {
1037 state->edid.blocks = state->edid.data[0x7e] + 1;
1038 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
d3ec7de4 1039 __func__, state->edid.blocks);
117a55b6 1040 }
bafd5d79 1041 if (!edid_verify_crc(sd, segment) ||
d3ec7de4 1042 !edid_verify_header(sd, segment)) {
117a55b6 1043 /* edid crc error, force reread of edid segment */
bafd5d79 1044 v4l2_err(sd, "%s: edid crc or header error\n", __func__);
7be4f888 1045 state->have_monitor = false;
117a55b6
HV		 1046 ad9389b_s_power(sd, false);
1047 ad9389b_s_power(sd, true);
1048 return false;
1049 }
1050 /* one more segment read ok */
1051 state->edid.segments = segment + 1;
1052 if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1053 /* Request next EDID segment */
1054 v4l2_dbg(1, debug, sd, "%s: request segment %d\n",
d3ec7de4 1055 __func__, state->edid.segments);
117a55b6
HV		 1056 ad9389b_wr(sd, 0xc9, 0xf);
1057 ad9389b_wr(sd, 0xc4, state->edid.segments);
1058 state->edid.read_retries = EDID_MAX_RETRIES;
1059 queue_delayed_work(state->work_queue,
d3ec7de4 1060 &state->edid_handler, EDID_DELAY);
117a55b6
HV		 1061 return false;
1062 }
1063
1064 /* report when we have all segments but report only for segment 0 */
1065 ed.present = true;
1066 ed.segment = 0;
1067 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
1068 state->edid_detect_counter++;
1069 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1070 return ed.present;
1071}
1072
1073/* ----------------------------------------------------------------------- */
1074
1075static void ad9389b_init_setup(struct v4l2_subdev *sd)
1076{
1077 struct ad9389b_state *state = get_ad9389b_state(sd);
1078 struct ad9389b_state_edid *edid = &state->edid;
1079
1080 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1081
1082 /* clear all interrupts */
1083 ad9389b_wr(sd, 0x96, 0xff);
1084
1085 memset(edid, 0, sizeof(struct ad9389b_state_edid));
1086 state->have_monitor = false;
1087 ad9389b_set_isr(sd, false);
1088}
1089
1090static int ad9389b_probe(struct i2c_client *client, const struct i2c_device_id *id)
1091{
1092 const struct v4l2_dv_timings dv1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
1093 struct ad9389b_state *state;
1094 struct ad9389b_platform_data *pdata = client->dev.platform_data;
1095 struct v4l2_ctrl_handler *hdl;
1096 struct v4l2_subdev *sd;
1097 int err = -EIO;
1098
1099 /* Check if the adapter supports the needed features */
1100 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1101 return -EIO;
1102
1103 v4l_dbg(1, debug, client, "detecting ad9389b client on address 0x%x\n",
d3ec7de4 1104 client->addr << 1);
117a55b6 1105
c02b211d 1106 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
117a55b6
HV		 1107 if (!state)
1108 return -ENOMEM;
1109
1110 /* Platform data */
1111 if (pdata == NULL) {
1112 v4l_err(client, "No platform data!\n");
c02b211d 1113 return -ENODEV;
117a55b6
HV		 1114 }
1115 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1116
1117 sd = &state->sd;
1118 v4l2_i2c_subdev_init(sd, client, &ad9389b_ops);
1119 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1120
1121 hdl = &state->hdl;
1122 v4l2_ctrl_handler_init(hdl, 5);
1123
1124 /* private controls */
1125
1126 state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1127 V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1128 0, V4L2_DV_TX_MODE_DVI_D);
117a55b6
HV		 1129 state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1130 V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
117a55b6
HV		 1131 state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1132 V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
117a55b6
HV		 1133 state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1134 V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
117a55b6
HV		 1135 state->rgb_quantization_range_ctrl =
1136 v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1137 V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1138 0, V4L2_DV_RGB_RANGE_AUTO);
117a55b6
HV		 1139 sd->ctrl_handler = hdl;
1140 if (hdl->error) {
1141 err = hdl->error;
1142
1143 goto err_hdl;
1144 }
265d3b55
HV		 1145 state->hdmi_mode_ctrl->is_private = true;
1146 state->hotplug_ctrl->is_private = true;
1147 state->rx_sense_ctrl->is_private = true;
1148 state->have_edid0_ctrl->is_private = true;
1149 state->rgb_quantization_range_ctrl->is_private = true;
117a55b6
HV		 1150
1151 state->pad.flags = MEDIA_PAD_FL_SINK;
1152 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
1153 if (err)
1154 goto err_hdl;
1155
1156 state->chip_revision = ad9389b_rd(sd, 0x0);
1157 if (state->chip_revision != 2) {
1158 v4l2_err(sd, "chip_revision %d != 2\n", state->chip_revision);
1159 err = -EIO;
1160 goto err_entity;
1161 }
1162 v4l2_dbg(1, debug, sd, "reg 0x41 0x%x, chip version (reg 0x00) 0x%x\n",
d3ec7de4 1163 ad9389b_rd(sd, 0x41), state->chip_revision);
117a55b6
HV		 1164
1165 state->edid_i2c_client = i2c_new_dummy(client->adapter, (0x7e>>1));
1166 if (state->edid_i2c_client == NULL) {
1167 v4l2_err(sd, "failed to register edid i2c client\n");
6ec735df 1168 err = -ENOMEM;
117a55b6
HV		 1169 goto err_entity;
1170 }
1171
1172 state->work_queue = create_singlethread_workqueue(sd->name);
1173 if (state->work_queue == NULL) {
1174 v4l2_err(sd, "could not create workqueue\n");
6ec735df 1175 err = -ENOMEM;
117a55b6
HV		 1176 goto err_unreg;
1177 }
1178
1179 INIT_DELAYED_WORK(&state->edid_handler, ad9389b_edid_handler);
1180 state->dv_timings = dv1080p60;
1181
1182 ad9389b_init_setup(sd);
1183 ad9389b_set_isr(sd, true);
1184
1185 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
d3ec7de4 1186 client->addr << 1, client->adapter->name);
117a55b6
HV		 1187 return 0;
1188
1189err_unreg:
1190 i2c_unregister_device(state->edid_i2c_client);
1191err_entity:
1192 media_entity_cleanup(&sd->entity);
1193err_hdl:
1194 v4l2_ctrl_handler_free(&state->hdl);
117a55b6
HV		 1195 return err;
1196}
1197
1198/* ----------------------------------------------------------------------- */
1199
1200static int ad9389b_remove(struct i2c_client *client)
1201{
1202 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1203 struct ad9389b_state *state = get_ad9389b_state(sd);
1204
1205 state->chip_revision = -1;
1206
1207 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1208 client->addr << 1, client->adapter->name);
1209
1210 ad9389b_s_stream(sd, false);
1211 ad9389b_s_audio_stream(sd, false);
1212 ad9389b_init_setup(sd);
1213 cancel_delayed_work(&state->edid_handler);
1214 i2c_unregister_device(state->edid_i2c_client);
1215 destroy_workqueue(state->work_queue);
1216 v4l2_device_unregister_subdev(sd);
1217 media_entity_cleanup(&sd->entity);
1218 v4l2_ctrl_handler_free(sd->ctrl_handler);
117a55b6
HV		 1219 return 0;
1220}
1221
1222/* ----------------------------------------------------------------------- */
1223
1224static struct i2c_device_id ad9389b_id[] = {
e1277110
HV		 1225 { "ad9389b", 0 },
1226 { "ad9889b", 0 },
117a55b6
HV		 1227 { }
1228};
1229MODULE_DEVICE_TABLE(i2c, ad9389b_id);
1230
1231static struct i2c_driver ad9389b_driver = {
1232 .driver = {
1233 .owner = THIS_MODULE,
1234 .name = "ad9389b",
1235 },
1236 .probe = ad9389b_probe,
1237 .remove = ad9389b_remove,
1238 .id_table = ad9389b_id,
1239};
1240
1241module_i2c_driver(ad9389b_driver);
Linux kernel - Deliverables
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