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Merge tag 'topic/drm-fixes-2015-07-16' of git://anongit.freedesktop.org/drm-intel...
[deliverable/linux.git] / drivers / media / i2c / adv7842.c
CommitLineData
a89bcd4c
HV		 1/*
2 * adv7842 - Analog Devices ADV7842 video decoder driver
3 *
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
5b64b205
MR		 23 * REF_01 - Analog devices, ADV7842,
24 * Register Settings Recommendations, Rev. 1.9, April 2011
7de6fab1
MR		 25 * REF_02 - Analog devices, Software User Guide, UG-206,
26 * ADV7842 I2C Register Maps, Rev. 0, November 2010
5b64b205
MR		 27 * REF_03 - Analog devices, Hardware User Guide, UG-214,
28 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
29 * Decoder and Digitizer , Rev. 0, January 2011
a89bcd4c
HV		 30 */
31
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/slab.h>
36#include <linux/i2c.h>
37#include <linux/delay.h>
38#include <linux/videodev2.h>
39#include <linux/workqueue.h>
40#include <linux/v4l2-dv-timings.h>
09f90c53 41#include <linux/hdmi.h>
a89bcd4c
HV		 42#include <media/v4l2-device.h>
43#include <media/v4l2-ctrls.h>
44#include <media/v4l2-dv-timings.h>
45#include <media/adv7842.h>
46
47static int debug;
48module_param(debug, int, 0644);
49MODULE_PARM_DESC(debug, "debug level (0-2)");
50
51MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
52MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
53MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
54MODULE_LICENSE("GPL");
55
56/* ADV7842 system clock frequency */
57#define ADV7842_fsc (28636360)
58
f888ae7e
HV		 59#define ADV7842_RGB_OUT (1 << 1)
60
61#define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0)
62#define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0)
63#define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0)
64
65#define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5)
66#define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5)
67#define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5)
68#define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5)
69#define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5)
70#define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5)
71
72#define ADV7842_OP_CH_SEL_GBR (0 << 5)
73#define ADV7842_OP_CH_SEL_GRB (1 << 5)
74#define ADV7842_OP_CH_SEL_BGR (2 << 5)
75#define ADV7842_OP_CH_SEL_RGB (3 << 5)
76#define ADV7842_OP_CH_SEL_BRG (4 << 5)
77#define ADV7842_OP_CH_SEL_RBG (5 << 5)
78
79#define ADV7842_OP_SWAP_CB_CR (1 << 0)
80
a89bcd4c
HV		 81/*
82**********************************************************************
83*
84* Arrays with configuration parameters for the ADV7842
85*
86**********************************************************************
87*/
88
f888ae7e
HV		 89struct adv7842_format_info {
90 u32 code;
91 u8 op_ch_sel;
92 bool rgb_out;
93 bool swap_cb_cr;
94 u8 op_format_sel;
95};
96
a89bcd4c 97struct adv7842_state {
7de5be44 98 struct adv7842_platform_data pdata;
a89bcd4c
HV		 99 struct v4l2_subdev sd;
100 struct media_pad pad;
101 struct v4l2_ctrl_handler hdl;
102 enum adv7842_mode mode;
103 struct v4l2_dv_timings timings;
104 enum adv7842_vid_std_select vid_std_select;
f888ae7e
HV		 105
106 const struct adv7842_format_info *format;
107
a89bcd4c
HV		 108 v4l2_std_id norm;
109 struct {
110 u8 edid[256];
111 u32 present;
112 } hdmi_edid;
113 struct {
114 u8 edid[256];
115 u32 present;
116 } vga_edid;
117 struct v4l2_fract aspect_ratio;
118 u32 rgb_quantization_range;
119 bool is_cea_format;
120 struct workqueue_struct *work_queues;
121 struct delayed_work delayed_work_enable_hotplug;
6e9071f2 122 bool restart_stdi_once;
a89bcd4c
HV		 123 bool hdmi_port_a;
124
125 /* i2c clients */
126 struct i2c_client *i2c_sdp_io;
127 struct i2c_client *i2c_sdp;
128 struct i2c_client *i2c_cp;
129 struct i2c_client *i2c_vdp;
130 struct i2c_client *i2c_afe;
131 struct i2c_client *i2c_hdmi;
132 struct i2c_client *i2c_repeater;
133 struct i2c_client *i2c_edid;
134 struct i2c_client *i2c_infoframe;
135 struct i2c_client *i2c_cec;
136 struct i2c_client *i2c_avlink;
137
138 /* controls */
139 struct v4l2_ctrl *detect_tx_5v_ctrl;
140 struct v4l2_ctrl *analog_sampling_phase_ctrl;
141 struct v4l2_ctrl *free_run_color_ctrl_manual;
142 struct v4l2_ctrl *free_run_color_ctrl;
143 struct v4l2_ctrl *rgb_quantization_range_ctrl;
144};
145
146/* Unsupported timings. This device cannot support 720p30. */
147static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
148 V4L2_DV_BT_CEA_1280X720P30,
149 { }
150};
151
152static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
153{
154 int i;
155
156 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
157 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
158 return false;
159 return true;
160}
161
162struct adv7842_video_standards {
163 struct v4l2_dv_timings timings;
164 u8 vid_std;
165 u8 v_freq;
166};
167
168/* sorted by number of lines */
169static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
170 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
171 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
172 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
173 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
174 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
175 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
176 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
177 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
178 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
179 /* TODO add 1920x1080P60_RB (CVT timing) */
180 { },
181};
182
183/* sorted by number of lines */
184static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
185 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
186 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
187 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
188 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
189 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
190 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
191 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
192 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
193 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
194 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
195 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
196 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
197 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
198 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
199 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
200 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
201 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
202 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
203 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
204 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
205 /* TODO add 1600X1200P60_RB (not a DMT timing) */
206 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
207 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
208 { },
209};
210
211/* sorted by number of lines */
212static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
213 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
214 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
215 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
216 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
217 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
218 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
219 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
220 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
221 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
222 { },
223};
224
225/* sorted by number of lines */
226static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
227 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
228 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
229 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
230 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
231 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
232 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
233 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
234 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
235 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
236 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
237 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
238 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
239 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
240 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
241 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
242 { },
243};
244
48519838
HV		 245static const struct v4l2_event adv7842_ev_fmt = {
246 .type = V4L2_EVENT_SOURCE_CHANGE,
247 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
248};
249
a89bcd4c
HV		 250/* ----------------------------------------------------------------------- */
251
252static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
253{
254 return container_of(sd, struct adv7842_state, sd);
255}
256
257static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
258{
259 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
260}
261
f888ae7e
HV		 262static inline unsigned hblanking(const struct v4l2_bt_timings *t)
263{
264 return V4L2_DV_BT_BLANKING_WIDTH(t);
265}
266
a89bcd4c
HV		 267static inline unsigned htotal(const struct v4l2_bt_timings *t)
268{
269 return V4L2_DV_BT_FRAME_WIDTH(t);
270}
271
f888ae7e
HV		 272static inline unsigned vblanking(const struct v4l2_bt_timings *t)
273{
274 return V4L2_DV_BT_BLANKING_HEIGHT(t);
275}
276
a89bcd4c
HV		 277static inline unsigned vtotal(const struct v4l2_bt_timings *t)
278{
279 return V4L2_DV_BT_FRAME_HEIGHT(t);
280}
281
282
283/* ----------------------------------------------------------------------- */
284
285static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
286 u8 command, bool check)
287{
288 union i2c_smbus_data data;
289
290 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
291 I2C_SMBUS_READ, command,
292 I2C_SMBUS_BYTE_DATA, &data))
293 return data.byte;
294 if (check)
295 v4l_err(client, "error reading %02x, %02x\n",
296 client->addr, command);
297 return -EIO;
298}
299
300static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
301{
302 int i;
303
304 for (i = 0; i < 3; i++) {
305 int ret = adv_smbus_read_byte_data_check(client, command, true);
306
307 if (ret >= 0) {
308 if (i)
309 v4l_err(client, "read ok after %d retries\n", i);
310 return ret;
311 }
312 }
313 v4l_err(client, "read failed\n");
314 return -EIO;
315}
316
317static s32 adv_smbus_write_byte_data(struct i2c_client *client,
318 u8 command, u8 value)
319{
320 union i2c_smbus_data data;
321 int err;
322 int i;
323
324 data.byte = value;
325 for (i = 0; i < 3; i++) {
326 err = i2c_smbus_xfer(client->adapter, client->addr,
327 client->flags,
328 I2C_SMBUS_WRITE, command,
329 I2C_SMBUS_BYTE_DATA, &data);
330 if (!err)
331 break;
332 }
333 if (err < 0)
334 v4l_err(client, "error writing %02x, %02x, %02x\n",
335 client->addr, command, value);
336 return err;
337}
338
339static void adv_smbus_write_byte_no_check(struct i2c_client *client,
340 u8 command, u8 value)
341{
342 union i2c_smbus_data data;
343 data.byte = value;
344
345 i2c_smbus_xfer(client->adapter, client->addr,
346 client->flags,
347 I2C_SMBUS_WRITE, command,
348 I2C_SMBUS_BYTE_DATA, &data);
349}
350
351static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
352 u8 command, unsigned length, const u8 *values)
353{
354 union i2c_smbus_data data;
355
356 if (length > I2C_SMBUS_BLOCK_MAX)
357 length = I2C_SMBUS_BLOCK_MAX;
358 data.block[0] = length;
359 memcpy(data.block + 1, values, length);
360 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
361 I2C_SMBUS_WRITE, command,
362 I2C_SMBUS_I2C_BLOCK_DATA, &data);
363}
364
365/* ----------------------------------------------------------------------- */
366
367static inline int io_read(struct v4l2_subdev *sd, u8 reg)
368{
369 struct i2c_client *client = v4l2_get_subdevdata(sd);
370
371 return adv_smbus_read_byte_data(client, reg);
372}
373
374static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
375{
376 struct i2c_client *client = v4l2_get_subdevdata(sd);
377
378 return adv_smbus_write_byte_data(client, reg, val);
379}
380
381static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
382{
383 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
384}
385
f888ae7e
HV		 386static inline int io_write_clr_set(struct v4l2_subdev *sd,
387 u8 reg, u8 mask, u8 val)
388{
389 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
390}
391
a89bcd4c
HV		 392static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
393{
394 struct adv7842_state *state = to_state(sd);
395
396 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
397}
398
399static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
400{
401 struct adv7842_state *state = to_state(sd);
402
403 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
404}
405
406static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
407{
408 struct adv7842_state *state = to_state(sd);
409
410 return adv_smbus_read_byte_data(state->i2c_cec, reg);
411}
412
413static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
414{
415 struct adv7842_state *state = to_state(sd);
416
417 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
418}
419
420static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
421{
422 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
423}
424
425static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
426{
427 struct adv7842_state *state = to_state(sd);
428
429 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
430}
431
432static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
433{
434 struct adv7842_state *state = to_state(sd);
435
436 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
437}
438
439static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
440{
441 struct adv7842_state *state = to_state(sd);
442
443 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
444}
445
446static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
447{
448 struct adv7842_state *state = to_state(sd);
449
450 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
451}
452
453static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
454{
455 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
456}
457
458static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
459{
460 struct adv7842_state *state = to_state(sd);
461
462 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
463}
464
465static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
466{
467 struct adv7842_state *state = to_state(sd);
468
469 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
470}
471
472static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
473{
474 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
475}
476
477static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
478{
479 struct adv7842_state *state = to_state(sd);
480
481 return adv_smbus_read_byte_data(state->i2c_afe, reg);
482}
483
484static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
485{
486 struct adv7842_state *state = to_state(sd);
487
488 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
489}
490
491static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
492{
493 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
494}
495
496static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
497{
498 struct adv7842_state *state = to_state(sd);
499
500 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
501}
502
503static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
504{
505 struct adv7842_state *state = to_state(sd);
506
507 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
508}
509
510static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
511{
512 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
513}
514
515static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
516{
517 struct adv7842_state *state = to_state(sd);
518
519 return adv_smbus_read_byte_data(state->i2c_edid, reg);
520}
521
522static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
523{
524 struct adv7842_state *state = to_state(sd);
525
526 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
527}
528
529static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
530{
531 struct adv7842_state *state = to_state(sd);
532
533 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
534}
535
536static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
537{
538 struct adv7842_state *state = to_state(sd);
539
540 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
541}
542
5b64b205
MR		 543static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
544{
545 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
546}
547
a89bcd4c
HV		 548static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
549{
550 struct adv7842_state *state = to_state(sd);
551
552 return adv_smbus_read_byte_data(state->i2c_cp, reg);
553}
554
555static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
556{
557 struct adv7842_state *state = to_state(sd);
558
559 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
560}
561
562static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
563{
564 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
565}
566
567static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
568{
569 struct adv7842_state *state = to_state(sd);
570
571 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
572}
573
574static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
575{
576 struct adv7842_state *state = to_state(sd);
577
578 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
579}
580
581static void main_reset(struct v4l2_subdev *sd)
582{
583 struct i2c_client *client = v4l2_get_subdevdata(sd);
584
585 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
586
587 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
588
84aeed53 589 mdelay(5);
a89bcd4c
HV		 590}
591
f888ae7e
HV		 592/* -----------------------------------------------------------------------------
593 * Format helpers
594 */
595
596static const struct adv7842_format_info adv7842_formats[] = {
597 { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false,
598 ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT },
599 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false,
600 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
601 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true,
602 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
603 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false,
604 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
605 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true,
606 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
607 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false,
608 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
609 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true,
610 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
611 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false,
612 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
613 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true,
614 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
615 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false,
616 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
617 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true,
618 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
619 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false,
620 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
621 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true,
622 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
623 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false,
624 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
625 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true,
626 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
627 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false,
628 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
629 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true,
630 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
631 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false,
632 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
633 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true,
634 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
635};
636
637static const struct adv7842_format_info *
638adv7842_format_info(struct adv7842_state *state, u32 code)
639{
640 unsigned int i;
641
642 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) {
643 if (adv7842_formats[i].code == code)
644 return &adv7842_formats[i];
645 }
646
647 return NULL;
648}
649
a89bcd4c
HV		 650/* ----------------------------------------------------------------------- */
651
933913da
MB		 652static inline bool is_analog_input(struct v4l2_subdev *sd)
653{
654 struct adv7842_state *state = to_state(sd);
655
656 return ((state->mode == ADV7842_MODE_RGB) ||
657 (state->mode == ADV7842_MODE_COMP));
658}
659
a89bcd4c
HV		 660static inline bool is_digital_input(struct v4l2_subdev *sd)
661{
662 struct adv7842_state *state = to_state(sd);
663
664 return state->mode == ADV7842_MODE_HDMI;
665}
666
667static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
668 .type = V4L2_DV_BT_656_1120,
9b51f175
GG		 669 /* keep this initialization for compatibility with GCC < 4.4.6 */
670 .reserved = { 0 },
671 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
672 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
a89bcd4c 673 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
9b51f175
GG		 674 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
675 V4L2_DV_BT_CAP_CUSTOM)
a89bcd4c
HV		 676};
677
678static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
679 .type = V4L2_DV_BT_656_1120,
9b51f175
GG		 680 /* keep this initialization for compatibility with GCC < 4.4.6 */
681 .reserved = { 0 },
682 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
683 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
a89bcd4c 684 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
9b51f175
GG		 685 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
686 V4L2_DV_BT_CAP_CUSTOM)
a89bcd4c
HV		 687};
688
689static inline const struct v4l2_dv_timings_cap *
690adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
691{
692 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
693 &adv7842_timings_cap_analog;
694}
695
696/* ----------------------------------------------------------------------- */
697
698static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
699{
700 struct delayed_work *dwork = to_delayed_work(work);
701 struct adv7842_state *state = container_of(dwork,
702 struct adv7842_state, delayed_work_enable_hotplug);
703 struct v4l2_subdev *sd = &state->sd;
704 int present = state->hdmi_edid.present;
705 u8 mask = 0;
706
707 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
708 __func__, present);
709
7de6fab1
MR		 710 if (present & (0x04 << ADV7842_EDID_PORT_A))
711 mask |= 0x20;
712 if (present & (0x04 << ADV7842_EDID_PORT_B))
713 mask |= 0x10;
a89bcd4c
HV		 714 io_write_and_or(sd, 0x20, 0xcf, mask);
715}
716
717static int edid_write_vga_segment(struct v4l2_subdev *sd)
718{
719 struct i2c_client *client = v4l2_get_subdevdata(sd);
720 struct adv7842_state *state = to_state(sd);
721 const u8 *val = state->vga_edid.edid;
722 int err = 0;
723 int i;
724
725 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
726
727 /* HPA disable on port A and B */
728 io_write_and_or(sd, 0x20, 0xcf, 0x00);
729
730 /* Disable I2C access to internal EDID ram from VGA DDC port */
731 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
732
733 /* edid segment pointer '1' for VGA port */
734 rep_write_and_or(sd, 0x77, 0xef, 0x10);
735
736 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
737 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
738 I2C_SMBUS_BLOCK_MAX, val + i);
739 if (err)
740 return err;
741
742 /* Calculates the checksums and enables I2C access
743 * to internal EDID ram from VGA DDC port.
744 */
745 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
746
747 for (i = 0; i < 1000; i++) {
748 if (rep_read(sd, 0x79) & 0x20)
749 break;
750 mdelay(1);
751 }
752 if (i == 1000) {
753 v4l_err(client, "error enabling edid on VGA port\n");
754 return -EIO;
755 }
756
757 /* enable hotplug after 200 ms */
758 queue_delayed_work(state->work_queues,
759 &state->delayed_work_enable_hotplug, HZ / 5);
760
761 return 0;
762}
763
764static int edid_spa_location(const u8 *edid)
765{
766 u8 d;
767
768 /*
769 * TODO, improve and update for other CEA extensions
770 * currently only for 1 segment (256 bytes),
771 * i.e. 1 extension block and CEA revision 3.
772 */
773 if ((edid[0x7e] != 1) ||
774 (edid[0x80] != 0x02) ||
775 (edid[0x81] != 0x03)) {
776 return -EINVAL;
777 }
778 /*
779 * search Vendor Specific Data Block (tag 3)
780 */
781 d = edid[0x82] & 0x7f;
782 if (d > 4) {
783 int i = 0x84;
784 int end = 0x80 + d;
785 do {
786 u8 tag = edid[i]>>5;
787 u8 len = edid[i] & 0x1f;
788
789 if ((tag == 3) && (len >= 5))
790 return i + 4;
791 i += len + 1;
792 } while (i < end);
793 }
794 return -EINVAL;
795}
796
797static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
798{
799 struct i2c_client *client = v4l2_get_subdevdata(sd);
800 struct adv7842_state *state = to_state(sd);
801 const u8 *val = state->hdmi_edid.edid;
a89bcd4c
HV		 802 int spa_loc = edid_spa_location(val);
803 int err = 0;
804 int i;
805
7de6fab1
MR		 806 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n",
807 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc);
a89bcd4c
HV		 808
809 /* HPA disable on port A and B */
810 io_write_and_or(sd, 0x20, 0xcf, 0x00);
811
812 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
813 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
814
fc2e991e
MB		 815 if (!state->hdmi_edid.present)
816 return 0;
817
a89bcd4c
HV		 818 /* edid segment pointer '0' for HDMI ports */
819 rep_write_and_or(sd, 0x77, 0xef, 0x00);
820
821 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
822 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
823 I2C_SMBUS_BLOCK_MAX, val + i);
824 if (err)
825 return err;
826
7de6fab1
MR		 827 if (spa_loc < 0)
828 spa_loc = 0xc0; /* Default value [REF_02, p. 199] */
829
830 if (port == ADV7842_EDID_PORT_A) {
831 rep_write(sd, 0x72, val[spa_loc]);
832 rep_write(sd, 0x73, val[spa_loc + 1]);
a89bcd4c 833 } else {
7de6fab1
MR		 834 rep_write(sd, 0x74, val[spa_loc]);
835 rep_write(sd, 0x75, val[spa_loc + 1]);
a89bcd4c 836 }
7de6fab1
MR		 837 rep_write(sd, 0x76, spa_loc & 0xff);
838 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
a89bcd4c
HV		 839
840 /* Calculates the checksums and enables I2C access to internal
841 * EDID ram from HDMI DDC ports
842 */
7de6fab1 843 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
a89bcd4c
HV		 844
845 for (i = 0; i < 1000; i++) {
7de6fab1 846 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
a89bcd4c
HV		 847 break;
848 mdelay(1);
849 }
850 if (i == 1000) {
7de6fab1
MR		 851 v4l_err(client, "error enabling edid on port %c\n",
852 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
a89bcd4c
HV		 853 return -EIO;
854 }
855
856 /* enable hotplug after 200 ms */
857 queue_delayed_work(state->work_queues,
858 &state->delayed_work_enable_hotplug, HZ / 5);
859
860 return 0;
861}
862
863/* ----------------------------------------------------------------------- */
864
865#ifdef CONFIG_VIDEO_ADV_DEBUG
866static void adv7842_inv_register(struct v4l2_subdev *sd)
867{
868 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
869 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
870 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
871 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
872 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
873 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
874 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
875 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
876 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
877 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
878 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
879 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
880}
881
882static int adv7842_g_register(struct v4l2_subdev *sd,
883 struct v4l2_dbg_register *reg)
884{
885 reg->size = 1;
886 switch (reg->reg >> 8) {
887 case 0:
888 reg->val = io_read(sd, reg->reg & 0xff);
889 break;
890 case 1:
891 reg->val = avlink_read(sd, reg->reg & 0xff);
892 break;
893 case 2:
894 reg->val = cec_read(sd, reg->reg & 0xff);
895 break;
896 case 3:
897 reg->val = infoframe_read(sd, reg->reg & 0xff);
898 break;
899 case 4:
900 reg->val = sdp_io_read(sd, reg->reg & 0xff);
901 break;
902 case 5:
903 reg->val = sdp_read(sd, reg->reg & 0xff);
904 break;
905 case 6:
906 reg->val = afe_read(sd, reg->reg & 0xff);
907 break;
908 case 7:
909 reg->val = rep_read(sd, reg->reg & 0xff);
910 break;
911 case 8:
912 reg->val = edid_read(sd, reg->reg & 0xff);
913 break;
914 case 9:
915 reg->val = hdmi_read(sd, reg->reg & 0xff);
916 break;
917 case 0xa:
918 reg->val = cp_read(sd, reg->reg & 0xff);
919 break;
920 case 0xb:
921 reg->val = vdp_read(sd, reg->reg & 0xff);
922 break;
923 default:
924 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
925 adv7842_inv_register(sd);
926 break;
927 }
928 return 0;
929}
930
931static int adv7842_s_register(struct v4l2_subdev *sd,
932 const struct v4l2_dbg_register *reg)
933{
934 u8 val = reg->val & 0xff;
935
936 switch (reg->reg >> 8) {
937 case 0:
938 io_write(sd, reg->reg & 0xff, val);
939 break;
940 case 1:
941 avlink_write(sd, reg->reg & 0xff, val);
942 break;
943 case 2:
944 cec_write(sd, reg->reg & 0xff, val);
945 break;
946 case 3:
947 infoframe_write(sd, reg->reg & 0xff, val);
948 break;
949 case 4:
950 sdp_io_write(sd, reg->reg & 0xff, val);
951 break;
952 case 5:
953 sdp_write(sd, reg->reg & 0xff, val);
954 break;
955 case 6:
956 afe_write(sd, reg->reg & 0xff, val);
957 break;
958 case 7:
959 rep_write(sd, reg->reg & 0xff, val);
960 break;
961 case 8:
962 edid_write(sd, reg->reg & 0xff, val);
963 break;
964 case 9:
965 hdmi_write(sd, reg->reg & 0xff, val);
966 break;
967 case 0xa:
968 cp_write(sd, reg->reg & 0xff, val);
969 break;
970 case 0xb:
971 vdp_write(sd, reg->reg & 0xff, val);
972 break;
973 default:
974 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
975 adv7842_inv_register(sd);
976 break;
977 }
978 return 0;
979}
980#endif
981
982static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
983{
984 struct adv7842_state *state = to_state(sd);
985 int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
986 u8 reg_io_6f = io_read(sd, 0x6f);
987 int val = 0;
988
989 if (reg_io_6f & 0x02)
990 val |= 1; /* port A */
991 if (reg_io_6f & 0x01)
992 val |= 2; /* port B */
993
994 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
995
996 if (val != prev)
997 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
998 return 0;
999}
1000
1001static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
1002 u8 prim_mode,
1003 const struct adv7842_video_standards *predef_vid_timings,
1004 const struct v4l2_dv_timings *timings)
1005{
1006 int i;
1007
1008 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
1009 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
1010 is_digital_input(sd) ? 250000 : 1000000))
1011 continue;
1012 /* video std */
1013 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
1014 /* v_freq and prim mode */
1015 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
1016 return 0;
1017 }
1018
1019 return -1;
1020}
1021
1022static int configure_predefined_video_timings(struct v4l2_subdev *sd,
1023 struct v4l2_dv_timings *timings)
1024{
1025 struct adv7842_state *state = to_state(sd);
1026 int err;
1027
1028 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1029
1030 /* reset to default values */
1031 io_write(sd, 0x16, 0x43);
1032 io_write(sd, 0x17, 0x5a);
1033 /* disable embedded syncs for auto graphics mode */
1034 cp_write_and_or(sd, 0x81, 0xef, 0x00);
1035 cp_write(sd, 0x26, 0x00);
1036 cp_write(sd, 0x27, 0x00);
1037 cp_write(sd, 0x28, 0x00);
1038 cp_write(sd, 0x29, 0x00);
6251e65f 1039 cp_write(sd, 0x8f, 0x40);
a89bcd4c
HV		 1040 cp_write(sd, 0x90, 0x00);
1041 cp_write(sd, 0xa5, 0x00);
1042 cp_write(sd, 0xa6, 0x00);
1043 cp_write(sd, 0xa7, 0x00);
1044 cp_write(sd, 0xab, 0x00);
1045 cp_write(sd, 0xac, 0x00);
1046
1047 switch (state->mode) {
1048 case ADV7842_MODE_COMP:
1049 case ADV7842_MODE_RGB:
1050 err = find_and_set_predefined_video_timings(sd,
1051 0x01, adv7842_prim_mode_comp, timings);
1052 if (err)
1053 err = find_and_set_predefined_video_timings(sd,
1054 0x02, adv7842_prim_mode_gr, timings);
1055 break;
1056 case ADV7842_MODE_HDMI:
1057 err = find_and_set_predefined_video_timings(sd,
1058 0x05, adv7842_prim_mode_hdmi_comp, timings);
1059 if (err)
1060 err = find_and_set_predefined_video_timings(sd,
1061 0x06, adv7842_prim_mode_hdmi_gr, timings);
1062 break;
1063 default:
1064 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1065 __func__, state->mode);
1066 err = -1;
1067 break;
1068 }
1069
1070
1071 return err;
1072}
1073
1074static void configure_custom_video_timings(struct v4l2_subdev *sd,
1075 const struct v4l2_bt_timings *bt)
1076{
1077 struct adv7842_state *state = to_state(sd);
1078 struct i2c_client *client = v4l2_get_subdevdata(sd);
1079 u32 width = htotal(bt);
1080 u32 height = vtotal(bt);
1081 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1082 u16 cp_start_eav = width - bt->hfrontporch;
1083 u16 cp_start_vbi = height - bt->vfrontporch + 1;
1084 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
1085 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1086 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1087 const u8 pll[2] = {
1088 0xc0 | ((width >> 8) & 0x1f),
1089 width & 0xff
1090 };
1091
1092 v4l2_dbg(2, debug, sd, "%s\n", __func__);
1093
1094 switch (state->mode) {
1095 case ADV7842_MODE_COMP:
1096 case ADV7842_MODE_RGB:
1097 /* auto graphics */
1098 io_write(sd, 0x00, 0x07); /* video std */
1099 io_write(sd, 0x01, 0x02); /* prim mode */
1100 /* enable embedded syncs for auto graphics mode */
1101 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1102
1103 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1104 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1105 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1106 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
1107 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1108 break;
1109 }
1110
1111 /* active video - horizontal timing */
1112 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1113 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1114 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1115 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1116
1117 /* active video - vertical timing */
1118 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1119 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1120 ((cp_end_vbi >> 8) & 0xf));
1121 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1122 break;
1123 case ADV7842_MODE_HDMI:
1124 /* set default prim_mode/vid_std for HDMI
39c1cb2b 1125 according to [REF_03, c. 4.2] */
a89bcd4c
HV		 1126 io_write(sd, 0x00, 0x02); /* video std */
1127 io_write(sd, 0x01, 0x06); /* prim mode */
1128 break;
1129 default:
1130 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1131 __func__, state->mode);
1132 break;
1133 }
1134
1135 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1136 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1137 cp_write(sd, 0xab, (height >> 4) & 0xff);
1138 cp_write(sd, 0xac, (height & 0x0f) << 4);
1139}
1140
933913da
MB		 1141static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1142{
1143 struct adv7842_state *state = to_state(sd);
1144 u8 offset_buf[4];
1145
1146 if (auto_offset) {
1147 offset_a = 0x3ff;
1148 offset_b = 0x3ff;
1149 offset_c = 0x3ff;
1150 }
1151
1152 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1153 __func__, auto_offset ? "Auto" : "Manual",
1154 offset_a, offset_b, offset_c);
1155
1156 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1157 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1158 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1159 offset_buf[3] = offset_c & 0x0ff;
1160
1161 /* Registers must be written in this order with no i2c access in between */
1162 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
1163 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1164}
1165
1166static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1167{
1168 struct adv7842_state *state = to_state(sd);
1169 u8 gain_buf[4];
1170 u8 gain_man = 1;
1171 u8 agc_mode_man = 1;
1172
1173 if (auto_gain) {
1174 gain_man = 0;
1175 agc_mode_man = 0;
1176 gain_a = 0x100;
1177 gain_b = 0x100;
1178 gain_c = 0x100;
1179 }
1180
1181 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1182 __func__, auto_gain ? "Auto" : "Manual",
1183 gain_a, gain_b, gain_c);
1184
1185 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1186 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1187 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1188 gain_buf[3] = ((gain_c & 0x0ff));
1189
1190 /* Registers must be written in this order with no i2c access in between */
1191 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
1192 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1193}
1194
a89bcd4c
HV		 1195static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1196{
1197 struct adv7842_state *state = to_state(sd);
933913da
MB		 1198 bool rgb_output = io_read(sd, 0x02) & 0x02;
1199 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1200
1201 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1202 __func__, state->rgb_quantization_range,
1203 rgb_output, hdmi_signal);
a89bcd4c 1204
933913da
MB		 1205 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
1206 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
69e9ba6f 1207
a89bcd4c
HV		 1208 switch (state->rgb_quantization_range) {
1209 case V4L2_DV_RGB_RANGE_AUTO:
69e9ba6f
HV		 1210 if (state->mode == ADV7842_MODE_RGB) {
1211 /* Receiving analog RGB signal
1212 * Set RGB full range (0-255) */
1213 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1214 break;
1215 }
1216
1217 if (state->mode == ADV7842_MODE_COMP) {
1218 /* Receiving analog YPbPr signal
1219 * Set automode */
1220 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1221 break;
1222 }
1223
933913da 1224 if (hdmi_signal) {
69e9ba6f
HV		 1225 /* Receiving HDMI signal
1226 * Set automode */
a89bcd4c 1227 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
69e9ba6f
HV		 1228 break;
1229 }
1230
1231 /* Receiving DVI-D signal
1232 * ADV7842 selects RGB limited range regardless of
1233 * input format (CE/IT) in automatic mode */
680fee04 1234 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
69e9ba6f
HV		 1235 /* RGB limited range (16-235) */
1236 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1237 } else {
1238 /* RGB full range (0-255) */
1239 io_write_and_or(sd, 0x02, 0x0f, 0x10);
933913da
MB		 1240
1241 if (is_digital_input(sd) && rgb_output) {
1242 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1243 } else {
1244 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1245 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1246 }
a89bcd4c
HV		 1247 }
1248 break;
1249 case V4L2_DV_RGB_RANGE_LIMITED:
69e9ba6f
HV		 1250 if (state->mode == ADV7842_MODE_COMP) {
1251 /* YCrCb limited range (16-235) */
1252 io_write_and_or(sd, 0x02, 0x0f, 0x20);
933913da 1253 break;
69e9ba6f 1254 }
933913da
MB		 1255
1256 /* RGB limited range (16-235) */
1257 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1258
a89bcd4c
HV		 1259 break;
1260 case V4L2_DV_RGB_RANGE_FULL:
69e9ba6f
HV		 1261 if (state->mode == ADV7842_MODE_COMP) {
1262 /* YCrCb full range (0-255) */
1263 io_write_and_or(sd, 0x02, 0x0f, 0x60);
933913da
MB		 1264 break;
1265 }
1266
1267 /* RGB full range (0-255) */
1268 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1269
1270 if (is_analog_input(sd) || hdmi_signal)
1271 break;
1272
1273 /* Adjust gain/offset for DVI-D signals only */
1274 if (rgb_output) {
1275 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
69e9ba6f 1276 } else {
933913da
MB		 1277 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1278 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
69e9ba6f 1279 }
a89bcd4c
HV		 1280 break;
1281 }
1282}
1283
1284static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1285{
1286 struct v4l2_subdev *sd = to_sd(ctrl);
1287 struct adv7842_state *state = to_state(sd);
1288
1289 /* TODO SDP ctrls
1290 contrast/brightness/hue/free run is acting a bit strange,
1291 not sure if sdp csc is correct.
1292 */
1293 switch (ctrl->id) {
1294 /* standard ctrls */
1295 case V4L2_CID_BRIGHTNESS:
1296 cp_write(sd, 0x3c, ctrl->val);
1297 sdp_write(sd, 0x14, ctrl->val);
1298 /* ignore lsb sdp 0x17[3:2] */
1299 return 0;
1300 case V4L2_CID_CONTRAST:
1301 cp_write(sd, 0x3a, ctrl->val);
1302 sdp_write(sd, 0x13, ctrl->val);
1303 /* ignore lsb sdp 0x17[1:0] */
1304 return 0;
1305 case V4L2_CID_SATURATION:
1306 cp_write(sd, 0x3b, ctrl->val);
1307 sdp_write(sd, 0x15, ctrl->val);
1308 /* ignore lsb sdp 0x17[5:4] */
1309 return 0;
1310 case V4L2_CID_HUE:
1311 cp_write(sd, 0x3d, ctrl->val);
1312 sdp_write(sd, 0x16, ctrl->val);
1313 /* ignore lsb sdp 0x17[7:6] */
1314 return 0;
1315 /* custom ctrls */
1316 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1317 afe_write(sd, 0xc8, ctrl->val);
1318 return 0;
1319 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1320 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1321 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1322 return 0;
1323 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1324 u8 R = (ctrl->val & 0xff0000) >> 16;
1325 u8 G = (ctrl->val & 0x00ff00) >> 8;
1326 u8 B = (ctrl->val & 0x0000ff);
1327 /* RGB -> YUV, numerical approximation */
1328 int Y = 66 * R + 129 * G + 25 * B;
1329 int U = -38 * R - 74 * G + 112 * B;
1330 int V = 112 * R - 94 * G - 18 * B;
1331
1332 /* Scale down to 8 bits with rounding */
1333 Y = (Y + 128) >> 8;
1334 U = (U + 128) >> 8;
1335 V = (V + 128) >> 8;
1336 /* make U,V positive */
1337 Y += 16;
1338 U += 128;
1339 V += 128;
1340
1341 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1342 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1343
1344 /* CP */
1345 cp_write(sd, 0xc1, R);
1346 cp_write(sd, 0xc0, G);
1347 cp_write(sd, 0xc2, B);
1348 /* SDP */
1349 sdp_write(sd, 0xde, Y);
1350 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1351 return 0;
1352 }
1353 case V4L2_CID_DV_RX_RGB_RANGE:
1354 state->rgb_quantization_range = ctrl->val;
1355 set_rgb_quantization_range(sd);
1356 return 0;
1357 }
1358 return -EINVAL;
1359}
1360
1361static inline bool no_power(struct v4l2_subdev *sd)
1362{
1363 return io_read(sd, 0x0c) & 0x24;
1364}
1365
1366static inline bool no_cp_signal(struct v4l2_subdev *sd)
1367{
1368 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1369}
1370
1371static inline bool is_hdmi(struct v4l2_subdev *sd)
1372{
1373 return hdmi_read(sd, 0x05) & 0x80;
1374}
1375
1376static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1377{
1378 struct adv7842_state *state = to_state(sd);
1379
1380 *status = 0;
1381
1382 if (io_read(sd, 0x0c) & 0x24)
1383 *status |= V4L2_IN_ST_NO_POWER;
1384
1385 if (state->mode == ADV7842_MODE_SDP) {
1386 /* status from SDP block */
1387 if (!(sdp_read(sd, 0x5A) & 0x01))
1388 *status |= V4L2_IN_ST_NO_SIGNAL;
1389
1390 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1391 __func__, *status);
1392 return 0;
1393 }
1394 /* status from CP block */
1395 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1396 !(cp_read(sd, 0xb1) & 0x80))
1397 /* TODO channel 2 */
1398 *status |= V4L2_IN_ST_NO_SIGNAL;
1399
1400 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1401 *status |= V4L2_IN_ST_NO_SIGNAL;
1402
1403 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1404 __func__, *status);
1405
1406 return 0;
1407}
1408
1409struct stdi_readback {
1410 u16 bl, lcf, lcvs;
1411 u8 hs_pol, vs_pol;
1412 bool interlaced;
1413};
1414
1415static int stdi2dv_timings(struct v4l2_subdev *sd,
1416 struct stdi_readback *stdi,
1417 struct v4l2_dv_timings *timings)
1418{
1419 struct adv7842_state *state = to_state(sd);
1420 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1421 u32 pix_clk;
1422 int i;
1423
1424 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1425 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1426
1427 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1428 adv7842_get_dv_timings_cap(sd),
1429 adv7842_check_dv_timings, NULL))
1430 continue;
1431 if (vtotal(bt) != stdi->lcf + 1)
1432 continue;
1433 if (bt->vsync != stdi->lcvs)
1434 continue;
1435
1436 pix_clk = hfreq * htotal(bt);
1437
1438 if ((pix_clk < bt->pixelclock + 1000000) &&
1439 (pix_clk > bt->pixelclock - 1000000)) {
1440 *timings = v4l2_dv_timings_presets[i];
1441 return 0;
1442 }
1443 }
1444
1445 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1446 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1447 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1448 false, timings))
a89bcd4c
HV		 1449 return 0;
1450 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1451 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1452 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1453 false, state->aspect_ratio, timings))
a89bcd4c
HV		 1454 return 0;
1455
1456 v4l2_dbg(2, debug, sd,
1457 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1458 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1459 stdi->hs_pol, stdi->vs_pol);
1460 return -1;
1461}
1462
1463static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1464{
1465 u32 status;
1466
1467 adv7842_g_input_status(sd, &status);
1468 if (status & V4L2_IN_ST_NO_SIGNAL) {
1469 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1470 return -ENOLINK;
1471 }
1472
1473 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1474 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1475 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1476
1477 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1478 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1479 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1480 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1481 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1482 } else {
1483 stdi->hs_pol = 'x';
1484 stdi->vs_pol = 'x';
1485 }
1486 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1487
1488 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1489 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1490 return -ENOLINK;
1491 }
1492
1493 v4l2_dbg(2, debug, sd,
1494 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1495 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1496 stdi->hs_pol, stdi->vs_pol,
1497 stdi->interlaced ? "interlaced" : "progressive");
1498
1499 return 0;
1500}
1501
1502static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1503 struct v4l2_enum_dv_timings *timings)
1504{
c916194c
LP		 1505 if (timings->pad != 0)
1506 return -EINVAL;
1507
a89bcd4c
HV		 1508 return v4l2_enum_dv_timings_cap(timings,
1509 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1510}
1511
1512static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1513 struct v4l2_dv_timings_cap *cap)
1514{
c916194c
LP		 1515 if (cap->pad != 0)
1516 return -EINVAL;
1517
a89bcd4c
HV		 1518 *cap = *adv7842_get_dv_timings_cap(sd);
1519 return 0;
1520}
1521
1522/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
69e9ba6f 1523 if the format is listed in adv7842_timings[] */
a89bcd4c
HV		 1524static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1525 struct v4l2_dv_timings *timings)
1526{
1527 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1528 is_digital_input(sd) ? 250000 : 1000000,
1529 adv7842_check_dv_timings, NULL);
1530}
1531
1532static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1533 struct v4l2_dv_timings *timings)
1534{
1535 struct adv7842_state *state = to_state(sd);
1536 struct v4l2_bt_timings *bt = &timings->bt;
1537 struct stdi_readback stdi = { 0 };
1538
e78d834a
MB		 1539 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1540
f8789e6d
HV		 1541 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1542
a89bcd4c
HV		 1543 /* SDP block */
1544 if (state->mode == ADV7842_MODE_SDP)
1545 return -ENODATA;
1546
1547 /* read STDI */
1548 if (read_stdi(sd, &stdi)) {
6e9071f2 1549 state->restart_stdi_once = true;
a89bcd4c
HV		 1550 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1551 return -ENOLINK;
1552 }
1553 bt->interlaced = stdi.interlaced ?
1554 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
f888ae7e
HV		 1555 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1556 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
a89bcd4c
HV		 1557
1558 if (is_digital_input(sd)) {
28a769f1 1559 u32 freq;
e78d834a
MB		 1560
1561 timings->type = V4L2_DV_BT_656_1120;
6e9071f2 1562
e78d834a
MB		 1563 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1564 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
81ba0a4e
MB		 1565 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
1566 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
a89bcd4c
HV		 1567 if (is_hdmi(sd)) {
1568 /* adjust for deep color mode */
81ba0a4e 1569 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
a89bcd4c 1570 }
e78d834a
MB		 1571 bt->pixelclock = freq;
1572 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
a89bcd4c 1573 hdmi_read(sd, 0x21);
e78d834a 1574 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
a89bcd4c 1575 hdmi_read(sd, 0x23);
e78d834a 1576 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
a89bcd4c 1577 hdmi_read(sd, 0x25);
e78d834a
MB		 1578 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1579 hdmi_read(sd, 0x2b)) / 2;
1580 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1581 hdmi_read(sd, 0x2f)) / 2;
1582 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1583 hdmi_read(sd, 0x33)) / 2;
1584 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1585 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1586 if (bt->interlaced == V4L2_DV_INTERLACED) {
1587 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1588 hdmi_read(sd, 0x0c);
1589 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1590 hdmi_read(sd, 0x2d)) / 2;
1591 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1592 hdmi_read(sd, 0x31)) / 2;
f8789e6d 1593 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
e78d834a 1594 hdmi_read(sd, 0x35)) / 2;
f888ae7e
HV		 1595 } else {
1596 bt->il_vfrontporch = 0;
1597 bt->il_vsync = 0;
1598 bt->il_vbackporch = 0;
e78d834a
MB		 1599 }
1600 adv7842_fill_optional_dv_timings_fields(sd, timings);
a89bcd4c 1601 } else {
6e9071f2
MB		 1602 /* find format
1603 * Since LCVS values are inaccurate [REF_03, p. 339-340],
1604 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1605 */
1606 if (!stdi2dv_timings(sd, &stdi, timings))
1607 goto found;
1608 stdi.lcvs += 1;
1609 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1610 if (!stdi2dv_timings(sd, &stdi, timings))
1611 goto found;
1612 stdi.lcvs -= 2;
1613 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
a89bcd4c 1614 if (stdi2dv_timings(sd, &stdi, timings)) {
6e9071f2
MB		 1615 /*
1616 * The STDI block may measure wrong values, especially
1617 * for lcvs and lcf. If the driver can not find any
1618 * valid timing, the STDI block is restarted to measure
1619 * the video timings again. The function will return an
1620 * error, but the restart of STDI will generate a new
1621 * STDI interrupt and the format detection process will
1622 * restart.
1623 */
1624 if (state->restart_stdi_once) {
1625 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1626 /* TODO restart STDI for Sync Channel 2 */
1627 /* enter one-shot mode */
1628 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1629 /* trigger STDI restart */
1630 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1631 /* reset to continuous mode */
1632 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1633 state->restart_stdi_once = false;
1634 return -ENOLINK;
1635 }
a89bcd4c
HV		 1636 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1637 return -ERANGE;
1638 }
6e9071f2 1639 state->restart_stdi_once = true;
a89bcd4c 1640 }
6e9071f2 1641found:
a89bcd4c
HV		 1642
1643 if (debug > 1)
6e9071f2
MB		 1644 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1645 timings, true);
a89bcd4c
HV		 1646 return 0;
1647}
1648
1649static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1650 struct v4l2_dv_timings *timings)
1651{
1652 struct adv7842_state *state = to_state(sd);
1653 struct v4l2_bt_timings *bt;
1654 int err;
1655
e78d834a
MB		 1656 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1657
a89bcd4c
HV		 1658 if (state->mode == ADV7842_MODE_SDP)
1659 return -ENODATA;
1660
834a8be1
MB		 1661 if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1662 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1663 return 0;
1664 }
1665
a89bcd4c
HV		 1666 bt = &timings->bt;
1667
1668 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1669 adv7842_check_dv_timings, NULL))
1670 return -ERANGE;
1671
1672 adv7842_fill_optional_dv_timings_fields(sd, timings);
1673
1674 state->timings = *timings;
1675
6251e65f 1676 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
a89bcd4c
HV		 1677
1678 /* Use prim_mode and vid_std when available */
1679 err = configure_predefined_video_timings(sd, timings);
1680 if (err) {
1681 /* custom settings when the video format
1682 does not have prim_mode/vid_std */
1683 configure_custom_video_timings(sd, bt);
1684 }
1685
1686 set_rgb_quantization_range(sd);
1687
1688
1689 if (debug > 1)
1690 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1691 timings, true);
1692 return 0;
1693}
1694
1695static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1696 struct v4l2_dv_timings *timings)
1697{
1698 struct adv7842_state *state = to_state(sd);
1699
1700 if (state->mode == ADV7842_MODE_SDP)
1701 return -ENODATA;
1702 *timings = state->timings;
1703 return 0;
1704}
1705
1706static void enable_input(struct v4l2_subdev *sd)
1707{
1708 struct adv7842_state *state = to_state(sd);
69e9ba6f
HV		 1709
1710 set_rgb_quantization_range(sd);
a89bcd4c
HV		 1711 switch (state->mode) {
1712 case ADV7842_MODE_SDP:
1713 case ADV7842_MODE_COMP:
1714 case ADV7842_MODE_RGB:
a89bcd4c
HV		 1715 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1716 break;
1717 case ADV7842_MODE_HDMI:
a89bcd4c
HV		 1718 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1719 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
5b64b205 1720 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
a89bcd4c
HV		 1721 break;
1722 default:
1723 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1724 __func__, state->mode);
1725 break;
1726 }
1727}
1728
1729static void disable_input(struct v4l2_subdev *sd)
1730{
5b64b205
MR		 1731 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1732 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
a89bcd4c 1733 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
a89bcd4c
HV		 1734 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1735}
1736
1737static void sdp_csc_coeff(struct v4l2_subdev *sd,
1738 const struct adv7842_sdp_csc_coeff *c)
1739{
1740 /* csc auto/manual */
1741 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1742
1743 if (!c->manual)
1744 return;
1745
1746 /* csc scaling */
1747 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1748
1749 /* A coeff */
1750 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1751 sdp_io_write(sd, 0xe1, c->A1);
1752 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1753 sdp_io_write(sd, 0xe3, c->A2);
1754 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1755 sdp_io_write(sd, 0xe5, c->A3);
1756
1757 /* A scale */
1758 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1759 sdp_io_write(sd, 0xe7, c->A4);
1760
1761 /* B coeff */
1762 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1763 sdp_io_write(sd, 0xe9, c->B1);
1764 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1765 sdp_io_write(sd, 0xeb, c->B2);
1766 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1767 sdp_io_write(sd, 0xed, c->B3);
1768
1769 /* B scale */
1770 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1771 sdp_io_write(sd, 0xef, c->B4);
1772
1773 /* C coeff */
1774 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1775 sdp_io_write(sd, 0xf1, c->C1);
1776 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1777 sdp_io_write(sd, 0xf3, c->C2);
1778 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1779 sdp_io_write(sd, 0xf5, c->C3);
1780
1781 /* C scale */
1782 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1783 sdp_io_write(sd, 0xf7, c->C4);
1784}
1785
1786static void select_input(struct v4l2_subdev *sd,
1787 enum adv7842_vid_std_select vid_std_select)
1788{
1789 struct adv7842_state *state = to_state(sd);
1790
1791 switch (state->mode) {
1792 case ADV7842_MODE_SDP:
1793 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1794 io_write(sd, 0x01, 0); /* prim mode */
1795 /* enable embedded syncs for auto graphics mode */
1796 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1797
1798 afe_write(sd, 0x00, 0x00); /* power up ADC */
1799 afe_write(sd, 0xc8, 0x00); /* phase control */
1800
a89bcd4c
HV		 1801 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1802 /* script says register 0xde, which don't exist in manual */
1803
1804 /* Manual analog input muxing mode, CVBS (6.4)*/
1805 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1806 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1807 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1808 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1809 } else {
1810 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1811 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1812 }
1813 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1814 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1815
1816 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1817 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1818
1819 /* SDP recommended settings */
1820 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1821 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1822
1823 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1824 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1825 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1826 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1827 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1828 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1829 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1830
1831 /* deinterlacer enabled and 3D comb */
1832 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1833
a89bcd4c
HV		 1834 break;
1835
1836 case ADV7842_MODE_COMP:
1837 case ADV7842_MODE_RGB:
1838 /* Automatic analog input muxing mode */
1839 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1840 /* set mode and select free run resolution */
1841 io_write(sd, 0x00, vid_std_select); /* video std */
1842 io_write(sd, 0x01, 0x02); /* prim mode */
1843 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1844 for auto graphics mode */
1845
1846 afe_write(sd, 0x00, 0x00); /* power up ADC */
1847 afe_write(sd, 0xc8, 0x00); /* phase control */
69e9ba6f
HV		 1848 if (state->mode == ADV7842_MODE_COMP) {
1849 /* force to YCrCb */
1850 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1851 } else {
1852 /* force to RGB */
1853 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1854 }
a89bcd4c
HV		 1855
1856 /* set ADI recommended settings for digitizer */
1857 /* "ADV7842 Register Settings Recommendations
1858 * (rev. 1.8, November 2010)" p. 9. */
1859 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1860 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1861
1862 /* set to default gain for RGB */
1863 cp_write(sd, 0x73, 0x10);
1864 cp_write(sd, 0x74, 0x04);
1865 cp_write(sd, 0x75, 0x01);
1866 cp_write(sd, 0x76, 0x00);
1867
1868 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1869 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1870 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1871 break;
1872
1873 case ADV7842_MODE_HDMI:
1874 /* Automatic analog input muxing mode */
1875 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1876 /* set mode and select free run resolution */
1877 if (state->hdmi_port_a)
1878 hdmi_write(sd, 0x00, 0x02); /* select port A */
1879 else
1880 hdmi_write(sd, 0x00, 0x03); /* select port B */
1881 io_write(sd, 0x00, vid_std_select); /* video std */
1882 io_write(sd, 0x01, 5); /* prim mode */
1883 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1884 for auto graphics mode */
1885
1886 /* set ADI recommended settings for HDMI: */
1887 /* "ADV7842 Register Settings Recommendations
1888 * (rev. 1.8, November 2010)" p. 3. */
1889 hdmi_write(sd, 0xc0, 0x00);
1890 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1891 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1892 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1893 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1894 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1895 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1896 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1897 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1898 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1899 Improve robustness */
1900 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1901 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1902 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1903 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1904 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1905 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1906 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1907 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1908 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1909 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1910
1911 afe_write(sd, 0x00, 0xff); /* power down ADC */
1912 afe_write(sd, 0xc8, 0x40); /* phase control */
1913
1914 /* set to default gain for HDMI */
1915 cp_write(sd, 0x73, 0x10);
1916 cp_write(sd, 0x74, 0x04);
1917 cp_write(sd, 0x75, 0x01);
1918 cp_write(sd, 0x76, 0x00);
1919
1920 /* reset ADI recommended settings for digitizer */
1921 /* "ADV7842 Register Settings Recommendations
1922 * (rev. 2.5, June 2010)" p. 17. */
1923 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1924 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
933913da
MB		 1925 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1926
a89bcd4c
HV		 1927 /* CP coast control */
1928 cp_write(sd, 0xc3, 0x33); /* Component mode */
1929
1930 /* color space conversion, autodetect color space */
1931 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1932 break;
1933
1934 default:
1935 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1936 __func__, state->mode);
1937 break;
1938 }
1939}
1940
1941static int adv7842_s_routing(struct v4l2_subdev *sd,
1942 u32 input, u32 output, u32 config)
1943{
1944 struct adv7842_state *state = to_state(sd);
1945
1946 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1947
1948 switch (input) {
1949 case ADV7842_SELECT_HDMI_PORT_A:
a89bcd4c
HV		 1950 state->mode = ADV7842_MODE_HDMI;
1951 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1952 state->hdmi_port_a = true;
1953 break;
1954 case ADV7842_SELECT_HDMI_PORT_B:
a89bcd4c
HV		 1955 state->mode = ADV7842_MODE_HDMI;
1956 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1957 state->hdmi_port_a = false;
1958 break;
1959 case ADV7842_SELECT_VGA_COMP:
69e9ba6f
HV		 1960 state->mode = ADV7842_MODE_COMP;
1961 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1962 break;
a89bcd4c
HV		 1963 case ADV7842_SELECT_VGA_RGB:
1964 state->mode = ADV7842_MODE_RGB;
1965 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1966 break;
1967 case ADV7842_SELECT_SDP_CVBS:
1968 state->mode = ADV7842_MODE_SDP;
1969 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1970 break;
1971 case ADV7842_SELECT_SDP_YC:
1972 state->mode = ADV7842_MODE_SDP;
1973 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1974 break;
1975 default:
1976 return -EINVAL;
1977 }
1978
1979 disable_input(sd);
1980 select_input(sd, state->vid_std_select);
1981 enable_input(sd);
1982
48519838
HV		 1983 v4l2_subdev_notify(sd, V4L2_DEVICE_NOTIFY_EVENT,
1984 (void *)&adv7842_ev_fmt);
a89bcd4c
HV		 1985
1986 return 0;
1987}
1988
ebcff5fc
HV		 1989static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,
1990 struct v4l2_subdev_pad_config *cfg,
1991 struct v4l2_subdev_mbus_code_enum *code)
a89bcd4c 1992{
f888ae7e 1993 if (code->index >= ARRAY_SIZE(adv7842_formats))
a89bcd4c 1994 return -EINVAL;
f888ae7e 1995 code->code = adv7842_formats[code->index].code;
a89bcd4c
HV		 1996 return 0;
1997}
1998
f888ae7e
HV		 1999static void adv7842_fill_format(struct adv7842_state *state,
2000 struct v4l2_mbus_framefmt *format)
2001{
2002 memset(format, 0, sizeof(*format));
2003
2004 format->width = state->timings.bt.width;
2005 format->height = state->timings.bt.height;
2006 format->field = V4L2_FIELD_NONE;
2007 format->colorspace = V4L2_COLORSPACE_SRGB;
2008
2009 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
2010 format->colorspace = (state->timings.bt.height <= 576) ?
2011 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
2012}
2013
2014/*
2015 * Compute the op_ch_sel value required to obtain on the bus the component order
2016 * corresponding to the selected format taking into account bus reordering
2017 * applied by the board at the output of the device.
2018 *
2019 * The following table gives the op_ch_value from the format component order
2020 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
2021 * adv7842_bus_order value in row).
2022 *
2023 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
2024 * ----------+-------------------------------------------------
2025 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
2026 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
2027 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
2028 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
2029 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
2030 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
2031 */
2032static unsigned int adv7842_op_ch_sel(struct adv7842_state *state)
2033{
2034#define _SEL(a, b, c, d, e, f) { \
2035 ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \
2036 ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f }
2037#define _BUS(x) [ADV7842_BUS_ORDER_##x]
2038
2039 static const unsigned int op_ch_sel[6][6] = {
2040 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
2041 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
2042 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
2043 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
2044 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
2045 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
2046 };
2047
2048 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
2049}
2050
2051static void adv7842_setup_format(struct adv7842_state *state)
2052{
2053 struct v4l2_subdev *sd = &state->sd;
2054
2055 io_write_clr_set(sd, 0x02, 0x02,
2056 state->format->rgb_out ? ADV7842_RGB_OUT : 0);
2057 io_write(sd, 0x03, state->format->op_format_sel |
2058 state->pdata.op_format_mode_sel);
2059 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));
2060 io_write_clr_set(sd, 0x05, 0x01,
2061 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0);
2062}
2063
2064static int adv7842_get_format(struct v4l2_subdev *sd,
2065 struct v4l2_subdev_pad_config *cfg,
2066 struct v4l2_subdev_format *format)
a89bcd4c
HV		 2067{
2068 struct adv7842_state *state = to_state(sd);
2069
f888ae7e 2070 if (format->pad != ADV7842_PAD_SOURCE)
da298c6d
HV		 2071 return -EINVAL;
2072
a89bcd4c
HV		 2073 if (state->mode == ADV7842_MODE_SDP) {
2074 /* SPD block */
f888ae7e 2075 if (!(sdp_read(sd, 0x5a) & 0x01))
a89bcd4c 2076 return -EINVAL;
f888ae7e
HV		 2077 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8;
2078 format->format.width = 720;
a89bcd4c
HV		 2079 /* valid signal */
2080 if (state->norm & V4L2_STD_525_60)
f888ae7e 2081 format->format.height = 480;
a89bcd4c 2082 else
f888ae7e
HV		 2083 format->format.height = 576;
2084 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
a89bcd4c
HV		 2085 return 0;
2086 }
2087
f888ae7e
HV		 2088 adv7842_fill_format(state, &format->format);
2089
2090 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2091 struct v4l2_mbus_framefmt *fmt;
2092
2093 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2094 format->format.code = fmt->code;
2095 } else {
2096 format->format.code = state->format->code;
a89bcd4c 2097 }
f888ae7e
HV		 2098
2099 return 0;
2100}
2101
2102static int adv7842_set_format(struct v4l2_subdev *sd,
2103 struct v4l2_subdev_pad_config *cfg,
2104 struct v4l2_subdev_format *format)
2105{
2106 struct adv7842_state *state = to_state(sd);
2107 const struct adv7842_format_info *info;
2108
2109 if (format->pad != ADV7842_PAD_SOURCE)
2110 return -EINVAL;
2111
2112 if (state->mode == ADV7842_MODE_SDP)
2113 return adv7842_get_format(sd, cfg, format);
2114
2115 info = adv7842_format_info(state, format->format.code);
2116 if (info == NULL)
2117 info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2118
2119 adv7842_fill_format(state, &format->format);
2120 format->format.code = info->code;
2121
2122 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2123 struct v4l2_mbus_framefmt *fmt;
2124
2125 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2126 fmt->code = format->format.code;
2127 } else {
2128 state->format = info;
2129 adv7842_setup_format(state);
2130 }
2131
a89bcd4c
HV		 2132 return 0;
2133}
2134
2135static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
2136{
2137 if (enable) {
2138 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
2139 io_write(sd, 0x46, 0x9c);
2140 /* ESDP_50HZ_DET interrupt */
2141 io_write(sd, 0x5a, 0x10);
2142 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
2143 io_write(sd, 0x73, 0x03);
2144 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2145 io_write(sd, 0x78, 0x03);
2146 /* Enable SDP Standard Detection Change and SDP Video Detected */
2147 io_write(sd, 0xa0, 0x09);
019aa8be
MB		 2148 /* Enable HDMI_MODE interrupt */
2149 io_write(sd, 0x69, 0x08);
a89bcd4c
HV		 2150 } else {
2151 io_write(sd, 0x46, 0x0);
2152 io_write(sd, 0x5a, 0x0);
2153 io_write(sd, 0x73, 0x0);
2154 io_write(sd, 0x78, 0x0);
2155 io_write(sd, 0xa0, 0x0);
019aa8be 2156 io_write(sd, 0x69, 0x0);
a89bcd4c
HV		 2157 }
2158}
2159
2160static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2161{
2162 struct adv7842_state *state = to_state(sd);
2163 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
019aa8be 2164 u8 irq_status[6];
a89bcd4c 2165
c9f1f271 2166 adv7842_irq_enable(sd, false);
a89bcd4c
HV		 2167
2168 /* read status */
2169 irq_status[0] = io_read(sd, 0x43);
2170 irq_status[1] = io_read(sd, 0x57);
2171 irq_status[2] = io_read(sd, 0x70);
2172 irq_status[3] = io_read(sd, 0x75);
2173 irq_status[4] = io_read(sd, 0x9d);
019aa8be 2174 irq_status[5] = io_read(sd, 0x66);
a89bcd4c
HV		 2175
2176 /* and clear */
2177 if (irq_status[0])
2178 io_write(sd, 0x44, irq_status[0]);
2179 if (irq_status[1])
2180 io_write(sd, 0x58, irq_status[1]);
2181 if (irq_status[2])
2182 io_write(sd, 0x71, irq_status[2]);
2183 if (irq_status[3])
2184 io_write(sd, 0x76, irq_status[3]);
2185 if (irq_status[4])
2186 io_write(sd, 0x9e, irq_status[4]);
019aa8be
MB		 2187 if (irq_status[5])
2188 io_write(sd, 0x67, irq_status[5]);
a89bcd4c 2189
c9f1f271
MB		 2190 adv7842_irq_enable(sd, true);
2191
019aa8be 2192 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
a89bcd4c 2193 irq_status[0], irq_status[1], irq_status[2],
019aa8be 2194 irq_status[3], irq_status[4], irq_status[5]);
a89bcd4c
HV		 2195
2196 /* format change CP */
2197 fmt_change_cp = irq_status[0] & 0x9c;
2198
2199 /* format change SDP */
2200 if (state->mode == ADV7842_MODE_SDP)
2201 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
2202 else
2203 fmt_change_sdp = 0;
2204
2205 /* digital format CP */
2206 if (is_digital_input(sd))
2207 fmt_change_digital = irq_status[3] & 0x03;
2208 else
2209 fmt_change_digital = 0;
2210
019aa8be 2211 /* format change */
a89bcd4c
HV		 2212 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
2213 v4l2_dbg(1, debug, sd,
2214 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
2215 __func__, fmt_change_cp, fmt_change_digital,
2216 fmt_change_sdp);
48519838
HV		 2217 v4l2_subdev_notify(sd, V4L2_DEVICE_NOTIFY_EVENT,
2218 (void *)&adv7842_ev_fmt);
019aa8be
MB		 2219 if (handled)
2220 *handled = true;
a89bcd4c
HV		 2221 }
2222
019aa8be
MB		 2223 /* HDMI/DVI mode */
2224 if (irq_status[5] & 0x08) {
2225 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2226 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
5046f26b 2227 set_rgb_quantization_range(sd);
019aa8be
MB		 2228 if (handled)
2229 *handled = true;
2230 }
a89bcd4c 2231
019aa8be
MB		 2232 /* tx 5v detect */
2233 if (irq_status[2] & 0x3) {
2234 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
2235 adv7842_s_detect_tx_5v_ctrl(sd);
2236 if (handled)
2237 *handled = true;
2238 }
a89bcd4c
HV		 2239 return 0;
2240}
2241
b09dfac8 2242static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
245b2b67
MB		 2243{
2244 struct adv7842_state *state = to_state(sd);
2245 u8 *data = NULL;
2246
c909e5ba 2247 memset(edid->reserved, 0, sizeof(edid->reserved));
245b2b67
MB		 2248
2249 switch (edid->pad) {
2250 case ADV7842_EDID_PORT_A:
2251 case ADV7842_EDID_PORT_B:
2252 if (state->hdmi_edid.present & (0x04 << edid->pad))
2253 data = state->hdmi_edid.edid;
2254 break;
2255 case ADV7842_EDID_PORT_VGA:
2256 if (state->vga_edid.present)
2257 data = state->vga_edid.edid;
2258 break;
2259 default:
2260 return -EINVAL;
2261 }
c909e5ba
HV		 2262
2263 if (edid->start_block == 0 && edid->blocks == 0) {
2264 edid->blocks = data ? 2 : 0;
2265 return 0;
2266 }
2267
245b2b67
MB		 2268 if (!data)
2269 return -ENODATA;
2270
c909e5ba
HV		 2271 if (edid->start_block >= 2)
2272 return -EINVAL;
2273
2274 if (edid->start_block + edid->blocks > 2)
2275 edid->blocks = 2 - edid->start_block;
2276
2277 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2278
245b2b67
MB		 2279 return 0;
2280}
2281
b09dfac8 2282static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
a89bcd4c
HV		 2283{
2284 struct adv7842_state *state = to_state(sd);
2285 int err = 0;
2286
c909e5ba
HV		 2287 memset(e->reserved, 0, sizeof(e->reserved));
2288
7de6fab1 2289 if (e->pad > ADV7842_EDID_PORT_VGA)
a89bcd4c
HV		 2290 return -EINVAL;
2291 if (e->start_block != 0)
2292 return -EINVAL;
c909e5ba
HV		 2293 if (e->blocks > 2) {
2294 e->blocks = 2;
a89bcd4c 2295 return -E2BIG;
c909e5ba 2296 }
a89bcd4c
HV		 2297
2298 /* todo, per edid */
2299 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
2300 e->edid[0x16]);
2301
7de6fab1
MR		 2302 switch (e->pad) {
2303 case ADV7842_EDID_PORT_VGA:
a89bcd4c
HV		 2304 memset(&state->vga_edid.edid, 0, 256);
2305 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
2306 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
2307 err = edid_write_vga_segment(sd);
7de6fab1
MR		 2308 break;
2309 case ADV7842_EDID_PORT_A:
2310 case ADV7842_EDID_PORT_B:
a89bcd4c
HV		 2311 memset(&state->hdmi_edid.edid, 0, 256);
2312 if (e->blocks)
7de6fab1 2313 state->hdmi_edid.present |= 0x04 << e->pad;
a89bcd4c 2314 else
7de6fab1
MR		 2315 state->hdmi_edid.present &= ~(0x04 << e->pad);
2316 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
a89bcd4c 2317 err = edid_write_hdmi_segment(sd, e->pad);
7de6fab1
MR		 2318 break;
2319 default:
2320 return -EINVAL;
a89bcd4c
HV		 2321 }
2322 if (err < 0)
2323 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2324 return err;
2325}
2326
09f90c53
MB		 2327struct adv7842_cfg_read_infoframe {
2328 const char *desc;
2329 u8 present_mask;
2330 u8 head_addr;
2331 u8 payload_addr;
a89bcd4c
HV		 2332};
2333
09f90c53 2334static void log_infoframe(struct v4l2_subdev *sd, struct adv7842_cfg_read_infoframe *cri)
a89bcd4c
HV		 2335{
2336 int i;
28a769f1 2337 u8 buffer[32];
09f90c53
MB		 2338 union hdmi_infoframe frame;
2339 u8 len;
2340 struct i2c_client *client = v4l2_get_subdevdata(sd);
2341 struct device *dev = &client->dev;
a89bcd4c 2342
09f90c53
MB		 2343 if (!(io_read(sd, 0x60) & cri->present_mask)) {
2344 v4l2_info(sd, "%s infoframe not received\n", cri->desc);
a89bcd4c
HV		 2345 return;
2346 }
2347
09f90c53
MB		 2348 for (i = 0; i < 3; i++)
2349 buffer[i] = infoframe_read(sd, cri->head_addr + i);
a89bcd4c 2350
09f90c53 2351 len = buffer[2] + 1;
a89bcd4c 2352
09f90c53
MB		 2353 if (len + 3 > sizeof(buffer)) {
2354 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
a89bcd4c 2355 return;
09f90c53 2356 }
a89bcd4c 2357
09f90c53
MB		 2358 for (i = 0; i < len; i++)
2359 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);
a89bcd4c 2360
09f90c53
MB		 2361 if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
2362 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
2363 return;
2364 }
a89bcd4c 2365
09f90c53
MB		 2366 hdmi_infoframe_log(KERN_INFO, dev, &frame);
2367}
a89bcd4c 2368
09f90c53
MB		 2369static void adv7842_log_infoframes(struct v4l2_subdev *sd)
2370{
2371 int i;
2372 struct adv7842_cfg_read_infoframe cri[] = {
2373 { "AVI", 0x01, 0xe0, 0x00 },
2374 { "Audio", 0x02, 0xe3, 0x1c },
2375 { "SDP", 0x04, 0xe6, 0x2a },
2376 { "Vendor", 0x10, 0xec, 0x54 }
2377 };
a89bcd4c 2378
09f90c53
MB		 2379 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2380 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2381 return;
2382 }
2383
2384 for (i = 0; i < ARRAY_SIZE(cri); i++)
2385 log_infoframe(sd, &cri[i]);
a89bcd4c
HV		 2386}
2387
2388static const char * const prim_mode_txt[] = {
2389 "SDP",
2390 "Component",
2391 "Graphics",
2392 "Reserved",
2393 "CVBS & HDMI AUDIO",
2394 "HDMI-Comp",
2395 "HDMI-GR",
2396 "Reserved",
2397 "Reserved",
2398 "Reserved",
2399 "Reserved",
2400 "Reserved",
2401 "Reserved",
2402 "Reserved",
2403 "Reserved",
2404 "Reserved",
2405};
2406
2407static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2408{
2409 /* SDP (Standard definition processor) block */
28a769f1 2410 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
a89bcd4c
HV		 2411
2412 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2413 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2414 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2415
2416 v4l2_info(sd, "SDP: free run: %s\n",
2417 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2418 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2419 "valid SD/PR signal detected" : "invalid/no signal");
2420 if (sdp_signal_detected) {
2421 static const char * const sdp_std_txt[] = {
2422 "NTSC-M/J",
2423 "1?",
2424 "NTSC-443",
2425 "60HzSECAM",
2426 "PAL-M",
2427 "5?",
2428 "PAL-60",
2429 "7?", "8?", "9?", "a?", "b?",
2430 "PAL-CombN",
2431 "d?",
2432 "PAL-BGHID",
2433 "SECAM"
2434 };
2435 v4l2_info(sd, "SDP: standard %s\n",
2436 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2437 v4l2_info(sd, "SDP: %s\n",
2438 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2439 v4l2_info(sd, "SDP: %s\n",
2440 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2441 v4l2_info(sd, "SDP: deinterlacer %s\n",
2442 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2443 v4l2_info(sd, "SDP: csc %s mode\n",
2444 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2445 }
2446 return 0;
2447}
2448
2449static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2450{
2451 /* CP block */
2452 struct adv7842_state *state = to_state(sd);
2453 struct v4l2_dv_timings timings;
28a769f1
HV		 2454 u8 reg_io_0x02 = io_read(sd, 0x02);
2455 u8 reg_io_0x21 = io_read(sd, 0x21);
2456 u8 reg_rep_0x77 = rep_read(sd, 0x77);
2457 u8 reg_rep_0x7d = rep_read(sd, 0x7d);
a89bcd4c
HV		 2458 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2459 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2460 bool audio_mute = io_read(sd, 0x65) & 0x40;
2461
2462 static const char * const csc_coeff_sel_rb[16] = {
2463 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2464 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2465 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2466 "reserved", "reserved", "reserved", "reserved", "manual"
2467 };
2468 static const char * const input_color_space_txt[16] = {
2469 "RGB limited range (16-235)", "RGB full range (0-255)",
2470 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
69e9ba6f 2471 "xvYCC Bt.601", "xvYCC Bt.709",
a89bcd4c
HV		 2472 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2473 "invalid", "invalid", "invalid", "invalid", "invalid",
2474 "invalid", "invalid", "automatic"
2475 };
2476 static const char * const rgb_quantization_range_txt[] = {
2477 "Automatic",
2478 "RGB limited range (16-235)",
2479 "RGB full range (0-255)",
2480 };
2481 static const char * const deep_color_mode_txt[4] = {
2482 "8-bits per channel",
2483 "10-bits per channel",
2484 "12-bits per channel",
2485 "16-bits per channel (not supported)"
2486 };
2487
2488 v4l2_info(sd, "-----Chip status-----\n");
2489 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
a89bcd4c
HV		 2490 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2491 state->hdmi_port_a ? "A" : "B");
2492 v4l2_info(sd, "EDID A %s, B %s\n",
2493 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2494 "enabled" : "disabled",
2495 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2496 "enabled" : "disabled");
2497 v4l2_info(sd, "HPD A %s, B %s\n",
2498 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2499 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2500 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2501 "enabled" : "disabled");
2502
2503 v4l2_info(sd, "-----Signal status-----\n");
2504 if (state->hdmi_port_a) {
2505 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2506 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2507 v4l2_info(sd, "TMDS signal detected: %s\n",
2508 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2509 v4l2_info(sd, "TMDS signal locked: %s\n",
2510 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2511 } else {
2512 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2513 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2514 v4l2_info(sd, "TMDS signal detected: %s\n",
2515 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2516 v4l2_info(sd, "TMDS signal locked: %s\n",
2517 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2518 }
2519 v4l2_info(sd, "CP free run: %s\n",
2520 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2521 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2522 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2523 (io_read(sd, 0x01) & 0x70) >> 4);
2524
2525 v4l2_info(sd, "-----Video Timings-----\n");
2526 if (no_cp_signal(sd)) {
2527 v4l2_info(sd, "STDI: not locked\n");
2528 } else {
28a769f1
HV		 2529 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2530 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2531 u32 lcvs = cp_read(sd, 0xb3) >> 3;
2532 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
a89bcd4c
HV		 2533 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2534 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2535 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2536 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2537 v4l2_info(sd,
2538 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2539 lcf, bl, lcvs, fcl,
2540 (cp_read(sd, 0xb1) & 0x40) ?
2541 "interlaced" : "progressive",
2542 hs_pol, vs_pol);
2543 }
2544 if (adv7842_query_dv_timings(sd, &timings))
2545 v4l2_info(sd, "No video detected\n");
2546 else
2547 v4l2_print_dv_timings(sd->name, "Detected format: ",
2548 &timings, true);
2549 v4l2_print_dv_timings(sd->name, "Configured format: ",
2550 &state->timings, true);
2551
2552 if (no_cp_signal(sd))
2553 return 0;
2554
2555 v4l2_info(sd, "-----Color space-----\n");
2556 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2557 rgb_quantization_range_txt[state->rgb_quantization_range]);
2558 v4l2_info(sd, "Input color space: %s\n",
2559 input_color_space_txt[reg_io_0x02 >> 4]);
2560 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2561 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2562 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2563 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2564 "enabled" : "disabled");
2565 v4l2_info(sd, "Color space conversion: %s\n",
2566 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2567
2568 if (!is_digital_input(sd))
2569 return 0;
2570
2571 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2572 v4l2_info(sd, "HDCP encrypted content: %s\n",
2573 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2574 v4l2_info(sd, "HDCP keys read: %s%s\n",
2575 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2576 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2577 if (!is_hdmi(sd))
2578 return 0;
2579
2580 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2581 audio_pll_locked ? "locked" : "not locked",
2582 audio_sample_packet_detect ? "detected" : "not detected",
2583 audio_mute ? "muted" : "enabled");
2584 if (audio_pll_locked && audio_sample_packet_detect) {
2585 v4l2_info(sd, "Audio format: %s\n",
2586 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2587 }
2588 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2589 (hdmi_read(sd, 0x5c) << 8) +
2590 (hdmi_read(sd, 0x5d) & 0xf0));
2591 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2592 (hdmi_read(sd, 0x5e) << 8) +
2593 hdmi_read(sd, 0x5f));
2594 v4l2_info(sd, "AV Mute: %s\n",
2595 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2596 v4l2_info(sd, "Deep color mode: %s\n",
2597 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2598
09f90c53
MB		 2599 adv7842_log_infoframes(sd);
2600
a89bcd4c
HV		 2601 return 0;
2602}
2603
2604static int adv7842_log_status(struct v4l2_subdev *sd)
2605{
2606 struct adv7842_state *state = to_state(sd);
2607
2608 if (state->mode == ADV7842_MODE_SDP)
2609 return adv7842_sdp_log_status(sd);
2610 return adv7842_cp_log_status(sd);
2611}
2612
2613static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2614{
2615 struct adv7842_state *state = to_state(sd);
2616
2617 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2618
2619 if (state->mode != ADV7842_MODE_SDP)
2620 return -ENODATA;
2621
2622 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2623 *std = 0;
2624 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2625 return 0;
2626 }
2627
2628 switch (sdp_read(sd, 0x52) & 0x0f) {
2629 case 0:
2630 /* NTSC-M/J */
2631 *std &= V4L2_STD_NTSC;
2632 break;
2633 case 2:
2634 /* NTSC-443 */
2635 *std &= V4L2_STD_NTSC_443;
2636 break;
2637 case 3:
2638 /* 60HzSECAM */
2639 *std &= V4L2_STD_SECAM;
2640 break;
2641 case 4:
2642 /* PAL-M */
2643 *std &= V4L2_STD_PAL_M;
2644 break;
2645 case 6:
2646 /* PAL-60 */
2647 *std &= V4L2_STD_PAL_60;
2648 break;
2649 case 0xc:
2650 /* PAL-CombN */
2651 *std &= V4L2_STD_PAL_Nc;
2652 break;
2653 case 0xe:
2654 /* PAL-BGHID */
2655 *std &= V4L2_STD_PAL;
2656 break;
2657 case 0xf:
2658 /* SECAM */
2659 *std &= V4L2_STD_SECAM;
2660 break;
2661 default:
2662 *std &= V4L2_STD_ALL;
2663 break;
2664 }
2665 return 0;
2666}
2667
3c4da74f
MB		 2668static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2669{
2670 if (s && s->adjust) {
2671 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2672 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2673 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2674 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2675 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2676 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2677 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2678 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
15058aac
MB		 2679 sdp_io_write(sd, 0xa8, s->vs_beg_o);
2680 sdp_io_write(sd, 0xa9, s->vs_beg_e);
2681 sdp_io_write(sd, 0xaa, s->vs_end_o);
2682 sdp_io_write(sd, 0xab, s->vs_end_e);
3c4da74f
MB		 2683 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2684 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2685 sdp_io_write(sd, 0xae, s->de_v_end_o);
2686 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2687 } else {
2688 /* set to default */
2689 sdp_io_write(sd, 0x94, 0x00);
2690 sdp_io_write(sd, 0x95, 0x00);
2691 sdp_io_write(sd, 0x96, 0x00);
2692 sdp_io_write(sd, 0x97, 0x20);
2693 sdp_io_write(sd, 0x98, 0x00);
2694 sdp_io_write(sd, 0x99, 0x00);
2695 sdp_io_write(sd, 0x9a, 0x00);
2696 sdp_io_write(sd, 0x9b, 0x00);
15058aac
MB		 2697 sdp_io_write(sd, 0xa8, 0x04);
2698 sdp_io_write(sd, 0xa9, 0x04);
2699 sdp_io_write(sd, 0xaa, 0x04);
2700 sdp_io_write(sd, 0xab, 0x04);
3c4da74f
MB		 2701 sdp_io_write(sd, 0xac, 0x04);
2702 sdp_io_write(sd, 0xad, 0x04);
2703 sdp_io_write(sd, 0xae, 0x04);
2704 sdp_io_write(sd, 0xaf, 0x04);
2705 }
2706}
2707
a89bcd4c
HV		 2708static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2709{
2710 struct adv7842_state *state = to_state(sd);
3c4da74f 2711 struct adv7842_platform_data *pdata = &state->pdata;
a89bcd4c
HV		 2712
2713 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2714
2715 if (state->mode != ADV7842_MODE_SDP)
2716 return -ENODATA;
2717
3c4da74f
MB		 2718 if (norm & V4L2_STD_625_50)
2719 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2720 else if (norm & V4L2_STD_525_60)
2721 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2722 else
2723 adv7842_s_sdp_io(sd, NULL);
2724
a89bcd4c
HV		 2725 if (norm & V4L2_STD_ALL) {
2726 state->norm = norm;
2727 return 0;
2728 }
2729 return -EINVAL;
2730}
2731
2732static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2733{
2734 struct adv7842_state *state = to_state(sd);
2735
2736 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2737
2738 if (state->mode != ADV7842_MODE_SDP)
2739 return -ENODATA;
2740
2741 *norm = state->norm;
2742 return 0;
2743}
2744
2745/* ----------------------------------------------------------------------- */
2746
69e9ba6f 2747static int adv7842_core_init(struct v4l2_subdev *sd)
a89bcd4c 2748{
69e9ba6f
HV		 2749 struct adv7842_state *state = to_state(sd);
2750 struct adv7842_platform_data *pdata = &state->pdata;
a89bcd4c
HV		 2751 hdmi_write(sd, 0x48,
2752 (pdata->disable_pwrdnb ? 0x80 : 0) |
2753 (pdata->disable_cable_det_rst ? 0x40 : 0));
2754
2755 disable_input(sd);
2756
2ff0f16d
MB		 2757 /*
2758 * Disable I2C access to internal EDID ram from HDMI DDC ports
2759 * Disable auto edid enable when leaving powerdown mode
2760 */
2761 rep_write_and_or(sd, 0x77, 0xd3, 0x20);
2762
a89bcd4c
HV		 2763 /* power */
2764 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2765 io_write(sd, 0x15, 0x80); /* Power up pads */
2766
2767 /* video format */
2768 io_write(sd, 0x02,
69e9ba6f 2769 0xf0 |
a89bcd4c
HV		 2770 pdata->alt_gamma << 3 |
2771 pdata->op_656_range << 2 |
a89bcd4c 2772 pdata->alt_data_sat << 0);
a89bcd4c
HV		 2773 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2774 pdata->insert_av_codes << 2 |
f888ae7e
HV		 2775 pdata->replicate_av_codes << 1);
2776 adv7842_setup_format(state);
a89bcd4c 2777
5b64b205
MR		 2778 /* HDMI audio */
2779 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2780
a89bcd4c 2781 /* Drive strength */
7f95c904
HV		 2782 io_write_and_or(sd, 0x14, 0xc0,
2783 pdata->dr_str_data << 4 |
2784 pdata->dr_str_clk << 2 |
2785 pdata->dr_str_sync);
a89bcd4c
HV		 2786
2787 /* HDMI free run */
f0ec1742
MB		 2788 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
2789 (pdata->hdmi_free_run_mode << 1));
2790
2791 /* SPD free run */
2792 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
2793 (pdata->sdp_free_run_cbar_en << 1) |
2794 (pdata->sdp_free_run_man_col_en << 2) |
57f0547f 2795 (pdata->sdp_free_run_auto << 3));
a89bcd4c
HV		 2796
2797 /* TODO from platform data */
2798 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
2799 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
2800 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2801 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2802
2803 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2804 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2805
2806 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
2807
a89bcd4c
HV		 2808 /* todo, improve settings for sdram */
2809 if (pdata->sd_ram_size >= 128) {
2810 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2811 if (pdata->sd_ram_ddr) {
2812 /* SDP setup for the AD eval board */
2813 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
2814 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
2815 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2816 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2817 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2818 } else {
2819 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
2820 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
2821 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
2822 depends on memory */
2823 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
2824 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2825 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2826 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2827 }
2828 } else {
2829 /*
2830 * Manual UG-214, rev 0 is bit confusing on this bit
2831 * but a '1' disables any signal if the Ram is active.
2832 */
2833 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
2834 }
2835
2836 select_input(sd, pdata->vid_std_select);
2837
2838 enable_input(sd);
2839
ce2d2b2d
MB		 2840 if (pdata->hpa_auto) {
2841 /* HPA auto, HPA 0.5s after Edid set and Cable detect */
2842 hdmi_write(sd, 0x69, 0x5c);
2843 } else {
2844 /* HPA manual */
2845 hdmi_write(sd, 0x69, 0xa3);
2846 /* HPA disable on port A and B */
2847 io_write_and_or(sd, 0x20, 0xcf, 0x00);
2848 }
a89bcd4c
HV		 2849
2850 /* LLC */
fe808f3c 2851 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
a89bcd4c
HV		 2852 io_write(sd, 0x33, 0x40);
2853
2854 /* interrupts */
c9f1f271 2855 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
a89bcd4c
HV		 2856
2857 adv7842_irq_enable(sd, true);
2858
2859 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2860}
2861
2862/* ----------------------------------------------------------------------- */
2863
2864static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
2865{
2866 /*
2867 * From ADV784x external Memory test.pdf
2868 *
2869 * Reset must just been performed before running test.
2870 * Recommended to reset after test.
2871 */
2872 int i;
2873 int pass = 0;
2874 int fail = 0;
2875 int complete = 0;
2876
2877 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
2878 io_write(sd, 0x01, 0x00); /* Program SDP mode */
2879 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
2880 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2881 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2882 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2883 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2884 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
2885 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
2886 io_write(sd, 0x15, 0xBA); /* Enable outputs */
2887 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2888 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
2889
2890 mdelay(5);
2891
2892 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
2893 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
2894 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
2895 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
2896 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
2897 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
2898 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
2899 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
2900 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
2901 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
2902 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
2903
2904 mdelay(5);
2905
2906 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
2907 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2908
2909 mdelay(20);
2910
2911 for (i = 0; i < 10; i++) {
2912 u8 result = sdp_io_read(sd, 0xdb);
2913 if (result & 0x10) {
2914 complete++;
2915 if (result & 0x20)
2916 fail++;
2917 else
2918 pass++;
2919 }
2920 mdelay(20);
2921 }
2922
2923 v4l2_dbg(1, debug, sd,
2924 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2925 complete, i, pass, fail);
2926
2927 if (!complete || fail)
2928 return -EIO;
2929 return 0;
2930}
2931
2932static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
2933 struct adv7842_platform_data *pdata)
2934{
2935 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
2936 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
2937 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
2938 io_write(sd, 0xf4, pdata->i2c_cec << 1);
2939 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
2940
2941 io_write(sd, 0xf8, pdata->i2c_afe << 1);
2942 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
2943 io_write(sd, 0xfa, pdata->i2c_edid << 1);
2944 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
2945
2946 io_write(sd, 0xfd, pdata->i2c_cp << 1);
2947 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
2948}
2949
2950static int adv7842_command_ram_test(struct v4l2_subdev *sd)
2951{
2952 struct i2c_client *client = v4l2_get_subdevdata(sd);
2953 struct adv7842_state *state = to_state(sd);
2954 struct adv7842_platform_data *pdata = client->dev.platform_data;
1961b720 2955 struct v4l2_dv_timings timings;
a89bcd4c
HV		 2956 int ret = 0;
2957
2958 if (!pdata)
2959 return -ENODEV;
2960
2961 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
2962 v4l2_info(sd, "no sdram or no ddr sdram\n");
2963 return -EINVAL;
2964 }
2965
2966 main_reset(sd);
2967
2968 adv7842_rewrite_i2c_addresses(sd, pdata);
2969
2970 /* run ram test */
2971 ret = adv7842_ddr_ram_test(sd);
2972
2973 main_reset(sd);
2974
2975 adv7842_rewrite_i2c_addresses(sd, pdata);
2976
2977 /* and re-init chip and state */
69e9ba6f 2978 adv7842_core_init(sd);
a89bcd4c
HV		 2979
2980 disable_input(sd);
2981
2982 select_input(sd, state->vid_std_select);
2983
2984 enable_input(sd);
2985
a89bcd4c 2986 edid_write_vga_segment(sd);
fc2e991e
MB		 2987 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
2988 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
a89bcd4c 2989
1961b720
MB		 2990 timings = state->timings;
2991
2992 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
2993
2994 adv7842_s_dv_timings(sd, &timings);
2995
a89bcd4c
HV		 2996 return ret;
2997}
2998
2999static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
3000{
3001 switch (cmd) {
3002 case ADV7842_CMD_RAM_TEST:
3003 return adv7842_command_ram_test(sd);
3004 }
3005 return -ENOTTY;
3006}
3007
3008/* ----------------------------------------------------------------------- */
3009
3010static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
3011 .s_ctrl = adv7842_s_ctrl,
3012};
3013
3014static const struct v4l2_subdev_core_ops adv7842_core_ops = {
3015 .log_status = adv7842_log_status,
a89bcd4c
HV		 3016 .ioctl = adv7842_ioctl,
3017 .interrupt_service_routine = adv7842_isr,
3018#ifdef CONFIG_VIDEO_ADV_DEBUG
3019 .g_register = adv7842_g_register,
3020 .s_register = adv7842_s_register,
3021#endif
3022};
3023
3024static const struct v4l2_subdev_video_ops adv7842_video_ops = {
8774bed9
LP		 3025 .g_std = adv7842_g_std,
3026 .s_std = adv7842_s_std,
a89bcd4c
HV		 3027 .s_routing = adv7842_s_routing,
3028 .querystd = adv7842_querystd,
3029 .g_input_status = adv7842_g_input_status,
3030 .s_dv_timings = adv7842_s_dv_timings,
3031 .g_dv_timings = adv7842_g_dv_timings,
3032 .query_dv_timings = adv7842_query_dv_timings,
a89bcd4c
HV		 3033};
3034
3035static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
f888ae7e
HV		 3036 .enum_mbus_code = adv7842_enum_mbus_code,
3037 .get_fmt = adv7842_get_format,
3038 .set_fmt = adv7842_set_format,
245b2b67 3039 .get_edid = adv7842_get_edid,
a89bcd4c 3040 .set_edid = adv7842_set_edid,
c916194c
LP		 3041 .enum_dv_timings = adv7842_enum_dv_timings,
3042 .dv_timings_cap = adv7842_dv_timings_cap,
a89bcd4c
HV		 3043};
3044
3045static const struct v4l2_subdev_ops adv7842_ops = {
3046 .core = &adv7842_core_ops,
3047 .video = &adv7842_video_ops,
3048 .pad = &adv7842_pad_ops,
3049};
3050
3051/* -------------------------- custom ctrls ---------------------------------- */
3052
3053static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
3054 .ops = &adv7842_ctrl_ops,
3055 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
3056 .name = "Analog Sampling Phase",
3057 .type = V4L2_CTRL_TYPE_INTEGER,
3058 .min = 0,
3059 .max = 0x1f,
3060 .step = 1,
3061 .def = 0,
3062};
3063
3064static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
3065 .ops = &adv7842_ctrl_ops,
3066 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
3067 .name = "Free Running Color, Manual",
3068 .type = V4L2_CTRL_TYPE_BOOLEAN,
3069 .max = 1,
3070 .step = 1,
3071 .def = 1,
3072};
3073
3074static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
3075 .ops = &adv7842_ctrl_ops,
3076 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
3077 .name = "Free Running Color",
3078 .type = V4L2_CTRL_TYPE_INTEGER,
3079 .max = 0xffffff,
3080 .step = 0x1,
3081};
3082
3083
b82e2793 3084static void adv7842_unregister_clients(struct v4l2_subdev *sd)
a89bcd4c 3085{
b82e2793 3086 struct adv7842_state *state = to_state(sd);
a89bcd4c
HV		 3087 if (state->i2c_avlink)
3088 i2c_unregister_device(state->i2c_avlink);
3089 if (state->i2c_cec)
3090 i2c_unregister_device(state->i2c_cec);
3091 if (state->i2c_infoframe)
3092 i2c_unregister_device(state->i2c_infoframe);
3093 if (state->i2c_sdp_io)
3094 i2c_unregister_device(state->i2c_sdp_io);
3095 if (state->i2c_sdp)
3096 i2c_unregister_device(state->i2c_sdp);
3097 if (state->i2c_afe)
3098 i2c_unregister_device(state->i2c_afe);
3099 if (state->i2c_repeater)
3100 i2c_unregister_device(state->i2c_repeater);
3101 if (state->i2c_edid)
3102 i2c_unregister_device(state->i2c_edid);
3103 if (state->i2c_hdmi)
3104 i2c_unregister_device(state->i2c_hdmi);
3105 if (state->i2c_cp)
3106 i2c_unregister_device(state->i2c_cp);
3107 if (state->i2c_vdp)
3108 i2c_unregister_device(state->i2c_vdp);
b82e2793
MB		 3109
3110 state->i2c_avlink = NULL;
3111 state->i2c_cec = NULL;
3112 state->i2c_infoframe = NULL;
3113 state->i2c_sdp_io = NULL;
3114 state->i2c_sdp = NULL;
3115 state->i2c_afe = NULL;
3116 state->i2c_repeater = NULL;
3117 state->i2c_edid = NULL;
3118 state->i2c_hdmi = NULL;
3119 state->i2c_cp = NULL;
3120 state->i2c_vdp = NULL;
a89bcd4c
HV		 3121}
3122
b82e2793 3123static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
a89bcd4c
HV		 3124 u8 addr, u8 io_reg)
3125{
3126 struct i2c_client *client = v4l2_get_subdevdata(sd);
b82e2793 3127 struct i2c_client *cp;
a89bcd4c
HV		 3128
3129 io_write(sd, io_reg, addr << 1);
b82e2793
MB		 3130
3131 if (addr == 0) {
3132 v4l2_err(sd, "no %s i2c addr configured\n", desc);
3133 return NULL;
3134 }
3135
3136 cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
3137 if (!cp)
3138 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr);
3139
3140 return cp;
3141}
3142
3143static int adv7842_register_clients(struct v4l2_subdev *sd)
3144{
3145 struct adv7842_state *state = to_state(sd);
3146 struct adv7842_platform_data *pdata = &state->pdata;
3147
3148 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
3149 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
3150 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
3151 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
3152 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
3153 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
3154 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
3155 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
3156 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
3157 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
3158 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
3159
3160 if (!state->i2c_avlink ||
3161 !state->i2c_cec ||
3162 !state->i2c_infoframe ||
3163 !state->i2c_sdp_io ||
3164 !state->i2c_sdp ||
3165 !state->i2c_afe ||
3166 !state->i2c_repeater ||
3167 !state->i2c_edid ||
3168 !state->i2c_hdmi ||
3169 !state->i2c_cp ||
3170 !state->i2c_vdp)
3171 return -1;
3172
3173 return 0;
a89bcd4c
HV		 3174}
3175
3176static int adv7842_probe(struct i2c_client *client,
3177 const struct i2c_device_id *id)
3178{
3179 struct adv7842_state *state;
0bb4e7ab
HV		 3180 static const struct v4l2_dv_timings cea640x480 =
3181 V4L2_DV_BT_CEA_640X480P59_94;
a89bcd4c
HV		 3182 struct adv7842_platform_data *pdata = client->dev.platform_data;
3183 struct v4l2_ctrl_handler *hdl;
3184 struct v4l2_subdev *sd;
3185 u16 rev;
3186 int err;
3187
3188 /* Check if the adapter supports the needed features */
3189 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3190 return -EIO;
3191
3192 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
3193 client->addr << 1);
3194
3195 if (!pdata) {
3196 v4l_err(client, "No platform data!\n");
3197 return -ENODEV;
3198 }
3199
3200 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
3201 if (!state) {
3202 v4l_err(client, "Could not allocate adv7842_state memory!\n");
3203 return -ENOMEM;
3204 }
3205
7de5be44
MB		 3206 /* platform data */
3207 state->pdata = *pdata;
0bb4e7ab 3208 state->timings = cea640x480;
f888ae7e 3209 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
7de5be44 3210
a89bcd4c
HV		 3211 sd = &state->sd;
3212 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
3213 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
a89bcd4c
HV		 3214 state->mode = pdata->mode;
3215
8e4e3631 3216 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
6e9071f2 3217 state->restart_stdi_once = true;
a89bcd4c
HV		 3218
3219 /* i2c access to adv7842? */
3220 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3221 adv_smbus_read_byte_data_check(client, 0xeb, false);
3222 if (rev != 0x2012) {
3223 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
3224 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3225 adv_smbus_read_byte_data_check(client, 0xeb, false);
3226 }
3227 if (rev != 0x2012) {
3228 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3229 client->addr << 1, rev);
3230 return -ENODEV;
3231 }
3232
3233 if (pdata->chip_reset)
3234 main_reset(sd);
3235
3236 /* control handlers */
3237 hdl = &state->hdl;
3238 v4l2_ctrl_handler_init(hdl, 6);
3239
3240 /* add in ascending ID order */
3241 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3242 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3243 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3244 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3245 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3246 V4L2_CID_SATURATION, 0, 255, 1, 128);
3247 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3248 V4L2_CID_HUE, 0, 128, 1, 0);
3249
3250 /* custom controls */
3251 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3252 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
3253 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
3254 &adv7842_ctrl_analog_sampling_phase, NULL);
3255 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
3256 &adv7842_ctrl_free_run_color_manual, NULL);
3257 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
3258 &adv7842_ctrl_free_run_color, NULL);
3259 state->rgb_quantization_range_ctrl =
3260 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3261 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3262 0, V4L2_DV_RGB_RANGE_AUTO);
3263 sd->ctrl_handler = hdl;
3264 if (hdl->error) {
3265 err = hdl->error;
3266 goto err_hdl;
3267 }
3268 state->detect_tx_5v_ctrl->is_private = true;
3269 state->rgb_quantization_range_ctrl->is_private = true;
3270 state->analog_sampling_phase_ctrl->is_private = true;
3271 state->free_run_color_ctrl_manual->is_private = true;
3272 state->free_run_color_ctrl->is_private = true;
3273
3274 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3275 err = -ENODEV;
3276 goto err_hdl;
3277 }
3278
b82e2793 3279 if (adv7842_register_clients(sd) < 0) {
a89bcd4c
HV		 3280 err = -ENOMEM;
3281 v4l2_err(sd, "failed to create all i2c clients\n");
3282 goto err_i2c;
3283 }
3284
3285 /* work queues */
3286 state->work_queues = create_singlethread_workqueue(client->name);
3287 if (!state->work_queues) {
3288 v4l2_err(sd, "Could not create work queue\n");
3289 err = -ENOMEM;
3290 goto err_i2c;
3291 }
3292
3293 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3294 adv7842_delayed_work_enable_hotplug);
3295
3296 state->pad.flags = MEDIA_PAD_FL_SOURCE;
3297 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
3298 if (err)
3299 goto err_work_queues;
3300
7de5be44 3301 err = adv7842_core_init(sd);
a89bcd4c
HV		 3302 if (err)
3303 goto err_entity;
3304
3305 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3306 client->addr << 1, client->adapter->name);
3307 return 0;
3308
3309err_entity:
3310 media_entity_cleanup(&sd->entity);
3311err_work_queues:
3312 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3313 destroy_workqueue(state->work_queues);
3314err_i2c:
b82e2793 3315 adv7842_unregister_clients(sd);
a89bcd4c
HV		 3316err_hdl:
3317 v4l2_ctrl_handler_free(hdl);
3318 return err;
3319}
3320
3321/* ----------------------------------------------------------------------- */
3322
3323static int adv7842_remove(struct i2c_client *client)
3324{
3325 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3326 struct adv7842_state *state = to_state(sd);
3327
3328 adv7842_irq_enable(sd, false);
3329
3330 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3331 destroy_workqueue(state->work_queues);
3332 v4l2_device_unregister_subdev(sd);
3333 media_entity_cleanup(&sd->entity);
b82e2793 3334 adv7842_unregister_clients(sd);
a89bcd4c
HV		 3335 v4l2_ctrl_handler_free(sd->ctrl_handler);
3336 return 0;
3337}
3338
3339/* ----------------------------------------------------------------------- */
3340
3341static struct i2c_device_id adv7842_id[] = {
3342 { "adv7842", 0 },
3343 { }
3344};
3345MODULE_DEVICE_TABLE(i2c, adv7842_id);
3346
3347/* ----------------------------------------------------------------------- */
3348
3349static struct i2c_driver adv7842_driver = {
3350 .driver = {
3351 .owner = THIS_MODULE,
3352 .name = "adv7842",
3353 },
3354 .probe = adv7842_probe,
3355 .remove = adv7842_remove,
3356 .id_table = adv7842_id,
3357};
3358
3359module_i2c_driver(adv7842_driver);
Linux kernel - Deliverables
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