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0b675536 SNC |
1 | /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics |
2 | * Digitizer with Horizontal PLL registers | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments Inc | |
5 | * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com> | |
6 | * | |
7 | * This code is partially based upon the TVP5150 driver | |
8 | * written by Mauro Carvalho Chehab (mchehab@infradead.org), | |
9 | * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com> | |
10 | * and the TVP7002 driver in the TI LSP 2.10.00.14. Revisions by | |
11 | * Muralidharan Karicheri and Snehaprabha Narnakaje (TI). | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | */ | |
27 | #include <linux/delay.h> | |
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
0b675536 | 30 | #include <linux/videodev2.h> |
7a707b89 | 31 | #include <linux/module.h> |
b91670a0 | 32 | #include <linux/of.h> |
fd9fdb78 | 33 | #include <linux/of_graph.h> |
eb8305b1 | 34 | #include <linux/v4l2-dv-timings.h> |
0b675536 | 35 | #include <media/tvp7002.h> |
25ba2c80 | 36 | #include <media/v4l2-async.h> |
0b675536 | 37 | #include <media/v4l2-device.h> |
0b675536 | 38 | #include <media/v4l2-common.h> |
0eb73de0 | 39 | #include <media/v4l2-ctrls.h> |
c0d9644f LP |
40 | #include <media/v4l2-of.h> |
41 | ||
0b675536 SNC |
42 | #include "tvp7002_reg.h" |
43 | ||
44 | MODULE_DESCRIPTION("TI TVP7002 Video and Graphics Digitizer driver"); | |
45 | MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>"); | |
46 | MODULE_LICENSE("GPL"); | |
47 | ||
0b675536 SNC |
48 | /* I2C retry attempts */ |
49 | #define I2C_RETRY_COUNT (5) | |
50 | ||
51 | /* End of registers */ | |
52 | #define TVP7002_EOR 0x5c | |
53 | ||
54 | /* Read write definition for registers */ | |
55 | #define TVP7002_READ 0 | |
56 | #define TVP7002_WRITE 1 | |
57 | #define TVP7002_RESERVED 2 | |
58 | ||
59 | /* Interlaced vs progressive mask and shift */ | |
60 | #define TVP7002_IP_SHIFT 5 | |
61 | #define TVP7002_INPR_MASK (0x01 << TVP7002_IP_SHIFT) | |
62 | ||
63 | /* Shift for CPL and LPF registers */ | |
64 | #define TVP7002_CL_SHIFT 8 | |
65 | #define TVP7002_CL_MASK 0x0f | |
66 | ||
67 | /* Debug functions */ | |
90ab5ee9 | 68 | static bool debug; |
0b675536 SNC |
69 | module_param(debug, bool, 0644); |
70 | MODULE_PARM_DESC(debug, "Debug level (0-2)"); | |
71 | ||
72 | /* Structure for register values */ | |
73 | struct i2c_reg_value { | |
74 | u8 reg; | |
75 | u8 value; | |
76 | u8 type; | |
77 | }; | |
78 | ||
79 | /* | |
80 | * Register default values (according to tvp7002 datasheet) | |
81 | * In the case of read-only registers, the value (0xff) is | |
82 | * never written. R/W functionality is controlled by the | |
83 | * writable bit in the register struct definition. | |
84 | */ | |
85 | static const struct i2c_reg_value tvp7002_init_default[] = { | |
86 | { TVP7002_CHIP_REV, 0xff, TVP7002_READ }, | |
87 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE }, | |
88 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE }, | |
89 | { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE }, | |
90 | { TVP7002_HPLL_PHASE_SEL, 0x80, TVP7002_WRITE }, | |
91 | { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, | |
92 | { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, | |
93 | { TVP7002_HSYNC_OUT_W, 0x60, TVP7002_WRITE }, | |
94 | { TVP7002_B_FINE_GAIN, 0x00, TVP7002_WRITE }, | |
95 | { TVP7002_G_FINE_GAIN, 0x00, TVP7002_WRITE }, | |
96 | { TVP7002_R_FINE_GAIN, 0x00, TVP7002_WRITE }, | |
97 | { TVP7002_B_FINE_OFF_MSBS, 0x80, TVP7002_WRITE }, | |
98 | { TVP7002_G_FINE_OFF_MSBS, 0x80, TVP7002_WRITE }, | |
99 | { TVP7002_R_FINE_OFF_MSBS, 0x80, TVP7002_WRITE }, | |
100 | { TVP7002_SYNC_CTL_1, 0x20, TVP7002_WRITE }, | |
101 | { TVP7002_HPLL_AND_CLAMP_CTL, 0x2e, TVP7002_WRITE }, | |
102 | { TVP7002_SYNC_ON_G_THRS, 0x5d, TVP7002_WRITE }, | |
103 | { TVP7002_SYNC_SEPARATOR_THRS, 0x47, TVP7002_WRITE }, | |
104 | { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE }, | |
105 | { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, | |
106 | { TVP7002_SYNC_DETECT_STAT, 0xff, TVP7002_READ }, | |
107 | { TVP7002_OUT_FORMATTER, 0x47, TVP7002_WRITE }, | |
108 | { TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE }, | |
109 | { TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE }, | |
110 | { TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE }, | |
111 | { TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE }, | |
112 | { TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE }, | |
113 | { TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE }, | |
114 | { TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE }, | |
115 | { TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE }, | |
116 | { TVP7002_B_COARSE_OFF, 0x10, TVP7002_WRITE }, | |
117 | { TVP7002_G_COARSE_OFF, 0x10, TVP7002_WRITE }, | |
118 | { TVP7002_R_COARSE_OFF, 0x10, TVP7002_WRITE }, | |
119 | { TVP7002_HSOUT_OUT_START, 0x08, TVP7002_WRITE }, | |
120 | { TVP7002_MISC_CTL_4, 0x00, TVP7002_WRITE }, | |
121 | { TVP7002_B_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ }, | |
122 | { TVP7002_G_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ }, | |
123 | { TVP7002_R_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ }, | |
124 | { TVP7002_AUTO_LVL_CTL_ENABLE, 0x80, TVP7002_WRITE }, | |
125 | { TVP7002_DGTL_ALC_OUT_MSBS, 0xff, TVP7002_READ }, | |
126 | { TVP7002_AUTO_LVL_CTL_FILTER, 0x53, TVP7002_WRITE }, | |
127 | { 0x29, 0x08, TVP7002_RESERVED }, | |
128 | { TVP7002_FINE_CLAMP_CTL, 0x07, TVP7002_WRITE }, | |
129 | /* PWR_CTL is controlled only by the probe and reset functions */ | |
130 | { TVP7002_PWR_CTL, 0x00, TVP7002_RESERVED }, | |
131 | { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE }, | |
132 | { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE }, | |
133 | { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE }, | |
425b91c9 | 134 | { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE }, |
0b675536 SNC |
135 | { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE }, |
136 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, | |
137 | { 0x32, 0x18, TVP7002_RESERVED }, | |
138 | { 0x33, 0x60, TVP7002_RESERVED }, | |
139 | { TVP7002_MVIS_STRIPPER_W, 0xff, TVP7002_RESERVED }, | |
140 | { TVP7002_VSYNC_ALGN, 0x10, TVP7002_WRITE }, | |
141 | { TVP7002_SYNC_BYPASS, 0x00, TVP7002_WRITE }, | |
142 | { TVP7002_L_FRAME_STAT_LSBS, 0xff, TVP7002_READ }, | |
143 | { TVP7002_L_FRAME_STAT_MSBS, 0xff, TVP7002_READ }, | |
144 | { TVP7002_CLK_L_STAT_LSBS, 0xff, TVP7002_READ }, | |
145 | { TVP7002_CLK_L_STAT_MSBS, 0xff, TVP7002_READ }, | |
146 | { TVP7002_HSYNC_W, 0xff, TVP7002_READ }, | |
147 | { TVP7002_VSYNC_W, 0xff, TVP7002_READ }, | |
148 | { TVP7002_L_LENGTH_TOL, 0x03, TVP7002_WRITE }, | |
149 | { 0x3e, 0x60, TVP7002_RESERVED }, | |
150 | { TVP7002_VIDEO_BWTH_CTL, 0x01, TVP7002_WRITE }, | |
151 | { TVP7002_AVID_START_PIXEL_LSBS, 0x01, TVP7002_WRITE }, | |
152 | { TVP7002_AVID_START_PIXEL_MSBS, 0x2c, TVP7002_WRITE }, | |
153 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x06, TVP7002_WRITE }, | |
154 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c, TVP7002_WRITE }, | |
155 | { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE }, | |
156 | { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, | |
157 | { TVP7002_VBLK_F_0_DURATION, 0x1e, TVP7002_WRITE }, | |
158 | { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, | |
159 | { TVP7002_FBIT_F_0_START_L_OFF, 0x00, TVP7002_WRITE }, | |
160 | { TVP7002_FBIT_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, | |
161 | { TVP7002_YUV_Y_G_COEF_LSBS, 0xe3, TVP7002_WRITE }, | |
162 | { TVP7002_YUV_Y_G_COEF_MSBS, 0x16, TVP7002_WRITE }, | |
163 | { TVP7002_YUV_Y_B_COEF_LSBS, 0x4f, TVP7002_WRITE }, | |
164 | { TVP7002_YUV_Y_B_COEF_MSBS, 0x02, TVP7002_WRITE }, | |
165 | { TVP7002_YUV_Y_R_COEF_LSBS, 0xce, TVP7002_WRITE }, | |
166 | { TVP7002_YUV_Y_R_COEF_MSBS, 0x06, TVP7002_WRITE }, | |
167 | { TVP7002_YUV_U_G_COEF_LSBS, 0xab, TVP7002_WRITE }, | |
168 | { TVP7002_YUV_U_G_COEF_MSBS, 0xf3, TVP7002_WRITE }, | |
169 | { TVP7002_YUV_U_B_COEF_LSBS, 0x00, TVP7002_WRITE }, | |
170 | { TVP7002_YUV_U_B_COEF_MSBS, 0x10, TVP7002_WRITE }, | |
171 | { TVP7002_YUV_U_R_COEF_LSBS, 0x55, TVP7002_WRITE }, | |
172 | { TVP7002_YUV_U_R_COEF_MSBS, 0xfc, TVP7002_WRITE }, | |
173 | { TVP7002_YUV_V_G_COEF_LSBS, 0x78, TVP7002_WRITE }, | |
174 | { TVP7002_YUV_V_G_COEF_MSBS, 0xf1, TVP7002_WRITE }, | |
175 | { TVP7002_YUV_V_B_COEF_LSBS, 0x88, TVP7002_WRITE }, | |
176 | { TVP7002_YUV_V_B_COEF_MSBS, 0xfe, TVP7002_WRITE }, | |
177 | { TVP7002_YUV_V_R_COEF_LSBS, 0x00, TVP7002_WRITE }, | |
178 | { TVP7002_YUV_V_R_COEF_MSBS, 0x10, TVP7002_WRITE }, | |
179 | /* This signals end of register values */ | |
180 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
181 | }; | |
182 | ||
183 | /* Register parameters for 480P */ | |
184 | static const struct i2c_reg_value tvp7002_parms_480P[] = { | |
185 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE }, | |
560afa7d | 186 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE }, |
0b675536 | 187 | { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE }, |
0b675536 SNC |
188 | { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE }, |
189 | { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, | |
190 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE }, | |
191 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE }, | |
192 | { TVP7002_VBLK_F_0_START_L_OFF, 0x03, TVP7002_WRITE }, | |
193 | { TVP7002_VBLK_F_1_START_L_OFF, 0x01, TVP7002_WRITE }, | |
194 | { TVP7002_VBLK_F_0_DURATION, 0x13, TVP7002_WRITE }, | |
195 | { TVP7002_VBLK_F_1_DURATION, 0x13, TVP7002_WRITE }, | |
196 | { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE }, | |
197 | { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE }, | |
198 | { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE }, | |
199 | { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE }, | |
200 | { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE }, | |
201 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
202 | }; | |
203 | ||
204 | /* Register parameters for 576P */ | |
205 | static const struct i2c_reg_value tvp7002_parms_576P[] = { | |
206 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE }, | |
207 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, | |
208 | { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE }, | |
0b675536 SNC |
209 | { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE }, |
210 | { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, | |
211 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE }, | |
212 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE }, | |
213 | { TVP7002_VBLK_F_0_START_L_OFF, 0x00, TVP7002_WRITE }, | |
214 | { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, | |
215 | { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE }, | |
216 | { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, | |
217 | { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE }, | |
218 | { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE }, | |
219 | { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE }, | |
220 | { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE }, | |
221 | { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE }, | |
222 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
223 | }; | |
224 | ||
225 | /* Register parameters for 1080I60 */ | |
226 | static const struct i2c_reg_value tvp7002_parms_1080I60[] = { | |
227 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, | |
560afa7d | 228 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, |
0b675536 | 229 | { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, |
0b675536 SNC |
230 | { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, |
231 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | |
232 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, | |
233 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE }, | |
234 | { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE }, | |
235 | { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, | |
236 | { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, | |
237 | { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE }, | |
238 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, | |
239 | { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, | |
240 | { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, | |
241 | { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, | |
242 | { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, | |
243 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
244 | }; | |
245 | ||
246 | /* Register parameters for 1080P60 */ | |
247 | static const struct i2c_reg_value tvp7002_parms_1080P60[] = { | |
248 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, | |
560afa7d | 249 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, |
0b675536 | 250 | { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE }, |
0b675536 SNC |
251 | { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, |
252 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | |
253 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, | |
254 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE }, | |
255 | { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE }, | |
256 | { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, | |
257 | { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, | |
258 | { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE }, | |
259 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, | |
260 | { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, | |
261 | { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, | |
262 | { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, | |
263 | { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, | |
264 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
265 | }; | |
266 | ||
267 | /* Register parameters for 1080I50 */ | |
268 | static const struct i2c_reg_value tvp7002_parms_1080I50[] = { | |
269 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE }, | |
270 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, | |
271 | { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, | |
0b675536 SNC |
272 | { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, |
273 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | |
274 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, | |
275 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE }, | |
276 | { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE }, | |
277 | { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, | |
278 | { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, | |
279 | { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE }, | |
280 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, | |
281 | { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, | |
282 | { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, | |
283 | { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, | |
284 | { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, | |
285 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
286 | }; | |
287 | ||
288 | /* Register parameters for 720P60 */ | |
289 | static const struct i2c_reg_value tvp7002_parms_720P60[] = { | |
290 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE }, | |
560afa7d | 291 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE }, |
0b675536 | 292 | { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE }, |
0b675536 SNC |
293 | { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, |
294 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | |
295 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE }, | |
296 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE }, | |
297 | { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE }, | |
298 | { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, | |
299 | { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE }, | |
300 | { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, | |
301 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, | |
302 | { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, | |
303 | { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, | |
304 | { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE }, | |
305 | { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, | |
306 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
307 | }; | |
308 | ||
309 | /* Register parameters for 720P50 */ | |
310 | static const struct i2c_reg_value tvp7002_parms_720P50[] = { | |
311 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE }, | |
560afa7d | 312 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE }, |
0b675536 | 313 | { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, |
0b675536 SNC |
314 | { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, |
315 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | |
316 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE }, | |
317 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE }, | |
318 | { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE }, | |
319 | { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, | |
320 | { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE }, | |
321 | { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, | |
322 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, | |
323 | { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, | |
324 | { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, | |
325 | { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, | |
326 | { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, | |
327 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
328 | }; | |
329 | ||
f0cd015e HV |
330 | /* Timings definition for handling device operation */ |
331 | struct tvp7002_timings_definition { | |
eb8305b1 | 332 | struct v4l2_dv_timings timings; |
0b675536 SNC |
333 | const struct i2c_reg_value *p_settings; |
334 | enum v4l2_colorspace color_space; | |
335 | enum v4l2_field scanmode; | |
336 | u16 progressive; | |
337 | u16 lines_per_frame; | |
338 | u16 cpl_min; | |
339 | u16 cpl_max; | |
340 | }; | |
341 | ||
f0cd015e HV |
342 | /* Struct list for digital video timings */ |
343 | static const struct tvp7002_timings_definition tvp7002_timings[] = { | |
0b675536 | 344 | { |
eb8305b1 | 345 | V4L2_DV_BT_CEA_1280X720P60, |
0b675536 SNC |
346 | tvp7002_parms_720P60, |
347 | V4L2_COLORSPACE_REC709, | |
348 | V4L2_FIELD_NONE, | |
349 | 1, | |
350 | 0x2EE, | |
351 | 135, | |
352 | 153 | |
353 | }, | |
354 | { | |
eb8305b1 | 355 | V4L2_DV_BT_CEA_1920X1080I60, |
0b675536 SNC |
356 | tvp7002_parms_1080I60, |
357 | V4L2_COLORSPACE_REC709, | |
358 | V4L2_FIELD_INTERLACED, | |
359 | 0, | |
360 | 0x465, | |
361 | 181, | |
362 | 205 | |
363 | }, | |
364 | { | |
eb8305b1 | 365 | V4L2_DV_BT_CEA_1920X1080I50, |
0b675536 SNC |
366 | tvp7002_parms_1080I50, |
367 | V4L2_COLORSPACE_REC709, | |
368 | V4L2_FIELD_INTERLACED, | |
369 | 0, | |
370 | 0x465, | |
371 | 217, | |
372 | 245 | |
373 | }, | |
374 | { | |
eb8305b1 | 375 | V4L2_DV_BT_CEA_1280X720P50, |
0b675536 SNC |
376 | tvp7002_parms_720P50, |
377 | V4L2_COLORSPACE_REC709, | |
378 | V4L2_FIELD_NONE, | |
379 | 1, | |
380 | 0x2EE, | |
381 | 163, | |
382 | 183 | |
383 | }, | |
384 | { | |
eb8305b1 | 385 | V4L2_DV_BT_CEA_1920X1080P60, |
0b675536 SNC |
386 | tvp7002_parms_1080P60, |
387 | V4L2_COLORSPACE_REC709, | |
388 | V4L2_FIELD_NONE, | |
389 | 1, | |
390 | 0x465, | |
391 | 90, | |
392 | 102 | |
393 | }, | |
394 | { | |
eb8305b1 | 395 | V4L2_DV_BT_CEA_720X480P59_94, |
0b675536 SNC |
396 | tvp7002_parms_480P, |
397 | V4L2_COLORSPACE_SMPTE170M, | |
398 | V4L2_FIELD_NONE, | |
399 | 1, | |
400 | 0x20D, | |
401 | 0xffff, | |
402 | 0xffff | |
403 | }, | |
404 | { | |
eb8305b1 | 405 | V4L2_DV_BT_CEA_720X576P50, |
0b675536 SNC |
406 | tvp7002_parms_576P, |
407 | V4L2_COLORSPACE_SMPTE170M, | |
408 | V4L2_FIELD_NONE, | |
409 | 1, | |
410 | 0x271, | |
411 | 0xffff, | |
412 | 0xffff | |
413 | } | |
414 | }; | |
415 | ||
f0cd015e | 416 | #define NUM_TIMINGS ARRAY_SIZE(tvp7002_timings) |
0b675536 SNC |
417 | |
418 | /* Device definition */ | |
419 | struct tvp7002 { | |
420 | struct v4l2_subdev sd; | |
0eb73de0 | 421 | struct v4l2_ctrl_handler hdl; |
0b675536 SNC |
422 | const struct tvp7002_config *pdata; |
423 | ||
424 | int ver; | |
425 | int streaming; | |
426 | ||
f0cd015e | 427 | const struct tvp7002_timings_definition *current_timings; |
63eb2ca1 | 428 | struct media_pad pad; |
0b675536 SNC |
429 | }; |
430 | ||
431 | /* | |
432 | * to_tvp7002 - Obtain device handler TVP7002 | |
433 | * @sd: ptr to v4l2_subdev struct | |
434 | * | |
435 | * Returns device handler tvp7002. | |
436 | */ | |
437 | static inline struct tvp7002 *to_tvp7002(struct v4l2_subdev *sd) | |
438 | { | |
439 | return container_of(sd, struct tvp7002, sd); | |
440 | } | |
441 | ||
0eb73de0 HV |
442 | static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) |
443 | { | |
444 | return &container_of(ctrl->handler, struct tvp7002, hdl)->sd; | |
445 | } | |
446 | ||
0b675536 SNC |
447 | /* |
448 | * tvp7002_read - Read a value from a register in an TVP7002 | |
449 | * @sd: ptr to v4l2_subdev struct | |
6fa7dac4 | 450 | * @addr: TVP7002 register address |
0b675536 SNC |
451 | * @dst: pointer to 8-bit destination |
452 | * | |
453 | * Returns value read if successful, or non-zero (-1) otherwise. | |
454 | */ | |
455 | static int tvp7002_read(struct v4l2_subdev *sd, u8 addr, u8 *dst) | |
456 | { | |
457 | struct i2c_client *c = v4l2_get_subdevdata(sd); | |
458 | int retry; | |
459 | int error; | |
460 | ||
461 | for (retry = 0; retry < I2C_RETRY_COUNT; retry++) { | |
462 | error = i2c_smbus_read_byte_data(c, addr); | |
463 | ||
464 | if (error >= 0) { | |
465 | *dst = (u8)error; | |
466 | return 0; | |
467 | } | |
468 | ||
469 | msleep_interruptible(10); | |
470 | } | |
471 | v4l2_err(sd, "TVP7002 read error %d\n", error); | |
472 | return error; | |
473 | } | |
474 | ||
475 | /* | |
476 | * tvp7002_read_err() - Read a register value with error code | |
477 | * @sd: pointer to standard V4L2 sub-device structure | |
478 | * @reg: destination register | |
479 | * @val: value to be read | |
6fa7dac4 | 480 | * @err: pointer to error value |
0b675536 SNC |
481 | * |
482 | * Read a value in a register and save error value in pointer. | |
483 | * Also update the register table if successful | |
484 | */ | |
485 | static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg, | |
486 | u8 *dst, int *err) | |
487 | { | |
488 | if (!*err) | |
489 | *err = tvp7002_read(sd, reg, dst); | |
490 | } | |
491 | ||
492 | /* | |
493 | * tvp7002_write() - Write a value to a register in TVP7002 | |
494 | * @sd: ptr to v4l2_subdev struct | |
495 | * @addr: TVP7002 register address | |
496 | * @value: value to be written to the register | |
497 | * | |
498 | * Write a value to a register in an TVP7002 decoder device. | |
499 | * Returns zero if successful, or non-zero otherwise. | |
500 | */ | |
501 | static int tvp7002_write(struct v4l2_subdev *sd, u8 addr, u8 value) | |
502 | { | |
503 | struct i2c_client *c; | |
504 | int retry; | |
505 | int error; | |
506 | ||
507 | c = v4l2_get_subdevdata(sd); | |
508 | ||
509 | for (retry = 0; retry < I2C_RETRY_COUNT; retry++) { | |
510 | error = i2c_smbus_write_byte_data(c, addr, value); | |
511 | ||
512 | if (error >= 0) | |
513 | return 0; | |
514 | ||
515 | v4l2_warn(sd, "Write: retry ... %d\n", retry); | |
516 | msleep_interruptible(10); | |
517 | } | |
518 | v4l2_err(sd, "TVP7002 write error %d\n", error); | |
519 | return error; | |
520 | } | |
521 | ||
522 | /* | |
523 | * tvp7002_write_err() - Write a register value with error code | |
524 | * @sd: pointer to standard V4L2 sub-device structure | |
525 | * @reg: destination register | |
526 | * @val: value to be written | |
6fa7dac4 | 527 | * @err: pointer to error value |
0b675536 SNC |
528 | * |
529 | * Write a value in a register and save error value in pointer. | |
530 | * Also update the register table if successful | |
531 | */ | |
532 | static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg, | |
533 | u8 val, int *err) | |
534 | { | |
535 | if (!*err) | |
536 | *err = tvp7002_write(sd, reg, val); | |
537 | } | |
538 | ||
0b675536 SNC |
539 | /* |
540 | * tvp7002_write_inittab() - Write initialization values | |
541 | * @sd: ptr to v4l2_subdev struct | |
542 | * @regs: ptr to i2c_reg_value struct | |
543 | * | |
544 | * Write initialization values. | |
545 | * Returns zero or -EINVAL if read operation fails. | |
546 | */ | |
547 | static int tvp7002_write_inittab(struct v4l2_subdev *sd, | |
548 | const struct i2c_reg_value *regs) | |
549 | { | |
550 | int error = 0; | |
551 | ||
552 | /* Initialize the first (defined) registers */ | |
553 | while (TVP7002_EOR != regs->reg) { | |
554 | if (TVP7002_WRITE == regs->type) | |
555 | tvp7002_write_err(sd, regs->reg, regs->value, &error); | |
556 | regs++; | |
557 | } | |
558 | ||
559 | return error; | |
560 | } | |
561 | ||
eb8305b1 HV |
562 | static int tvp7002_s_dv_timings(struct v4l2_subdev *sd, |
563 | struct v4l2_dv_timings *dv_timings) | |
564 | { | |
565 | struct tvp7002 *device = to_tvp7002(sd); | |
566 | const struct v4l2_bt_timings *bt = &dv_timings->bt; | |
567 | int i; | |
568 | ||
569 | if (dv_timings->type != V4L2_DV_BT_656_1120) | |
570 | return -EINVAL; | |
f0cd015e HV |
571 | for (i = 0; i < NUM_TIMINGS; i++) { |
572 | const struct v4l2_bt_timings *t = &tvp7002_timings[i].timings.bt; | |
eb8305b1 HV |
573 | |
574 | if (!memcmp(bt, t, &bt->standards - &bt->width)) { | |
f0cd015e HV |
575 | device->current_timings = &tvp7002_timings[i]; |
576 | return tvp7002_write_inittab(sd, tvp7002_timings[i].p_settings); | |
eb8305b1 HV |
577 | } |
578 | } | |
579 | return -EINVAL; | |
580 | } | |
581 | ||
582 | static int tvp7002_g_dv_timings(struct v4l2_subdev *sd, | |
583 | struct v4l2_dv_timings *dv_timings) | |
584 | { | |
585 | struct tvp7002 *device = to_tvp7002(sd); | |
586 | ||
f0cd015e | 587 | *dv_timings = device->current_timings->timings; |
eb8305b1 HV |
588 | return 0; |
589 | } | |
590 | ||
0b675536 SNC |
591 | /* |
592 | * tvp7002_s_ctrl() - Set a control | |
0eb73de0 | 593 | * @ctrl: ptr to v4l2_ctrl struct |
0b675536 SNC |
594 | * |
595 | * Set a control in TVP7002 decoder device. | |
596 | * Returns zero when successful or -EINVAL if register access fails. | |
597 | */ | |
0eb73de0 | 598 | static int tvp7002_s_ctrl(struct v4l2_ctrl *ctrl) |
0b675536 | 599 | { |
0eb73de0 | 600 | struct v4l2_subdev *sd = to_sd(ctrl); |
0b675536 SNC |
601 | int error = 0; |
602 | ||
603 | switch (ctrl->id) { | |
604 | case V4L2_CID_GAIN: | |
0eb73de0 HV |
605 | tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error); |
606 | tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error); | |
607 | tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error); | |
608 | return error; | |
0b675536 | 609 | } |
0eb73de0 | 610 | return -EINVAL; |
0b675536 SNC |
611 | } |
612 | ||
db7b5460 HV |
613 | /* |
614 | * tvp7002_mbus_fmt() - V4L2 decoder interface handler for try/s/g_mbus_fmt | |
615 | * @sd: pointer to standard V4L2 sub-device structure | |
616 | * @f: pointer to mediabus format structure | |
617 | * | |
618 | * Negotiate the image capture size and mediabus format. | |
619 | * There is only one possible format, so this single function works for | |
620 | * get, set and try. | |
621 | */ | |
622 | static int tvp7002_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *f) | |
623 | { | |
624 | struct tvp7002 *device = to_tvp7002(sd); | |
f96067af | 625 | const struct v4l2_bt_timings *bt = &device->current_timings->timings.bt; |
db7b5460 | 626 | |
f96067af HV |
627 | f->width = bt->width; |
628 | f->height = bt->height; | |
db7b5460 | 629 | f->code = V4L2_MBUS_FMT_YUYV10_1X20; |
f0cd015e HV |
630 | f->field = device->current_timings->scanmode; |
631 | f->colorspace = device->current_timings->color_space; | |
db7b5460 HV |
632 | |
633 | v4l2_dbg(1, debug, sd, "MBUS_FMT: Width - %d, Height - %d", | |
634 | f->width, f->height); | |
635 | return 0; | |
636 | } | |
637 | ||
0b675536 | 638 | /* |
f0cd015e | 639 | * tvp7002_query_dv() - query DV timings |
0b675536 | 640 | * @sd: pointer to standard V4L2 sub-device structure |
f0cd015e | 641 | * @index: index into the tvp7002_timings array |
0b675536 | 642 | * |
f0cd015e | 643 | * Returns the current DV timings detected by TVP7002. If no active input is |
0b675536 SNC |
644 | * detected, returns -EINVAL |
645 | */ | |
eb8305b1 | 646 | static int tvp7002_query_dv(struct v4l2_subdev *sd, int *index) |
0b675536 | 647 | { |
f0cd015e | 648 | const struct tvp7002_timings_definition *timings = tvp7002_timings; |
0b675536 SNC |
649 | u8 progressive; |
650 | u32 lpfr; | |
651 | u32 cpln; | |
652 | int error = 0; | |
653 | u8 lpf_lsb; | |
654 | u8 lpf_msb; | |
655 | u8 cpl_lsb; | |
656 | u8 cpl_msb; | |
0b675536 | 657 | |
eb8305b1 | 658 | /* Return invalid index if no active input is detected */ |
f0cd015e | 659 | *index = NUM_TIMINGS; |
ab0ab190 | 660 | |
0b675536 SNC |
661 | /* Read standards from device registers */ |
662 | tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_LSBS, &lpf_lsb, &error); | |
663 | tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_MSBS, &lpf_msb, &error); | |
664 | ||
665 | if (error < 0) | |
666 | return error; | |
667 | ||
668 | tvp7002_read_err(sd, TVP7002_CLK_L_STAT_LSBS, &cpl_lsb, &error); | |
669 | tvp7002_read_err(sd, TVP7002_CLK_L_STAT_MSBS, &cpl_msb, &error); | |
670 | ||
671 | if (error < 0) | |
672 | return error; | |
673 | ||
674 | /* Get lines per frame, clocks per line and interlaced/progresive */ | |
675 | lpfr = lpf_lsb | ((TVP7002_CL_MASK & lpf_msb) << TVP7002_CL_SHIFT); | |
676 | cpln = cpl_lsb | ((TVP7002_CL_MASK & cpl_msb) << TVP7002_CL_SHIFT); | |
677 | progressive = (lpf_msb & TVP7002_INPR_MASK) >> TVP7002_IP_SHIFT; | |
678 | ||
679 | /* Do checking of video modes */ | |
f0cd015e HV |
680 | for (*index = 0; *index < NUM_TIMINGS; (*index)++, timings++) |
681 | if (lpfr == timings->lines_per_frame && | |
682 | progressive == timings->progressive) { | |
683 | if (timings->cpl_min == 0xffff) | |
0b675536 | 684 | break; |
f0cd015e | 685 | if (cpln >= timings->cpl_min && cpln <= timings->cpl_max) |
0b675536 SNC |
686 | break; |
687 | } | |
688 | ||
f0cd015e | 689 | if (*index == NUM_TIMINGS) { |
cf19cd3d | 690 | v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n", |
0b675536 | 691 | lpfr, cpln); |
eb8305b1 | 692 | return -ENOLINK; |
0b675536 SNC |
693 | } |
694 | ||
0b675536 | 695 | /* Update lines per frame and clocks per line info */ |
f0cd015e | 696 | v4l2_dbg(1, debug, sd, "detected timings: %d\n", *index); |
eb8305b1 HV |
697 | return 0; |
698 | } | |
699 | ||
eb8305b1 HV |
700 | static int tvp7002_query_dv_timings(struct v4l2_subdev *sd, |
701 | struct v4l2_dv_timings *timings) | |
702 | { | |
703 | int index; | |
704 | int err = tvp7002_query_dv(sd, &index); | |
705 | ||
706 | if (err) | |
707 | return err; | |
f0cd015e | 708 | *timings = tvp7002_timings[index].timings; |
0b675536 SNC |
709 | return 0; |
710 | } | |
711 | ||
712 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
713 | /* | |
714 | * tvp7002_g_register() - Get the value of a register | |
715 | * @sd: ptr to v4l2_subdev struct | |
6fa7dac4 | 716 | * @reg: ptr to v4l2_dbg_register struct |
0b675536 SNC |
717 | * |
718 | * Get the value of a TVP7002 decoder device register. | |
719 | * Returns zero when successful, -EINVAL if register read fails or | |
7e89bd9f | 720 | * access to I2C client fails. |
0b675536 SNC |
721 | */ |
722 | static int tvp7002_g_register(struct v4l2_subdev *sd, | |
723 | struct v4l2_dbg_register *reg) | |
724 | { | |
dfbd5d4d HV |
725 | u8 val; |
726 | int ret; | |
0b675536 | 727 | |
dfbd5d4d HV |
728 | ret = tvp7002_read(sd, reg->reg & 0xff, &val); |
729 | reg->val = val; | |
15c4fee3 | 730 | reg->size = 1; |
dfbd5d4d | 731 | return ret; |
0b675536 SNC |
732 | } |
733 | ||
734 | /* | |
735 | * tvp7002_s_register() - set a control | |
736 | * @sd: ptr to v4l2_subdev struct | |
6fa7dac4 | 737 | * @reg: ptr to v4l2_dbg_register struct |
0b675536 SNC |
738 | * |
739 | * Get the value of a TVP7002 decoder device register. | |
7e89bd9f | 740 | * Returns zero when successful, -EINVAL if register read fails. |
0b675536 SNC |
741 | */ |
742 | static int tvp7002_s_register(struct v4l2_subdev *sd, | |
977ba3b1 | 743 | const struct v4l2_dbg_register *reg) |
0b675536 | 744 | { |
dfbd5d4d | 745 | return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff); |
0b675536 SNC |
746 | } |
747 | #endif | |
748 | ||
db7b5460 HV |
749 | /* |
750 | * tvp7002_enum_mbus_fmt() - Enum supported mediabus formats | |
751 | * @sd: pointer to standard V4L2 sub-device structure | |
752 | * @index: format index | |
753 | * @code: pointer to mediabus format | |
754 | * | |
755 | * Enumerate supported mediabus formats. | |
756 | */ | |
757 | ||
758 | static int tvp7002_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index, | |
759 | enum v4l2_mbus_pixelcode *code) | |
760 | { | |
761 | /* Check requested format index is within range */ | |
762 | if (index) | |
763 | return -EINVAL; | |
764 | *code = V4L2_MBUS_FMT_YUYV10_1X20; | |
765 | return 0; | |
766 | } | |
767 | ||
0b675536 SNC |
768 | /* |
769 | * tvp7002_s_stream() - V4L2 decoder i/f handler for s_stream | |
770 | * @sd: pointer to standard V4L2 sub-device structure | |
771 | * @enable: streaming enable or disable | |
772 | * | |
773 | * Sets streaming to enable or disable, if possible. | |
774 | */ | |
775 | static int tvp7002_s_stream(struct v4l2_subdev *sd, int enable) | |
776 | { | |
777 | struct tvp7002 *device = to_tvp7002(sd); | |
778 | int error = 0; | |
779 | ||
780 | if (device->streaming == enable) | |
781 | return 0; | |
782 | ||
783 | if (enable) { | |
784 | /* Set output state on (low impedance means stream on) */ | |
785 | error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x00); | |
786 | device->streaming = enable; | |
787 | } else { | |
788 | /* Set output state off (high impedance means stream off) */ | |
789 | error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x03); | |
790 | if (error) | |
791 | v4l2_dbg(1, debug, sd, "Unable to stop streaming\n"); | |
792 | ||
793 | device->streaming = enable; | |
794 | } | |
795 | ||
796 | return error; | |
797 | } | |
798 | ||
799 | /* | |
800 | * tvp7002_log_status() - Print information about register settings | |
801 | * @sd: ptr to v4l2_subdev struct | |
802 | * | |
803 | * Log register values of a TVP7002 decoder device. | |
804 | * Returns zero or -EINVAL if read operation fails. | |
805 | */ | |
806 | static int tvp7002_log_status(struct v4l2_subdev *sd) | |
807 | { | |
0b675536 | 808 | struct tvp7002 *device = to_tvp7002(sd); |
f96067af HV |
809 | const struct v4l2_bt_timings *bt; |
810 | int detected; | |
0b675536 | 811 | |
f96067af HV |
812 | /* Find my current timings */ |
813 | tvp7002_query_dv(sd, &detected); | |
0b675536 | 814 | |
f96067af HV |
815 | bt = &device->current_timings->timings.bt; |
816 | v4l2_info(sd, "Selected DV Timings: %ux%u\n", bt->width, bt->height); | |
817 | if (detected == NUM_TIMINGS) { | |
818 | v4l2_info(sd, "Detected DV Timings: None\n"); | |
0b675536 | 819 | } else { |
f96067af HV |
820 | bt = &tvp7002_timings[detected].timings.bt; |
821 | v4l2_info(sd, "Detected DV Timings: %ux%u\n", | |
822 | bt->width, bt->height); | |
0b675536 SNC |
823 | } |
824 | v4l2_info(sd, "Streaming enabled: %s\n", | |
825 | device->streaming ? "yes" : "no"); | |
826 | ||
827 | /* Print the current value of the gain control */ | |
0eb73de0 | 828 | v4l2_ctrl_handler_log_status(&device->hdl, sd->name); |
0b675536 SNC |
829 | |
830 | return 0; | |
831 | } | |
832 | ||
eb8305b1 HV |
833 | static int tvp7002_enum_dv_timings(struct v4l2_subdev *sd, |
834 | struct v4l2_enum_dv_timings *timings) | |
835 | { | |
307d3bd4 LP |
836 | if (timings->pad != 0) |
837 | return -EINVAL; | |
838 | ||
eb8305b1 | 839 | /* Check requested format index is within range */ |
f0cd015e | 840 | if (timings->index >= NUM_TIMINGS) |
eb8305b1 HV |
841 | return -EINVAL; |
842 | ||
f0cd015e | 843 | timings->timings = tvp7002_timings[timings->index].timings; |
eb8305b1 HV |
844 | return 0; |
845 | } | |
846 | ||
0eb73de0 HV |
847 | static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = { |
848 | .s_ctrl = tvp7002_s_ctrl, | |
849 | }; | |
850 | ||
63eb2ca1 LP |
851 | /* |
852 | * tvp7002_enum_mbus_code() - Enum supported digital video format on pad | |
853 | * @sd: pointer to standard V4L2 sub-device structure | |
854 | * @fh: file handle for the subdev | |
855 | * @code: pointer to subdev enum mbus code struct | |
856 | * | |
857 | * Enumerate supported digital video formats for pad. | |
858 | */ | |
859 | static int | |
860 | tvp7002_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
861 | struct v4l2_subdev_mbus_code_enum *code) | |
862 | { | |
863 | /* Check requested format index is within range */ | |
864 | if (code->index != 0) | |
865 | return -EINVAL; | |
866 | ||
867 | code->code = V4L2_MBUS_FMT_YUYV10_1X20; | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
872 | /* | |
873 | * tvp7002_get_pad_format() - get video format on pad | |
874 | * @sd: pointer to standard V4L2 sub-device structure | |
875 | * @fh: file handle for the subdev | |
876 | * @fmt: pointer to subdev format struct | |
877 | * | |
878 | * get video format for pad. | |
879 | */ | |
880 | static int | |
881 | tvp7002_get_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
882 | struct v4l2_subdev_format *fmt) | |
883 | { | |
884 | struct tvp7002 *tvp7002 = to_tvp7002(sd); | |
885 | ||
886 | fmt->format.code = V4L2_MBUS_FMT_YUYV10_1X20; | |
887 | fmt->format.width = tvp7002->current_timings->timings.bt.width; | |
888 | fmt->format.height = tvp7002->current_timings->timings.bt.height; | |
889 | fmt->format.field = tvp7002->current_timings->scanmode; | |
890 | fmt->format.colorspace = tvp7002->current_timings->color_space; | |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
895 | /* | |
896 | * tvp7002_set_pad_format() - set video format on pad | |
897 | * @sd: pointer to standard V4L2 sub-device structure | |
898 | * @fh: file handle for the subdev | |
899 | * @fmt: pointer to subdev format struct | |
900 | * | |
901 | * set video format for pad. | |
902 | */ | |
903 | static int | |
904 | tvp7002_set_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
905 | struct v4l2_subdev_format *fmt) | |
906 | { | |
907 | return tvp7002_get_pad_format(sd, fh, fmt); | |
908 | } | |
909 | ||
0b675536 SNC |
910 | /* V4L2 core operation handlers */ |
911 | static const struct v4l2_subdev_core_ops tvp7002_core_ops = { | |
0b675536 | 912 | .log_status = tvp7002_log_status, |
0eb73de0 HV |
913 | .g_ext_ctrls = v4l2_subdev_g_ext_ctrls, |
914 | .try_ext_ctrls = v4l2_subdev_try_ext_ctrls, | |
915 | .s_ext_ctrls = v4l2_subdev_s_ext_ctrls, | |
916 | .g_ctrl = v4l2_subdev_g_ctrl, | |
917 | .s_ctrl = v4l2_subdev_s_ctrl, | |
918 | .queryctrl = v4l2_subdev_queryctrl, | |
919 | .querymenu = v4l2_subdev_querymenu, | |
0b675536 SNC |
920 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
921 | .g_register = tvp7002_g_register, | |
922 | .s_register = tvp7002_s_register, | |
923 | #endif | |
924 | }; | |
925 | ||
926 | /* Specific video subsystem operation handlers */ | |
927 | static const struct v4l2_subdev_video_ops tvp7002_video_ops = { | |
eb8305b1 HV |
928 | .g_dv_timings = tvp7002_g_dv_timings, |
929 | .s_dv_timings = tvp7002_s_dv_timings, | |
eb8305b1 | 930 | .query_dv_timings = tvp7002_query_dv_timings, |
0b675536 | 931 | .s_stream = tvp7002_s_stream, |
db7b5460 HV |
932 | .g_mbus_fmt = tvp7002_mbus_fmt, |
933 | .try_mbus_fmt = tvp7002_mbus_fmt, | |
934 | .s_mbus_fmt = tvp7002_mbus_fmt, | |
935 | .enum_mbus_fmt = tvp7002_enum_mbus_fmt, | |
0b675536 SNC |
936 | }; |
937 | ||
63eb2ca1 LP |
938 | /* media pad related operation handlers */ |
939 | static const struct v4l2_subdev_pad_ops tvp7002_pad_ops = { | |
940 | .enum_mbus_code = tvp7002_enum_mbus_code, | |
941 | .get_fmt = tvp7002_get_pad_format, | |
942 | .set_fmt = tvp7002_set_pad_format, | |
307d3bd4 | 943 | .enum_dv_timings = tvp7002_enum_dv_timings, |
63eb2ca1 LP |
944 | }; |
945 | ||
0b675536 SNC |
946 | /* V4L2 top level operation handlers */ |
947 | static const struct v4l2_subdev_ops tvp7002_ops = { | |
948 | .core = &tvp7002_core_ops, | |
949 | .video = &tvp7002_video_ops, | |
63eb2ca1 | 950 | .pad = &tvp7002_pad_ops, |
0b675536 SNC |
951 | }; |
952 | ||
c0d9644f LP |
953 | static struct tvp7002_config * |
954 | tvp7002_get_pdata(struct i2c_client *client) | |
955 | { | |
956 | struct v4l2_of_endpoint bus_cfg; | |
957 | struct tvp7002_config *pdata; | |
958 | struct device_node *endpoint; | |
959 | unsigned int flags; | |
960 | ||
961 | if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) | |
962 | return client->dev.platform_data; | |
963 | ||
fd9fdb78 | 964 | endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL); |
c0d9644f LP |
965 | if (!endpoint) |
966 | return NULL; | |
967 | ||
968 | pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); | |
969 | if (!pdata) | |
970 | goto done; | |
971 | ||
972 | v4l2_of_parse_endpoint(endpoint, &bus_cfg); | |
973 | flags = bus_cfg.bus.parallel.flags; | |
974 | ||
975 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) | |
976 | pdata->hs_polarity = 1; | |
977 | ||
978 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) | |
979 | pdata->vs_polarity = 1; | |
980 | ||
981 | if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) | |
982 | pdata->clk_polarity = 1; | |
983 | ||
984 | if (flags & V4L2_MBUS_FIELD_EVEN_HIGH) | |
985 | pdata->fid_polarity = 1; | |
986 | ||
987 | if (flags & V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH) | |
988 | pdata->sog_polarity = 1; | |
989 | ||
990 | done: | |
991 | of_node_put(endpoint); | |
992 | return pdata; | |
993 | } | |
994 | ||
0b675536 SNC |
995 | /* |
996 | * tvp7002_probe - Probe a TVP7002 device | |
6fa7dac4 MR |
997 | * @c: ptr to i2c_client struct |
998 | * @id: ptr to i2c_device_id struct | |
0b675536 SNC |
999 | * |
1000 | * Initialize the TVP7002 device | |
1001 | * Returns zero when successful, -EINVAL if register read fails or | |
1002 | * -EIO if i2c access is not available. | |
1003 | */ | |
1004 | static int tvp7002_probe(struct i2c_client *c, const struct i2c_device_id *id) | |
1005 | { | |
c0d9644f | 1006 | struct tvp7002_config *pdata = tvp7002_get_pdata(c); |
0b675536 SNC |
1007 | struct v4l2_subdev *sd; |
1008 | struct tvp7002 *device; | |
f96067af | 1009 | struct v4l2_dv_timings timings; |
0b675536 SNC |
1010 | int polarity_a; |
1011 | int polarity_b; | |
1012 | u8 revision; | |
0b675536 SNC |
1013 | int error; |
1014 | ||
c0d9644f LP |
1015 | if (pdata == NULL) { |
1016 | dev_err(&c->dev, "No platform data\n"); | |
1017 | return -EINVAL; | |
1018 | } | |
1019 | ||
0b675536 SNC |
1020 | /* Check if the adapter supports the needed features */ |
1021 | if (!i2c_check_functionality(c->adapter, | |
1022 | I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) | |
1023 | return -EIO; | |
1024 | ||
f3e8e4f1 | 1025 | device = devm_kzalloc(&c->dev, sizeof(struct tvp7002), GFP_KERNEL); |
0b675536 SNC |
1026 | |
1027 | if (!device) | |
1028 | return -ENOMEM; | |
1029 | ||
0b675536 | 1030 | sd = &device->sd; |
c0d9644f | 1031 | device->pdata = pdata; |
f0cd015e | 1032 | device->current_timings = tvp7002_timings; |
0b675536 SNC |
1033 | |
1034 | /* Tell v4l2 the device is ready */ | |
1035 | v4l2_i2c_subdev_init(sd, c, &tvp7002_ops); | |
1036 | v4l_info(c, "tvp7002 found @ 0x%02x (%s)\n", | |
1037 | c->addr, c->adapter->name); | |
1038 | ||
1039 | error = tvp7002_read(sd, TVP7002_CHIP_REV, &revision); | |
1040 | if (error < 0) | |
f3e8e4f1 | 1041 | return error; |
0b675536 SNC |
1042 | |
1043 | /* Get revision number */ | |
1044 | v4l2_info(sd, "Rev. %02x detected.\n", revision); | |
1045 | if (revision != 0x02) | |
1046 | v4l2_info(sd, "Unknown revision detected.\n"); | |
1047 | ||
1048 | /* Initializes TVP7002 to its default values */ | |
1049 | error = tvp7002_write_inittab(sd, tvp7002_init_default); | |
1050 | ||
1051 | if (error < 0) | |
f3e8e4f1 | 1052 | return error; |
0b675536 SNC |
1053 | |
1054 | /* Set polarity information after registers have been set */ | |
1055 | polarity_a = 0x20 | device->pdata->hs_polarity << 5 | |
1056 | | device->pdata->vs_polarity << 2; | |
1057 | error = tvp7002_write(sd, TVP7002_SYNC_CTL_1, polarity_a); | |
1058 | if (error < 0) | |
f3e8e4f1 | 1059 | return error; |
0b675536 SNC |
1060 | |
1061 | polarity_b = 0x01 | device->pdata->fid_polarity << 2 | |
1062 | | device->pdata->sog_polarity << 1 | |
1063 | | device->pdata->clk_polarity; | |
1064 | error = tvp7002_write(sd, TVP7002_MISC_CTL_3, polarity_b); | |
1065 | if (error < 0) | |
f3e8e4f1 | 1066 | return error; |
0b675536 SNC |
1067 | |
1068 | /* Set registers according to default video mode */ | |
f96067af HV |
1069 | timings = device->current_timings->timings; |
1070 | error = tvp7002_s_dv_timings(sd, &timings); | |
0b675536 | 1071 | |
63eb2ca1 | 1072 | #if defined(CONFIG_MEDIA_CONTROLLER) |
63eb2ca1 LP |
1073 | device->pad.flags = MEDIA_PAD_FL_SOURCE; |
1074 | device->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; | |
1075 | device->sd.entity.flags |= MEDIA_ENT_T_V4L2_SUBDEV_DECODER; | |
1076 | ||
1077 | error = media_entity_init(&device->sd.entity, 1, &device->pad, 0); | |
1078 | if (error < 0) | |
1079 | return error; | |
1080 | #endif | |
1081 | ||
0eb73de0 HV |
1082 | v4l2_ctrl_handler_init(&device->hdl, 1); |
1083 | v4l2_ctrl_new_std(&device->hdl, &tvp7002_ctrl_ops, | |
1084 | V4L2_CID_GAIN, 0, 255, 1, 0); | |
1085 | sd->ctrl_handler = &device->hdl; | |
1086 | if (device->hdl.error) { | |
63eb2ca1 LP |
1087 | error = device->hdl.error; |
1088 | goto error; | |
0eb73de0 HV |
1089 | } |
1090 | v4l2_ctrl_handler_setup(&device->hdl); | |
1091 | ||
25ba2c80 LP |
1092 | error = v4l2_async_register_subdev(&device->sd); |
1093 | if (error) | |
1094 | goto error; | |
1095 | ||
f3e8e4f1 | 1096 | return 0; |
63eb2ca1 LP |
1097 | |
1098 | error: | |
1099 | v4l2_ctrl_handler_free(&device->hdl); | |
1100 | #if defined(CONFIG_MEDIA_CONTROLLER) | |
1101 | media_entity_cleanup(&device->sd.entity); | |
1102 | #endif | |
1103 | return error; | |
0b675536 SNC |
1104 | } |
1105 | ||
1106 | /* | |
1107 | * tvp7002_remove - Remove TVP7002 device support | |
1108 | * @c: ptr to i2c_client struct | |
1109 | * | |
1110 | * Reset the TVP7002 device | |
1111 | * Returns zero. | |
1112 | */ | |
1113 | static int tvp7002_remove(struct i2c_client *c) | |
1114 | { | |
1115 | struct v4l2_subdev *sd = i2c_get_clientdata(c); | |
1116 | struct tvp7002 *device = to_tvp7002(sd); | |
1117 | ||
1118 | v4l2_dbg(1, debug, sd, "Removing tvp7002 adapter" | |
1119 | "on address 0x%x\n", c->addr); | |
25ba2c80 | 1120 | v4l2_async_unregister_subdev(&device->sd); |
63eb2ca1 LP |
1121 | #if defined(CONFIG_MEDIA_CONTROLLER) |
1122 | media_entity_cleanup(&device->sd.entity); | |
1123 | #endif | |
0b675536 | 1124 | v4l2_device_unregister_subdev(sd); |
0eb73de0 | 1125 | v4l2_ctrl_handler_free(&device->hdl); |
0b675536 SNC |
1126 | return 0; |
1127 | } | |
1128 | ||
1129 | /* I2C Device ID table */ | |
1130 | static const struct i2c_device_id tvp7002_id[] = { | |
1131 | { "tvp7002", 0 }, | |
1132 | { } | |
1133 | }; | |
1134 | MODULE_DEVICE_TABLE(i2c, tvp7002_id); | |
1135 | ||
c0d9644f LP |
1136 | #if IS_ENABLED(CONFIG_OF) |
1137 | static const struct of_device_id tvp7002_of_match[] = { | |
1138 | { .compatible = "ti,tvp7002", }, | |
1139 | { /* sentinel */ }, | |
1140 | }; | |
1141 | MODULE_DEVICE_TABLE(of, tvp7002_of_match); | |
1142 | #endif | |
1143 | ||
0b675536 SNC |
1144 | /* I2C driver data */ |
1145 | static struct i2c_driver tvp7002_driver = { | |
1146 | .driver = { | |
c0d9644f | 1147 | .of_match_table = of_match_ptr(tvp7002_of_match), |
0b675536 SNC |
1148 | .owner = THIS_MODULE, |
1149 | .name = TVP7002_MODULE_NAME, | |
1150 | }, | |
1151 | .probe = tvp7002_probe, | |
1152 | .remove = tvp7002_remove, | |
1153 | .id_table = tvp7002_id, | |
1154 | }; | |
1155 | ||
c6e8d86f | 1156 | module_i2c_driver(tvp7002_driver); |