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[media] saa7164: fix sparse warnings
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885.h
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
d19770e5
ST		 16 */
17
18#include <linux/pci.h>
19#include <linux/i2c.h>
d19770e5 20#include <linux/kdev_t.h>
5a0e3ad6 21#include <linux/slab.h>
d19770e5 22
c0714f6c 23#include <media/v4l2-device.h>
86dd9831 24#include <media/v4l2-fh.h>
da59a4de 25#include <media/v4l2-ctrls.h>
d19770e5
ST		 26#include <media/tuner.h>
27#include <media/tveeprom.h>
453afdd9
HV		 28#include <media/videobuf2-dma-sg.h>
29#include <media/videobuf2-dvb.h>
6bda9644 30#include <media/rc-core.h>
d19770e5 31
d19770e5 32#include "cx23885-reg.h"
b1b81f1d 33#include "media/cx2341x.h"
d19770e5 34
d19770e5
ST		 35#include <linux/mutex.h>
36
453afdd9 37#define CX23885_VERSION "0.0.4"
d19770e5
ST		 38
39#define UNSET (-1U)
40
41#define CX23885_MAXBOARDS 8
42
d19770e5
ST		 43/* Max number of inputs by card */
44#define MAX_CX23885_INPUT 8
7b888014 45#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
d19770e5 46
d19770e5
ST		 47#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
48
49#define CX23885_BOARD_NOAUTO UNSET
50#define CX23885_BOARD_UNKNOWN 0
51#define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
52#define CX23885_BOARD_HAUPPAUGE_HVR1800 2
a77743bc 53#define CX23885_BOARD_HAUPPAUGE_HVR1250 3
9bc37caa 54#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
d1987d55 55#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
07b4a835 56#define CX23885_BOARD_HAUPPAUGE_HVR1500 6
b3ea0166 57#define CX23885_BOARD_HAUPPAUGE_HVR1200 7
a780a31c 58#define CX23885_BOARD_HAUPPAUGE_HVR1700 8
66762373 59#define CX23885_BOARD_HAUPPAUGE_HVR1400 9
335377b7 60#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
aef2d186 61#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
4c56b04a 62#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
9bb1b7e8 63#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
96318d0c 64#define CX23885_BOARD_TBS_6920 14
579943f5 65#define CX23885_BOARD_TEVII_S470 15
c9b8b04b 66#define CX23885_BOARD_DVBWORLD_2005 16
5a23b076 67#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
2074dffa 68#define CX23885_BOARD_HAUPPAUGE_HVR1270 18
d099becb 69#define CX23885_BOARD_HAUPPAUGE_HVR1275 19
19bc5796 70#define CX23885_BOARD_HAUPPAUGE_HVR1255 20
6b926eca 71#define CX23885_BOARD_HAUPPAUGE_HVR1210 21
493b7127 72#define CX23885_BOARD_MYGICA_X8506 22
2365b2d3 73#define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
13697380 74#define CX23885_BOARD_HAUPPAUGE_HVR1850 24
34e383dd 75#define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
aee0b24c 76#define CX23885_BOARD_HAUPPAUGE_HVR1290 26
ea5697fe 77#define CX23885_BOARD_MYGICA_X8558PRO 27
0b32d65c 78#define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
9028f58f 79#define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 29
78db8547 80#define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 30
0cf8af57 81#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000 31
2cb9ccd4 82#define CX23885_BOARD_MPX885 32
87988753 83#define CX23885_BOARD_MYGICA_X8507 33
722c90eb 84#define CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL 34
7b134e85 85#define CX23885_BOARD_TEVII_S471 35
0ac60acb 86#define CX23885_BOARD_HAUPPAUGE_HVR1255_22111 36
f667190b 87#define CX23885_BOARD_PROF_8000 37
7c62f5a1 88#define CX23885_BOARD_HAUPPAUGE_HVR4400 38
e8d42373 89#define CX23885_BOARD_AVERMEDIA_HC81R 39
e6001482
LA		 90#define CX23885_BOARD_TBS_6981 40
91#define CX23885_BOARD_TBS_6980 41
642ca1a0 92#define CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200 42
cce11b09 93#define CX23885_BOARD_HAUPPAUGE_IMPACTVCBE 43
46b21bba 94#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2 44
29442266 95#define CX23885_BOARD_DVBSKY_T9580 45
82c10276 96#define CX23885_BOARD_DVBSKY_T980C 46
0e6c7b01 97#define CX23885_BOARD_DVBSKY_S950C 47
61b103e8 98#define CX23885_BOARD_TT_CT2_4500_CI 48
d19770e5 99
6f8bee9b
ST		 100#define GPIO_0 0x00000001
101#define GPIO_1 0x00000002
102#define GPIO_2 0x00000004
103#define GPIO_3 0x00000008
104#define GPIO_4 0x00000010
105#define GPIO_5 0x00000020
106#define GPIO_6 0x00000040
107#define GPIO_7 0x00000080
108#define GPIO_8 0x00000100
109#define GPIO_9 0x00000200
f659c513
ST		 110#define GPIO_10 0x00000400
111#define GPIO_11 0x00000800
112#define GPIO_12 0x00001000
113#define GPIO_13 0x00002000
114#define GPIO_14 0x00004000
115#define GPIO_15 0x00008000
6f8bee9b 116
7b888014
ST		 117/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
118#define CX23885_NORMS (\
119 V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
120 V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
121 V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
122 V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
123
124struct cx23885_fmt {
125 char *name;
126 u32 fourcc; /* v4l2 format id */
127 int depth;
128 int flags;
129 u32 cxformat;
130};
131
7b888014
ST		 132struct cx23885_tvnorm {
133 char *name;
134 v4l2_std_id id;
135 u32 cxiformat;
136 u32 cxoformat;
137};
138
d19770e5
ST		 139enum cx23885_itype {
140 CX23885_VMUX_COMPOSITE1 = 1,
141 CX23885_VMUX_COMPOSITE2,
142 CX23885_VMUX_COMPOSITE3,
143 CX23885_VMUX_COMPOSITE4,
144 CX23885_VMUX_SVIDEO,
dac65fa1 145 CX23885_VMUX_COMPONENT,
d19770e5
ST		 146 CX23885_VMUX_TELEVISION,
147 CX23885_VMUX_CABLE,
148 CX23885_VMUX_DVB,
149 CX23885_VMUX_DEBUG,
150 CX23885_RADIO,
151};
152
579f1163
ST		 153enum cx23885_src_sel_type {
154 CX23885_SRC_SEL_EXT_656_VIDEO = 0,
155 CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
156};
157
4d63a25c
HV		 158struct cx23885_riscmem {
159 unsigned int size;
160 __le32 *cpu;
161 __le32 *jmp;
162 dma_addr_t dma;
163};
164
d19770e5
ST		 165/* buffer for one video frame */
166struct cx23885_buffer {
167 /* common v4l buffer stuff -- must be first */
453afdd9
HV		 168 struct vb2_buffer vb;
169 struct list_head queue;
d19770e5
ST		 170
171 /* cx23885 specific */
172 unsigned int bpl;
4d63a25c 173 struct cx23885_riscmem risc;
d19770e5
ST		 174 struct cx23885_fmt *fmt;
175 u32 count;
176};
177
178struct cx23885_input {
179 enum cx23885_itype type;
180 unsigned int vmux;
8304be88 181 unsigned int amux;
d19770e5
ST		 182 u32 gpio0, gpio1, gpio2, gpio3;
183};
184
661c7e44
ST		 185typedef enum {
186 CX23885_MPEG_UNDEFINED = 0,
7b888014
ST		 187 CX23885_MPEG_DVB,
188 CX23885_ANALOG_VIDEO,
b1b81f1d 189 CX23885_MPEG_ENCODER,
661c7e44
ST		 190} port_t;
191
d19770e5
ST		 192struct cx23885_board {
193 char *name;
7b888014 194 port_t porta, portb, portc;
10d0dcd7 195 int num_fds_portb, num_fds_portc;
7b888014
ST		 196 unsigned int tuner_type;
197 unsigned int radio_type;
198 unsigned char tuner_addr;
199 unsigned char radio_addr;
557f48d5 200 unsigned int tuner_bus;
c7712613
ST		 201
202 /* Vendors can and do run the PCIe bridge at different
203 * clock rates, driven physically by crystals on the PCBs.
25985edc 204 * The core has to accommodate this. This allows the user
c7712613
ST		 205 * to add new boards with new frequencys. The value is
206 * expressed in Hz.
207 *
208 * The core framework will default this value based on
209 * current designs, but it can vary.
210 */
211 u32 clk_freq;
d19770e5 212 struct cx23885_input input[MAX_CX23885_INPUT];
78db8547 213 int ci_type; /* for NetUP */
35045137
ST		 214 /* Force bottom field first during DMA (888 workaround) */
215 u32 force_bff;
d19770e5
ST		 216};
217
218struct cx23885_subid {
219 u16 subvendor;
220 u16 subdevice;
221 u32 card;
222};
223
224struct cx23885_i2c {
225 struct cx23885_dev *dev;
226
227 int nr;
228
229 /* i2c i/o */
230 struct i2c_adapter i2c_adap;
d19770e5
ST		 231 struct i2c_client i2c_client;
232 u32 i2c_rc;
233
234 /* 885 registers used for raw addess */
235 u32 i2c_period;
236 u32 reg_ctrl;
237 u32 reg_stat;
238 u32 reg_addr;
239 u32 reg_rdata;
240 u32 reg_wdata;
241};
242
243struct cx23885_dmaqueue {
244 struct list_head active;
d19770e5
ST		 245 u32 count;
246};
247
248struct cx23885_tsport {
249 struct cx23885_dev *dev;
250
251 int nr;
252 int sram_chno;
253
453afdd9 254 struct vb2_dvb_frontends frontends;
d19770e5
ST		 255
256 /* dma queues */
257 struct cx23885_dmaqueue mpegq;
258 u32 ts_packet_size;
259 u32 ts_packet_count;
260
261 int width;
262 int height;
263
264 spinlock_t slock;
265
266 /* registers */
267 u32 reg_gpcnt;
268 u32 reg_gpcnt_ctl;
269 u32 reg_dma_ctl;
270 u32 reg_lngth;
271 u32 reg_hw_sop_ctrl;
272 u32 reg_gen_ctrl;
273 u32 reg_bd_pkt_status;
274 u32 reg_sop_status;
275 u32 reg_fifo_ovfl_stat;
276 u32 reg_vld_misc;
277 u32 reg_ts_clk_en;
278 u32 reg_ts_int_msk;
a6a3f140 279 u32 reg_ts_int_stat;
579f1163 280 u32 reg_src_sel;
d19770e5
ST		 281
282 /* Default register vals */
283 int pci_irqmask;
284 u32 dma_ctl_val;
285 u32 ts_int_msk_val;
286 u32 gen_ctrl_val;
287 u32 ts_clk_en_val;
579f1163 288 u32 src_sel_val;
b1b81f1d
ST		 289 u32 vld_misc_val;
290 u32 hw_sop_ctrl_val;
a739a7e4
ST		 291
292 /* Allow a single tsport to have multiple frontends */
293 u32 num_frontends;
78db8547 294 void (*gate_ctrl)(struct cx23885_tsport *port, int open);
5a23b076 295 void *port_priv;
35045137
ST		 296
297 /* Workaround for a temp dvb_frontend that the tuner can attached to */
298 struct dvb_frontend analog_fe;
15472faf 299
b0b12e63
OS		 300 struct i2c_client *i2c_client_demod;
301 struct i2c_client *i2c_client_tuner;
e450de45 302 struct i2c_client *i2c_client_ci;
b0b12e63 303
15472faf 304 int (*set_frontend)(struct dvb_frontend *fe);
5cd3b6b4
OS		 305 int (*fe_set_voltage)(struct dvb_frontend *fe,
306 fe_sec_voltage_t voltage);
d19770e5
ST		 307};
308
43c24078
AW		 309struct cx23885_kernel_ir {
310 struct cx23885_dev *cx;
eeefae53
AW		 311 char *name;
312 char *phys;
313
d8b4b582 314 struct rc_dev *rc;
eeefae53
AW		 315};
316
9e44d632
MM		 317struct cx23885_audio_buffer {
318 unsigned int bpl;
4d63a25c 319 struct cx23885_riscmem risc;
9529a4b0
HV		 320 void *vaddr;
321 struct scatterlist *sglist;
322 int sglen;
323 int nr_pages;
9e44d632
MM		 324};
325
326struct cx23885_audio_dev {
327 struct cx23885_dev *dev;
328
329 struct pci_dev *pci;
330
331 struct snd_card *card;
332
333 spinlock_t lock;
334
335 atomic_t count;
336
337 unsigned int dma_size;
338 unsigned int period_size;
339 unsigned int num_periods;
340
9e44d632
MM		 341 struct cx23885_audio_buffer *buf;
342
343 struct snd_pcm_substream *substream;
344};
345
d19770e5 346struct cx23885_dev {
d19770e5 347 atomic_t refcount;
c0714f6c 348 struct v4l2_device v4l2_dev;
da59a4de 349 struct v4l2_ctrl_handler ctrl_handler;
d19770e5
ST		 350
351 /* pci stuff */
352 struct pci_dev *pci;
353 unsigned char pci_rev, pci_lat;
354 int pci_bus, pci_slot;
355 u32 __iomem *lmmio;
356 u8 __iomem *bmmio;
d19770e5 357 int pci_irqmask;
dbe83a3b 358 spinlock_t pci_irqmask_lock; /* protects mask reg too */
0ac5881a 359 int hwrevision;
d19770e5 360
c7712613
ST		 361 /* This valud is board specific and is used to configure the
362 * AV core so we see nice clean and stable video and audio. */
363 u32 clk_freq;
364
44a6481d 365 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
d19770e5
ST		 366 struct cx23885_i2c i2c_bus[3];
367
368 int nr;
369 struct mutex lock;
8386c27f 370 struct mutex gpio_lock;
d19770e5
ST		 371
372 /* board details */
373 unsigned int board;
374 char name[32];
375
a6a3f140 376 struct cx23885_tsport ts1, ts2;
d19770e5
ST		 377
378 /* sram configuration */
379 struct sram_channel *sram_channels;
e133be0f
ST		 380
381 enum {
382 CX23885_BRIDGE_UNDEFINED = 0,
383 CX23885_BRIDGE_885 = 885,
384 CX23885_BRIDGE_887 = 887,
25ea66e2 385 CX23885_BRIDGE_888 = 888,
e133be0f 386 } bridge;
7b888014
ST		 387
388 /* Analog video */
7b888014 389 unsigned int input;
fc1a889d 390 unsigned int audinput; /* Selectable audio input */
7b888014
ST		 391 u32 tvaudio;
392 v4l2_std_id tvnorm;
393 unsigned int tuner_type;
394 unsigned char tuner_addr;
557f48d5 395 unsigned int tuner_bus;
7b888014
ST		 396 unsigned int radio_type;
397 unsigned char radio_addr;
0d5a19f1 398 struct v4l2_subdev *sd_cx25840;
e5514f10 399 struct work_struct cx25840_work;
f59ad611
AW		 400
401 /* Infrared */
402 struct v4l2_subdev *sd_ir;
403 struct work_struct ir_rx_work;
404 unsigned long ir_rx_notifications;
405 struct work_struct ir_tx_work;
406 unsigned long ir_tx_notifications;
7b888014 407
43c24078 408 struct cx23885_kernel_ir *kernel_ir;
dbda8f70
AW		 409 atomic_t ir_input_stopping;
410
7b888014
ST		 411 /* V4l */
412 u32 freq;
413 struct video_device *video_dev;
414 struct video_device *vbi_dev;
7b888014 415
91d2d674
HV		 416 /* video capture */
417 struct cx23885_fmt *fmt;
418 unsigned int width, height;
453afdd9 419 unsigned field;
91d2d674 420
7b888014 421 struct cx23885_dmaqueue vidq;
453afdd9 422 struct vb2_queue vb2_vidq;
7b888014 423 struct cx23885_dmaqueue vbiq;
453afdd9
HV		 424 struct vb2_queue vb2_vbiq;
425
7b888014 426 spinlock_t slock;
b1b81f1d
ST		 427
428 /* MPEG Encoder ONLY settings */
429 u32 cx23417_mailbox;
5150392c 430 struct cx2341x_handler cxhdl;
b1b81f1d 431 struct video_device *v4l_device;
453afdd9 432 struct vb2_queue vb2_mpegq;
b1b81f1d
ST		 433 struct cx23885_tvnorm encodernorm;
434
9e44d632
MM		 435 /* Analog raw audio */
436 struct cx23885_audio_dev *audio_dev;
437
d19770e5
ST		 438};
439
c0714f6c
HV		 440static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
441{
442 return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
443}
444
0d5a19f1
HV		 445#define call_all(dev, o, f, args...) \
446 v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
447
d6b1850d
AW		 448#define CX23885_HW_888_IR (1 << 0)
449#define CX23885_HW_AV_CORE (1 << 1)
29f8a0a5
AW		 450
451#define call_hw(dev, grpid, o, f, args...) \
452 v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
453
454extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
455
d19770e5
ST		 456#define SRAM_CH01 0 /* Video A */
457#define SRAM_CH02 1 /* VBI A */
458#define SRAM_CH03 2 /* Video B */
459#define SRAM_CH04 3 /* Transport via B */
460#define SRAM_CH05 4 /* VBI B */
461#define SRAM_CH06 5 /* Video C */
462#define SRAM_CH07 6 /* Transport via C */
463#define SRAM_CH08 7 /* Audio Internal A */
464#define SRAM_CH09 8 /* Audio Internal B */
465#define SRAM_CH10 9 /* Audio External */
466#define SRAM_CH11 10 /* COMB_3D_N */
467#define SRAM_CH12 11 /* Comb 3D N1 */
468#define SRAM_CH13 12 /* Comb 3D N2 */
469#define SRAM_CH14 13 /* MOE Vid */
470#define SRAM_CH15 14 /* MOE RSLT */
471
472struct sram_channel {
473 char *name;
474 u32 cmds_start;
475 u32 ctrl_start;
476 u32 cdt;
1ebcad77 477 u32 fifo_start;
d19770e5
ST		 478 u32 fifo_size;
479 u32 ptr1_reg;
480 u32 ptr2_reg;
481 u32 cnt1_reg;
482 u32 cnt2_reg;
483 u32 jumponly;
484};
485
486/* ----------------------------------------------------------- */
487
488#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
9c8ced51 489#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
d19770e5 490
9c8ced51 491#define cx_andor(reg, mask, value) \
d19770e5
ST		 492 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
493 ((value) & (mask)), dev->lmmio+((reg)>>2))
494
9c8ced51
ST		 495#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
496#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
d19770e5 497
d19770e5 498/* ----------------------------------------------------------- */
7b888014
ST		 499/* cx23885-core.c */
500
501extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
502 struct sram_channel *ch,
503 unsigned int bpl, u32 risc);
504
505extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
506 struct sram_channel *ch);
d19770e5 507
4d63a25c 508extern int cx23885_risc_buffer(struct pci_dev *pci, struct cx23885_riscmem *risc,
7b888014
ST		 509 struct scatterlist *sglist,
510 unsigned int top_offset, unsigned int bottom_offset,
511 unsigned int bpl, unsigned int padding, unsigned int lines);
512
5ab27e6d 513extern int cx23885_risc_vbibuffer(struct pci_dev *pci,
4d63a25c 514 struct cx23885_riscmem *risc, struct scatterlist *sglist,
5ab27e6d
ST		 515 unsigned int top_offset, unsigned int bottom_offset,
516 unsigned int bpl, unsigned int padding, unsigned int lines);
517
453afdd9
HV		 518int cx23885_start_dma(struct cx23885_tsport *port,
519 struct cx23885_dmaqueue *q,
520 struct cx23885_buffer *buf);
7b888014
ST		 521void cx23885_cancel_buffers(struct cx23885_tsport *port);
522
7b888014 523
6f8bee9b
ST		 524extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
525extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
09ea33e5 526extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
6f8bee9b
ST		 527extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
528 int asoutput);
529
dbe83a3b
AW		 530extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);
531extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);
532extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);
533extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);
7b888014
ST		 534
535/* ----------------------------------------------------------- */
536/* cx23885-cards.c */
d19770e5
ST		 537extern struct cx23885_board cx23885_boards[];
538extern const unsigned int cx23885_bcount;
539
540extern struct cx23885_subid cx23885_subids[];
541extern const unsigned int cx23885_idcount;
542
9c8ced51
ST		 543extern int cx23885_tuner_callback(void *priv, int component,
544 int command, int arg);
d19770e5 545extern void cx23885_card_list(struct cx23885_dev *dev);
a6a3f140 546extern int cx23885_ir_init(struct cx23885_dev *dev);
f59ad611
AW		 547extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
548extern void cx23885_ir_fini(struct cx23885_dev *dev);
a6a3f140 549extern void cx23885_gpio_setup(struct cx23885_dev *dev);
d19770e5
ST		 550extern void cx23885_card_setup(struct cx23885_dev *dev);
551extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
552
553extern int cx23885_dvb_register(struct cx23885_tsport *port);
554extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
555
453afdd9
HV		 556extern int cx23885_buf_prepare(struct cx23885_buffer *buf,
557 struct cx23885_tsport *port);
44a6481d
MK		 558extern void cx23885_buf_queue(struct cx23885_tsport *port,
559 struct cx23885_buffer *buf);
453afdd9 560extern void cx23885_free_buffer(struct cx23885_dev *dev,
44a6481d 561 struct cx23885_buffer *buf);
d19770e5
ST		 562
563/* ----------------------------------------------------------- */
7b888014
ST		 564/* cx23885-video.c */
565/* Video */
566extern int cx23885_video_register(struct cx23885_dev *dev);
567extern void cx23885_video_unregister(struct cx23885_dev *dev);
568extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
b5f74050
ST		 569extern void cx23885_video_wakeup(struct cx23885_dev *dev,
570 struct cx23885_dmaqueue *q, u32 count);
35045137
ST		 571int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i);
572int cx23885_set_input(struct file *file, void *priv, unsigned int i);
573int cx23885_get_input(struct file *file, void *priv, unsigned int *i);
b530a447 574int cx23885_set_frequency(struct file *file, void *priv, const struct v4l2_frequency *f);
35045137 575int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm);
7b888014
ST		 576
577/* ----------------------------------------------------------- */
578/* cx23885-vbi.c */
579extern int cx23885_vbi_fmt(struct file *file, void *priv,
580 struct v4l2_format *f);
581extern void cx23885_vbi_timeout(unsigned long data);
453afdd9 582extern struct vb2_ops cx23885_vbi_qops;
b5f74050 583extern int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status);
7b888014 584
d19770e5
ST		 585/* cx23885-i2c.c */
586extern int cx23885_i2c_register(struct cx23885_i2c *bus);
587extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
a589b665 588extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
d19770e5 589
b1b81f1d
ST		 590/* ----------------------------------------------------------- */
591/* cx23885-417.c */
592extern int cx23885_417_register(struct cx23885_dev *dev);
593extern void cx23885_417_unregister(struct cx23885_dev *dev);
594extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
595extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
596extern void cx23885_mc417_init(struct cx23885_dev *dev);
597extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
598extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
74618244
AW		 599extern int mc417_register_read(struct cx23885_dev *dev,
600 u16 address, u32 *value);
601extern int mc417_register_write(struct cx23885_dev *dev,
602 u16 address, u32 value);
f659c513
ST		 603extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
604extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
605extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
b1b81f1d 606
9e44d632
MM		 607/* ----------------------------------------------------------- */
608/* cx23885-alsa.c */
efa762f5
ST		 609extern struct cx23885_audio_dev *cx23885_audio_register(
610 struct cx23885_dev *dev);
611extern void cx23885_audio_unregister(struct cx23885_dev *dev);
9e44d632
MM		 612extern int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask);
613extern int cx23885_risc_databuffer(struct pci_dev *pci,
4d63a25c 614 struct cx23885_riscmem *risc,
9e44d632
MM		 615 struct scatterlist *sglist,
616 unsigned int bpl,
617 unsigned int lines,
618 unsigned int lpi);
b1b81f1d 619
7b888014
ST		 620/* ----------------------------------------------------------- */
621/* tv norms */
622
623static inline unsigned int norm_maxw(v4l2_std_id norm)
624{
1c5eaa23 625 return (norm & V4L2_STD_525_60) ? 720 : 768;
7b888014
ST		 626}
627
628static inline unsigned int norm_maxh(v4l2_std_id norm)
629{
1c5eaa23 630 return (norm & V4L2_STD_525_60) ? 480 : 576;
7b888014 631}
Linux kernel - Deliverables
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