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[media] vmalloc_sg: make sure all pages in vmalloc area are really DMA-ready
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885.h
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/pci.h>
23#include <linux/i2c.h>
d19770e5 24#include <linux/kdev_t.h>
5a0e3ad6 25#include <linux/slab.h>
d19770e5 26
c0714f6c 27#include <media/v4l2-device.h>
d19770e5
ST		 28#include <media/tuner.h>
29#include <media/tveeprom.h>
409d84f8
TP		 30#include <media/videobuf-dma-sg.h>
31#include <media/videobuf-dvb.h>
6bda9644 32#include <media/rc-core.h>
d19770e5
ST		 33
34#include "btcx-risc.h"
35#include "cx23885-reg.h"
b1b81f1d 36#include "media/cx2341x.h"
d19770e5 37
d19770e5
ST		 38#include <linux/mutex.h>
39
1990d50b 40#define CX23885_VERSION "0.0.3"
d19770e5
ST		 41
42#define UNSET (-1U)
43
44#define CX23885_MAXBOARDS 8
45
d19770e5
ST		 46/* Max number of inputs by card */
47#define MAX_CX23885_INPUT 8
7b888014
ST		 48#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
49#define RESOURCE_OVERLAY 1
50#define RESOURCE_VIDEO 2
51#define RESOURCE_VBI 4
d19770e5 52
d19770e5
ST		 53#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
54
55#define CX23885_BOARD_NOAUTO UNSET
56#define CX23885_BOARD_UNKNOWN 0
57#define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
58#define CX23885_BOARD_HAUPPAUGE_HVR1800 2
a77743bc 59#define CX23885_BOARD_HAUPPAUGE_HVR1250 3
9bc37caa 60#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
d1987d55 61#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
07b4a835 62#define CX23885_BOARD_HAUPPAUGE_HVR1500 6
b3ea0166 63#define CX23885_BOARD_HAUPPAUGE_HVR1200 7
a780a31c 64#define CX23885_BOARD_HAUPPAUGE_HVR1700 8
66762373 65#define CX23885_BOARD_HAUPPAUGE_HVR1400 9
335377b7 66#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
aef2d186 67#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
4c56b04a 68#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
9bb1b7e8 69#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
96318d0c 70#define CX23885_BOARD_TBS_6920 14
579943f5 71#define CX23885_BOARD_TEVII_S470 15
c9b8b04b 72#define CX23885_BOARD_DVBWORLD_2005 16
5a23b076 73#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
2074dffa 74#define CX23885_BOARD_HAUPPAUGE_HVR1270 18
d099becb 75#define CX23885_BOARD_HAUPPAUGE_HVR1275 19
19bc5796 76#define CX23885_BOARD_HAUPPAUGE_HVR1255 20
6b926eca 77#define CX23885_BOARD_HAUPPAUGE_HVR1210 21
493b7127 78#define CX23885_BOARD_MYGICA_X8506 22
2365b2d3 79#define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
13697380 80#define CX23885_BOARD_HAUPPAUGE_HVR1850 24
34e383dd 81#define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
aee0b24c 82#define CX23885_BOARD_HAUPPAUGE_HVR1290 26
ea5697fe 83#define CX23885_BOARD_MYGICA_X8558PRO 27
0b32d65c 84#define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
9028f58f 85#define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 29
78db8547 86#define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 30
0cf8af57 87#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000 31
2cb9ccd4 88#define CX23885_BOARD_MPX885 32
87988753 89#define CX23885_BOARD_MYGICA_X8507 33
722c90eb 90#define CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL 34
7b134e85 91#define CX23885_BOARD_TEVII_S471 35
0ac60acb 92#define CX23885_BOARD_HAUPPAUGE_HVR1255_22111 36
f667190b 93#define CX23885_BOARD_PROF_8000 37
7c62f5a1 94#define CX23885_BOARD_HAUPPAUGE_HVR4400 38
e8d42373 95#define CX23885_BOARD_AVERMEDIA_HC81R 39
e6001482
LA		 96#define CX23885_BOARD_TBS_6981 40
97#define CX23885_BOARD_TBS_6980 41
642ca1a0 98#define CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200 42
cce11b09 99#define CX23885_BOARD_HAUPPAUGE_IMPACTVCBE 43
d19770e5 100
6f8bee9b
ST		 101#define GPIO_0 0x00000001
102#define GPIO_1 0x00000002
103#define GPIO_2 0x00000004
104#define GPIO_3 0x00000008
105#define GPIO_4 0x00000010
106#define GPIO_5 0x00000020
107#define GPIO_6 0x00000040
108#define GPIO_7 0x00000080
109#define GPIO_8 0x00000100
110#define GPIO_9 0x00000200
f659c513
ST		 111#define GPIO_10 0x00000400
112#define GPIO_11 0x00000800
113#define GPIO_12 0x00001000
114#define GPIO_13 0x00002000
115#define GPIO_14 0x00004000
116#define GPIO_15 0x00008000
6f8bee9b 117
7b888014
ST		 118/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
119#define CX23885_NORMS (\
120 V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
121 V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
122 V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
123 V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
124
125struct cx23885_fmt {
126 char *name;
127 u32 fourcc; /* v4l2 format id */
128 int depth;
129 int flags;
130 u32 cxformat;
131};
132
133struct cx23885_ctrl {
134 struct v4l2_queryctrl v;
135 u32 off;
136 u32 reg;
137 u32 mask;
138 u32 shift;
139};
140
141struct cx23885_tvnorm {
142 char *name;
143 v4l2_std_id id;
144 u32 cxiformat;
145 u32 cxoformat;
146};
147
148struct cx23885_fh {
149 struct cx23885_dev *dev;
150 enum v4l2_buf_type type;
151 int radio;
152 u32 resources;
153
154 /* video overlay */
155 struct v4l2_window win;
156 struct v4l2_clip *clips;
157 unsigned int nclips;
158
159 /* video capture */
160 struct cx23885_fmt *fmt;
161 unsigned int width, height;
162
163 /* vbi capture */
164 struct videobuf_queue vidq;
165 struct videobuf_queue vbiq;
166
167 /* MPEG Encoder specifics ONLY */
168 struct videobuf_queue mpegq;
169 atomic_t v4l_reading;
170};
171
d19770e5
ST		 172enum cx23885_itype {
173 CX23885_VMUX_COMPOSITE1 = 1,
174 CX23885_VMUX_COMPOSITE2,
175 CX23885_VMUX_COMPOSITE3,
176 CX23885_VMUX_COMPOSITE4,
177 CX23885_VMUX_SVIDEO,
dac65fa1 178 CX23885_VMUX_COMPONENT,
d19770e5
ST		 179 CX23885_VMUX_TELEVISION,
180 CX23885_VMUX_CABLE,
181 CX23885_VMUX_DVB,
182 CX23885_VMUX_DEBUG,
183 CX23885_RADIO,
184};
185
579f1163
ST		 186enum cx23885_src_sel_type {
187 CX23885_SRC_SEL_EXT_656_VIDEO = 0,
188 CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
189};
190
d19770e5
ST		 191/* buffer for one video frame */
192struct cx23885_buffer {
193 /* common v4l buffer stuff -- must be first */
194 struct videobuf_buffer vb;
195
196 /* cx23885 specific */
197 unsigned int bpl;
198 struct btcx_riscmem risc;
199 struct cx23885_fmt *fmt;
200 u32 count;
201};
202
203struct cx23885_input {
204 enum cx23885_itype type;
205 unsigned int vmux;
8304be88 206 unsigned int amux;
d19770e5
ST		 207 u32 gpio0, gpio1, gpio2, gpio3;
208};
209
661c7e44
ST		 210typedef enum {
211 CX23885_MPEG_UNDEFINED = 0,
7b888014
ST		 212 CX23885_MPEG_DVB,
213 CX23885_ANALOG_VIDEO,
b1b81f1d 214 CX23885_MPEG_ENCODER,
661c7e44
ST		 215} port_t;
216
d19770e5
ST		 217struct cx23885_board {
218 char *name;
7b888014 219 port_t porta, portb, portc;
10d0dcd7 220 int num_fds_portb, num_fds_portc;
7b888014
ST		 221 unsigned int tuner_type;
222 unsigned int radio_type;
223 unsigned char tuner_addr;
224 unsigned char radio_addr;
557f48d5 225 unsigned int tuner_bus;
c7712613
ST		 226
227 /* Vendors can and do run the PCIe bridge at different
228 * clock rates, driven physically by crystals on the PCBs.
25985edc 229 * The core has to accommodate this. This allows the user
c7712613
ST		 230 * to add new boards with new frequencys. The value is
231 * expressed in Hz.
232 *
233 * The core framework will default this value based on
234 * current designs, but it can vary.
235 */
236 u32 clk_freq;
d19770e5 237 struct cx23885_input input[MAX_CX23885_INPUT];
78db8547 238 int ci_type; /* for NetUP */
35045137
ST		 239 /* Force bottom field first during DMA (888 workaround) */
240 u32 force_bff;
d19770e5
ST		 241};
242
243struct cx23885_subid {
244 u16 subvendor;
245 u16 subdevice;
246 u32 card;
247};
248
249struct cx23885_i2c {
250 struct cx23885_dev *dev;
251
252 int nr;
253
254 /* i2c i/o */
255 struct i2c_adapter i2c_adap;
d19770e5
ST		 256 struct i2c_client i2c_client;
257 u32 i2c_rc;
258
259 /* 885 registers used for raw addess */
260 u32 i2c_period;
261 u32 reg_ctrl;
262 u32 reg_stat;
263 u32 reg_addr;
264 u32 reg_rdata;
265 u32 reg_wdata;
266};
267
268struct cx23885_dmaqueue {
269 struct list_head active;
270 struct list_head queued;
271 struct timer_list timeout;
272 struct btcx_riscmem stopper;
273 u32 count;
274};
275
276struct cx23885_tsport {
277 struct cx23885_dev *dev;
278
279 int nr;
280 int sram_chno;
281
363c35fc 282 struct videobuf_dvb_frontends frontends;
d19770e5
ST		 283
284 /* dma queues */
285 struct cx23885_dmaqueue mpegq;
286 u32 ts_packet_size;
287 u32 ts_packet_count;
288
289 int width;
290 int height;
291
292 spinlock_t slock;
293
294 /* registers */
295 u32 reg_gpcnt;
296 u32 reg_gpcnt_ctl;
297 u32 reg_dma_ctl;
298 u32 reg_lngth;
299 u32 reg_hw_sop_ctrl;
300 u32 reg_gen_ctrl;
301 u32 reg_bd_pkt_status;
302 u32 reg_sop_status;
303 u32 reg_fifo_ovfl_stat;
304 u32 reg_vld_misc;
305 u32 reg_ts_clk_en;
306 u32 reg_ts_int_msk;
a6a3f140 307 u32 reg_ts_int_stat;
579f1163 308 u32 reg_src_sel;
d19770e5
ST		 309
310 /* Default register vals */
311 int pci_irqmask;
312 u32 dma_ctl_val;
313 u32 ts_int_msk_val;
314 u32 gen_ctrl_val;
315 u32 ts_clk_en_val;
579f1163 316 u32 src_sel_val;
b1b81f1d
ST		 317 u32 vld_misc_val;
318 u32 hw_sop_ctrl_val;
a739a7e4
ST		 319
320 /* Allow a single tsport to have multiple frontends */
321 u32 num_frontends;
78db8547 322 void (*gate_ctrl)(struct cx23885_tsport *port, int open);
5a23b076 323 void *port_priv;
35045137
ST		 324
325 /* Workaround for a temp dvb_frontend that the tuner can attached to */
326 struct dvb_frontend analog_fe;
15472faf
MCC		 327
328 int (*set_frontend)(struct dvb_frontend *fe);
d19770e5
ST		 329};
330
43c24078
AW		 331struct cx23885_kernel_ir {
332 struct cx23885_dev *cx;
eeefae53
AW		 333 char *name;
334 char *phys;
335
d8b4b582 336 struct rc_dev *rc;
eeefae53
AW		 337};
338
9e44d632
MM		 339struct cx23885_audio_buffer {
340 unsigned int bpl;
341 struct btcx_riscmem risc;
342 struct videobuf_dmabuf dma;
343};
344
345struct cx23885_audio_dev {
346 struct cx23885_dev *dev;
347
348 struct pci_dev *pci;
349
350 struct snd_card *card;
351
352 spinlock_t lock;
353
354 atomic_t count;
355
356 unsigned int dma_size;
357 unsigned int period_size;
358 unsigned int num_periods;
359
360 struct videobuf_dmabuf *dma_risc;
361
362 struct cx23885_audio_buffer *buf;
363
364 struct snd_pcm_substream *substream;
365};
366
d19770e5 367struct cx23885_dev {
d19770e5 368 atomic_t refcount;
c0714f6c 369 struct v4l2_device v4l2_dev;
d19770e5
ST		 370
371 /* pci stuff */
372 struct pci_dev *pci;
373 unsigned char pci_rev, pci_lat;
374 int pci_bus, pci_slot;
375 u32 __iomem *lmmio;
376 u8 __iomem *bmmio;
d19770e5 377 int pci_irqmask;
dbe83a3b 378 spinlock_t pci_irqmask_lock; /* protects mask reg too */
0ac5881a 379 int hwrevision;
d19770e5 380
c7712613
ST		 381 /* This valud is board specific and is used to configure the
382 * AV core so we see nice clean and stable video and audio. */
383 u32 clk_freq;
384
44a6481d 385 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
d19770e5
ST		 386 struct cx23885_i2c i2c_bus[3];
387
388 int nr;
389 struct mutex lock;
8386c27f 390 struct mutex gpio_lock;
d19770e5
ST		 391
392 /* board details */
393 unsigned int board;
394 char name[32];
395
a6a3f140 396 struct cx23885_tsport ts1, ts2;
d19770e5
ST		 397
398 /* sram configuration */
399 struct sram_channel *sram_channels;
e133be0f
ST		 400
401 enum {
402 CX23885_BRIDGE_UNDEFINED = 0,
403 CX23885_BRIDGE_885 = 885,
404 CX23885_BRIDGE_887 = 887,
25ea66e2 405 CX23885_BRIDGE_888 = 888,
e133be0f 406 } bridge;
7b888014
ST		 407
408 /* Analog video */
409 u32 resources;
410 unsigned int input;
fc1a889d 411 unsigned int audinput; /* Selectable audio input */
7b888014
ST		 412 u32 tvaudio;
413 v4l2_std_id tvnorm;
414 unsigned int tuner_type;
415 unsigned char tuner_addr;
557f48d5 416 unsigned int tuner_bus;
7b888014
ST		 417 unsigned int radio_type;
418 unsigned char radio_addr;
419 unsigned int has_radio;
0d5a19f1 420 struct v4l2_subdev *sd_cx25840;
e5514f10 421 struct work_struct cx25840_work;
f59ad611
AW		 422
423 /* Infrared */
424 struct v4l2_subdev *sd_ir;
425 struct work_struct ir_rx_work;
426 unsigned long ir_rx_notifications;
427 struct work_struct ir_tx_work;
428 unsigned long ir_tx_notifications;
7b888014 429
43c24078 430 struct cx23885_kernel_ir *kernel_ir;
dbda8f70
AW		 431 atomic_t ir_input_stopping;
432
7b888014
ST		 433 /* V4l */
434 u32 freq;
435 struct video_device *video_dev;
436 struct video_device *vbi_dev;
437 struct video_device *radio_dev;
438
439 struct cx23885_dmaqueue vidq;
440 struct cx23885_dmaqueue vbiq;
441 spinlock_t slock;
b1b81f1d
ST		 442
443 /* MPEG Encoder ONLY settings */
444 u32 cx23417_mailbox;
445 struct cx2341x_mpeg_params mpeg_params;
446 struct video_device *v4l_device;
447 atomic_t v4l_reader_count;
448 struct cx23885_tvnorm encodernorm;
449
9e44d632
MM		 450 /* Analog raw audio */
451 struct cx23885_audio_dev *audio_dev;
452
d19770e5
ST		 453};
454
c0714f6c
HV		 455static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
456{
457 return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
458}
459
0d5a19f1
HV		 460#define call_all(dev, o, f, args...) \
461 v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
462
d6b1850d
AW		 463#define CX23885_HW_888_IR (1 << 0)
464#define CX23885_HW_AV_CORE (1 << 1)
29f8a0a5
AW		 465
466#define call_hw(dev, grpid, o, f, args...) \
467 v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
468
469extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
470
d19770e5
ST		 471#define SRAM_CH01 0 /* Video A */
472#define SRAM_CH02 1 /* VBI A */
473#define SRAM_CH03 2 /* Video B */
474#define SRAM_CH04 3 /* Transport via B */
475#define SRAM_CH05 4 /* VBI B */
476#define SRAM_CH06 5 /* Video C */
477#define SRAM_CH07 6 /* Transport via C */
478#define SRAM_CH08 7 /* Audio Internal A */
479#define SRAM_CH09 8 /* Audio Internal B */
480#define SRAM_CH10 9 /* Audio External */
481#define SRAM_CH11 10 /* COMB_3D_N */
482#define SRAM_CH12 11 /* Comb 3D N1 */
483#define SRAM_CH13 12 /* Comb 3D N2 */
484#define SRAM_CH14 13 /* MOE Vid */
485#define SRAM_CH15 14 /* MOE RSLT */
486
487struct sram_channel {
488 char *name;
489 u32 cmds_start;
490 u32 ctrl_start;
491 u32 cdt;
1ebcad77 492 u32 fifo_start;
d19770e5
ST		 493 u32 fifo_size;
494 u32 ptr1_reg;
495 u32 ptr2_reg;
496 u32 cnt1_reg;
497 u32 cnt2_reg;
498 u32 jumponly;
499};
500
501/* ----------------------------------------------------------- */
502
503#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
9c8ced51 504#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
d19770e5 505
9c8ced51 506#define cx_andor(reg, mask, value) \
d19770e5
ST		 507 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
508 ((value) & (mask)), dev->lmmio+((reg)>>2))
509
9c8ced51
ST		 510#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
511#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
d19770e5 512
d19770e5 513/* ----------------------------------------------------------- */
7b888014
ST		 514/* cx23885-core.c */
515
516extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
517 struct sram_channel *ch,
518 unsigned int bpl, u32 risc);
519
520extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
521 struct sram_channel *ch);
d19770e5 522
7b888014
ST		 523extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
524 u32 reg, u32 mask, u32 value);
525
526extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
527 struct scatterlist *sglist,
528 unsigned int top_offset, unsigned int bottom_offset,
529 unsigned int bpl, unsigned int padding, unsigned int lines);
530
5ab27e6d
ST		 531extern int cx23885_risc_vbibuffer(struct pci_dev *pci,
532 struct btcx_riscmem *risc, struct scatterlist *sglist,
533 unsigned int top_offset, unsigned int bottom_offset,
534 unsigned int bpl, unsigned int padding, unsigned int lines);
535
7b888014
ST		 536void cx23885_cancel_buffers(struct cx23885_tsport *port);
537
538extern int cx23885_restart_queue(struct cx23885_tsport *port,
539 struct cx23885_dmaqueue *q);
540
541extern void cx23885_wakeup(struct cx23885_tsport *port,
542 struct cx23885_dmaqueue *q, u32 count);
543
6f8bee9b
ST		 544extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
545extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
09ea33e5 546extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
6f8bee9b
ST		 547extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
548 int asoutput);
549
dbe83a3b
AW		 550extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);
551extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);
552extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);
553extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);
7b888014
ST		 554
555/* ----------------------------------------------------------- */
556/* cx23885-cards.c */
d19770e5
ST		 557extern struct cx23885_board cx23885_boards[];
558extern const unsigned int cx23885_bcount;
559
560extern struct cx23885_subid cx23885_subids[];
561extern const unsigned int cx23885_idcount;
562
9c8ced51
ST		 563extern int cx23885_tuner_callback(void *priv, int component,
564 int command, int arg);
d19770e5 565extern void cx23885_card_list(struct cx23885_dev *dev);
a6a3f140 566extern int cx23885_ir_init(struct cx23885_dev *dev);
f59ad611
AW		 567extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
568extern void cx23885_ir_fini(struct cx23885_dev *dev);
a6a3f140 569extern void cx23885_gpio_setup(struct cx23885_dev *dev);
d19770e5
ST		 570extern void cx23885_card_setup(struct cx23885_dev *dev);
571extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
572
573extern int cx23885_dvb_register(struct cx23885_tsport *port);
574extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
575
44a6481d
MK		 576extern int cx23885_buf_prepare(struct videobuf_queue *q,
577 struct cx23885_tsport *port,
578 struct cx23885_buffer *buf,
579 enum v4l2_field field);
44a6481d
MK		 580extern void cx23885_buf_queue(struct cx23885_tsport *port,
581 struct cx23885_buffer *buf);
582extern void cx23885_free_buffer(struct videobuf_queue *q,
583 struct cx23885_buffer *buf);
d19770e5
ST		 584
585/* ----------------------------------------------------------- */
7b888014
ST		 586/* cx23885-video.c */
587/* Video */
588extern int cx23885_video_register(struct cx23885_dev *dev);
589extern void cx23885_video_unregister(struct cx23885_dev *dev);
590extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
b5f74050
ST		 591extern void cx23885_video_wakeup(struct cx23885_dev *dev,
592 struct cx23885_dmaqueue *q, u32 count);
35045137
ST		 593int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i);
594int cx23885_set_input(struct file *file, void *priv, unsigned int i);
595int cx23885_get_input(struct file *file, void *priv, unsigned int *i);
b530a447 596int cx23885_set_frequency(struct file *file, void *priv, const struct v4l2_frequency *f);
35045137
ST		 597int cx23885_set_control(struct cx23885_dev *dev, struct v4l2_control *ctl);
598int cx23885_get_control(struct cx23885_dev *dev, struct v4l2_control *ctl);
599int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm);
7b888014
ST		 600
601/* ----------------------------------------------------------- */
602/* cx23885-vbi.c */
603extern int cx23885_vbi_fmt(struct file *file, void *priv,
604 struct v4l2_format *f);
605extern void cx23885_vbi_timeout(unsigned long data);
606extern struct videobuf_queue_ops cx23885_vbi_qops;
b5f74050
ST		 607extern int cx23885_restart_vbi_queue(struct cx23885_dev *dev,
608 struct cx23885_dmaqueue *q);
609extern int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status);
7b888014 610
d19770e5
ST		 611/* cx23885-i2c.c */
612extern int cx23885_i2c_register(struct cx23885_i2c *bus);
613extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
a589b665 614extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
d19770e5 615
b1b81f1d
ST		 616/* ----------------------------------------------------------- */
617/* cx23885-417.c */
618extern int cx23885_417_register(struct cx23885_dev *dev);
619extern void cx23885_417_unregister(struct cx23885_dev *dev);
620extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
621extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
622extern void cx23885_mc417_init(struct cx23885_dev *dev);
623extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
624extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
74618244
AW		 625extern int mc417_register_read(struct cx23885_dev *dev,
626 u16 address, u32 *value);
627extern int mc417_register_write(struct cx23885_dev *dev,
628 u16 address, u32 value);
f659c513
ST		 629extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
630extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
631extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
b1b81f1d 632
9e44d632
MM		 633/* ----------------------------------------------------------- */
634/* cx23885-alsa.c */
efa762f5
ST		 635extern struct cx23885_audio_dev *cx23885_audio_register(
636 struct cx23885_dev *dev);
637extern void cx23885_audio_unregister(struct cx23885_dev *dev);
9e44d632
MM		 638extern int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask);
639extern int cx23885_risc_databuffer(struct pci_dev *pci,
640 struct btcx_riscmem *risc,
641 struct scatterlist *sglist,
642 unsigned int bpl,
643 unsigned int lines,
644 unsigned int lpi);
b1b81f1d 645
7b888014
ST		 646/* ----------------------------------------------------------- */
647/* tv norms */
648
649static inline unsigned int norm_maxw(v4l2_std_id norm)
650{
651 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
652}
653
654static inline unsigned int norm_maxh(v4l2_std_id norm)
655{
656 return (norm & V4L2_STD_625_50) ? 576 : 480;
657}
658
659static inline unsigned int norm_swidth(v4l2_std_id norm)
660{
661 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
662}
Linux kernel - Deliverables
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