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2c3fb08b | 1 | /* linux/drivers/media/platform/s5p-jpeg/jpeg-regs.h |
bb677f3a AP |
2 | * |
3 | * Register definition file for Samsung JPEG codec driver | |
4 | * | |
3246fdaa | 5 | * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. |
bb677f3a AP |
6 | * http://www.samsung.com |
7 | * | |
8 | * Author: Andrzej Pietrasiewicz <andrzej.p@samsung.com> | |
80529ae5 | 9 | * Author: Jacek Anaszewski <j.anaszewski@samsung.com> |
bb677f3a AP |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #ifndef JPEG_REGS_H_ | |
17 | #define JPEG_REGS_H_ | |
18 | ||
80529ae5 JA |
19 | /* Register and bit definitions for S5PC210 */ |
20 | ||
bb677f3a AP |
21 | /* JPEG mode register */ |
22 | #define S5P_JPGMOD 0x00 | |
23 | #define S5P_PROC_MODE_MASK (0x1 << 3) | |
24 | #define S5P_PROC_MODE_DECOMPR (0x1 << 3) | |
25 | #define S5P_PROC_MODE_COMPR (0x0 << 3) | |
26 | #define S5P_SUBSAMPLING_MODE_MASK 0x7 | |
27 | #define S5P_SUBSAMPLING_MODE_444 (0x0 << 0) | |
28 | #define S5P_SUBSAMPLING_MODE_422 (0x1 << 0) | |
29 | #define S5P_SUBSAMPLING_MODE_420 (0x2 << 0) | |
30 | #define S5P_SUBSAMPLING_MODE_GRAY (0x3 << 0) | |
31 | ||
32 | /* JPEG operation status register */ | |
33 | #define S5P_JPGOPR 0x04 | |
34 | ||
35 | /* Quantization tables*/ | |
36 | #define S5P_JPG_QTBL 0x08 | |
37 | #define S5P_QT_NUMt_SHIFT(t) (((t) - 1) << 1) | |
38 | #define S5P_QT_NUMt_MASK(t) (0x3 << S5P_QT_NUMt_SHIFT(t)) | |
39 | ||
40 | /* Huffman tables */ | |
41 | #define S5P_JPG_HTBL 0x0c | |
42 | #define S5P_HT_NUMt_AC_SHIFT(t) (((t) << 1) - 1) | |
43 | #define S5P_HT_NUMt_AC_MASK(t) (0x1 << S5P_HT_NUMt_AC_SHIFT(t)) | |
44 | ||
45 | #define S5P_HT_NUMt_DC_SHIFT(t) (((t) - 1) << 1) | |
46 | #define S5P_HT_NUMt_DC_MASK(t) (0x1 << S5P_HT_NUMt_DC_SHIFT(t)) | |
47 | ||
48 | /* JPEG restart interval register upper byte */ | |
49 | #define S5P_JPGDRI_U 0x10 | |
50 | ||
51 | /* JPEG restart interval register lower byte */ | |
52 | #define S5P_JPGDRI_L 0x14 | |
53 | ||
54 | /* JPEG vertical resolution register upper byte */ | |
55 | #define S5P_JPGY_U 0x18 | |
56 | ||
57 | /* JPEG vertical resolution register lower byte */ | |
58 | #define S5P_JPGY_L 0x1c | |
59 | ||
60 | /* JPEG horizontal resolution register upper byte */ | |
61 | #define S5P_JPGX_U 0x20 | |
62 | ||
63 | /* JPEG horizontal resolution register lower byte */ | |
64 | #define S5P_JPGX_L 0x24 | |
65 | ||
66 | /* JPEG byte count register upper byte */ | |
67 | #define S5P_JPGCNT_U 0x28 | |
68 | ||
69 | /* JPEG byte count register middle byte */ | |
70 | #define S5P_JPGCNT_M 0x2c | |
71 | ||
72 | /* JPEG byte count register lower byte */ | |
73 | #define S5P_JPGCNT_L 0x30 | |
74 | ||
75 | /* JPEG interrupt setting register */ | |
76 | #define S5P_JPGINTSE 0x34 | |
77 | #define S5P_RSTm_INT_EN_MASK (0x1 << 7) | |
78 | #define S5P_RSTm_INT_EN (0x1 << 7) | |
79 | #define S5P_DATA_NUM_INT_EN_MASK (0x1 << 6) | |
80 | #define S5P_DATA_NUM_INT_EN (0x1 << 6) | |
81 | #define S5P_FINAL_MCU_NUM_INT_EN_MASK (0x1 << 5) | |
82 | #define S5P_FINAL_MCU_NUM_INT_EN (0x1 << 5) | |
83 | ||
84 | /* JPEG interrupt status register */ | |
85 | #define S5P_JPGINTST 0x38 | |
86 | #define S5P_RESULT_STAT_SHIFT 6 | |
87 | #define S5P_RESULT_STAT_MASK (0x1 << S5P_RESULT_STAT_SHIFT) | |
88 | #define S5P_STREAM_STAT_SHIFT 5 | |
89 | #define S5P_STREAM_STAT_MASK (0x1 << S5P_STREAM_STAT_SHIFT) | |
90 | ||
91 | /* JPEG command register */ | |
92 | #define S5P_JPGCOM 0x4c | |
93 | #define S5P_INT_RELEASE (0x1 << 2) | |
94 | ||
95 | /* Raw image data r/w address register */ | |
96 | #define S5P_JPG_IMGADR 0x50 | |
97 | ||
98 | /* JPEG file r/w address register */ | |
99 | #define S5P_JPG_JPGADR 0x58 | |
100 | ||
101 | /* Coefficient for RGB-to-YCbCr converter register */ | |
102 | #define S5P_JPG_COEF(n) (0x5c + (((n) - 1) << 2)) | |
103 | #define S5P_COEFn_SHIFT(j) ((3 - (j)) << 3) | |
104 | #define S5P_COEFn_MASK(j) (0xff << S5P_COEFn_SHIFT(j)) | |
105 | ||
106 | /* JPEG color mode register */ | |
107 | #define S5P_JPGCMOD 0x68 | |
108 | #define S5P_MOD_SEL_MASK (0x7 << 5) | |
109 | #define S5P_MOD_SEL_422 (0x1 << 5) | |
110 | #define S5P_MOD_SEL_565 (0x2 << 5) | |
111 | #define S5P_MODE_Y16_MASK (0x1 << 1) | |
112 | #define S5P_MODE_Y16 (0x1 << 1) | |
113 | ||
114 | /* JPEG clock control register */ | |
115 | #define S5P_JPGCLKCON 0x6c | |
116 | #define S5P_CLK_DOWN_READY (0x1 << 1) | |
117 | #define S5P_POWER_ON (0x1 << 0) | |
118 | ||
119 | /* JPEG start register */ | |
120 | #define S5P_JSTART 0x70 | |
121 | ||
122 | /* JPEG SW reset register */ | |
123 | #define S5P_JPG_SW_RESET 0x78 | |
124 | ||
125 | /* JPEG timer setting register */ | |
126 | #define S5P_JPG_TIMER_SE 0x7c | |
127 | #define S5P_TIMER_INT_EN_MASK (0x1 << 31) | |
128 | #define S5P_TIMER_INT_EN (0x1 << 31) | |
129 | #define S5P_TIMER_INIT_MASK 0x7fffffff | |
130 | ||
131 | /* JPEG timer status register */ | |
132 | #define S5P_JPG_TIMER_ST 0x80 | |
133 | #define S5P_TIMER_INT_STAT_SHIFT 31 | |
134 | #define S5P_TIMER_INT_STAT_MASK (0x1 << S5P_TIMER_INT_STAT_SHIFT) | |
135 | #define S5P_TIMER_CNT_SHIFT 0 | |
136 | #define S5P_TIMER_CNT_MASK 0x7fffffff | |
137 | ||
138 | /* JPEG decompression output format register */ | |
139 | #define S5P_JPG_OUTFORM 0x88 | |
140 | #define S5P_DEC_OUT_FORMAT_MASK (0x1 << 0) | |
141 | #define S5P_DEC_OUT_FORMAT_422 (0x0 << 0) | |
142 | #define S5P_DEC_OUT_FORMAT_420 (0x1 << 0) | |
143 | ||
144 | /* JPEG version register */ | |
145 | #define S5P_JPG_VERSION 0x8c | |
146 | ||
147 | /* JPEG compressed stream size interrupt setting register */ | |
148 | #define S5P_JPG_ENC_STREAM_INTSE 0x98 | |
149 | #define S5P_ENC_STREAM_INT_MASK (0x1 << 24) | |
150 | #define S5P_ENC_STREAM_INT_EN (0x1 << 24) | |
151 | #define S5P_ENC_STREAM_BOUND_MASK 0xffffff | |
152 | ||
153 | /* JPEG compressed stream size interrupt status register */ | |
154 | #define S5P_JPG_ENC_STREAM_INTST 0x9c | |
155 | #define S5P_ENC_STREAM_INT_STAT_MASK 0x1 | |
156 | ||
157 | /* JPEG quantizer table register */ | |
158 | #define S5P_JPG_QTBL_CONTENT(n) (0x400 + (n) * 0x100) | |
159 | ||
160 | /* JPEG DC Huffman table register */ | |
161 | #define S5P_JPG_HDCTBL(n) (0x800 + (n) * 0x400) | |
162 | ||
163 | /* JPEG DC Huffman table register */ | |
164 | #define S5P_JPG_HDCTBLG(n) (0x840 + (n) * 0x400) | |
165 | ||
166 | /* JPEG AC Huffman table register */ | |
167 | #define S5P_JPG_HACTBL(n) (0x880 + (n) * 0x400) | |
168 | ||
169 | /* JPEG AC Huffman table register */ | |
170 | #define S5P_JPG_HACTBLG(n) (0x8c0 + (n) * 0x400) | |
171 | ||
80529ae5 JA |
172 | |
173 | /* Register and bit definitions for Exynos 4x12 */ | |
174 | ||
175 | /* JPEG Codec Control Registers */ | |
176 | #define EXYNOS4_JPEG_CNTL_REG 0x00 | |
177 | #define EXYNOS4_INT_EN_REG 0x04 | |
178 | #define EXYNOS4_INT_TIMER_COUNT_REG 0x08 | |
179 | #define EXYNOS4_INT_STATUS_REG 0x0c | |
180 | #define EXYNOS4_OUT_MEM_BASE_REG 0x10 | |
181 | #define EXYNOS4_JPEG_IMG_SIZE_REG 0x14 | |
182 | #define EXYNOS4_IMG_BA_PLANE_1_REG 0x18 | |
183 | #define EXYNOS4_IMG_SO_PLANE_1_REG 0x1c | |
184 | #define EXYNOS4_IMG_PO_PLANE_1_REG 0x20 | |
185 | #define EXYNOS4_IMG_BA_PLANE_2_REG 0x24 | |
186 | #define EXYNOS4_IMG_SO_PLANE_2_REG 0x28 | |
187 | #define EXYNOS4_IMG_PO_PLANE_2_REG 0x2c | |
188 | #define EXYNOS4_IMG_BA_PLANE_3_REG 0x30 | |
189 | #define EXYNOS4_IMG_SO_PLANE_3_REG 0x34 | |
190 | #define EXYNOS4_IMG_PO_PLANE_3_REG 0x38 | |
191 | ||
192 | #define EXYNOS4_TBL_SEL_REG 0x3c | |
193 | ||
194 | #define EXYNOS4_IMG_FMT_REG 0x40 | |
195 | ||
196 | #define EXYNOS4_BITSTREAM_SIZE_REG 0x44 | |
197 | #define EXYNOS4_PADDING_REG 0x48 | |
198 | #define EXYNOS4_HUFF_CNT_REG 0x4c | |
199 | #define EXYNOS4_FIFO_STATUS_REG 0x50 | |
200 | #define EXYNOS4_DECODE_XY_SIZE_REG 0x54 | |
201 | #define EXYNOS4_DECODE_IMG_FMT_REG 0x58 | |
202 | ||
203 | #define EXYNOS4_QUAN_TBL_ENTRY_REG 0x100 | |
204 | #define EXYNOS4_HUFF_TBL_ENTRY_REG 0x200 | |
205 | ||
206 | ||
207 | /****************************************************************/ | |
208 | /* Bit definition part */ | |
209 | /****************************************************************/ | |
210 | ||
211 | /* JPEG CNTL Register bit */ | |
212 | #define EXYNOS4_ENC_DEC_MODE_MASK (0xfffffffc << 0) | |
9982d82e JA |
213 | #define EXYNOS4_DEC_MODE (1 << 0) |
214 | #define EXYNOS4_ENC_MODE (1 << 1) | |
80529ae5 JA |
215 | #define EXYNOS4_AUTO_RST_MARKER (1 << 2) |
216 | #define EXYNOS4_RST_INTERVAL_SHIFT 3 | |
217 | #define EXYNOS4_RST_INTERVAL(x) (((x) & 0xffff) \ | |
218 | << EXYNOS4_RST_INTERVAL_SHIFT) | |
219 | #define EXYNOS4_HUF_TBL_EN (1 << 19) | |
220 | #define EXYNOS4_HOR_SCALING_SHIFT 20 | |
9982d82e | 221 | #define EXYNOS4_HOR_SCALING_MASK (3 << EXYNOS4_HOR_SCALING_SHIFT) |
80529ae5 JA |
222 | #define EXYNOS4_HOR_SCALING(x) (((x) & 0x3) \ |
223 | << EXYNOS4_HOR_SCALING_SHIFT) | |
224 | #define EXYNOS4_VER_SCALING_SHIFT 22 | |
9982d82e | 225 | #define EXYNOS4_VER_SCALING_MASK (3 << EXYNOS4_VER_SCALING_SHIFT) |
80529ae5 JA |
226 | #define EXYNOS4_VER_SCALING(x) (((x) & 0x3) \ |
227 | << EXYNOS4_VER_SCALING_SHIFT) | |
228 | #define EXYNOS4_PADDING (1 << 27) | |
229 | #define EXYNOS4_SYS_INT_EN (1 << 28) | |
230 | #define EXYNOS4_SOFT_RESET_HI (1 << 29) | |
231 | ||
232 | /* JPEG INT Register bit */ | |
233 | #define EXYNOS4_INT_EN_MASK (0x1f << 0) | |
6c96dbbc | 234 | #define EXYNOS5433_INT_EN_MASK (0x1ff << 0) |
80529ae5 JA |
235 | #define EXYNOS4_PROT_ERR_INT_EN (1 << 0) |
236 | #define EXYNOS4_IMG_COMPLETION_INT_EN (1 << 1) | |
237 | #define EXYNOS4_DEC_INVALID_FORMAT_EN (1 << 2) | |
238 | #define EXYNOS4_MULTI_SCAN_ERROR_EN (1 << 3) | |
239 | #define EXYNOS4_FRAME_ERR_EN (1 << 4) | |
240 | #define EXYNOS4_INT_EN_ALL (0x1f << 0) | |
6c96dbbc | 241 | #define EXYNOS5433_INT_EN_ALL (0x1b6 << 0) |
80529ae5 | 242 | |
9982d82e JA |
243 | #define EXYNOS4_MOD_REG_PROC_ENC (0 << 3) |
244 | #define EXYNOS4_MOD_REG_PROC_DEC (1 << 3) | |
80529ae5 JA |
245 | |
246 | #define EXYNOS4_MOD_REG_SUBSAMPLE_444 (0 << 0) | |
247 | #define EXYNOS4_MOD_REG_SUBSAMPLE_422 (1 << 0) | |
248 | #define EXYNOS4_MOD_REG_SUBSAMPLE_420 (2 << 0) | |
249 | #define EXYNOS4_MOD_REG_SUBSAMPLE_GRAY (3 << 0) | |
250 | ||
251 | ||
252 | /* JPEG IMAGE SIZE Register bit */ | |
253 | #define EXYNOS4_X_SIZE_SHIFT 0 | |
254 | #define EXYNOS4_X_SIZE_MASK (0xffff << EXYNOS4_X_SIZE_SHIFT) | |
255 | #define EXYNOS4_X_SIZE(x) (((x) & 0xffff) << EXYNOS4_X_SIZE_SHIFT) | |
256 | #define EXYNOS4_Y_SIZE_SHIFT 16 | |
257 | #define EXYNOS4_Y_SIZE_MASK (0xffff << EXYNOS4_Y_SIZE_SHIFT) | |
258 | #define EXYNOS4_Y_SIZE(x) (((x) & 0xffff) << EXYNOS4_Y_SIZE_SHIFT) | |
259 | ||
260 | /* JPEG IMAGE FORMAT Register bit */ | |
261 | #define EXYNOS4_ENC_IN_FMT_MASK 0xffff0000 | |
262 | #define EXYNOS4_ENC_GRAY_IMG (0 << 0) | |
263 | #define EXYNOS4_ENC_RGB_IMG (1 << 0) | |
264 | #define EXYNOS4_ENC_YUV_444_IMG (2 << 0) | |
265 | #define EXYNOS4_ENC_YUV_422_IMG (3 << 0) | |
266 | #define EXYNOS4_ENC_YUV_440_IMG (4 << 0) | |
267 | ||
268 | #define EXYNOS4_DEC_GRAY_IMG (0 << 0) | |
269 | #define EXYNOS4_DEC_RGB_IMG (1 << 0) | |
270 | #define EXYNOS4_DEC_YUV_444_IMG (2 << 0) | |
271 | #define EXYNOS4_DEC_YUV_422_IMG (3 << 0) | |
272 | #define EXYNOS4_DEC_YUV_420_IMG (4 << 0) | |
273 | ||
274 | #define EXYNOS4_GRAY_IMG_IP_SHIFT 3 | |
9982d82e | 275 | #define EXYNOS4_GRAY_IMG_IP_MASK (7 << EXYNOS4_GRAY_IMG_IP_SHIFT) |
80529ae5 JA |
276 | #define EXYNOS4_GRAY_IMG_IP (4 << EXYNOS4_GRAY_IMG_IP_SHIFT) |
277 | ||
278 | #define EXYNOS4_RGB_IP_SHIFT 6 | |
279 | #define EXYNOS4_RGB_IP_MASK (7 << EXYNOS4_RGB_IP_SHIFT) | |
280 | #define EXYNOS4_RGB_IP_RGB_16BIT_IMG (4 << EXYNOS4_RGB_IP_SHIFT) | |
281 | #define EXYNOS4_RGB_IP_RGB_32BIT_IMG (5 << EXYNOS4_RGB_IP_SHIFT) | |
282 | ||
9982d82e | 283 | #define EXYNOS4_YUV_444_IP_SHIFT 9 |
80529ae5 JA |
284 | #define EXYNOS4_YUV_444_IP_MASK (7 << EXYNOS4_YUV_444_IP_SHIFT) |
285 | #define EXYNOS4_YUV_444_IP_YUV_444_2P_IMG (4 << EXYNOS4_YUV_444_IP_SHIFT) | |
286 | #define EXYNOS4_YUV_444_IP_YUV_444_3P_IMG (5 << EXYNOS4_YUV_444_IP_SHIFT) | |
287 | ||
9982d82e | 288 | #define EXYNOS4_YUV_422_IP_SHIFT 12 |
80529ae5 JA |
289 | #define EXYNOS4_YUV_422_IP_MASK (7 << EXYNOS4_YUV_422_IP_SHIFT) |
290 | #define EXYNOS4_YUV_422_IP_YUV_422_1P_IMG (4 << EXYNOS4_YUV_422_IP_SHIFT) | |
291 | #define EXYNOS4_YUV_422_IP_YUV_422_2P_IMG (5 << EXYNOS4_YUV_422_IP_SHIFT) | |
292 | #define EXYNOS4_YUV_422_IP_YUV_422_3P_IMG (6 << EXYNOS4_YUV_422_IP_SHIFT) | |
293 | ||
9982d82e | 294 | #define EXYNOS4_YUV_420_IP_SHIFT 15 |
80529ae5 JA |
295 | #define EXYNOS4_YUV_420_IP_MASK (7 << EXYNOS4_YUV_420_IP_SHIFT) |
296 | #define EXYNOS4_YUV_420_IP_YUV_420_2P_IMG (4 << EXYNOS4_YUV_420_IP_SHIFT) | |
297 | #define EXYNOS4_YUV_420_IP_YUV_420_3P_IMG (5 << EXYNOS4_YUV_420_IP_SHIFT) | |
298 | ||
299 | #define EXYNOS4_ENC_FMT_SHIFT 24 | |
300 | #define EXYNOS4_ENC_FMT_MASK (3 << EXYNOS4_ENC_FMT_SHIFT) | |
6c96dbbc AP |
301 | #define EXYNOS5433_ENC_FMT_MASK (7 << EXYNOS4_ENC_FMT_SHIFT) |
302 | ||
80529ae5 JA |
303 | #define EXYNOS4_ENC_FMT_GRAY (0 << EXYNOS4_ENC_FMT_SHIFT) |
304 | #define EXYNOS4_ENC_FMT_YUV_444 (1 << EXYNOS4_ENC_FMT_SHIFT) | |
305 | #define EXYNOS4_ENC_FMT_YUV_422 (2 << EXYNOS4_ENC_FMT_SHIFT) | |
306 | #define EXYNOS4_ENC_FMT_YUV_420 (3 << EXYNOS4_ENC_FMT_SHIFT) | |
307 | ||
308 | #define EXYNOS4_JPEG_DECODED_IMG_FMT_MASK 0x03 | |
309 | ||
9982d82e JA |
310 | #define EXYNOS4_SWAP_CHROMA_CRCB (1 << 26) |
311 | #define EXYNOS4_SWAP_CHROMA_CBCR (0 << 26) | |
6c96dbbc AP |
312 | #define EXYNOS5433_SWAP_CHROMA_CRCB (1 << 27) |
313 | #define EXYNOS5433_SWAP_CHROMA_CBCR (0 << 27) | |
80529ae5 JA |
314 | |
315 | /* JPEG HUFF count Register bit */ | |
316 | #define EXYNOS4_HUFF_COUNT_MASK 0xffff | |
317 | ||
318 | /* JPEG Decoded_img_x_y_size Register bit */ | |
319 | #define EXYNOS4_DECODED_SIZE_MASK 0x0000ffff | |
320 | ||
321 | /* JPEG Decoded image format Register bit */ | |
322 | #define EXYNOS4_DECODED_IMG_FMT_MASK 0x3 | |
323 | ||
324 | /* JPEG TBL SEL Register bit */ | |
6c96dbbc AP |
325 | #define EXYNOS4_Q_TBL_COMP(c, n) ((n) << (((c) - 1) << 1)) |
326 | ||
327 | #define EXYNOS4_Q_TBL_COMP1_0 EXYNOS4_Q_TBL_COMP(1, 0) | |
328 | #define EXYNOS4_Q_TBL_COMP1_1 EXYNOS4_Q_TBL_COMP(1, 1) | |
329 | #define EXYNOS4_Q_TBL_COMP1_2 EXYNOS4_Q_TBL_COMP(1, 2) | |
330 | #define EXYNOS4_Q_TBL_COMP1_3 EXYNOS4_Q_TBL_COMP(1, 3) | |
331 | ||
332 | #define EXYNOS4_Q_TBL_COMP2_0 EXYNOS4_Q_TBL_COMP(2, 0) | |
333 | #define EXYNOS4_Q_TBL_COMP2_1 EXYNOS4_Q_TBL_COMP(2, 1) | |
334 | #define EXYNOS4_Q_TBL_COMP2_2 EXYNOS4_Q_TBL_COMP(2, 2) | |
335 | #define EXYNOS4_Q_TBL_COMP2_3 EXYNOS4_Q_TBL_COMP(2, 3) | |
336 | ||
337 | #define EXYNOS4_Q_TBL_COMP3_0 EXYNOS4_Q_TBL_COMP(3, 0) | |
338 | #define EXYNOS4_Q_TBL_COMP3_1 EXYNOS4_Q_TBL_COMP(3, 1) | |
339 | #define EXYNOS4_Q_TBL_COMP3_2 EXYNOS4_Q_TBL_COMP(3, 2) | |
340 | #define EXYNOS4_Q_TBL_COMP3_3 EXYNOS4_Q_TBL_COMP(3, 3) | |
341 | ||
342 | #define EXYNOS4_HUFF_TBL_COMP(c, n) ((n) << ((((c) - 1) << 1) + 6)) | |
343 | ||
344 | #define EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_0 \ | |
345 | EXYNOS4_HUFF_TBL_COMP(1, 0) | |
346 | #define EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_1 \ | |
347 | EXYNOS4_HUFF_TBL_COMP(1, 1) | |
348 | #define EXYNOS4_HUFF_TBL_COMP1_AC_1_DC_0 \ | |
349 | EXYNOS4_HUFF_TBL_COMP(1, 2) | |
350 | #define EXYNOS4_HUFF_TBL_COMP1_AC_1_DC_1 \ | |
351 | EXYNOS4_HUFF_TBL_COMP(1, 3) | |
352 | ||
353 | #define EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_0 \ | |
354 | EXYNOS4_HUFF_TBL_COMP(2, 0) | |
355 | #define EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_1 \ | |
356 | EXYNOS4_HUFF_TBL_COMP(2, 1) | |
357 | #define EXYNOS4_HUFF_TBL_COMP2_AC_1_DC_0 \ | |
358 | EXYNOS4_HUFF_TBL_COMP(2, 2) | |
359 | #define EXYNOS4_HUFF_TBL_COMP2_AC_1_DC_1 \ | |
360 | EXYNOS4_HUFF_TBL_COMP(2, 3) | |
361 | ||
362 | #define EXYNOS4_HUFF_TBL_COMP3_AC_0_DC_0 \ | |
363 | EXYNOS4_HUFF_TBL_COMP(3, 0) | |
364 | #define EXYNOS4_HUFF_TBL_COMP3_AC_0_DC_1 \ | |
365 | EXYNOS4_HUFF_TBL_COMP(3, 1) | |
366 | #define EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_0 \ | |
367 | EXYNOS4_HUFF_TBL_COMP(3, 2) | |
368 | #define EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_1 \ | |
369 | EXYNOS4_HUFF_TBL_COMP(3, 3) | |
370 | ||
371 | #define EXYNOS4_NF_SHIFT 16 | |
372 | #define EXYNOS4_NF_MASK 0xff | |
373 | #define EXYNOS4_NF(x) \ | |
374 | (((x) << EXYNOS4_NF_SHIFT) & EXYNOS4_NF_MASK) | |
80529ae5 JA |
375 | |
376 | /* JPEG quantizer table register */ | |
377 | #define EXYNOS4_QTBL_CONTENT(n) (0x100 + (n) * 0x40) | |
378 | ||
379 | /* JPEG DC luminance (code length) Huffman table register */ | |
380 | #define EXYNOS4_HUFF_TBL_HDCLL 0x200 | |
381 | ||
382 | /* JPEG DC luminance (values) Huffman table register */ | |
383 | #define EXYNOS4_HUFF_TBL_HDCLV 0x210 | |
384 | ||
385 | /* JPEG DC chrominance (code length) Huffman table register */ | |
386 | #define EXYNOS4_HUFF_TBL_HDCCL 0x220 | |
387 | ||
388 | /* JPEG DC chrominance (values) Huffman table register */ | |
389 | #define EXYNOS4_HUFF_TBL_HDCCV 0x230 | |
390 | ||
391 | /* JPEG AC luminance (code length) Huffman table register */ | |
392 | #define EXYNOS4_HUFF_TBL_HACLL 0x240 | |
393 | ||
394 | /* JPEG AC luminance (values) Huffman table register */ | |
395 | #define EXYNOS4_HUFF_TBL_HACLV 0x250 | |
396 | ||
397 | /* JPEG AC chrominance (code length) Huffman table register */ | |
398 | #define EXYNOS4_HUFF_TBL_HACCL 0x300 | |
399 | ||
400 | /* JPEG AC chrominance (values) Huffman table register */ | |
401 | #define EXYNOS4_HUFF_TBL_HACCV 0x310 | |
402 | ||
3246fdaa JA |
403 | /* Register and bit definitions for Exynos 3250 */ |
404 | ||
405 | /* JPEG mode register */ | |
406 | #define EXYNOS3250_JPGMOD 0x00 | |
407 | #define EXYNOS3250_PROC_MODE_MASK (0x1 << 3) | |
408 | #define EXYNOS3250_PROC_MODE_DECOMPR (0x1 << 3) | |
409 | #define EXYNOS3250_PROC_MODE_COMPR (0x0 << 3) | |
410 | #define EXYNOS3250_SUBSAMPLING_MODE_MASK (0x7 << 0) | |
411 | #define EXYNOS3250_SUBSAMPLING_MODE_444 (0x0 << 0) | |
412 | #define EXYNOS3250_SUBSAMPLING_MODE_422 (0x1 << 0) | |
413 | #define EXYNOS3250_SUBSAMPLING_MODE_420 (0x2 << 0) | |
414 | #define EXYNOS3250_SUBSAMPLING_MODE_411 (0x6 << 0) | |
415 | #define EXYNOS3250_SUBSAMPLING_MODE_GRAY (0x3 << 0) | |
416 | ||
417 | /* JPEG operation status register */ | |
418 | #define EXYNOS3250_JPGOPR 0x04 | |
419 | #define EXYNOS3250_JPGOPR_MASK 0x01 | |
420 | ||
421 | /* Quantization and Huffman tables register */ | |
422 | #define EXYNOS3250_QHTBL 0x08 | |
423 | #define EXYNOS3250_QT_NUM_SHIFT(t) ((((t) - 1) << 1) + 8) | |
424 | #define EXYNOS3250_QT_NUM_MASK(t) (0x3 << EXYNOS3250_QT_NUM_SHIFT(t)) | |
425 | ||
426 | /* Huffman tables */ | |
427 | #define EXYNOS3250_HT_NUM_AC_SHIFT(t) (((t) << 1) - 1) | |
428 | #define EXYNOS3250_HT_NUM_AC_MASK(t) (0x1 << EXYNOS3250_HT_NUM_AC_SHIFT(t)) | |
429 | ||
430 | #define EXYNOS3250_HT_NUM_DC_SHIFT(t) (((t) - 1) << 1) | |
431 | #define EXYNOS3250_HT_NUM_DC_MASK(t) (0x1 << EXYNOS3250_HT_NUM_DC_SHIFT(t)) | |
432 | ||
433 | /* JPEG restart interval register */ | |
434 | #define EXYNOS3250_JPGDRI 0x0c | |
435 | #define EXYNOS3250_JPGDRI_MASK 0xffff | |
436 | ||
437 | /* JPEG vertical resolution register */ | |
438 | #define EXYNOS3250_JPGY 0x10 | |
439 | #define EXYNOS3250_JPGY_MASK 0xffff | |
440 | ||
441 | /* JPEG horizontal resolution register */ | |
442 | #define EXYNOS3250_JPGX 0x14 | |
443 | #define EXYNOS3250_JPGX_MASK 0xffff | |
444 | ||
445 | /* JPEG byte count register */ | |
446 | #define EXYNOS3250_JPGCNT 0x18 | |
447 | #define EXYNOS3250_JPGCNT_MASK 0xffffff | |
448 | ||
449 | /* JPEG interrupt mask register */ | |
450 | #define EXYNOS3250_JPGINTSE 0x1c | |
451 | #define EXYNOS3250_JPEG_DONE_EN (1 << 11) | |
452 | #define EXYNOS3250_WDMA_DONE_EN (1 << 10) | |
453 | #define EXYNOS3250_RDMA_DONE_EN (1 << 9) | |
454 | #define EXYNOS3250_ENC_STREAM_INT_EN (1 << 8) | |
455 | #define EXYNOS3250_CORE_DONE_EN (1 << 5) | |
456 | #define EXYNOS3250_ERR_INT_EN (1 << 4) | |
457 | #define EXYNOS3250_HEAD_INT_EN (1 << 3) | |
458 | ||
459 | /* JPEG interrupt status register */ | |
460 | #define EXYNOS3250_JPGINTST 0x20 | |
461 | #define EXYNOS3250_JPEG_DONE (1 << 11) | |
462 | #define EXYNOS3250_WDMA_DONE (1 << 10) | |
463 | #define EXYNOS3250_RDMA_DONE (1 << 9) | |
464 | #define EXYNOS3250_ENC_STREAM_STAT (1 << 8) | |
465 | #define EXYNOS3250_RESULT_STAT (1 << 5) | |
466 | #define EXYNOS3250_STREAM_STAT (1 << 4) | |
467 | #define EXYNOS3250_HEADER_STAT (1 << 3) | |
468 | ||
469 | /* | |
470 | * Base address of the luma component DMA buffer | |
471 | * of the raw input or output image. | |
472 | */ | |
473 | #define EXYNOS3250_LUMA_BASE 0x100 | |
474 | #define EXYNOS3250_SRC_TILE_EN_MASK 0x100 | |
475 | ||
476 | /* Stride of source or destination luma raw image buffer */ | |
477 | #define EXYNOS3250_LUMA_STRIDE 0x104 | |
478 | ||
479 | /* Horizontal/vertical offset of active region in luma raw image buffer */ | |
480 | #define EXYNOS3250_LUMA_XY_OFFSET 0x108 | |
481 | #define EXYNOS3250_LUMA_YY_OFFSET_SHIFT 18 | |
482 | #define EXYNOS3250_LUMA_YY_OFFSET_MASK (0x1fff << EXYNOS3250_LUMA_YY_OFFSET_SHIFT) | |
483 | #define EXYNOS3250_LUMA_YX_OFFSET_SHIFT 2 | |
484 | #define EXYNOS3250_LUMA_YX_OFFSET_MASK (0x1fff << EXYNOS3250_LUMA_YX_OFFSET_SHIFT) | |
485 | ||
486 | /* | |
487 | * Base address of the chroma(Cb) component DMA buffer | |
488 | * of the raw input or output image. | |
489 | */ | |
490 | #define EXYNOS3250_CHROMA_BASE 0x10c | |
491 | ||
492 | /* Stride of source or destination chroma(Cb) raw image buffer */ | |
493 | #define EXYNOS3250_CHROMA_STRIDE 0x110 | |
494 | ||
495 | /* Horizontal/vertical offset of active region in chroma(Cb) raw image buffer */ | |
496 | #define EXYNOS3250_CHROMA_XY_OFFSET 0x114 | |
497 | #define EXYNOS3250_CHROMA_YY_OFFSET_SHIFT 18 | |
498 | #define EXYNOS3250_CHROMA_YY_OFFSET_MASK (0x1fff << EXYNOS3250_CHROMA_YY_OFFSET_SHIFT) | |
499 | #define EXYNOS3250_CHROMA_YX_OFFSET_SHIFT 2 | |
500 | #define EXYNOS3250_CHROMA_YX_OFFSET_MASK (0x1fff << EXYNOS3250_CHROMA_YX_OFFSET_SHIFT) | |
501 | ||
502 | /* | |
503 | * Base address of the chroma(Cr) component DMA buffer | |
504 | * of the raw input or output image. | |
505 | */ | |
506 | #define EXYNOS3250_CHROMA_CR_BASE 0x118 | |
507 | ||
508 | /* Stride of source or destination chroma(Cr) raw image buffer */ | |
509 | #define EXYNOS3250_CHROMA_CR_STRIDE 0x11c | |
510 | ||
511 | /* Horizontal/vertical offset of active region in chroma(Cb) raw image buffer */ | |
512 | #define EXYNOS3250_CHROMA_CR_XY_OFFSET 0x120 | |
513 | #define EXYNOS3250_CHROMA_CR_YY_OFFSET_SHIFT 18 | |
514 | #define EXYNOS3250_CHROMA_CR_YY_OFFSET_MASK (0x1fff << EXYNOS3250_CHROMA_CR_YY_OFFSET_SHIFT) | |
515 | #define EXYNOS3250_CHROMA_CR_YX_OFFSET_SHIFT 2 | |
516 | #define EXYNOS3250_CHROMA_CR_YX_OFFSET_MASK (0x1fff << EXYNOS3250_CHROMA_CR_YX_OFFSET_SHIFT) | |
517 | ||
518 | /* Raw image data r/w address register */ | |
519 | #define EXYNOS3250_JPG_IMGADR 0x50 | |
520 | ||
521 | /* Source or destination JPEG file DMA buffer address */ | |
522 | #define EXYNOS3250_JPG_JPGADR 0x124 | |
523 | ||
524 | /* Coefficients for RGB-to-YCbCr converter register */ | |
525 | #define EXYNOS3250_JPG_COEF(n) (0x128 + (((n) - 1) << 2)) | |
526 | #define EXYNOS3250_COEF_SHIFT(j) ((3 - (j)) << 3) | |
527 | #define EXYNOS3250_COEF_MASK(j) (0xff << EXYNOS3250_COEF_SHIFT(j)) | |
528 | ||
529 | /* Raw input format setting */ | |
530 | #define EXYNOS3250_JPGCMOD 0x134 | |
531 | #define EXYNOS3250_SRC_TILE_EN (0x1 << 10) | |
532 | #define EXYNOS3250_SRC_NV_MASK (0x1 << 9) | |
533 | #define EXYNOS3250_SRC_NV12 (0x0 << 9) | |
534 | #define EXYNOS3250_SRC_NV21 (0x1 << 9) | |
535 | #define EXYNOS3250_SRC_BIG_ENDIAN_MASK (0x1 << 8) | |
536 | #define EXYNOS3250_SRC_BIG_ENDIAN (0x1 << 8) | |
537 | #define EXYNOS3250_MODE_SEL_MASK (0x7 << 5) | |
538 | #define EXYNOS3250_MODE_SEL_420_2P (0x0 << 5) | |
539 | #define EXYNOS3250_MODE_SEL_422_1P_LUM_CHR (0x1 << 5) | |
540 | #define EXYNOS3250_MODE_SEL_RGB565 (0x2 << 5) | |
541 | #define EXYNOS3250_MODE_SEL_422_1P_CHR_LUM (0x3 << 5) | |
542 | #define EXYNOS3250_MODE_SEL_ARGB8888 (0x4 << 5) | |
543 | #define EXYNOS3250_MODE_SEL_420_3P (0x5 << 5) | |
544 | #define EXYNOS3250_SRC_SWAP_RGB (0x1 << 3) | |
545 | #define EXYNOS3250_SRC_SWAP_UV (0x1 << 2) | |
546 | #define EXYNOS3250_MODE_Y16_MASK (0x1 << 1) | |
547 | #define EXYNOS3250_MODE_Y16 (0x1 << 1) | |
548 | #define EXYNOS3250_HALF_EN_MASK (0x1 << 0) | |
549 | #define EXYNOS3250_HALF_EN (0x1 << 0) | |
550 | ||
551 | /* Power on/off and clock down control */ | |
552 | #define EXYNOS3250_JPGCLKCON 0x138 | |
553 | #define EXYNOS3250_CLK_DOWN_READY (0x1 << 1) | |
554 | #define EXYNOS3250_POWER_ON (0x1 << 0) | |
555 | ||
556 | /* Start compression or decompression */ | |
557 | #define EXYNOS3250_JSTART 0x13c | |
558 | ||
559 | /* Restart decompression after header analysis */ | |
560 | #define EXYNOS3250_JRSTART 0x140 | |
561 | ||
562 | /* JPEG SW reset register */ | |
563 | #define EXYNOS3250_SW_RESET 0x144 | |
564 | ||
565 | /* JPEG timer setting register */ | |
566 | #define EXYNOS3250_TIMER_SE 0x148 | |
567 | #define EXYNOS3250_TIMER_INT_EN_SHIFT 31 | |
568 | #define EXYNOS3250_TIMER_INT_EN (1 << EXYNOS3250_TIMER_INT_EN_SHIFT) | |
569 | #define EXYNOS3250_TIMER_INIT_MASK 0x7fffffff | |
570 | ||
571 | /* JPEG timer status register */ | |
572 | #define EXYNOS3250_TIMER_ST 0x14c | |
573 | #define EXYNOS3250_TIMER_INT_STAT_SHIFT 31 | |
574 | #define EXYNOS3250_TIMER_INT_STAT (1 << EXYNOS3250_TIMER_INT_STAT_SHIFT) | |
575 | #define EXYNOS3250_TIMER_CNT_SHIFT 0 | |
576 | #define EXYNOS3250_TIMER_CNT_MASK 0x7fffffff | |
577 | ||
578 | /* Command status register */ | |
579 | #define EXYNOS3250_COMSTAT 0x150 | |
580 | #define EXYNOS3250_CUR_PROC_MODE (0x1 << 1) | |
581 | #define EXYNOS3250_CUR_COM_MODE (0x1 << 0) | |
582 | ||
583 | /* JPEG decompression output format register */ | |
584 | #define EXYNOS3250_OUTFORM 0x154 | |
585 | #define EXYNOS3250_OUT_ALPHA_MASK (0xff << 24) | |
586 | #define EXYNOS3250_OUT_TILE_EN (0x1 << 10) | |
587 | #define EXYNOS3250_OUT_NV_MASK (0x1 << 9) | |
588 | #define EXYNOS3250_OUT_NV12 (0x0 << 9) | |
589 | #define EXYNOS3250_OUT_NV21 (0x1 << 9) | |
590 | #define EXYNOS3250_OUT_BIG_ENDIAN_MASK (0x1 << 8) | |
591 | #define EXYNOS3250_OUT_BIG_ENDIAN (0x1 << 8) | |
592 | #define EXYNOS3250_OUT_SWAP_RGB (0x1 << 7) | |
593 | #define EXYNOS3250_OUT_SWAP_UV (0x1 << 6) | |
594 | #define EXYNOS3250_OUT_FMT_MASK (0x7 << 0) | |
595 | #define EXYNOS3250_OUT_FMT_420_2P (0x0 << 0) | |
596 | #define EXYNOS3250_OUT_FMT_422_1P_LUM_CHR (0x1 << 0) | |
597 | #define EXYNOS3250_OUT_FMT_422_1P_CHR_LUM (0x3 << 0) | |
598 | #define EXYNOS3250_OUT_FMT_420_3P (0x4 << 0) | |
599 | #define EXYNOS3250_OUT_FMT_RGB565 (0x5 << 0) | |
600 | #define EXYNOS3250_OUT_FMT_ARGB8888 (0x6 << 0) | |
601 | ||
602 | /* Input JPEG stream byte size for decompression */ | |
603 | #define EXYNOS3250_DEC_STREAM_SIZE 0x158 | |
604 | #define EXYNOS3250_DEC_STREAM_MASK 0x1fffffff | |
605 | ||
606 | /* The upper bound of the byte size of output compressed stream */ | |
607 | #define EXYNOS3250_ENC_STREAM_BOUND 0x15c | |
608 | #define EXYNOS3250_ENC_STREAM_BOUND_MASK 0xffffc0 | |
609 | ||
610 | /* Scale-down ratio when decoding */ | |
611 | #define EXYNOS3250_DEC_SCALING_RATIO 0x160 | |
612 | #define EXYNOS3250_DEC_SCALE_FACTOR_MASK 0x3 | |
613 | #define EXYNOS3250_DEC_SCALE_FACTOR_8_8 0x0 | |
614 | #define EXYNOS3250_DEC_SCALE_FACTOR_4_8 0x1 | |
615 | #define EXYNOS3250_DEC_SCALE_FACTOR_2_8 0x2 | |
616 | #define EXYNOS3250_DEC_SCALE_FACTOR_1_8 0x3 | |
617 | ||
618 | /* Error check */ | |
619 | #define EXYNOS3250_CRC_RESULT 0x164 | |
620 | ||
621 | /* RDMA and WDMA operation status register */ | |
622 | #define EXYNOS3250_DMA_OPER_STATUS 0x168 | |
623 | #define EXYNOS3250_WDMA_OPER_STATUS (0x1 << 1) | |
624 | #define EXYNOS3250_RDMA_OPER_STATUS (0x1 << 0) | |
625 | ||
626 | /* DMA issue gathering number and issue number settings */ | |
627 | #define EXYNOS3250_DMA_ISSUE_NUM 0x16c | |
628 | #define EXYNOS3250_WDMA_ISSUE_NUM_SHIFT 16 | |
629 | #define EXYNOS3250_WDMA_ISSUE_NUM_MASK (0x7 << EXYNOS3250_WDMA_ISSUE_NUM_SHIFT) | |
630 | #define EXYNOS3250_RDMA_ISSUE_NUM_SHIFT 8 | |
631 | #define EXYNOS3250_RDMA_ISSUE_NUM_MASK (0x7 << EXYNOS3250_RDMA_ISSUE_NUM_SHIFT) | |
632 | #define EXYNOS3250_ISSUE_GATHER_NUM_SHIFT 0 | |
633 | #define EXYNOS3250_ISSUE_GATHER_NUM_MASK (0x7 << EXYNOS3250_ISSUE_GATHER_NUM_SHIFT) | |
634 | #define EXYNOS3250_DMA_MO_COUNT 0x7 | |
635 | ||
636 | /* Version register */ | |
637 | #define EXYNOS3250_VERSION 0x1fc | |
638 | ||
639 | /* RGB <-> YUV conversion coefficients */ | |
640 | #define EXYNOS3250_JPEG_ENC_COEF1 0x01352e1e | |
641 | #define EXYNOS3250_JPEG_ENC_COEF2 0x00b0ae83 | |
642 | #define EXYNOS3250_JPEG_ENC_COEF3 0x020cdc13 | |
643 | ||
644 | #define EXYNOS3250_JPEG_DEC_COEF1 0x04a80199 | |
645 | #define EXYNOS3250_JPEG_DEC_COEF2 0x04a9a064 | |
646 | #define EXYNOS3250_JPEG_DEC_COEF3 0x04a80102 | |
647 | ||
bb677f3a AP |
648 | #endif /* JPEG_REGS_H_ */ |
649 |