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f3af9572 LP |
1 | /* |
2 | * vsp1_drm.c -- R-Car VSP1 DRM API | |
3 | * | |
4 | * Copyright (C) 2015 Renesas Electronics Corporation | |
5 | * | |
6 | * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/device.h> | |
15 | #include <linux/slab.h> | |
f3af9572 LP |
16 | |
17 | #include <media/media-entity.h> | |
18 | #include <media/v4l2-subdev.h> | |
c1741af7 | 19 | #include <media/vsp1.h> |
f3af9572 LP |
20 | |
21 | #include "vsp1.h" | |
22 | #include "vsp1_bru.h" | |
1517b039 | 23 | #include "vsp1_dl.h" |
f3af9572 LP |
24 | #include "vsp1_drm.h" |
25 | #include "vsp1_lif.h" | |
26 | #include "vsp1_pipe.h" | |
27 | #include "vsp1_rwpf.h" | |
28 | ||
c2dd2513 LP |
29 | |
30 | /* ----------------------------------------------------------------------------- | |
31 | * Interrupt Handling | |
32 | */ | |
33 | ||
34 | void vsp1_drm_frame_end(struct vsp1_pipeline *pipe) | |
35 | { | |
36 | struct vsp1_device *vsp1 = pipe->output->entity.vsp1; | |
37 | ||
38 | vsp1_dlm_irq_frame_end(&vsp1->drm->dlm); | |
39 | } | |
40 | ||
f3af9572 LP |
41 | /* ----------------------------------------------------------------------------- |
42 | * DU Driver API | |
43 | */ | |
44 | ||
45 | int vsp1_du_init(struct device *dev) | |
46 | { | |
47 | struct vsp1_device *vsp1 = dev_get_drvdata(dev); | |
48 | ||
49 | if (!vsp1) | |
50 | return -EPROBE_DEFER; | |
51 | ||
52 | return 0; | |
53 | } | |
54 | EXPORT_SYMBOL_GPL(vsp1_du_init); | |
55 | ||
56 | /** | |
57 | * vsp1_du_setup_lif - Setup the output part of the VSP pipeline | |
58 | * @dev: the VSP device | |
59 | * @width: output frame width in pixels | |
60 | * @height: output frame height in pixels | |
61 | * | |
62 | * Configure the output part of VSP DRM pipeline for the given frame @width and | |
63 | * @height. This sets up formats on the BRU source pad, the WPF0 sink and source | |
64 | * pads, and the LIF sink pad. | |
65 | * | |
66 | * As the media bus code on the BRU source pad is conditioned by the | |
67 | * configuration of the BRU sink 0 pad, we also set up the formats on all BRU | |
68 | * sinks, even if the configuration will be overwritten later by | |
69 | * vsp1_du_setup_rpf(). This ensures that the BRU configuration is set to a well | |
70 | * defined state. | |
71 | * | |
72 | * Return 0 on success or a negative error code on failure. | |
73 | */ | |
74 | int vsp1_du_setup_lif(struct device *dev, unsigned int width, | |
75 | unsigned int height) | |
76 | { | |
77 | struct vsp1_device *vsp1 = dev_get_drvdata(dev); | |
78 | struct vsp1_pipeline *pipe = &vsp1->drm->pipe; | |
79 | struct vsp1_bru *bru = vsp1->bru; | |
80 | struct v4l2_subdev_format format; | |
81 | unsigned int i; | |
82 | int ret; | |
83 | ||
84 | dev_dbg(vsp1->dev, "%s: configuring LIF with format %ux%u\n", | |
85 | __func__, width, height); | |
86 | ||
87 | if (width == 0 || height == 0) { | |
88 | /* Zero width or height means the CRTC is being disabled, stop | |
89 | * the pipeline and turn the light off. | |
90 | */ | |
91 | ret = vsp1_pipeline_stop(pipe); | |
92 | if (ret == -ETIMEDOUT) | |
93 | dev_err(vsp1->dev, "DRM pipeline stop timeout\n"); | |
94 | ||
95 | media_entity_pipeline_stop(&pipe->output->entity.subdev.entity); | |
96 | ||
97 | for (i = 0; i < bru->entity.source_pad; ++i) { | |
98 | bru->inputs[i].rpf = NULL; | |
99 | pipe->inputs[i] = NULL; | |
100 | } | |
101 | ||
102 | pipe->num_inputs = 0; | |
103 | ||
c2dd2513 | 104 | vsp1_dlm_reset(&vsp1->drm->dlm); |
f3af9572 LP |
105 | vsp1_device_put(vsp1); |
106 | ||
107 | dev_dbg(vsp1->dev, "%s: pipeline disabled\n", __func__); | |
108 | ||
109 | return 0; | |
110 | } | |
111 | ||
112 | /* Configure the format at the BRU sinks and propagate it through the | |
113 | * pipeline. | |
114 | */ | |
115 | memset(&format, 0, sizeof(format)); | |
116 | format.which = V4L2_SUBDEV_FORMAT_ACTIVE; | |
117 | ||
118 | for (i = 0; i < bru->entity.source_pad; ++i) { | |
119 | format.pad = i; | |
120 | ||
121 | format.format.width = width; | |
122 | format.format.height = height; | |
123 | format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32; | |
124 | format.format.field = V4L2_FIELD_NONE; | |
125 | ||
126 | ret = v4l2_subdev_call(&bru->entity.subdev, pad, | |
127 | set_fmt, NULL, &format); | |
128 | if (ret < 0) | |
129 | return ret; | |
130 | ||
131 | dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on BRU pad %u\n", | |
132 | __func__, format.format.width, format.format.height, | |
133 | format.format.code, i); | |
134 | } | |
135 | ||
136 | format.pad = bru->entity.source_pad; | |
137 | format.format.width = width; | |
138 | format.format.height = height; | |
139 | format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32; | |
140 | format.format.field = V4L2_FIELD_NONE; | |
141 | ||
142 | ret = v4l2_subdev_call(&bru->entity.subdev, pad, set_fmt, NULL, | |
143 | &format); | |
144 | if (ret < 0) | |
145 | return ret; | |
146 | ||
147 | dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on BRU pad %u\n", | |
148 | __func__, format.format.width, format.format.height, | |
149 | format.format.code, i); | |
150 | ||
151 | format.pad = RWPF_PAD_SINK; | |
152 | ret = v4l2_subdev_call(&vsp1->wpf[0]->entity.subdev, pad, set_fmt, NULL, | |
153 | &format); | |
154 | if (ret < 0) | |
155 | return ret; | |
156 | ||
157 | dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF0 sink\n", | |
158 | __func__, format.format.width, format.format.height, | |
159 | format.format.code); | |
160 | ||
161 | format.pad = RWPF_PAD_SOURCE; | |
162 | ret = v4l2_subdev_call(&vsp1->wpf[0]->entity.subdev, pad, get_fmt, NULL, | |
163 | &format); | |
164 | if (ret < 0) | |
165 | return ret; | |
166 | ||
167 | dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF0 source\n", | |
168 | __func__, format.format.width, format.format.height, | |
169 | format.format.code); | |
170 | ||
171 | format.pad = LIF_PAD_SINK; | |
172 | ret = v4l2_subdev_call(&vsp1->lif->entity.subdev, pad, set_fmt, NULL, | |
173 | &format); | |
174 | if (ret < 0) | |
175 | return ret; | |
176 | ||
177 | dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF sink\n", | |
178 | __func__, format.format.width, format.format.height, | |
179 | format.format.code); | |
180 | ||
181 | /* Verify that the format at the output of the pipeline matches the | |
182 | * requested frame size and media bus code. | |
183 | */ | |
184 | if (format.format.width != width || format.format.height != height || | |
185 | format.format.code != MEDIA_BUS_FMT_ARGB8888_1X32) { | |
186 | dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__); | |
187 | return -EPIPE; | |
188 | } | |
189 | ||
190 | /* Mark the pipeline as streaming and enable the VSP1. This will store | |
191 | * the pipeline pointer in all entities, which the s_stream handlers | |
192 | * will need. We don't start the entities themselves right at this point | |
193 | * as there's no plane configured yet, so we can't start processing | |
194 | * buffers. | |
195 | */ | |
196 | ret = vsp1_device_get(vsp1); | |
197 | if (ret < 0) | |
198 | return ret; | |
199 | ||
200 | ret = media_entity_pipeline_start(&pipe->output->entity.subdev.entity, | |
201 | &pipe->pipe); | |
202 | if (ret < 0) { | |
203 | dev_dbg(vsp1->dev, "%s: pipeline start failed\n", __func__); | |
204 | vsp1_device_put(vsp1); | |
205 | return ret; | |
206 | } | |
207 | ||
208 | dev_dbg(vsp1->dev, "%s: pipeline enabled\n", __func__); | |
209 | ||
210 | return 0; | |
211 | } | |
212 | EXPORT_SYMBOL_GPL(vsp1_du_setup_lif); | |
213 | ||
214 | /** | |
7b4baddc LP |
215 | * vsp1_du_atomic_begin - Prepare for an atomic update |
216 | * @dev: the VSP device | |
217 | */ | |
218 | void vsp1_du_atomic_begin(struct device *dev) | |
219 | { | |
220 | struct vsp1_device *vsp1 = dev_get_drvdata(dev); | |
221 | struct vsp1_pipeline *pipe = &vsp1->drm->pipe; | |
222 | unsigned long flags; | |
223 | ||
224 | spin_lock_irqsave(&pipe->irqlock, flags); | |
225 | ||
226 | vsp1->drm->num_inputs = pipe->num_inputs; | |
7b4baddc LP |
227 | |
228 | spin_unlock_irqrestore(&pipe->irqlock, flags); | |
1517b039 TS |
229 | |
230 | /* Prepare the display list. */ | |
c2dd2513 | 231 | pipe->dl = vsp1_dl_list_get(&vsp1->drm->dlm); |
7b4baddc LP |
232 | } |
233 | EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin); | |
234 | ||
235 | /** | |
236 | * vsp1_du_atomic_update - Setup one RPF input of the VSP pipeline | |
f3af9572 LP |
237 | * @dev: the VSP device |
238 | * @rpf_index: index of the RPF to setup (0-based) | |
239 | * @pixelformat: V4L2 pixel format for the RPF memory input | |
240 | * @pitch: number of bytes per line in the image stored in memory | |
241 | * @mem: DMA addresses of the memory buffers (one per plane) | |
242 | * @src: the source crop rectangle for the RPF | |
243 | * @dst: the destination compose rectangle for the BRU input | |
244 | * | |
245 | * Configure the VSP to perform composition of the image referenced by @mem | |
246 | * through RPF @rpf_index, using the @src crop rectangle and the @dst | |
247 | * composition rectangle. The Z-order is fixed with RPF 0 at the bottom. | |
248 | * | |
249 | * Image format as stored in memory is expressed as a V4L2 @pixelformat value. | |
250 | * As a special case, setting the pixel format to 0 will disable the RPF. The | |
251 | * @pitch, @mem, @src and @dst parameters are ignored in that case. Calling the | |
252 | * function on a disabled RPF is allowed. | |
253 | * | |
254 | * The memory pitch is configurable to allow for padding at end of lines, or | |
255 | * simple for images that extend beyond the crop rectangle boundaries. The | |
256 | * @pitch value is expressed in bytes and applies to all planes for multiplanar | |
257 | * formats. | |
258 | * | |
259 | * The source memory buffer is referenced by the DMA address of its planes in | |
260 | * the @mem array. Up to two planes are supported. The second plane DMA address | |
261 | * is ignored for formats using a single plane. | |
262 | * | |
263 | * This function isn't reentrant, the caller needs to serialize calls. | |
264 | * | |
265 | * TODO: Implement Z-order control by decoupling the RPF index from the BRU | |
266 | * input index. | |
267 | * | |
268 | * Return 0 on success or a negative error code on failure. | |
269 | */ | |
7b4baddc LP |
270 | int vsp1_du_atomic_update(struct device *dev, unsigned int rpf_index, |
271 | u32 pixelformat, unsigned int pitch, | |
272 | dma_addr_t mem[2], const struct v4l2_rect *src, | |
273 | const struct v4l2_rect *dst) | |
f3af9572 LP |
274 | { |
275 | struct vsp1_device *vsp1 = dev_get_drvdata(dev); | |
276 | struct vsp1_pipeline *pipe = &vsp1->drm->pipe; | |
277 | const struct vsp1_format_info *fmtinfo; | |
278 | struct v4l2_subdev_selection sel; | |
279 | struct v4l2_subdev_format format; | |
280 | struct vsp1_rwpf_memory memory; | |
281 | struct vsp1_rwpf *rpf; | |
282 | unsigned long flags; | |
f3af9572 LP |
283 | int ret; |
284 | ||
5aa2eb3c | 285 | if (rpf_index >= vsp1->info->rpf_count) |
f3af9572 LP |
286 | return -EINVAL; |
287 | ||
288 | rpf = vsp1->rpf[rpf_index]; | |
289 | ||
290 | if (pixelformat == 0) { | |
291 | dev_dbg(vsp1->dev, "%s: RPF%u: disable requested\n", __func__, | |
292 | rpf_index); | |
293 | ||
294 | spin_lock_irqsave(&pipe->irqlock, flags); | |
295 | ||
296 | if (pipe->inputs[rpf_index]) { | |
297 | /* Remove the RPF from the pipeline if it was previously | |
298 | * enabled. | |
299 | */ | |
300 | vsp1->bru->inputs[rpf_index].rpf = NULL; | |
301 | pipe->inputs[rpf_index] = NULL; | |
302 | ||
7b4baddc | 303 | pipe->num_inputs--; |
f3af9572 LP |
304 | } |
305 | ||
306 | spin_unlock_irqrestore(&pipe->irqlock, flags); | |
307 | ||
f3af9572 LP |
308 | return 0; |
309 | } | |
310 | ||
311 | dev_dbg(vsp1->dev, | |
312 | "%s: RPF%u: (%u,%u)/%ux%u -> (%u,%u)/%ux%u (%08x), pitch %u dma { %pad, %pad }\n", | |
313 | __func__, rpf_index, | |
314 | src->left, src->top, src->width, src->height, | |
315 | dst->left, dst->top, dst->width, dst->height, | |
316 | pixelformat, pitch, &mem[0], &mem[1]); | |
317 | ||
318 | /* Set the stride at the RPF input. */ | |
319 | fmtinfo = vsp1_get_format_info(pixelformat); | |
320 | if (!fmtinfo) { | |
321 | dev_dbg(vsp1->dev, "Unsupport pixel format %08x for RPF\n", | |
322 | pixelformat); | |
323 | return -EINVAL; | |
324 | } | |
325 | ||
326 | rpf->fmtinfo = fmtinfo; | |
327 | rpf->format.num_planes = fmtinfo->planes; | |
328 | rpf->format.plane_fmt[0].bytesperline = pitch; | |
329 | rpf->format.plane_fmt[1].bytesperline = pitch; | |
330 | ||
331 | /* Configure the format on the RPF sink pad and propagate it up to the | |
332 | * BRU sink pad. | |
333 | */ | |
334 | memset(&format, 0, sizeof(format)); | |
335 | format.which = V4L2_SUBDEV_FORMAT_ACTIVE; | |
336 | format.pad = RWPF_PAD_SINK; | |
337 | format.format.width = src->width + src->left; | |
338 | format.format.height = src->height + src->top; | |
339 | format.format.code = fmtinfo->mbus; | |
340 | format.format.field = V4L2_FIELD_NONE; | |
341 | ||
342 | ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL, | |
343 | &format); | |
344 | if (ret < 0) | |
345 | return ret; | |
346 | ||
347 | dev_dbg(vsp1->dev, | |
348 | "%s: set format %ux%u (%x) on RPF%u sink\n", | |
349 | __func__, format.format.width, format.format.height, | |
350 | format.format.code, rpf->entity.index); | |
351 | ||
352 | memset(&sel, 0, sizeof(sel)); | |
353 | sel.which = V4L2_SUBDEV_FORMAT_ACTIVE; | |
354 | sel.pad = RWPF_PAD_SINK; | |
355 | sel.target = V4L2_SEL_TGT_CROP; | |
356 | sel.r = *src; | |
357 | ||
358 | ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_selection, NULL, | |
359 | &sel); | |
360 | if (ret < 0) | |
361 | return ret; | |
362 | ||
363 | dev_dbg(vsp1->dev, | |
364 | "%s: set selection (%u,%u)/%ux%u on RPF%u sink\n", | |
365 | __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height, | |
366 | rpf->entity.index); | |
367 | ||
368 | /* RPF source, hardcode the format to ARGB8888 to turn on format | |
369 | * conversion if needed. | |
370 | */ | |
371 | format.pad = RWPF_PAD_SOURCE; | |
372 | ||
373 | ret = v4l2_subdev_call(&rpf->entity.subdev, pad, get_fmt, NULL, | |
374 | &format); | |
375 | if (ret < 0) | |
376 | return ret; | |
377 | ||
378 | dev_dbg(vsp1->dev, | |
379 | "%s: got format %ux%u (%x) on RPF%u source\n", | |
380 | __func__, format.format.width, format.format.height, | |
381 | format.format.code, rpf->entity.index); | |
382 | ||
383 | format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32; | |
384 | ||
385 | ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL, | |
386 | &format); | |
387 | if (ret < 0) | |
388 | return ret; | |
389 | ||
390 | /* BRU sink, propagate the format from the RPF source. */ | |
391 | format.pad = rpf->entity.index; | |
392 | ||
393 | ret = v4l2_subdev_call(&vsp1->bru->entity.subdev, pad, set_fmt, NULL, | |
394 | &format); | |
395 | if (ret < 0) | |
396 | return ret; | |
397 | ||
398 | dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on BRU pad %u\n", | |
399 | __func__, format.format.width, format.format.height, | |
400 | format.format.code, format.pad); | |
401 | ||
402 | sel.pad = rpf->entity.index; | |
403 | sel.target = V4L2_SEL_TGT_COMPOSE; | |
404 | sel.r = *dst; | |
405 | ||
406 | ret = v4l2_subdev_call(&vsp1->bru->entity.subdev, pad, set_selection, | |
407 | NULL, &sel); | |
408 | if (ret < 0) | |
409 | return ret; | |
410 | ||
411 | dev_dbg(vsp1->dev, | |
412 | "%s: set selection (%u,%u)/%ux%u on BRU pad %u\n", | |
413 | __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height, | |
414 | sel.pad); | |
415 | ||
416 | /* Store the compose rectangle coordinates in the RPF. */ | |
417 | rpf->location.left = dst->left; | |
418 | rpf->location.top = dst->top; | |
419 | ||
420 | /* Set the memory buffer address. */ | |
421 | memory.num_planes = fmtinfo->planes; | |
422 | memory.addr[0] = mem[0]; | |
423 | memory.addr[1] = mem[1]; | |
424 | ||
425 | rpf->ops->set_memory(rpf, &memory); | |
426 | ||
427 | spin_lock_irqsave(&pipe->irqlock, flags); | |
428 | ||
429 | /* If the RPF was previously stopped set the BRU input to the RPF and | |
430 | * store the RPF in the pipeline inputs array. | |
431 | */ | |
432 | if (!pipe->inputs[rpf->entity.index]) { | |
433 | vsp1->bru->inputs[rpf_index].rpf = rpf; | |
434 | pipe->inputs[rpf->entity.index] = rpf; | |
7b4baddc | 435 | pipe->num_inputs++; |
f3af9572 LP |
436 | } |
437 | ||
7b4baddc LP |
438 | spin_unlock_irqrestore(&pipe->irqlock, flags); |
439 | ||
440 | return 0; | |
441 | } | |
442 | EXPORT_SYMBOL_GPL(vsp1_du_atomic_update); | |
443 | ||
444 | /** | |
445 | * vsp1_du_atomic_flush - Commit an atomic update | |
446 | * @dev: the VSP device | |
447 | */ | |
448 | void vsp1_du_atomic_flush(struct device *dev) | |
449 | { | |
450 | struct vsp1_device *vsp1 = dev_get_drvdata(dev); | |
451 | struct vsp1_pipeline *pipe = &vsp1->drm->pipe; | |
1517b039 | 452 | struct vsp1_entity *entity; |
7b4baddc LP |
453 | unsigned long flags; |
454 | bool stop = false; | |
1517b039 | 455 | int ret; |
7b4baddc | 456 | |
1517b039 TS |
457 | list_for_each_entry(entity, &pipe->entities, list_pipe) { |
458 | /* Disconnect unused RPFs from the pipeline. */ | |
459 | if (entity->type == VSP1_ENTITY_RPF) { | |
460 | struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev); | |
461 | ||
462 | if (!pipe->inputs[rpf->entity.index]) { | |
463 | vsp1_mod_write(entity, entity->route->reg, | |
464 | VI6_DPR_NODE_UNUSED); | |
465 | continue; | |
466 | } | |
467 | } | |
468 | ||
469 | vsp1_entity_route_setup(entity); | |
470 | ||
471 | ret = v4l2_subdev_call(&entity->subdev, video, | |
472 | s_stream, 1); | |
473 | if (ret < 0) { | |
474 | dev_err(vsp1->dev, | |
475 | "DRM pipeline start failure on entity %s\n", | |
476 | entity->subdev.name); | |
477 | return; | |
478 | } | |
479 | } | |
480 | ||
c2dd2513 LP |
481 | vsp1_dl_list_commit(pipe->dl); |
482 | pipe->dl = NULL; | |
7b4baddc | 483 | |
1517b039 | 484 | spin_lock_irqsave(&pipe->irqlock, flags); |
7b4baddc LP |
485 | |
486 | /* Start or stop the pipeline if needed. */ | |
1517b039 TS |
487 | if (!vsp1->drm->num_inputs && pipe->num_inputs) { |
488 | vsp1_write(vsp1, VI6_DISP_IRQ_STA, 0); | |
489 | vsp1_write(vsp1, VI6_DISP_IRQ_ENB, VI6_DISP_IRQ_ENB_DSTE); | |
490 | vsp1_pipeline_run(pipe); | |
491 | } else if (vsp1->drm->num_inputs && !pipe->num_inputs) { | |
7b4baddc | 492 | stop = true; |
1517b039 | 493 | } |
f3af9572 LP |
494 | |
495 | spin_unlock_irqrestore(&pipe->irqlock, flags); | |
496 | ||
1517b039 TS |
497 | if (stop) { |
498 | vsp1_write(vsp1, VI6_DISP_IRQ_ENB, 0); | |
7b4baddc | 499 | vsp1_pipeline_stop(pipe); |
1517b039 | 500 | } |
f3af9572 | 501 | } |
7b4baddc | 502 | EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush); |
f3af9572 LP |
503 | |
504 | /* ----------------------------------------------------------------------------- | |
505 | * Initialization | |
506 | */ | |
507 | ||
508 | int vsp1_drm_create_links(struct vsp1_device *vsp1) | |
509 | { | |
510 | const u32 flags = MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE; | |
511 | unsigned int i; | |
512 | int ret; | |
513 | ||
514 | /* VSPD instances require a BRU to perform composition and a LIF to | |
515 | * output to the DU. | |
516 | */ | |
517 | if (!vsp1->bru || !vsp1->lif) | |
518 | return -ENXIO; | |
519 | ||
5aa2eb3c | 520 | for (i = 0; i < vsp1->info->rpf_count; ++i) { |
f3af9572 LP |
521 | struct vsp1_rwpf *rpf = vsp1->rpf[i]; |
522 | ||
523 | ret = media_create_pad_link(&rpf->entity.subdev.entity, | |
524 | RWPF_PAD_SOURCE, | |
525 | &vsp1->bru->entity.subdev.entity, | |
526 | i, flags); | |
527 | if (ret < 0) | |
528 | return ret; | |
529 | ||
530 | rpf->entity.sink = &vsp1->bru->entity.subdev.entity; | |
531 | rpf->entity.sink_pad = i; | |
532 | } | |
533 | ||
534 | ret = media_create_pad_link(&vsp1->bru->entity.subdev.entity, | |
535 | vsp1->bru->entity.source_pad, | |
536 | &vsp1->wpf[0]->entity.subdev.entity, | |
537 | RWPF_PAD_SINK, flags); | |
538 | if (ret < 0) | |
539 | return ret; | |
540 | ||
541 | vsp1->bru->entity.sink = &vsp1->wpf[0]->entity.subdev.entity; | |
542 | vsp1->bru->entity.sink_pad = RWPF_PAD_SINK; | |
543 | ||
544 | ret = media_create_pad_link(&vsp1->wpf[0]->entity.subdev.entity, | |
545 | RWPF_PAD_SOURCE, | |
546 | &vsp1->lif->entity.subdev.entity, | |
547 | LIF_PAD_SINK, flags); | |
548 | if (ret < 0) | |
549 | return ret; | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
554 | int vsp1_drm_init(struct vsp1_device *vsp1) | |
555 | { | |
556 | struct vsp1_pipeline *pipe; | |
557 | unsigned int i; | |
c2dd2513 | 558 | int ret; |
f3af9572 LP |
559 | |
560 | vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL); | |
561 | if (!vsp1->drm) | |
562 | return -ENOMEM; | |
563 | ||
c2dd2513 LP |
564 | ret = vsp1_dlm_init(vsp1, &vsp1->drm->dlm, 4); |
565 | if (ret < 0) | |
566 | return ret; | |
1517b039 | 567 | |
f3af9572 LP |
568 | pipe = &vsp1->drm->pipe; |
569 | ||
570 | vsp1_pipeline_init(pipe); | |
c2dd2513 | 571 | pipe->frame_end = vsp1_drm_frame_end; |
f3af9572 LP |
572 | |
573 | /* The DRM pipeline is static, add entities manually. */ | |
5aa2eb3c | 574 | for (i = 0; i < vsp1->info->rpf_count; ++i) { |
f3af9572 LP |
575 | struct vsp1_rwpf *input = vsp1->rpf[i]; |
576 | ||
577 | list_add_tail(&input->entity.list_pipe, &pipe->entities); | |
578 | } | |
579 | ||
580 | list_add_tail(&vsp1->bru->entity.list_pipe, &pipe->entities); | |
581 | list_add_tail(&vsp1->wpf[0]->entity.list_pipe, &pipe->entities); | |
582 | list_add_tail(&vsp1->lif->entity.list_pipe, &pipe->entities); | |
583 | ||
584 | pipe->bru = &vsp1->bru->entity; | |
585 | pipe->lif = &vsp1->lif->entity; | |
586 | pipe->output = vsp1->wpf[0]; | |
587 | ||
588 | return 0; | |
589 | } | |
1517b039 TS |
590 | |
591 | void vsp1_drm_cleanup(struct vsp1_device *vsp1) | |
592 | { | |
c2dd2513 | 593 | vsp1_dlm_cleanup(&vsp1->drm->dlm); |
1517b039 | 594 | } |