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[media] nuvoton-cir: simplify nvt_cir_tx_inactive
[deliverable/linux.git] / drivers / media / rc / nuvoton-cir.c
CommitLineData
6d2f5c27
JW		 1/*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
563cd5ce
JP		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
6d2f5c27
JW		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pnp.h>
33#include <linux/io.h>
34#include <linux/interrupt.h>
35#include <linux/sched.h>
36#include <linux/slab.h>
6bda9644 37#include <media/rc-core.h>
6d2f5c27
JW		 38#include <linux/pci_ids.h>
39
40#include "nuvoton-cir.h"
41
b5cf725c
HK		 42static const struct nvt_chip nvt_chips[] = {
43 { "w83667hg", NVT_W83667HG },
44 { "NCT6775F", NVT_6775F },
45 { "NCT6776F", NVT_6776F },
d0b528d5 46 { "NCT6779D", NVT_6779D },
b5cf725c
HK		 47};
48
49static inline bool is_w83667hg(struct nvt_dev *nvt)
50{
51 return nvt->chip_ver == NVT_W83667HG;
52}
53
6d2f5c27
JW		 54/* write val to config reg */
55static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
56{
57 outb(reg, nvt->cr_efir);
58 outb(val, nvt->cr_efdr);
59}
60
61/* read val from config reg */
62static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
63{
64 outb(reg, nvt->cr_efir);
65 return inb(nvt->cr_efdr);
66}
67
68/* update config register bit without changing other bits */
69static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
70{
71 u8 tmp = nvt_cr_read(nvt, reg) | val;
72 nvt_cr_write(nvt, tmp, reg);
73}
74
75/* clear config register bit without changing other bits */
76static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
77{
78 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
79 nvt_cr_write(nvt, tmp, reg);
80}
81
82/* enter extended function mode */
3def9ad6 83static inline int nvt_efm_enable(struct nvt_dev *nvt)
6d2f5c27 84{
3def9ad6
HK		 85 if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME))
86 return -EBUSY;
87
6d2f5c27
JW		 88 /* Enabling Extended Function Mode explicitly requires writing 2x */
89 outb(EFER_EFM_ENABLE, nvt->cr_efir);
90 outb(EFER_EFM_ENABLE, nvt->cr_efir);
3def9ad6
HK		 91
92 return 0;
6d2f5c27
JW		 93}
94
95/* exit extended function mode */
96static inline void nvt_efm_disable(struct nvt_dev *nvt)
97{
98 outb(EFER_EFM_DISABLE, nvt->cr_efir);
3def9ad6
HK		 99
100 release_region(nvt->cr_efir, 2);
6d2f5c27
JW		 101}
102
103/*
104 * When you want to address a specific logical device, write its logical
105 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
106 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
107 */
108static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
109{
7a89836e 110 nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL);
6d2f5c27
JW		 111}
112
113/* write val to cir config register */
114static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
115{
116 outb(val, nvt->cir_addr + offset);
117}
118
119/* read val from cir config register */
120static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
121{
122 u8 val;
123
124 val = inb(nvt->cir_addr + offset);
125
126 return val;
127}
128
129/* write val to cir wake register */
130static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
131 u8 val, u8 offset)
132{
133 outb(val, nvt->cir_wake_addr + offset);
134}
135
136/* read val from cir wake config register */
137static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
138{
139 u8 val;
140
141 val = inb(nvt->cir_wake_addr + offset);
142
143 return val;
144}
145
146/* dump current cir register contents */
147static void cir_dump_regs(struct nvt_dev *nvt)
148{
149 nvt_efm_enable(nvt);
150 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
151
563cd5ce
JP		 152 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
153 pr_info(" * CR CIR ACTIVE : 0x%x\n",
154 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
155 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
156 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
6d2f5c27 157 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
563cd5ce
JP		 158 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
159 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
6d2f5c27
JW		 160
161 nvt_efm_disable(nvt);
162
563cd5ce
JP		 163 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
164 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
165 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
166 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
167 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
168 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
169 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
170 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
171 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
172 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
173 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
174 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
175 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
176 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
177 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
178 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
179 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
6d2f5c27
JW		 180}
181
182/* dump current cir wake register contents */
183static void cir_wake_dump_regs(struct nvt_dev *nvt)
184{
185 u8 i, fifo_len;
186
187 nvt_efm_enable(nvt);
188 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
189
563cd5ce
JP		 190 pr_info("%s: Dump CIR WAKE logical device registers:\n",
191 NVT_DRIVER_NAME);
192 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
193 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
194 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
195 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
4e6e29ad 196 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
563cd5ce
JP		 197 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
198 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
6d2f5c27
JW		 199
200 nvt_efm_disable(nvt);
201
563cd5ce
JP		 202 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
203 pr_info(" * IRCON: 0x%x\n",
204 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
205 pr_info(" * IRSTS: 0x%x\n",
206 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
207 pr_info(" * IREN: 0x%x\n",
208 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
209 pr_info(" * FIFO CMP DEEP: 0x%x\n",
210 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
211 pr_info(" * FIFO CMP TOL: 0x%x\n",
212 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
213 pr_info(" * FIFO COUNT: 0x%x\n",
214 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
215 pr_info(" * SLCH: 0x%x\n",
216 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
217 pr_info(" * SLCL: 0x%x\n",
218 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
219 pr_info(" * FIFOCON: 0x%x\n",
220 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
221 pr_info(" * SRXFSTS: 0x%x\n",
222 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
223 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
224 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
225 pr_info(" * WR FIFO DATA: 0x%x\n",
226 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
227 pr_info(" * RD FIFO ONLY: 0x%x\n",
228 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
229 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
230 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
231 pr_info(" * FIFO IGNORE: 0x%x\n",
232 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
233 pr_info(" * IRFSM: 0x%x\n",
234 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
6d2f5c27
JW		 235
236 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
563cd5ce
JP		 237 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
238 pr_info("* Contents =");
6d2f5c27 239 for (i = 0; i < fifo_len; i++)
563cd5ce
JP		 240 pr_cont(" %02x",
241 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
242 pr_cont("\n");
6d2f5c27
JW		 243}
244
b5cf725c
HK		 245static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
246{
247 int i;
248
249 for (i = 0; i < ARRAY_SIZE(nvt_chips); i++)
250 if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) {
251 nvt->chip_ver = nvt_chips[i].chip_ver;
252 return nvt_chips[i].name;
253 }
254
255 return NULL;
256}
257
258
6d2f5c27 259/* detect hardware features */
6a5a3360 260static void nvt_hw_detect(struct nvt_dev *nvt)
6d2f5c27 261{
b5cf725c
HK		 262 const char *chip_name;
263 int chip_id;
6d2f5c27
JW		 264
265 nvt_efm_enable(nvt);
266
267 /* Check if we're wired for the alternate EFER setup */
b5cf725c
HK		 268 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
269 if (nvt->chip_major == 0xff) {
6d2f5c27
JW		 270 nvt->cr_efir = CR_EFIR2;
271 nvt->cr_efdr = CR_EFDR2;
272 nvt_efm_enable(nvt);
b5cf725c 273 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
6d2f5c27
JW		 274 }
275
b5cf725c
HK		 276 nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
277
278 chip_id = nvt->chip_major << 8 | nvt->chip_minor;
279 chip_name = nvt_find_chip(nvt, chip_id);
6d2f5c27 280
362d3a3a 281 /* warn, but still let the driver load, if we don't know this chip */
b5cf725c 282 if (!chip_name)
211477fe
HK		 283 dev_warn(&nvt->pdev->dev,
284 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
285 nvt->chip_major, nvt->chip_minor);
362d3a3a 286 else
af082334
HK		 287 dev_info(&nvt->pdev->dev,
288 "found %s or compatible: chip id: 0x%02x 0x%02x",
289 chip_name, nvt->chip_major, nvt->chip_minor);
362d3a3a 290
6d2f5c27 291 nvt_efm_disable(nvt);
6d2f5c27
JW		 292}
293
294static void nvt_cir_ldev_init(struct nvt_dev *nvt)
295{
39381d4f
JW		 296 u8 val, psreg, psmask, psval;
297
b5cf725c 298 if (is_w83667hg(nvt)) {
39381d4f
JW		 299 psreg = CR_MULTIFUNC_PIN_SEL;
300 psmask = MULTIFUNC_PIN_SEL_MASK;
301 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
302 } else {
303 psreg = CR_OUTPUT_PIN_SEL;
304 psmask = OUTPUT_PIN_SEL_MASK;
305 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
306 }
6d2f5c27 307
39381d4f
JW		 308 /* output pin selection: enable CIR, with WB sensor enabled */
309 val = nvt_cr_read(nvt, psreg);
310 val &= psmask;
311 val |= psval;
312 nvt_cr_write(nvt, val, psreg);
6d2f5c27
JW		 313
314 /* Select CIR logical device and enable */
315 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
316 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
317
318 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
319 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
320
321 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
322
323 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
324 nvt->cir_addr, nvt->cir_irq);
325}
326
327static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
328{
329 /* Select ACPI logical device, enable it and CIR Wake */
330 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
331 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
332
333 /* Enable CIR Wake via PSOUT# (Pin60) */
334 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
335
6d2f5c27
JW		 336 /* enable pme interrupt of cir wakeup event */
337 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
338
339 /* Select CIR Wake logical device and enable */
340 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
341 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
342
343 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
344 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
345
346 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
347
348 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
349 nvt->cir_wake_addr, nvt->cir_wake_irq);
350}
351
352/* clear out the hardware's cir rx fifo */
353static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
354{
355 u8 val;
356
357 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
358 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
359}
360
361/* clear out the hardware's cir wake rx fifo */
362static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
363{
364 u8 val;
365
366 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
367 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
368 CIR_WAKE_FIFOCON);
369}
370
371/* clear out the hardware's cir tx fifo */
372static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
373{
374 u8 val;
375
376 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
377 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
378}
379
fbdc781c
JW		 380/* enable RX Trigger Level Reach and Packet End interrupts */
381static void nvt_set_cir_iren(struct nvt_dev *nvt)
382{
383 u8 iren;
384
385 iren = CIR_IREN_RTR | CIR_IREN_PE;
386 nvt_cir_reg_write(nvt, iren, CIR_IREN);
387}
388
6d2f5c27
JW		 389static void nvt_cir_regs_init(struct nvt_dev *nvt)
390{
391 /* set sample limit count (PE interrupt raised when reached) */
392 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
393 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
394
395 /* set fifo irq trigger levels */
396 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
397 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
398
399 /*
400 * Enable TX and RX, specify carrier on = low, off = high, and set
401 * sample period (currently 50us)
402 */
4e6e29ad
JW		 403 nvt_cir_reg_write(nvt,
404 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
405 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
406 CIR_IRCON);
6d2f5c27
JW		 407
408 /* clear hardware rx and tx fifos */
409 nvt_clear_cir_fifo(nvt);
410 nvt_clear_tx_fifo(nvt);
411
412 /* clear any and all stray interrupts */
413 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
414
fbdc781c
JW		 415 /* and finally, enable interrupts */
416 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 417}
418
419static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
420{
3198ed16
JW		 421 /* set number of bytes needed for wake from s3 (default 65) */
422 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
423 CIR_WAKE_FIFO_CMP_DEEP);
6d2f5c27
JW		 424
425 /* set tolerance/variance allowed per byte during wake compare */
426 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
427 CIR_WAKE_FIFO_CMP_TOL);
428
429 /* set sample limit count (PE interrupt raised when reached) */
430 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
431 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
432
433 /* set cir wake fifo rx trigger level (currently 67) */
434 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
435 CIR_WAKE_FIFOCON);
436
437 /*
438 * Enable TX and RX, specific carrier on = low, off = high, and set
439 * sample period (currently 50us)
440 */
441 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
442 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
443 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
444 CIR_WAKE_IRCON);
445
446 /* clear cir wake rx fifo */
447 nvt_clear_cir_wake_fifo(nvt);
448
449 /* clear any and all stray interrupts */
450 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
451}
452
453static void nvt_enable_wake(struct nvt_dev *nvt)
454{
455 nvt_efm_enable(nvt);
456
457 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
458 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
6d2f5c27
JW		 459 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
460
461 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
462 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
463
464 nvt_efm_disable(nvt);
465
466 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
467 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
4e6e29ad
JW		 468 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
469 CIR_WAKE_IRCON);
6d2f5c27
JW		 470 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
471 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
472}
473
230dc94a 474#if 0 /* Currently unused */
6d2f5c27
JW		 475/* rx carrier detect only works in learning mode, must be called w/nvt_lock */
476static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
477{
478 u32 count, carrier, duration = 0;
479 int i;
480
481 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
482 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
483
484 for (i = 0; i < nvt->pkts; i++) {
485 if (nvt->buf[i] & BUF_PULSE_BIT)
486 duration += nvt->buf[i] & BUF_LEN_MASK;
487 }
488
489 duration *= SAMPLE_PERIOD;
490
491 if (!count || !duration) {
211477fe
HK		 492 dev_notice(&nvt->pdev->dev,
493 "Unable to determine carrier! (c:%u, d:%u)",
494 count, duration);
6d2f5c27
JW		 495 return 0;
496 }
497
b4608fae 498 carrier = MS_TO_NS(count) / duration;
6d2f5c27
JW		 499
500 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
501 nvt_dbg("WTF? Carrier frequency out of range!");
502
503 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
504 carrier, count, duration);
505
506 return carrier;
507}
230dc94a 508#endif
6d2f5c27
JW		 509/*
510 * set carrier frequency
511 *
512 * set carrier on 2 registers: CP & CC
513 * always set CP as 0x81
514 * set CC by SPEC, CC = 3MHz/carrier - 1
515 */
d8b4b582 516static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
6d2f5c27 517{
d8b4b582 518 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 519 u16 val;
520
48cafec9
DC		 521 if (carrier == 0)
522 return -EINVAL;
523
6d2f5c27
JW		 524 nvt_cir_reg_write(nvt, 1, CIR_CP);
525 val = 3000000 / (carrier) - 1;
526 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
527
528 nvt_dbg("cp: 0x%x cc: 0x%x\n",
529 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
530
531 return 0;
532}
533
534/*
535 * nvt_tx_ir
536 *
537 * 1) clean TX fifo first (handled by AP)
538 * 2) copy data from user space
539 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
540 * 4) send 9 packets to TX FIFO to open TTR
541 * in interrupt_handler:
542 * 5) send all data out
543 * go back to write():
544 * 6) disable TX interrupts, re-enable RX interupts
545 *
546 * The key problem of this function is user space data may larger than
547 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
548 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
549 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
550 * set TXFCONT as 0xff, until buf_count less than 0xff.
551 */
5588dc2b 552static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
6d2f5c27 553{
d8b4b582 554 struct nvt_dev *nvt = dev->priv;
6d2f5c27 555 unsigned long flags;
6d2f5c27
JW		 556 unsigned int i;
557 u8 iren;
558 int ret;
559
560 spin_lock_irqsave(&nvt->tx.lock, flags);
561
5588dc2b
DH		 562 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
563 nvt->tx.buf_count = (ret * sizeof(unsigned));
6d2f5c27
JW		 564
565 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
566
567 nvt->tx.cur_buf_num = 0;
568
569 /* save currently enabled interrupts */
570 iren = nvt_cir_reg_read(nvt, CIR_IREN);
571
572 /* now disable all interrupts, save TFU & TTR */
573 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
574
575 nvt->tx.tx_state = ST_TX_REPLY;
576
577 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
578 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
579
580 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
581 for (i = 0; i < 9; i++)
582 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
583
584 spin_unlock_irqrestore(&nvt->tx.lock, flags);
585
586 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
587
588 spin_lock_irqsave(&nvt->tx.lock, flags);
589 nvt->tx.tx_state = ST_TX_NONE;
590 spin_unlock_irqrestore(&nvt->tx.lock, flags);
591
592 /* restore enabled interrupts to prior state */
593 nvt_cir_reg_write(nvt, iren, CIR_IREN);
594
595 return ret;
596}
597
598/* dump contents of the last rx buffer we got from the hw rx fifo */
599static void nvt_dump_rx_buf(struct nvt_dev *nvt)
600{
601 int i;
602
4e6e29ad 603 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
6d2f5c27 604 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
4e6e29ad
JW		 605 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
606 printk(KERN_CONT "\n");
6d2f5c27
JW		 607}
608
609/*
610 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
611 * trigger decode when appropriate.
612 *
613 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
614 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
615 * (default 50us) intervals for that pulse/space. A discrete signal is
616 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
617 * to signal more IR coming (repeats) or end of IR, respectively. We store
618 * sample data in the raw event kfifo until we see 0x7<something> (except f)
619 * or 0x80, at which time, we trigger a decode operation.
620 */
621static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
622{
4651918a 623 DEFINE_IR_RAW_EVENT(rawir);
6d2f5c27
JW		 624 u8 sample;
625 int i;
626
627 nvt_dbg_verbose("%s firing", __func__);
628
629 if (debug)
630 nvt_dump_rx_buf(nvt);
631
de4ed0c1 632 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
6d2f5c27 633
b7582815
JW		 634 init_ir_raw_event(&rawir);
635
de4ed0c1 636 for (i = 0; i < nvt->pkts; i++) {
6d2f5c27
JW		 637 sample = nvt->buf[i];
638
639 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
b4608fae
JW		 640 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
641 * SAMPLE_PERIOD);
6d2f5c27 642
de4ed0c1
JW		 643 nvt_dbg("Storing %s with duration %d",
644 rawir.pulse ? "pulse" : "space", rawir.duration);
4651918a 645
de4ed0c1 646 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
6d2f5c27
JW		 647
648 /*
649 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
650 * indicates end of IR signal, but new data incoming. In both
651 * cases, it means we're ready to call ir_raw_event_handle
652 */
de4ed0c1 653 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
b7582815 654 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
6d2f5c27 655 ir_raw_event_handle(nvt->rdev);
b7582815 656 }
6d2f5c27
JW		 657 }
658
de4ed0c1
JW		 659 nvt->pkts = 0;
660
b7582815
JW		 661 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
662 ir_raw_event_handle(nvt->rdev);
663
6d2f5c27
JW		 664 nvt_dbg_verbose("%s done", __func__);
665}
666
fbdc781c
JW		 667static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
668{
211477fe 669 dev_warn(&nvt->pdev->dev, "RX FIFO overrun detected, flushing data!");
fbdc781c
JW		 670
671 nvt->pkts = 0;
672 nvt_clear_cir_fifo(nvt);
673 ir_raw_event_reset(nvt->rdev);
674}
675
6d2f5c27
JW		 676/* copy data from hardware rx fifo into driver buffer */
677static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
678{
679 unsigned long flags;
680 u8 fifocount, val;
681 unsigned int b_idx;
fbdc781c 682 bool overrun = false;
6d2f5c27
JW		 683 int i;
684
685 /* Get count of how many bytes to read from RX FIFO */
686 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
687 /* if we get 0xff, probably means the logical dev is disabled */
688 if (fifocount == 0xff)
689 return;
fbdc781c 690 /* watch out for a fifo overrun condition */
6d2f5c27 691 else if (fifocount > RX_BUF_LEN) {
fbdc781c
JW		 692 overrun = true;
693 fifocount = RX_BUF_LEN;
6d2f5c27
JW		 694 }
695
696 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
697
698 spin_lock_irqsave(&nvt->nvt_lock, flags);
699
700 b_idx = nvt->pkts;
701
702 /* This should never happen, but lets check anyway... */
703 if (b_idx + fifocount > RX_BUF_LEN) {
704 nvt_process_rx_ir_data(nvt);
705 b_idx = 0;
706 }
707
708 /* Read fifocount bytes from CIR Sample RX FIFO register */
709 for (i = 0; i < fifocount; i++) {
710 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
711 nvt->buf[b_idx + i] = val;
712 }
713
714 nvt->pkts += fifocount;
715 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
716
717 nvt_process_rx_ir_data(nvt);
718
fbdc781c
JW		 719 if (overrun)
720 nvt_handle_rx_fifo_overrun(nvt);
721
6d2f5c27
JW		 722 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
723}
724
725static void nvt_cir_log_irqs(u8 status, u8 iren)
726{
068fb7dd 727 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
6d2f5c27
JW		 728 status, iren,
729 status & CIR_IRSTS_RDR ? " RDR" : "",
730 status & CIR_IRSTS_RTR ? " RTR" : "",
731 status & CIR_IRSTS_PE ? " PE" : "",
732 status & CIR_IRSTS_RFO ? " RFO" : "",
733 status & CIR_IRSTS_TE ? " TE" : "",
734 status & CIR_IRSTS_TTR ? " TTR" : "",
735 status & CIR_IRSTS_TFU ? " TFU" : "",
736 status & CIR_IRSTS_GH ? " GH" : "",
737 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
738 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
739 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
740}
741
742static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
743{
744 unsigned long flags;
6d2f5c27
JW		 745 u8 tx_state;
746
747 spin_lock_irqsave(&nvt->tx.lock, flags);
748 tx_state = nvt->tx.tx_state;
749 spin_unlock_irqrestore(&nvt->tx.lock, flags);
750
1feac493 751 return tx_state == ST_TX_NONE;
6d2f5c27
JW		 752}
753
754/* interrupt service routine for incoming and outgoing CIR data */
755static irqreturn_t nvt_cir_isr(int irq, void *data)
756{
757 struct nvt_dev *nvt = data;
758 u8 status, iren, cur_state;
759 unsigned long flags;
760
761 nvt_dbg_verbose("%s firing", __func__);
762
763 nvt_efm_enable(nvt);
764 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
765 nvt_efm_disable(nvt);
766
767 /*
768 * Get IR Status register contents. Write 1 to ack/clear
769 *
770 * bit: reg name - description
771 * 7: CIR_IRSTS_RDR - RX Data Ready
772 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
773 * 5: CIR_IRSTS_PE - Packet End
774 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
775 * 3: CIR_IRSTS_TE - TX FIFO Empty
776 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
777 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
778 * 0: CIR_IRSTS_GH - Min Length Detected
779 */
780 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
781 if (!status) {
782 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
783 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
2bbf9e06 784 return IRQ_NONE;
6d2f5c27
JW		 785 }
786
787 /* ack/clear all irq flags we've got */
788 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
789 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
790
791 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
792 iren = nvt_cir_reg_read(nvt, CIR_IREN);
793 if (!iren) {
794 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
2bbf9e06 795 return IRQ_NONE;
6d2f5c27
JW		 796 }
797
068fb7dd 798 nvt_cir_log_irqs(status, iren);
6d2f5c27
JW		 799
800 if (status & CIR_IRSTS_RTR) {
801 /* FIXME: add code for study/learn mode */
802 /* We only do rx if not tx'ing */
803 if (nvt_cir_tx_inactive(nvt))
804 nvt_get_rx_ir_data(nvt);
805 }
806
807 if (status & CIR_IRSTS_PE) {
808 if (nvt_cir_tx_inactive(nvt))
809 nvt_get_rx_ir_data(nvt);
810
811 spin_lock_irqsave(&nvt->nvt_lock, flags);
812
813 cur_state = nvt->study_state;
814
815 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
816
817 if (cur_state == ST_STUDY_NONE)
818 nvt_clear_cir_fifo(nvt);
819 }
820
821 if (status & CIR_IRSTS_TE)
822 nvt_clear_tx_fifo(nvt);
823
824 if (status & CIR_IRSTS_TTR) {
825 unsigned int pos, count;
826 u8 tmp;
827
828 spin_lock_irqsave(&nvt->tx.lock, flags);
829
830 pos = nvt->tx.cur_buf_num;
831 count = nvt->tx.buf_count;
832
833 /* Write data into the hardware tx fifo while pos < count */
834 if (pos < count) {
835 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
836 nvt->tx.cur_buf_num++;
837 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
838 } else {
839 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
840 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
841 }
842
843 spin_unlock_irqrestore(&nvt->tx.lock, flags);
844
845 }
846
847 if (status & CIR_IRSTS_TFU) {
848 spin_lock_irqsave(&nvt->tx.lock, flags);
849 if (nvt->tx.tx_state == ST_TX_REPLY) {
850 nvt->tx.tx_state = ST_TX_REQUEST;
851 wake_up(&nvt->tx.queue);
852 }
853 spin_unlock_irqrestore(&nvt->tx.lock, flags);
854 }
855
856 nvt_dbg_verbose("%s done", __func__);
2bbf9e06 857 return IRQ_HANDLED;
6d2f5c27
JW		 858}
859
860/* Interrupt service routine for CIR Wake */
861static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
862{
863 u8 status, iren, val;
864 struct nvt_dev *nvt = data;
865 unsigned long flags;
866
867 nvt_dbg_wake("%s firing", __func__);
868
869 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
870 if (!status)
2bbf9e06 871 return IRQ_NONE;
6d2f5c27
JW		 872
873 if (status & CIR_WAKE_IRSTS_IR_PENDING)
874 nvt_clear_cir_wake_fifo(nvt);
875
876 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
877 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
878
879 /* Interrupt may be shared with CIR, bail if Wake not enabled */
880 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
881 if (!iren) {
882 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
2bbf9e06 883 return IRQ_HANDLED;
6d2f5c27
JW		 884 }
885
886 if ((status & CIR_WAKE_IRSTS_PE) &&
887 (nvt->wake_state == ST_WAKE_START)) {
888 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
889 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
890 nvt_dbg("setting wake up key: 0x%x", val);
891 }
892
893 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
894 spin_lock_irqsave(&nvt->nvt_lock, flags);
895 nvt->wake_state = ST_WAKE_FINISH;
896 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
897 }
898
899 nvt_dbg_wake("%s done", __func__);
2bbf9e06 900 return IRQ_HANDLED;
6d2f5c27
JW		 901}
902
903static void nvt_enable_cir(struct nvt_dev *nvt)
904{
905 /* set function enable flags */
906 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
907 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
908 CIR_IRCON);
909
910 nvt_efm_enable(nvt);
911
912 /* enable the CIR logical device */
913 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
914 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
915
916 nvt_efm_disable(nvt);
917
918 /* clear all pending interrupts */
919 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
920
921 /* enable interrupts */
fbdc781c 922 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 923}
924
925static void nvt_disable_cir(struct nvt_dev *nvt)
926{
927 /* disable CIR interrupts */
928 nvt_cir_reg_write(nvt, 0, CIR_IREN);
929
930 /* clear any and all pending interrupts */
931 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
932
933 /* clear all function enable flags */
934 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
935
936 /* clear hardware rx and tx fifos */
937 nvt_clear_cir_fifo(nvt);
938 nvt_clear_tx_fifo(nvt);
939
940 nvt_efm_enable(nvt);
941
942 /* disable the CIR logical device */
943 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
944 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
945
946 nvt_efm_disable(nvt);
947}
948
d8b4b582 949static int nvt_open(struct rc_dev *dev)
6d2f5c27 950{
d8b4b582 951 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 952 unsigned long flags;
953
954 spin_lock_irqsave(&nvt->nvt_lock, flags);
6d2f5c27
JW		 955 nvt_enable_cir(nvt);
956 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
957
958 return 0;
959}
960
d8b4b582 961static void nvt_close(struct rc_dev *dev)
6d2f5c27 962{
d8b4b582 963 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 964 unsigned long flags;
965
966 spin_lock_irqsave(&nvt->nvt_lock, flags);
6d2f5c27
JW		 967 nvt_disable_cir(nvt);
968 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
969}
970
971/* Allocate memory, probe hardware, and initialize everything */
972static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
973{
d8b4b582
DH		 974 struct nvt_dev *nvt;
975 struct rc_dev *rdev;
6d2f5c27
JW		 976 int ret = -ENOMEM;
977
099256e5 978 nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
6d2f5c27
JW		 979 if (!nvt)
980 return ret;
981
6d2f5c27 982 /* input device for IR remote (and tx) */
d8b4b582 983 rdev = rc_allocate_device();
6d2f5c27 984 if (!rdev)
70ef6991 985 goto exit_free_dev_rdev;
6d2f5c27
JW		 986
987 ret = -ENODEV;
c3c2077d
AS		 988 /* activate pnp device */
989 if (pnp_activate_dev(pdev) < 0) {
990 dev_err(&pdev->dev, "Could not activate PNP device!\n");
991 goto exit_free_dev_rdev;
992 }
993
6d2f5c27
JW		 994 /* validate pnp resources */
995 if (!pnp_port_valid(pdev, 0) ||
996 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
997 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
70ef6991 998 goto exit_free_dev_rdev;
6d2f5c27
JW		 999 }
1000
1001 if (!pnp_irq_valid(pdev, 0)) {
1002 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
70ef6991 1003 goto exit_free_dev_rdev;
6d2f5c27
JW		 1004 }
1005
1006 if (!pnp_port_valid(pdev, 1) ||
1007 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1008 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
70ef6991 1009 goto exit_free_dev_rdev;
6d2f5c27
JW		 1010 }
1011
1012 nvt->cir_addr = pnp_port_start(pdev, 0);
1013 nvt->cir_irq = pnp_irq(pdev, 0);
1014
1015 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1016 /* irq is always shared between cir and cir wake */
1017 nvt->cir_wake_irq = nvt->cir_irq;
1018
1019 nvt->cr_efir = CR_EFIR;
1020 nvt->cr_efdr = CR_EFDR;
1021
1022 spin_lock_init(&nvt->nvt_lock);
1023 spin_lock_init(&nvt->tx.lock);
1024
6d2f5c27
JW		 1025 pnp_set_drvdata(pdev, nvt);
1026 nvt->pdev = pdev;
1027
1028 init_waitqueue_head(&nvt->tx.queue);
1029
6a5a3360 1030 nvt_hw_detect(nvt);
6d2f5c27
JW		 1031
1032 /* Initialize CIR & CIR Wake Logical Devices */
1033 nvt_efm_enable(nvt);
1034 nvt_cir_ldev_init(nvt);
1035 nvt_cir_wake_ldev_init(nvt);
1036 nvt_efm_disable(nvt);
1037
1038 /* Initialize CIR & CIR Wake Config Registers */
1039 nvt_cir_regs_init(nvt);
1040 nvt_cir_wake_regs_init(nvt);
1041
d8b4b582
DH		 1042 /* Set up the rc device */
1043 rdev->priv = nvt;
1044 rdev->driver_type = RC_DRIVER_IR_RAW;
c5540fbb 1045 rdev->allowed_protocols = RC_BIT_ALL;
d8b4b582
DH		 1046 rdev->open = nvt_open;
1047 rdev->close = nvt_close;
1048 rdev->tx_ir = nvt_tx_ir;
1049 rdev->s_tx_carrier = nvt_set_tx_carrier;
1050 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
46872d27 1051 rdev->input_phys = "nuvoton/cir0";
d8b4b582
DH		 1052 rdev->input_id.bustype = BUS_HOST;
1053 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1054 rdev->input_id.product = nvt->chip_major;
1055 rdev->input_id.version = nvt->chip_minor;
46872d27 1056 rdev->dev.parent = &pdev->dev;
d8b4b582
DH		 1057 rdev->driver_name = NVT_DRIVER_NAME;
1058 rdev->map_name = RC_MAP_RC6_MCE;
d7b290a1 1059 rdev->timeout = MS_TO_NS(100);
46872d27
JW		 1060 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1061 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
6d2f5c27 1062#if 0
d8b4b582
DH		 1063 rdev->min_timeout = XYZ;
1064 rdev->max_timeout = XYZ;
6d2f5c27 1065 /* tx bits */
d8b4b582 1066 rdev->tx_resolution = XYZ;
6d2f5c27 1067#endif
d62b6818 1068 nvt->rdev = rdev;
6d2f5c27 1069
9fa35204
MK		 1070 ret = rc_register_device(rdev);
1071 if (ret)
1072 goto exit_free_dev_rdev;
1073
9ef449c6
LH		 1074 ret = -EBUSY;
1075 /* now claim resources */
099256e5 1076 if (!devm_request_region(&pdev->dev, nvt->cir_addr,
9ef449c6 1077 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
9fa35204 1078 goto exit_unregister_device;
9ef449c6 1079
099256e5
HK		 1080 if (devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1081 IRQF_SHARED, NVT_DRIVER_NAME, (void *)nvt))
1082 goto exit_unregister_device;
9ef449c6 1083
099256e5 1084 if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
33cb5401 1085 CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake"))
099256e5 1086 goto exit_unregister_device;
9ef449c6 1087
099256e5
HK		 1088 if (devm_request_irq(&pdev->dev, nvt->cir_wake_irq,
1089 nvt_cir_wake_isr, IRQF_SHARED,
33cb5401 1090 NVT_DRIVER_NAME "-wake", (void *)nvt))
099256e5 1091 goto exit_unregister_device;
9ef449c6 1092
46872d27 1093 device_init_wakeup(&pdev->dev, true);
d62b6818 1094
211477fe 1095 dev_notice(&pdev->dev, "driver has been successfully loaded\n");
6d2f5c27
JW		 1096 if (debug) {
1097 cir_dump_regs(nvt);
1098 cir_wake_dump_regs(nvt);
1099 }
1100
1101 return 0;
1102
9fa35204
MK		 1103exit_unregister_device:
1104 rc_unregister_device(rdev);
f73e1851 1105 rdev = NULL;
70ef6991 1106exit_free_dev_rdev:
d8b4b582 1107 rc_free_device(rdev);
6d2f5c27
JW		 1108
1109 return ret;
1110}
1111
4c62e976 1112static void nvt_remove(struct pnp_dev *pdev)
6d2f5c27
JW		 1113{
1114 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1115 unsigned long flags;
1116
1117 spin_lock_irqsave(&nvt->nvt_lock, flags);
1118 /* disable CIR */
1119 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1120 nvt_disable_cir(nvt);
1121 /* enable CIR Wake (for IR power-on) */
1122 nvt_enable_wake(nvt);
1123 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1124
d8b4b582 1125 rc_unregister_device(nvt->rdev);
6d2f5c27
JW		 1126}
1127
1128static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1129{
1130 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1131 unsigned long flags;
1132
1133 nvt_dbg("%s called", __func__);
1134
1135 /* zero out misc state tracking */
1136 spin_lock_irqsave(&nvt->nvt_lock, flags);
1137 nvt->study_state = ST_STUDY_NONE;
1138 nvt->wake_state = ST_WAKE_NONE;
1139 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1140
1141 spin_lock_irqsave(&nvt->tx.lock, flags);
1142 nvt->tx.tx_state = ST_TX_NONE;
1143 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1144
1145 /* disable all CIR interrupts */
1146 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1147
1148 nvt_efm_enable(nvt);
1149
1150 /* disable cir logical dev */
1151 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1152 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1153
1154 nvt_efm_disable(nvt);
1155
1156 /* make sure wake is enabled */
1157 nvt_enable_wake(nvt);
1158
1159 return 0;
1160}
1161
1162static int nvt_resume(struct pnp_dev *pdev)
1163{
6d2f5c27
JW		 1164 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1165
1166 nvt_dbg("%s called", __func__);
1167
1168 /* open interrupt */
fbdc781c 1169 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 1170
1171 /* Enable CIR logical device */
1172 nvt_efm_enable(nvt);
1173 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1174 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1175
1176 nvt_efm_disable(nvt);
1177
1178 nvt_cir_regs_init(nvt);
1179 nvt_cir_wake_regs_init(nvt);
1180
f2747cf6 1181 return 0;
6d2f5c27
JW		 1182}
1183
1184static void nvt_shutdown(struct pnp_dev *pdev)
1185{
1186 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1187 nvt_enable_wake(nvt);
1188}
1189
1190static const struct pnp_device_id nvt_ids[] = {
1191 { "WEC0530", 0 }, /* CIR */
1192 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1193 { "", 0 },
1194};
1195
1196static struct pnp_driver nvt_driver = {
1197 .name = NVT_DRIVER_NAME,
1198 .id_table = nvt_ids,
1199 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1200 .probe = nvt_probe,
4c62e976 1201 .remove = nvt_remove,
6d2f5c27
JW		 1202 .suspend = nvt_suspend,
1203 .resume = nvt_resume,
1204 .shutdown = nvt_shutdown,
1205};
1206
6d2f5c27
JW		 1207module_param(debug, int, S_IRUGO | S_IWUSR);
1208MODULE_PARM_DESC(debug, "Enable debugging output");
1209
1210MODULE_DEVICE_TABLE(pnp, nvt_ids);
1211MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1212
1213MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1214MODULE_LICENSE("GPL");
1215
af638a04 1216module_pnp_driver(nvt_driver);
Linux kernel - Deliverables
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