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[media] r820t: Fix hp_cor filter mask
[deliverable/linux.git] / drivers / media / tuners / r820t.c
CommitLineData
a80abc58
MCC		 1/*
2 * Rafael Micro R820T driver
3 *
4 * Copyright (C) 2013 Mauro Carvalho Chehab <mchehab@redhat.com>
5 *
6 * This driver was written from scratch, based on an existing driver
7 * that it is part of rtl-sdr git tree, released under GPLv2:
8 * https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
9 * https://github.com/n1gp/gr-baz
10 *
11 * From what I understood from the threads, the original driver was converted
12 * to userspace from a Realtek tree. I couldn't find the original tree.
13 * However, the original driver look awkward on my eyes. So, I decided to
14 * write a new version from it from the scratch, while trying to reproduce
15 * everything found there.
16 *
17 * TODO:
18 * After locking, the original driver seems to have some routines to
19 * improve reception. This was not implemented here yet.
20 *
21 * RF Gain set/get is not implemented.
22 *
23 * This program is free software; you can redistribute it and/or modify
24 * it under the terms of the GNU General Public License as published by
25 * the Free Software Foundation; either version 2 of the License, or
26 * (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 */
34
35#include <linux/videodev2.h>
36#include <linux/mutex.h>
37#include <linux/slab.h>
103fe2fb 38#include <linux/bitrev.h>
103fe2fb
MCC		 39
40#include "tuner-i2c.h"
a80abc58
MCC		 41#include "r820t.h"
42
43/*
44 * FIXME: I think that there are only 32 registers, but better safe than
45 * sorry. After finishing the driver, we may review it.
46 */
47#define REG_SHADOW_START 5
48#define NUM_REGS 27
25cf4d46
MCC		 49#define NUM_IMR 5
50#define IMR_TRIAL 9
a80abc58
MCC		 51
52#define VER_NUM 49
53
54static int debug;
55module_param(debug, int, 0644);
56MODULE_PARM_DESC(debug, "enable verbose debug messages");
57
52775fd5
MCC		 58static int no_imr_cal;
59module_param(no_imr_cal, int, 0444);
60MODULE_PARM_DESC(no_imr_cal, "Disable IMR calibration at module init");
61
62
a80abc58
MCC		 63/*
64 * enums and structures
65 */
66
67enum xtal_cap_value {
68 XTAL_LOW_CAP_30P = 0,
69 XTAL_LOW_CAP_20P,
70 XTAL_LOW_CAP_10P,
71 XTAL_LOW_CAP_0P,
72 XTAL_HIGH_CAP_0P
73};
74
25cf4d46
MCC		 75struct r820t_sect_type {
76 u8 phase_y;
77 u8 gain_x;
78 u16 value;
79};
80
a80abc58
MCC		 81struct r820t_priv {
82 struct list_head hybrid_tuner_instance_list;
83 const struct r820t_config *cfg;
84 struct tuner_i2c_props i2c_props;
85 struct mutex lock;
86
87 u8 regs[NUM_REGS];
88 u8 buf[NUM_REGS + 1];
89 enum xtal_cap_value xtal_cap_sel;
90 u16 pll; /* kHz */
91 u32 int_freq;
92 u8 fil_cal_code;
93 bool imr_done;
52775fd5
MCC		 94 bool has_lock;
95 bool init_done;
25cf4d46
MCC		 96 struct r820t_sect_type imr_data[NUM_IMR];
97
a80abc58
MCC		 98 /* Store current mode */
99 u32 delsys;
100 enum v4l2_tuner_type type;
101 v4l2_std_id std;
102 u32 bw; /* in MHz */
a80abc58
MCC		 103};
104
105struct r820t_freq_range {
106 u32 freq;
107 u8 open_d;
108 u8 rf_mux_ploy;
109 u8 tf_c;
110 u8 xtal_cap20p;
111 u8 xtal_cap10p;
112 u8 xtal_cap0p;
113 u8 imr_mem; /* Not used, currently */
114};
115
116#define VCO_POWER_REF 0x02
84ddc33c 117#define DIP_FREQ 32000000
a80abc58
MCC		 118
119/*
120 * Static constants
121 */
122
123static LIST_HEAD(hybrid_tuner_instance_list);
124static DEFINE_MUTEX(r820t_list_mutex);
125
126/* Those initial values start from REG_SHADOW_START */
127static const u8 r820t_init_array[NUM_REGS] = {
128 0x83, 0x32, 0x75, /* 05 to 07 */
129 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */
130 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */
131 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */
132 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */
133 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */
134 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */
135};
136
137/* Tuner frequency ranges */
138static const struct r820t_freq_range freq_ranges[] = {
139 {
140 .freq = 0,
141 .open_d = 0x08, /* low */
142 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
143 .tf_c = 0xdf, /* R27[7:0] band2,band0 */
144 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
145 .xtal_cap10p = 0x01,
146 .xtal_cap0p = 0x00,
147 .imr_mem = 0,
148 }, {
149 .freq = 50, /* Start freq, in MHz */
150 .open_d = 0x08, /* low */
151 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
152 .tf_c = 0xbe, /* R27[7:0] band4,band1 */
153 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
154 .xtal_cap10p = 0x01,
155 .xtal_cap0p = 0x00,
156 .imr_mem = 0,
157 }, {
158 .freq = 55, /* Start freq, in MHz */
159 .open_d = 0x08, /* low */
160 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
161 .tf_c = 0x8b, /* R27[7:0] band7,band4 */
162 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
163 .xtal_cap10p = 0x01,
164 .xtal_cap0p = 0x00,
165 .imr_mem = 0,
166 }, {
167 .freq = 60, /* Start freq, in MHz */
168 .open_d = 0x08, /* low */
169 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
170 .tf_c = 0x7b, /* R27[7:0] band8,band4 */
171 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
172 .xtal_cap10p = 0x01,
173 .xtal_cap0p = 0x00,
174 .imr_mem = 0,
175 }, {
176 .freq = 65, /* Start freq, in MHz */
177 .open_d = 0x08, /* low */
178 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
179 .tf_c = 0x69, /* R27[7:0] band9,band6 */
180 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
181 .xtal_cap10p = 0x01,
182 .xtal_cap0p = 0x00,
183 .imr_mem = 0,
184 }, {
185 .freq = 70, /* Start freq, in MHz */
186 .open_d = 0x08, /* low */
187 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
188 .tf_c = 0x58, /* R27[7:0] band10,band7 */
189 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
190 .xtal_cap10p = 0x01,
191 .xtal_cap0p = 0x00,
192 .imr_mem = 0,
193 }, {
194 .freq = 75, /* Start freq, in MHz */
195 .open_d = 0x00, /* high */
196 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
197 .tf_c = 0x44, /* R27[7:0] band11,band11 */
198 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
199 .xtal_cap10p = 0x01,
200 .xtal_cap0p = 0x00,
201 .imr_mem = 0,
202 }, {
203 .freq = 80, /* Start freq, in MHz */
204 .open_d = 0x00, /* high */
205 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
206 .tf_c = 0x44, /* R27[7:0] band11,band11 */
207 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
208 .xtal_cap10p = 0x01,
209 .xtal_cap0p = 0x00,
210 .imr_mem = 0,
211 }, {
212 .freq = 90, /* Start freq, in MHz */
213 .open_d = 0x00, /* high */
214 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
215 .tf_c = 0x34, /* R27[7:0] band12,band11 */
216 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
217 .xtal_cap10p = 0x01,
218 .xtal_cap0p = 0x00,
219 .imr_mem = 0,
220 }, {
221 .freq = 100, /* Start freq, in MHz */
222 .open_d = 0x00, /* high */
223 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
224 .tf_c = 0x34, /* R27[7:0] band12,band11 */
225 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
226 .xtal_cap10p = 0x01,
227 .xtal_cap0p = 0x00,
228 .imr_mem = 0,
229 }, {
230 .freq = 110, /* Start freq, in MHz */
231 .open_d = 0x00, /* high */
232 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
233 .tf_c = 0x24, /* R27[7:0] band13,band11 */
234 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
235 .xtal_cap10p = 0x01,
236 .xtal_cap0p = 0x00,
237 .imr_mem = 1,
238 }, {
239 .freq = 120, /* Start freq, in MHz */
240 .open_d = 0x00, /* high */
241 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
242 .tf_c = 0x24, /* R27[7:0] band13,band11 */
243 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
244 .xtal_cap10p = 0x01,
245 .xtal_cap0p = 0x00,
246 .imr_mem = 1,
247 }, {
248 .freq = 140, /* Start freq, in MHz */
249 .open_d = 0x00, /* high */
250 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
251 .tf_c = 0x14, /* R27[7:0] band14,band11 */
252 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
253 .xtal_cap10p = 0x01,
254 .xtal_cap0p = 0x00,
255 .imr_mem = 1,
256 }, {
257 .freq = 180, /* Start freq, in MHz */
258 .open_d = 0x00, /* high */
259 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
260 .tf_c = 0x13, /* R27[7:0] band14,band12 */
261 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
262 .xtal_cap10p = 0x00,
263 .xtal_cap0p = 0x00,
264 .imr_mem = 1,
265 }, {
266 .freq = 220, /* Start freq, in MHz */
267 .open_d = 0x00, /* high */
268 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
269 .tf_c = 0x13, /* R27[7:0] band14,band12 */
270 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
271 .xtal_cap10p = 0x00,
272 .xtal_cap0p = 0x00,
273 .imr_mem = 2,
274 }, {
275 .freq = 250, /* Start freq, in MHz */
276 .open_d = 0x00, /* high */
277 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
278 .tf_c = 0x11, /* R27[7:0] highest,highest */
279 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
280 .xtal_cap10p = 0x00,
281 .xtal_cap0p = 0x00,
282 .imr_mem = 2,
283 }, {
284 .freq = 280, /* Start freq, in MHz */
285 .open_d = 0x00, /* high */
286 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
287 .tf_c = 0x00, /* R27[7:0] highest,highest */
288 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
289 .xtal_cap10p = 0x00,
290 .xtal_cap0p = 0x00,
291 .imr_mem = 2,
292 }, {
293 .freq = 310, /* Start freq, in MHz */
294 .open_d = 0x00, /* high */
295 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
296 .tf_c = 0x00, /* R27[7:0] highest,highest */
297 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
298 .xtal_cap10p = 0x00,
299 .xtal_cap0p = 0x00,
300 .imr_mem = 2,
301 }, {
302 .freq = 450, /* Start freq, in MHz */
303 .open_d = 0x00, /* high */
304 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
305 .tf_c = 0x00, /* R27[7:0] highest,highest */
306 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
307 .xtal_cap10p = 0x00,
308 .xtal_cap0p = 0x00,
309 .imr_mem = 3,
310 }, {
311 .freq = 588, /* Start freq, in MHz */
312 .open_d = 0x00, /* high */
313 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
314 .tf_c = 0x00, /* R27[7:0] highest,highest */
315 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
316 .xtal_cap10p = 0x00,
317 .xtal_cap0p = 0x00,
318 .imr_mem = 3,
319 }, {
320 .freq = 650, /* Start freq, in MHz */
321 .open_d = 0x00, /* high */
322 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
323 .tf_c = 0x00, /* R27[7:0] highest,highest */
324 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
325 .xtal_cap10p = 0x00,
326 .xtal_cap0p = 0x00,
327 .imr_mem = 4,
328 }
329};
330
331static int r820t_xtal_capacitor[][2] = {
332 { 0x0b, XTAL_LOW_CAP_30P },
333 { 0x02, XTAL_LOW_CAP_20P },
334 { 0x01, XTAL_LOW_CAP_10P },
335 { 0x00, XTAL_LOW_CAP_0P },
336 { 0x10, XTAL_HIGH_CAP_0P },
337};
338
50786ddf
MCC		 339/*
340 * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
341 * input power, for raw results see:
342 * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
343 */
344
345static const int r820t_lna_gain_steps[] = {
346 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
347};
348
349static const int r820t_mixer_gain_steps[] = {
350 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
351};
352
a80abc58
MCC		 353/*
354 * I2C read/write code and shadow registers logic
355 */
356static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val,
357 int len)
358{
359 int r = reg - REG_SHADOW_START;
360
361 if (r < 0) {
362 len += r;
363 r = 0;
364 }
365 if (len <= 0)
366 return;
367 if (len > NUM_REGS)
368 len = NUM_REGS;
369
370 tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n",
371 __func__, r + REG_SHADOW_START, len, len, val);
372
373 memcpy(&priv->regs[r], val, len);
374}
375
376static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val,
377 int len)
378{
379 int rc, size, pos = 0;
380
381 /* Store the shadow registers */
382 shadow_store(priv, reg, val, len);
383
384 do {
385 if (len > priv->cfg->max_i2c_msg_len - 1)
386 size = priv->cfg->max_i2c_msg_len - 1;
387 else
388 size = len;
389
390 /* Fill I2C buffer */
391 priv->buf[0] = reg;
392 memcpy(&priv->buf[1], &val[pos], size);
393
394 rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1);
395 if (rc != size + 1) {
396 tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
397 __func__, rc, reg, size, size, &priv->buf[1]);
398 if (rc < 0)
399 return rc;
400 return -EREMOTEIO;
401 }
402 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
403 __func__, reg, size, size, &priv->buf[1]);
404
405 reg += size;
406 len -= size;
407 pos += size;
408 } while (len > 0);
409
410 return 0;
411}
412
413static int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val)
414{
415 return r820t_write(priv, reg, &val, 1);
416}
417
8678b034 418static int r820t_read_cache_reg(struct r820t_priv *priv, int reg)
a80abc58 419{
8678b034 420 reg -= REG_SHADOW_START;
a80abc58 421
8678b034
MCC		 422 if (reg >= 0 && reg < NUM_REGS)
423 return priv->regs[reg];
a80abc58
MCC		 424 else
425 return -EINVAL;
8678b034
MCC		 426}
427
428static int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val,
429 u8 bit_mask)
430{
431 int rc = r820t_read_cache_reg(priv, reg);
432
433 if (rc < 0)
434 return rc;
435
436 val = (rc & ~bit_mask) | (val & bit_mask);
a80abc58
MCC		 437
438 return r820t_write(priv, reg, &val, 1);
439}
440
226471a1 441static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len)
a80abc58 442{
103fe2fb 443 int rc, i;
a80abc58
MCC		 444 u8 *p = &priv->buf[1];
445
446 priv->buf[0] = reg;
447
448 rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len);
449 if (rc != len) {
450 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
451 __func__, rc, reg, len, len, p);
452 if (rc < 0)
453 return rc;
454 return -EREMOTEIO;
455 }
a80abc58
MCC		 456
457 /* Copy data to the output buffer */
103fe2fb
MCC		 458 for (i = 0; i < len; i++)
459 val[i] = bitrev8(p[i]);
a80abc58 460
6b8c2308
MCC		 461 tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
462 __func__, reg, len, len, val);
463
a80abc58
MCC		 464 return 0;
465}
466
467/*
468 * r820t tuning logic
469 */
470
471static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
472{
473 const struct r820t_freq_range *range;
474 int i, rc;
25cf4d46 475 u8 val, reg08, reg09;
a80abc58
MCC		 476
477 /* Get the proper frequency range */
478 freq = freq / 1000000;
479 for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) {
480 if (freq < freq_ranges[i + 1].freq)
481 break;
482 }
483 range = &freq_ranges[i];
484
485 tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq);
486
487 /* Open Drain */
488 rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08);
489 if (rc < 0)
490 return rc;
491
492 /* RF_MUX,Polymux */
493 rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3);
494 if (rc < 0)
495 return rc;
496
497 /* TF BAND */
498 rc = r820t_write_reg(priv, 0x1b, range->tf_c);
499 if (rc < 0)
500 return rc;
501
502 /* XTAL CAP & Drive */
503 switch (priv->xtal_cap_sel) {
504 case XTAL_LOW_CAP_30P:
505 case XTAL_LOW_CAP_20P:
506 val = range->xtal_cap20p | 0x08;
507 break;
508 case XTAL_LOW_CAP_10P:
509 val = range->xtal_cap10p | 0x08;
510 break;
511 case XTAL_HIGH_CAP_0P:
512 val = range->xtal_cap0p | 0x00;
513 break;
514 default:
515 case XTAL_LOW_CAP_0P:
516 val = range->xtal_cap0p | 0x08;
517 break;
518 }
519 rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b);
520 if (rc < 0)
521 return rc;
522
25cf4d46
MCC		 523 if (priv->imr_done) {
524 reg08 = priv->imr_data[range->imr_mem].gain_x;
525 reg09 = priv->imr_data[range->imr_mem].phase_y;
526 } else {
527 reg08 = 0;
528 reg09 = 0;
529 }
530 rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f);
a80abc58
MCC		 531 if (rc < 0)
532 return rc;
533
25cf4d46 534 rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f);
a80abc58
MCC		 535
536 return rc;
537}
538
d75d5388
MCC		 539static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type,
540 u32 freq)
a80abc58 541{
c0c6ed8d 542 u32 vco_freq;
a80abc58 543 int rc, i;
d75d5388 544 unsigned sleep_time = 10000;
a80abc58
MCC		 545 u32 vco_fra; /* VCO contribution by SDM (kHz) */
546 u32 vco_min = 1770000;
547 u32 vco_max = vco_min * 2;
548 u32 pll_ref;
549 u16 n_sdm = 2;
550 u16 sdm = 0;
551 u8 mix_div = 2;
552 u8 div_buf = 0;
553 u8 div_num = 0;
d75d5388 554 u8 refdiv2 = 0;
a80abc58
MCC		 555 u8 ni, si, nint, vco_fine_tune, val;
556 u8 data[5];
557
d75d5388
MCC		 558 /* Frequency in kHz */
559 freq = freq / 1000;
a80abc58
MCC		 560 pll_ref = priv->cfg->xtal / 1000;
561
d75d5388
MCC		 562 if ((priv->cfg->rafael_chip == CHIP_R620D) ||
563 (priv->cfg->rafael_chip == CHIP_R828D) ||
564 (priv->cfg->rafael_chip == CHIP_R828)) {
565 /* ref set refdiv2, reffreq = Xtal/2 on ATV application */
566 if (type != V4L2_TUNER_DIGITAL_TV) {
567 pll_ref /= 2;
568 refdiv2 = 0x10;
569 sleep_time = 20000;
570 }
571 } else {
572 if (priv->cfg->xtal > 24000000) {
573 pll_ref /= 2;
574 refdiv2 = 0x10;
575 }
576 }
a80abc58 577
d75d5388 578 rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10);
a80abc58
MCC		 579 if (rc < 0)
580 return rc;
581
582 /* set pll autotune = 128kHz */
583 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
584 if (rc < 0)
585 return rc;
586
587 /* set VCO current = 100 */
588 rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0);
589 if (rc < 0)
590 return rc;
591
592 /* Calculate divider */
593 while (mix_div <= 64) {
594 if (((freq * mix_div) >= vco_min) &&
595 ((freq * mix_div) < vco_max)) {
596 div_buf = mix_div;
597 while (div_buf > 2) {
598 div_buf = div_buf >> 1;
599 div_num++;
600 }
601 break;
602 }
603 mix_div = mix_div << 1;
604 }
605
226471a1 606 rc = r820t_read(priv, 0x00, data, sizeof(data));
a80abc58
MCC		 607 if (rc < 0)
608 return rc;
609
610 vco_fine_tune = (data[4] & 0x30) >> 4;
611
612 if (vco_fine_tune > VCO_POWER_REF)
613 div_num = div_num - 1;
614 else if (vco_fine_tune < VCO_POWER_REF)
615 div_num = div_num + 1;
616
617 rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
618 if (rc < 0)
619 return rc;
620
c0c6ed8d
MCC		 621 vco_freq = freq * mix_div;
622 nint = vco_freq / (2 * pll_ref);
623 vco_fra = vco_freq - 2 * pll_ref * nint;
a80abc58 624
a80abc58
MCC		 625 /* boundary spur prevention */
626 if (vco_fra < pll_ref / 64) {
627 vco_fra = 0;
628 } else if (vco_fra > pll_ref * 127 / 64) {
629 vco_fra = 0;
630 nint++;
631 } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) {
632 vco_fra = pll_ref * 127 / 128;
633 } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) {
634 vco_fra = pll_ref * 129 / 128;
635 }
636
637 if (nint > 63) {
638 tuner_info("No valid PLL values for %u kHz!\n", freq);
639 return -EINVAL;
640 }
641
642 ni = (nint - 13) / 4;
643 si = nint - 4 * ni - 13;
644
645 rc = r820t_write_reg(priv, 0x14, ni + (si << 6));
646 if (rc < 0)
647 return rc;
648
649 /* pw_sdm */
650 if (!vco_fra)
651 val = 0x08;
652 else
653 val = 0x00;
654
655 rc = r820t_write_reg_mask(priv, 0x12, val, 0x08);
656 if (rc < 0)
657 return rc;
658
659 /* sdm calculator */
660 while (vco_fra > 1) {
661 if (vco_fra > (2 * pll_ref / n_sdm)) {
662 sdm = sdm + 32768 / (n_sdm / 2);
663 vco_fra = vco_fra - 2 * pll_ref / n_sdm;
664 if (n_sdm >= 0x8000)
665 break;
666 }
667 n_sdm = n_sdm << 1;
668 }
669
c0c6ed8d
MCC		 670 tuner_dbg("freq %d kHz, pll ref %d%s, sdm=0x%04x\n",
671 freq, pll_ref, refdiv2 ? " / 2" : "", sdm);
672
673 rc = r820t_write_reg(priv, 0x16, sdm >> 8);
a80abc58
MCC		 674 if (rc < 0)
675 return rc;
c0c6ed8d 676 rc = r820t_write_reg(priv, 0x15, sdm & 0xff);
a80abc58
MCC		 677 if (rc < 0)
678 return rc;
679
680 for (i = 0; i < 2; i++) {
d75d5388 681 usleep_range(sleep_time, sleep_time + 1000);
a80abc58
MCC		 682
683 /* Check if PLL has locked */
226471a1 684 rc = r820t_read(priv, 0x00, data, 3);
a80abc58
MCC		 685 if (rc < 0)
686 return rc;
687 if (data[2] & 0x40)
688 break;
689
690 if (!i) {
691 /* Didn't lock. Increase VCO current */
692 rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0);
693 if (rc < 0)
694 return rc;
695 }
696 }
697
698 if (!(data[2] & 0x40)) {
699 priv->has_lock = false;
700 return 0;
701 }
702
703 priv->has_lock = true;
704 tuner_dbg("tuner has lock at frequency %d kHz\n", freq);
705
706 /* set pll autotune = 8kHz */
707 rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08);
708
709 return rc;
710}
711
712static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq,
713 enum v4l2_tuner_type type,
714 v4l2_std_id std,
715 u32 delsys)
716{
717 int rc;
718 u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l;
719 u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur;
720
721 tuner_dbg("adjusting tuner parameters for the standard\n");
722
723 switch (delsys) {
724 case SYS_DVBT:
725 if ((freq == 506000000) || (freq == 666000000) ||
726 (freq == 818000000)) {
727 mixer_top = 0x14; /* mixer top:14 , top-1, low-discharge */
728 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
729 cp_cur = 0x28; /* 101, 0.2 */
730 div_buf_cur = 0x20; /* 10, 200u */
731 } else {
732 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
733 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
734 cp_cur = 0x38; /* 111, auto */
735 div_buf_cur = 0x30; /* 11, 150u */
736 }
737 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
738 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
739 air_cable1_in = 0x00;
740 cable2_in = 0x00;
741 pre_dect = 0x40;
742 lna_discharge = 14;
743 filter_cur = 0x40; /* 10, low */
744 break;
745 case SYS_DVBT2:
746 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
747 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
748 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
749 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
750 air_cable1_in = 0x00;
751 cable2_in = 0x00;
752 pre_dect = 0x40;
753 lna_discharge = 14;
754 cp_cur = 0x38; /* 111, auto */
755 div_buf_cur = 0x30; /* 11, 150u */
756 filter_cur = 0x40; /* 10, low */
757 break;
758 case SYS_ISDBT:
759 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
760 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
761 lna_vth_l = 0x75; /* lna vth 1.04 , vtl 0.84 */
762 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
763 air_cable1_in = 0x00;
764 cable2_in = 0x00;
765 pre_dect = 0x40;
766 lna_discharge = 14;
767 cp_cur = 0x38; /* 111, auto */
768 div_buf_cur = 0x30; /* 11, 150u */
769 filter_cur = 0x40; /* 10, low */
770 break;
771 default: /* DVB-T 8M */
772 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
773 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
774 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
775 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
776 air_cable1_in = 0x00;
777 cable2_in = 0x00;
778 pre_dect = 0x40;
779 lna_discharge = 14;
780 cp_cur = 0x38; /* 111, auto */
781 div_buf_cur = 0x30; /* 11, 150u */
782 filter_cur = 0x40; /* 10, low */
783 break;
784 }
785
84ddc33c
MCC		 786 if (priv->cfg->use_diplexer &&
787 ((priv->cfg->rafael_chip == CHIP_R820T) ||
788 (priv->cfg->rafael_chip == CHIP_R828S) ||
789 (priv->cfg->rafael_chip == CHIP_R820C))) {
790 if (freq > DIP_FREQ)
791 air_cable1_in = 0x00;
792 else
793 air_cable1_in = 0x60;
794 cable2_in = 0x00;
795 }
796
a80abc58
MCC		 797 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7);
798 if (rc < 0)
799 return rc;
800 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8);
801 if (rc < 0)
802 return rc;
803 rc = r820t_write_reg(priv, 0x0d, lna_vth_l);
804 if (rc < 0)
805 return rc;
806 rc = r820t_write_reg(priv, 0x0e, mixer_vth_l);
807 if (rc < 0)
808 return rc;
809
810 /* Air-IN only for Astrometa */
811 rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60);
812 if (rc < 0)
813 return rc;
814 rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08);
815 if (rc < 0)
816 return rc;
817
818 rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38);
819 if (rc < 0)
820 return rc;
821 rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30);
822 if (rc < 0)
823 return rc;
824 rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60);
825 if (rc < 0)
826 return rc;
827 /*
828 * Original driver initializes regs 0x05 and 0x06 with the
829 * same value again on this point. Probably, it is just an
830 * error there
831 */
832
833 /*
834 * Set LNA
835 */
836
837 tuner_dbg("adjusting LNA parameters\n");
838 if (type != V4L2_TUNER_ANALOG_TV) {
839 /* LNA TOP: lowest */
840 rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38);
841 if (rc < 0)
842 return rc;
843
844 /* 0: normal mode */
845 rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04);
846 if (rc < 0)
847 return rc;
848
849 /* 0: PRE_DECT off */
850 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
851 if (rc < 0)
852 return rc;
853
854 /* agc clk 250hz */
855 rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30);
856 if (rc < 0)
857 return rc;
858
859 msleep(250);
860
861 /* write LNA TOP = 3 */
862 rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38);
863 if (rc < 0)
864 return rc;
865
866 /*
867 * write discharge mode
868 * FIXME: IMHO, the mask here is wrong, but it matches
869 * what's there at the original driver
870 */
871 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
872 if (rc < 0)
873 return rc;
874
875 /* LNA discharge current */
876 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
877 if (rc < 0)
878 return rc;
879
880 /* agc clk 60hz */
881 rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30);
882 if (rc < 0)
883 return rc;
884 } else {
885 /* PRE_DECT off */
886 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
887 if (rc < 0)
888 return rc;
889
890 /* write LNA TOP */
891 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38);
892 if (rc < 0)
893 return rc;
894
895 /*
896 * write discharge mode
897 * FIXME: IMHO, the mask here is wrong, but it matches
898 * what's there at the original driver
899 */
900 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
901 if (rc < 0)
902 return rc;
903
904 /* LNA discharge current */
905 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
906 if (rc < 0)
907 return rc;
908
909 /* agc clk 1Khz, external det1 cap 1u */
910 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30);
911 if (rc < 0)
912 return rc;
913
914 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04);
915 if (rc < 0)
916 return rc;
917 }
918 return 0;
919}
920
921static int r820t_set_tv_standard(struct r820t_priv *priv,
922 unsigned bw,
923 enum v4l2_tuner_type type,
924 v4l2_std_id std, u32 delsys)
925
926{
927 int rc, i;
928 u32 if_khz, filt_cal_lo;
929 u8 data[5], val;
930 u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through;
931 u8 lt_att, flt_ext_widest, polyfil_cur;
932 bool need_calibration;
933
934 tuner_dbg("selecting the delivery system\n");
935
936 if (delsys == SYS_ISDBT) {
937 if_khz = 4063;
938 filt_cal_lo = 59000;
939 filt_gain = 0x10; /* +3db, 6mhz on */
940 img_r = 0x00; /* image negative */
941 filt_q = 0x10; /* r10[4]:low q(1'b1) */
942 hp_cor = 0x6a; /* 1.7m disable, +2cap, 1.25mhz */
943 ext_enable = 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */
944 loop_through = 0x00; /* r5[7], lt on */
945 lt_att = 0x00; /* r31[7], lt att enable */
946 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
947 polyfil_cur = 0x60; /* r25[6:5]:min */
948 } else {
949 if (bw <= 6) {
950 if_khz = 3570;
951 filt_cal_lo = 56000; /* 52000->56000 */
952 filt_gain = 0x10; /* +3db, 6mhz on */
953 img_r = 0x00; /* image negative */
954 filt_q = 0x10; /* r10[4]:low q(1'b1) */
955 hp_cor = 0x6b; /* 1.7m disable, +2cap, 1.0mhz */
956 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
957 loop_through = 0x00; /* r5[7], lt on */
958 lt_att = 0x00; /* r31[7], lt att enable */
959 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
960 polyfil_cur = 0x60; /* r25[6:5]:min */
961 } else if (bw == 7) {
6189f80d
MCC		 962#if 0
963 /*
964 * There are two 7 MHz tables defined on the original
965 * driver, but just the second one seems to be visible
966 * by rtl2832. Keep this one here commented, as it
967 * might be needed in the future
968 */
969
a80abc58
MCC		 970 if_khz = 4070;
971 filt_cal_lo = 60000;
972 filt_gain = 0x10; /* +3db, 6mhz on */
973 img_r = 0x00; /* image negative */
974 filt_q = 0x10; /* r10[4]:low q(1'b1) */
975 hp_cor = 0x2b; /* 1.7m disable, +1cap, 1.0mhz */
976 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
977 loop_through = 0x00; /* r5[7], lt on */
978 lt_att = 0x00; /* r31[7], lt att enable */
979 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
980 polyfil_cur = 0x60; /* r25[6:5]:min */
6189f80d
MCC		 981#endif
982 /* 7 MHz, second table */
a80abc58
MCC		 983 if_khz = 4570;
984 filt_cal_lo = 63000;
985 filt_gain = 0x10; /* +3db, 6mhz on */
986 img_r = 0x00; /* image negative */
987 filt_q = 0x10; /* r10[4]:low q(1'b1) */
988 hp_cor = 0x2a; /* 1.7m disable, +1cap, 1.25mhz */
989 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
990 loop_through = 0x00; /* r5[7], lt on */
991 lt_att = 0x00; /* r31[7], lt att enable */
992 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
993 polyfil_cur = 0x60; /* r25[6:5]:min */
a80abc58
MCC		 994 } else {
995 if_khz = 4570;
996 filt_cal_lo = 68500;
997 filt_gain = 0x10; /* +3db, 6mhz on */
998 img_r = 0x00; /* image negative */
999 filt_q = 0x10; /* r10[4]:low q(1'b1) */
1000 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
1001 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1002 loop_through = 0x00; /* r5[7], lt on */
1003 lt_att = 0x00; /* r31[7], lt att enable */
1004 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
1005 polyfil_cur = 0x60; /* r25[6:5]:min */
1006 }
1007 }
1008
1009 /* Initialize the shadow registers */
1010 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1011
1012 /* Init Flag & Xtal_check Result */
1013 if (priv->imr_done)
1014 val = 1 | priv->xtal_cap_sel << 1;
1015 else
1016 val = 0;
1017 rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f);
1018 if (rc < 0)
1019 return rc;
1020
1021 /* version */
1022 rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f);
1023 if (rc < 0)
1024 return rc;
1025
1026 /* for LT Gain test */
1027 if (type != V4L2_TUNER_ANALOG_TV) {
1028 rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38);
1029 if (rc < 0)
1030 return rc;
9cc2570a 1031 usleep_range(1000, 2000);
a80abc58 1032 }
f60f5bcb 1033 priv->int_freq = if_khz * 1000;
a80abc58
MCC		 1034
1035 /* Check if standard changed. If so, filter calibration is needed */
1036 if (type != priv->type)
1037 need_calibration = true;
1038 else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std))
1039 need_calibration = true;
1040 else if ((type == V4L2_TUNER_DIGITAL_TV) &&
1041 ((delsys != priv->delsys) || bw != priv->bw))
1042 need_calibration = true;
1043 else
1044 need_calibration = false;
1045
1046 if (need_calibration) {
1047 tuner_dbg("calibrating the tuner\n");
1048 for (i = 0; i < 2; i++) {
1049 /* Set filt_cap */
1050 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60);
1051 if (rc < 0)
1052 return rc;
1053
1054 /* set cali clk =on */
1055 rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04);
1056 if (rc < 0)
1057 return rc;
1058
1059 /* X'tal cap 0pF for PLL */
1060 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03);
1061 if (rc < 0)
1062 return rc;
1063
c0c6ed8d 1064 rc = r820t_set_pll(priv, type, filt_cal_lo * 1000);
a80abc58
MCC		 1065 if (rc < 0 || !priv->has_lock)
1066 return rc;
1067
1068 /* Start Trigger */
1069 rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10);
1070 if (rc < 0)
1071 return rc;
1072
9cc2570a 1073 usleep_range(1000, 2000);
a80abc58
MCC		 1074
1075 /* Stop Trigger */
1076 rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10);
1077 if (rc < 0)
1078 return rc;
1079
1080 /* set cali clk =off */
1081 rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04);
1082 if (rc < 0)
1083 return rc;
1084
1085 /* Check if calibration worked */
226471a1 1086 rc = r820t_read(priv, 0x00, data, sizeof(data));
a80abc58
MCC		 1087 if (rc < 0)
1088 return rc;
1089
1090 priv->fil_cal_code = data[4] & 0x0f;
1091 if (priv->fil_cal_code && priv->fil_cal_code != 0x0f)
1092 break;
1093 }
1094 /* narrowest */
1095 if (priv->fil_cal_code == 0x0f)
1096 priv->fil_cal_code = 0;
1097 }
1098
1099 rc = r820t_write_reg_mask(priv, 0x0a,
1100 filt_q | priv->fil_cal_code, 0x1f);
1101 if (rc < 0)
1102 return rc;
1103
1104 /* Set BW, Filter_gain, & HP corner */
f2658894 1105 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0xef);
a80abc58
MCC		 1106 if (rc < 0)
1107 return rc;
1108
1109
1110 /* Set Img_R */
1111 rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80);
1112 if (rc < 0)
1113 return rc;
1114
1115 /* Set filt_3dB, V6MHz */
1116 rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30);
1117 if (rc < 0)
1118 return rc;
1119
1120 /* channel filter extension */
1121 rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60);
1122 if (rc < 0)
1123 return rc;
1124
1125 /* Loop through */
1126 rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80);
1127 if (rc < 0)
1128 return rc;
1129
1130 /* Loop through attenuation */
1131 rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80);
1132 if (rc < 0)
1133 return rc;
1134
1135 /* filter extension widest */
1136 rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80);
1137 if (rc < 0)
1138 return rc;
1139
1140 /* RF poly filter current */
1141 rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60);
1142 if (rc < 0)
1143 return rc;
1144
1145 /* Store current standard. If it changes, re-calibrate the tuner */
1146 priv->delsys = delsys;
1147 priv->type = type;
1148 priv->std = std;
1149 priv->bw = bw;
1150
1151 return 0;
1152}
1153
f8fde0e0
MCC		 1154static int r820t_read_gain(struct r820t_priv *priv)
1155{
1156 u8 data[4];
1157 int rc;
1158
226471a1 1159 rc = r820t_read(priv, 0x00, data, sizeof(data));
f8fde0e0
MCC		 1160 if (rc < 0)
1161 return rc;
1162
1163 return ((data[3] & 0x0f) << 1) + ((data[3] & 0xf0) >> 4);
1164}
1165
50786ddf
MCC		 1166static int r820t_set_gain_mode(struct r820t_priv *priv,
1167 bool set_manual_gain,
1168 int gain)
1169{
1170 int rc;
1171
1172 if (set_manual_gain) {
1173 int i, total_gain = 0;
1174 uint8_t mix_index = 0, lna_index = 0;
1175 u8 data[4];
1176
1177 /* LNA auto off */
1178 rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10);
1179 if (rc < 0)
1180 return rc;
1181
1182 /* Mixer auto off */
1183 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1184 if (rc < 0)
1185 return rc;
1186
226471a1 1187 rc = r820t_read(priv, 0x00, data, sizeof(data));
50786ddf
MCC		 1188 if (rc < 0)
1189 return rc;
1190
1191 /* set fixed VGA gain for now (16.3 dB) */
1192 rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f);
1193 if (rc < 0)
1194 return rc;
1195
1196 for (i = 0; i < 15; i++) {
1197 if (total_gain >= gain)
1198 break;
1199
1200 total_gain += r820t_lna_gain_steps[++lna_index];
1201
1202 if (total_gain >= gain)
1203 break;
1204
1205 total_gain += r820t_mixer_gain_steps[++mix_index];
1206 }
1207
1208 /* set LNA gain */
1209 rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f);
1210 if (rc < 0)
1211 return rc;
1212
1213 /* set Mixer gain */
1214 rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f);
1215 if (rc < 0)
1216 return rc;
1217 } else {
1218 /* LNA */
1219 rc = r820t_write_reg_mask(priv, 0x05, 0, 0xef);
1220 if (rc < 0)
1221 return rc;
1222
1223 /* Mixer */
1224 rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0xef);
1225 if (rc < 0)
1226 return rc;
1227
1228 /* set fixed VGA gain for now (26.5 dB) */
1229 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1230 if (rc < 0)
1231 return rc;
1232 }
1233
1234 return 0;
1235}
1236
1237
a80abc58
MCC		 1238static int generic_set_freq(struct dvb_frontend *fe,
1239 u32 freq /* in HZ */,
1240 unsigned bw,
1241 enum v4l2_tuner_type type,
1242 v4l2_std_id std, u32 delsys)
1243{
1244 struct r820t_priv *priv = fe->tuner_priv;
1245 int rc = -EINVAL;
1246 u32 lo_freq;
1247
1248 tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
1249 freq / 1000, bw);
1250
a7dd065f
MCC		 1251 rc = r820t_set_tv_standard(priv, bw, type, std, delsys);
1252 if (rc < 0)
1253 goto err;
1254
a80abc58
MCC		 1255 if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC))
1256 lo_freq = freq - priv->int_freq;
1257 else
1258 lo_freq = freq + priv->int_freq;
1259
a80abc58
MCC		 1260 rc = r820t_set_mux(priv, lo_freq);
1261 if (rc < 0)
1262 goto err;
50786ddf
MCC		 1263
1264 rc = r820t_set_gain_mode(priv, true, 0);
1265 if (rc < 0)
1266 goto err;
1267
d75d5388 1268 rc = r820t_set_pll(priv, type, lo_freq);
a80abc58
MCC		 1269 if (rc < 0 || !priv->has_lock)
1270 goto err;
1271
1272 rc = r820t_sysfreq_sel(priv, freq, type, std, delsys);
da31934f
MCC		 1273 if (rc < 0)
1274 goto err;
1275
1276 tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
1277 __func__, freq, r820t_read_gain(priv));
1278
a80abc58 1279err:
a80abc58
MCC		 1280
1281 if (rc < 0)
1282 tuner_dbg("%s: failed=%d\n", __func__, rc);
1283 return rc;
1284}
1285
1286/*
1287 * r820t standby logic
1288 */
1289
1290static int r820t_standby(struct r820t_priv *priv)
1291{
1292 int rc;
1293
064fd169
MCC		 1294 /* If device was not initialized yet, don't need to standby */
1295 if (!priv->init_done)
1296 return 0;
1297
a80abc58
MCC		 1298 rc = r820t_write_reg(priv, 0x06, 0xb1);
1299 if (rc < 0)
1300 return rc;
1301 rc = r820t_write_reg(priv, 0x05, 0x03);
1302 if (rc < 0)
1303 return rc;
1304 rc = r820t_write_reg(priv, 0x07, 0x3a);
1305 if (rc < 0)
1306 return rc;
1307 rc = r820t_write_reg(priv, 0x08, 0x40);
1308 if (rc < 0)
1309 return rc;
1310 rc = r820t_write_reg(priv, 0x09, 0xc0);
1311 if (rc < 0)
1312 return rc;
1313 rc = r820t_write_reg(priv, 0x0a, 0x36);
1314 if (rc < 0)
1315 return rc;
1316 rc = r820t_write_reg(priv, 0x0c, 0x35);
1317 if (rc < 0)
1318 return rc;
1319 rc = r820t_write_reg(priv, 0x0f, 0x68);
1320 if (rc < 0)
1321 return rc;
1322 rc = r820t_write_reg(priv, 0x11, 0x03);
1323 if (rc < 0)
1324 return rc;
1325 rc = r820t_write_reg(priv, 0x17, 0xf4);
1326 if (rc < 0)
1327 return rc;
1328 rc = r820t_write_reg(priv, 0x19, 0x0c);
1329
1330 /* Force initial calibration */
1331 priv->type = -1;
1332
1333 return rc;
1334}
1335
1336/*
1337 * r820t device init logic
1338 */
1339
1340static int r820t_xtal_check(struct r820t_priv *priv)
1341{
1342 int rc, i;
1343 u8 data[3], val;
1344
1345 /* Initialize the shadow registers */
1346 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1347
1348 /* cap 30pF & Drive Low */
1349 rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b);
1350 if (rc < 0)
1351 return rc;
1352
1353 /* set pll autotune = 128kHz */
1354 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
1355 if (rc < 0)
1356 return rc;
1357
1358 /* set manual initial reg = 111111; */
1359 rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f);
1360 if (rc < 0)
1361 return rc;
1362
1363 /* set auto */
1364 rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40);
1365 if (rc < 0)
1366 return rc;
1367
1368 /* Try several xtal capacitor alternatives */
1369 for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) {
1370 rc = r820t_write_reg_mask(priv, 0x10,
1371 r820t_xtal_capacitor[i][0], 0x1b);
1372 if (rc < 0)
1373 return rc;
1374
9cc2570a 1375 usleep_range(5000, 6000);
a80abc58 1376
226471a1 1377 rc = r820t_read(priv, 0x00, data, sizeof(data));
a80abc58
MCC		 1378 if (rc < 0)
1379 return rc;
1380 if ((!data[2]) & 0x40)
1381 continue;
1382
1383 val = data[2] & 0x3f;
1384
1385 if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23))
1386 break;
1387
1388 if (val != 0x3f)
1389 break;
1390 }
1391
1392 if (i == ARRAY_SIZE(r820t_xtal_capacitor))
1393 return -EINVAL;
1394
1395 return r820t_xtal_capacitor[i][1];
1396}
1397
25cf4d46
MCC		 1398static int r820t_imr_prepare(struct r820t_priv *priv)
1399{
1400 int rc;
a80abc58 1401
25cf4d46
MCC		 1402 /* Initialize the shadow registers */
1403 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1404
1405 /* lna off (air-in off) */
1406 rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20);
1407 if (rc < 0)
1408 return rc;
1409
1410 /* mixer gain mode = manual */
1411 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1412 if (rc < 0)
1413 return rc;
1414
1415 /* filter corner = lowest */
1416 rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f);
1417 if (rc < 0)
1418 return rc;
1419
1420 /* filter bw=+2cap, hp=5M */
1421 rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f);
1422 if (rc < 0)
1423 return rc;
1424
1425 /* adc=on, vga code mode, gain = 26.5dB */
1426 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1427 if (rc < 0)
1428 return rc;
1429
1430 /* ring clk = on */
1431 rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08);
1432 if (rc < 0)
1433 return rc;
1434
1435 /* ring power = on */
1436 rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10);
1437 if (rc < 0)
1438 return rc;
1439
1440 /* from ring = ring pll in */
1441 rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02);
1442 if (rc < 0)
1443 return rc;
1444
1445 /* sw_pdect = det3 */
1446 rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80);
1447 if (rc < 0)
1448 return rc;
1449
1450 /* Set filt_3dB */
1451 rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20);
1452
1453 return rc;
1454}
1455
1456static int r820t_multi_read(struct r820t_priv *priv)
1457{
1458 int rc, i;
1459 u8 data[2], min = 0, max = 255, sum = 0;
1460
1461 usleep_range(5000, 6000);
1462
1463 for (i = 0; i < 6; i++) {
1464 rc = r820t_read(priv, 0x00, data, sizeof(data));
1465 if (rc < 0)
1466 return rc;
1467
1468 sum += data[1];
1469
1470 if (data[1] < min)
1471 min = data[1];
1472
1473 if (data[1] > max)
1474 max = data[1];
1475 }
1476 rc = sum - max - min;
1477
1478 return rc;
1479}
1480
1481static int r820t_imr_cross(struct r820t_priv *priv,
1482 struct r820t_sect_type iq_point[3],
1483 u8 *x_direct)
1484{
1485 struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */
1486 struct r820t_sect_type tmp;
1487 int i, rc;
1488 u8 reg08, reg09;
1489
1490 reg08 = r820t_read_cache_reg(priv, 8) & 0xc0;
1491 reg09 = r820t_read_cache_reg(priv, 9) & 0xc0;
1492
1493 tmp.gain_x = 0;
1494 tmp.phase_y = 0;
1495 tmp.value = 255;
1496
1497 for (i = 0; i < 5; i++) {
1498 switch (i) {
1499 case 0:
1500 cross[i].gain_x = reg08;
1501 cross[i].phase_y = reg09;
1502 break;
1503 case 1:
1504 cross[i].gain_x = reg08; /* 0 */
1505 cross[i].phase_y = reg09 + 1; /* Q-1 */
1506 break;
1507 case 2:
1508 cross[i].gain_x = reg08; /* 0 */
1509 cross[i].phase_y = (reg09 | 0x20) + 1; /* I-1 */
1510 break;
1511 case 3:
1512 cross[i].gain_x = reg08 + 1; /* Q-1 */
1513 cross[i].phase_y = reg09;
1514 break;
1515 default:
1516 cross[i].gain_x = (reg08 | 0x20) + 1; /* I-1 */
1517 cross[i].phase_y = reg09;
1518 }
1519
1520 rc = r820t_write_reg(priv, 0x08, cross[i].gain_x);
1521 if (rc < 0)
1522 return rc;
1523
1524 rc = r820t_write_reg(priv, 0x09, cross[i].phase_y);
1525 if (rc < 0)
1526 return rc;
1527
1528 rc = r820t_multi_read(priv);
1529 if (rc < 0)
1530 return rc;
1531
1532 cross[i].value = rc;
1533
1534 if (cross[i].value < tmp.value)
1535 memcpy(&tmp, &cross[i], sizeof(tmp));
1536 }
1537
1538 if ((tmp.phase_y & 0x1f) == 1) { /* y-direction */
1539 *x_direct = 0;
1540
1541 iq_point[0] = cross[0];
1542 iq_point[1] = cross[1];
1543 iq_point[2] = cross[2];
1544 } else { /* (0,0) or x-direction */
1545 *x_direct = 1;
1546
1547 iq_point[0] = cross[0];
1548 iq_point[1] = cross[3];
1549 iq_point[2] = cross[4];
1550 }
1551 return 0;
1552}
1553
1554static void r820t_compre_cor(struct r820t_sect_type iq[3])
1555{
1556 int i;
1557
1558 for (i = 3; i > 0; i--) {
1559 if (iq[0].value > iq[i - 1].value)
1560 swap(iq[0], iq[i - 1]);
1561 }
1562}
1563
1564static int r820t_compre_step(struct r820t_priv *priv,
1565 struct r820t_sect_type iq[3], u8 reg)
1566{
1567 int rc;
1568 struct r820t_sect_type tmp;
1569
1570 /*
1571 * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare
1572 * with min value:
1573 * new < min => update to min and continue
1574 * new > min => Exit
1575 */
1576
1577 /* min value already saved in iq[0] */
1578 tmp.phase_y = iq[0].phase_y;
1579 tmp.gain_x = iq[0].gain_x;
1580
1581 while (((tmp.gain_x & 0x1f) < IMR_TRIAL) &&
1582 ((tmp.phase_y & 0x1f) < IMR_TRIAL)) {
1583 if (reg == 0x08)
1584 tmp.gain_x++;
1585 else
1586 tmp.phase_y++;
1587
1588 rc = r820t_write_reg(priv, 0x08, tmp.gain_x);
1589 if (rc < 0)
1590 return rc;
1591
1592 rc = r820t_write_reg(priv, 0x09, tmp.phase_y);
1593 if (rc < 0)
1594 return rc;
1595
1596 rc = r820t_multi_read(priv);
1597 if (rc < 0)
1598 return rc;
1599 tmp.value = rc;
1600
1601 if (tmp.value <= iq[0].value) {
1602 iq[0].gain_x = tmp.gain_x;
1603 iq[0].phase_y = tmp.phase_y;
1604 iq[0].value = tmp.value;
1605 } else {
1606 return 0;
1607 }
1608
1609 }
1610
1611 return 0;
1612}
1613
1614static int r820t_iq_tree(struct r820t_priv *priv,
1615 struct r820t_sect_type iq[3],
1616 u8 fix_val, u8 var_val, u8 fix_reg)
1617{
1618 int rc, i;
1619 u8 tmp, var_reg;
1620
1621 /*
1622 * record IMC results by input gain/phase location then adjust
1623 * gain or phase positive 1 step and negtive 1 step,
1624 * both record results
1625 */
1626
1627 if (fix_reg == 0x08)
1628 var_reg = 0x09;
1629 else
1630 var_reg = 0x08;
1631
1632 for (i = 0; i < 3; i++) {
1633 rc = r820t_write_reg(priv, fix_reg, fix_val);
1634 if (rc < 0)
1635 return rc;
1636
1637 rc = r820t_write_reg(priv, var_reg, var_val);
1638 if (rc < 0)
1639 return rc;
1640
1641 rc = r820t_multi_read(priv);
1642 if (rc < 0)
1643 return rc;
1644 iq[i].value = rc;
1645
1646 if (fix_reg == 0x08) {
1647 iq[i].gain_x = fix_val;
1648 iq[i].phase_y = var_val;
1649 } else {
1650 iq[i].phase_y = fix_val;
1651 iq[i].gain_x = var_val;
1652 }
1653
1654 if (i == 0) { /* try right-side point */
1655 var_val++;
1656 } else if (i == 1) { /* try left-side point */
1657 /* if absolute location is 1, change I/Q direction */
1658 if ((var_val & 0x1f) < 0x02) {
1659 tmp = 2 - (var_val & 0x1f);
1660
1661 /* b[5]:I/Q selection. 0:Q-path, 1:I-path */
1662 if (var_val & 0x20) {
1663 var_val &= 0xc0;
1664 var_val |= tmp;
1665 } else {
1666 var_val |= 0x20 | tmp;
1667 }
1668 } else {
1669 var_val -= 2;
1670 }
1671 }
1672 }
1673
1674 return 0;
1675}
1676
1677static int r820t_section(struct r820t_priv *priv,
1678 struct r820t_sect_type *iq_point)
1679{
1680 int rc;
1681 struct r820t_sect_type compare_iq[3], compare_bet[3];
1682
1683 /* Try X-1 column and save min result to compare_bet[0] */
1684 if (!(iq_point->gain_x & 0x1f))
1685 compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1; /* Q-path, Gain=1 */
1686 else
1687 compare_iq[0].gain_x = iq_point->gain_x - 1; /* left point */
1688 compare_iq[0].phase_y = iq_point->phase_y;
1689
1690 /* y-direction */
1691 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1692 compare_iq[0].phase_y, 0x08);
1693 if (rc < 0)
1694 return rc;
1695
1696 r820t_compre_cor(compare_iq);
1697
1698 compare_bet[0] = compare_iq[0];
1699
1700 /* Try X column and save min result to compare_bet[1] */
1701 compare_iq[0].gain_x = iq_point->gain_x;
1702 compare_iq[0].phase_y = iq_point->phase_y;
1703
1704 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1705 compare_iq[0].phase_y, 0x08);
1706 if (rc < 0)
1707 return rc;
1708
1709 r820t_compre_cor(compare_iq);
1710
1711 compare_bet[1] = compare_iq[0];
1712
1713 /* Try X+1 column and save min result to compare_bet[2] */
1714 if ((iq_point->gain_x & 0x1f) == 0x00)
1715 compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1; /* I-path, Gain=1 */
1716 else
1717 compare_iq[0].gain_x = iq_point->gain_x + 1;
1718 compare_iq[0].phase_y = iq_point->phase_y;
1719
1720 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1721 compare_iq[0].phase_y, 0x08);
1722 if (rc < 0)
1723 return rc;
1724
1725 r820t_compre_cor(compare_iq);
1726
1727 compare_bet[2] = compare_iq[0];
1728
1729 r820t_compre_cor(compare_bet);
1730
1731 *iq_point = compare_bet[0];
1732
1733 return 0;
1734}
1735
1736static int r820t_vga_adjust(struct r820t_priv *priv)
1737{
1738 int rc;
1739 u8 vga_count;
1740
1741 /* increase vga power to let image significant */
1742 for (vga_count = 12; vga_count < 16; vga_count++) {
1743 rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f);
1744 if (rc < 0)
1745 return rc;
1746
1747 usleep_range(10000, 11000);
1748
1749 rc = r820t_multi_read(priv);
1750 if (rc < 0)
1751 return rc;
1752
1753 if (rc > 40 * 4)
1754 break;
1755 }
1756
1757 return 0;
1758}
1759
1760static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1761{
1762 struct r820t_sect_type compare_iq[3];
1763 int rc;
1764 u8 x_direction = 0; /* 1:x, 0:y */
1765 u8 dir_reg, other_reg;
1766
1767 r820t_vga_adjust(priv);
1768
1769 rc = r820t_imr_cross(priv, compare_iq, &x_direction);
1770 if (rc < 0)
1771 return rc;
1772
1773 if (x_direction == 1) {
1774 dir_reg = 0x08;
1775 other_reg = 0x09;
1776 } else {
1777 dir_reg = 0x09;
1778 other_reg = 0x08;
1779 }
1780
1781 /* compare and find min of 3 points. determine i/q direction */
1782 r820t_compre_cor(compare_iq);
1783
1784 /* increase step to find min value of this direction */
1785 rc = r820t_compre_step(priv, compare_iq, dir_reg);
1786 if (rc < 0)
1787 return rc;
1788
1789 /* the other direction */
1790 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1791 compare_iq[0].phase_y, dir_reg);
1792 if (rc < 0)
1793 return rc;
1794
1795 /* compare and find min of 3 points. determine i/q direction */
1796 r820t_compre_cor(compare_iq);
1797
1798 /* increase step to find min value on this direction */
1799 rc = r820t_compre_step(priv, compare_iq, other_reg);
1800 if (rc < 0)
1801 return rc;
1802
1803 /* check 3 points again */
1804 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1805 compare_iq[0].phase_y, other_reg);
1806 if (rc < 0)
1807 return rc;
1808
1809 r820t_compre_cor(compare_iq);
1810
1811 /* section-9 check */
1812 rc = r820t_section(priv, compare_iq);
1813
1814 *iq_pont = compare_iq[0];
1815
1816 /* reset gain/phase control setting */
1817 rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
1818 if (rc < 0)
1819 return rc;
1820
1821 rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
1822
1823 return rc;
1824}
1825
1826static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1827{
1828 int rc;
1829
1830 r820t_vga_adjust(priv);
1831
1832 /*
1833 * search surrounding points from previous point
1834 * try (x-1), (x), (x+1) columns, and find min IMR result point
1835 */
1836 rc = r820t_section(priv, iq_pont);
1837 if (rc < 0)
1838 return rc;
1839
1840 return 0;
1841}
1842
1843static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag)
1844{
1845 struct r820t_sect_type imr_point;
1846 int rc;
1847 u32 ring_vco, ring_freq, ring_ref;
1848 u8 n_ring, n;
1849 int reg18, reg19, reg1f;
1850
1851 if (priv->cfg->xtal > 24000000)
1852 ring_ref = priv->cfg->xtal / 2;
1853 else
1854 ring_ref = priv->cfg->xtal;
1855
1856 for (n = 0; n < 16; n++) {
1857 if ((16 + n) * 8 * ring_ref >= 3100000) {
1858 n_ring = n;
1859 break;
1860 }
1861
1862 /* n_ring not found */
1863 if (n == 15)
1864 n_ring = n;
1865 }
1866
1867 reg18 = r820t_read_cache_reg(priv, 0x18);
1868 reg19 = r820t_read_cache_reg(priv, 0x19);
1869 reg1f = r820t_read_cache_reg(priv, 0x1f);
1870
1871 reg18 &= 0xf0; /* set ring[3:0] */
1872 reg18 |= n_ring;
1873
1874 ring_vco = (16 + n_ring) * 8 * ring_ref;
1875
1876 reg18 &= 0xdf; /* clear ring_se23 */
1877 reg19 &= 0xfc; /* clear ring_seldiv */
1878 reg1f &= 0xfc; /* clear ring_att */
1879
1880 switch (imr_mem) {
1881 case 0:
1882 ring_freq = ring_vco / 48;
1883 reg18 |= 0x20; /* ring_se23 = 1 */
1884 reg19 |= 0x03; /* ring_seldiv = 3 */
1885 reg1f |= 0x02; /* ring_att 10 */
1886 break;
1887 case 1:
1888 ring_freq = ring_vco / 16;
1889 reg18 |= 0x00; /* ring_se23 = 0 */
1890 reg19 |= 0x02; /* ring_seldiv = 2 */
1891 reg1f |= 0x00; /* pw_ring 00 */
1892 break;
1893 case 2:
1894 ring_freq = ring_vco / 8;
1895 reg18 |= 0x00; /* ring_se23 = 0 */
1896 reg19 |= 0x01; /* ring_seldiv = 1 */
1897 reg1f |= 0x03; /* pw_ring 11 */
1898 break;
1899 case 3:
1900 ring_freq = ring_vco / 6;
1901 reg18 |= 0x20; /* ring_se23 = 1 */
1902 reg19 |= 0x00; /* ring_seldiv = 0 */
1903 reg1f |= 0x03; /* pw_ring 11 */
1904 break;
1905 case 4:
1906 ring_freq = ring_vco / 4;
1907 reg18 |= 0x00; /* ring_se23 = 0 */
1908 reg19 |= 0x00; /* ring_seldiv = 0 */
1909 reg1f |= 0x01; /* pw_ring 01 */
1910 break;
1911 default:
1912 ring_freq = ring_vco / 4;
1913 reg18 |= 0x00; /* ring_se23 = 0 */
1914 reg19 |= 0x00; /* ring_seldiv = 0 */
1915 reg1f |= 0x01; /* pw_ring 01 */
1916 break;
1917 }
1918
1919
1920 /* write pw_ring, n_ring, ringdiv2 registers */
1921
1922 /* n_ring, ring_se23 */
1923 rc = r820t_write_reg(priv, 0x18, reg18);
1924 if (rc < 0)
1925 return rc;
1926
1927 /* ring_sediv */
1928 rc = r820t_write_reg(priv, 0x19, reg19);
1929 if (rc < 0)
1930 return rc;
1931
1932 /* pw_ring */
1933 rc = r820t_write_reg(priv, 0x1f, reg1f);
1934 if (rc < 0)
1935 return rc;
1936
1937 /* mux input freq ~ rf_in freq */
1938 rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000);
1939 if (rc < 0)
1940 return rc;
1941
1942 rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV,
1943 (ring_freq - 5300) * 1000);
1944 if (!priv->has_lock)
1945 rc = -EINVAL;
1946 if (rc < 0)
1947 return rc;
1948
1949 if (im_flag) {
1950 rc = r820t_iq(priv, &imr_point);
1951 } else {
1952 imr_point.gain_x = priv->imr_data[3].gain_x;
1953 imr_point.phase_y = priv->imr_data[3].phase_y;
1954 imr_point.value = priv->imr_data[3].value;
1955
1956 rc = r820t_f_imr(priv, &imr_point);
1957 }
1958 if (rc < 0)
1959 return rc;
1960
1961 /* save IMR value */
1962 switch (imr_mem) {
1963 case 0:
1964 priv->imr_data[0].gain_x = imr_point.gain_x;
1965 priv->imr_data[0].phase_y = imr_point.phase_y;
1966 priv->imr_data[0].value = imr_point.value;
1967 break;
1968 case 1:
1969 priv->imr_data[1].gain_x = imr_point.gain_x;
1970 priv->imr_data[1].phase_y = imr_point.phase_y;
1971 priv->imr_data[1].value = imr_point.value;
1972 break;
1973 case 2:
1974 priv->imr_data[2].gain_x = imr_point.gain_x;
1975 priv->imr_data[2].phase_y = imr_point.phase_y;
1976 priv->imr_data[2].value = imr_point.value;
1977 break;
1978 case 3:
1979 priv->imr_data[3].gain_x = imr_point.gain_x;
1980 priv->imr_data[3].phase_y = imr_point.phase_y;
1981 priv->imr_data[3].value = imr_point.value;
1982 break;
1983 case 4:
1984 priv->imr_data[4].gain_x = imr_point.gain_x;
1985 priv->imr_data[4].phase_y = imr_point.phase_y;
1986 priv->imr_data[4].value = imr_point.value;
1987 break;
1988 default:
1989 priv->imr_data[4].gain_x = imr_point.gain_x;
1990 priv->imr_data[4].phase_y = imr_point.phase_y;
1991 priv->imr_data[4].value = imr_point.value;
1992 break;
1993 }
1994
1995 return 0;
1996}
1997
1998static int r820t_imr_callibrate(struct r820t_priv *priv)
a80abc58 1999{
a80abc58
MCC		 2000 int rc, i;
2001 int xtal_cap = 0;
2002
52775fd5 2003 if (priv->init_done)
25cf4d46 2004 return 0;
a80abc58 2005
25cf4d46 2006 /* Detect Xtal capacitance */
a80abc58
MCC		 2007 if ((priv->cfg->rafael_chip == CHIP_R820T) ||
2008 (priv->cfg->rafael_chip == CHIP_R828S) ||
2009 (priv->cfg->rafael_chip == CHIP_R820C)) {
2010 priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
2011 } else {
4176e7ea
MCC		 2012 /* Initialize registers */
2013 rc = r820t_write(priv, 0x05,
2014 r820t_init_array, sizeof(r820t_init_array));
2015 if (rc < 0)
2016 return rc;
a80abc58
MCC		 2017 for (i = 0; i < 3; i++) {
2018 rc = r820t_xtal_check(priv);
2019 if (rc < 0)
25cf4d46 2020 return rc;
a80abc58
MCC		 2021 if (!i || rc > xtal_cap)
2022 xtal_cap = rc;
2023 }
2024 priv->xtal_cap_sel = xtal_cap;
2025 }
2026
52775fd5
MCC		 2027 /*
2028 * Disables IMR callibration. That emulates the same behaviour
2029 * as what is done by rtl-sdr userspace library. Useful for testing
2030 */
2031 if (no_imr_cal) {
2032 priv->init_done = true;
2033
2034 return 0;
2035 }
2036
a80abc58
MCC		 2037 /* Initialize registers */
2038 rc = r820t_write(priv, 0x05,
2039 r820t_init_array, sizeof(r820t_init_array));
25cf4d46
MCC		 2040 if (rc < 0)
2041 return rc;
2042
2043 rc = r820t_imr_prepare(priv);
2044 if (rc < 0)
2045 return rc;
2046
2047 rc = r820t_imr(priv, 3, true);
2048 if (rc < 0)
2049 return rc;
2050 rc = r820t_imr(priv, 1, false);
2051 if (rc < 0)
2052 return rc;
2053 rc = r820t_imr(priv, 0, false);
2054 if (rc < 0)
2055 return rc;
2056 rc = r820t_imr(priv, 2, false);
2057 if (rc < 0)
2058 return rc;
2059 rc = r820t_imr(priv, 4, false);
2060 if (rc < 0)
2061 return rc;
2062
52775fd5 2063 priv->init_done = true;
25cf4d46
MCC		 2064 priv->imr_done = true;
2065
2066 return 0;
2067}
2068
6596e880
MCC		 2069#if 0
2070/* Not used, for now */
2071static int r820t_gpio(struct r820t_priv *priv, bool enable)
2072{
2073 return r820t_write_reg_mask(priv, 0x0f, enable ? 1 : 0, 0x01);
2074}
2075#endif
2076
25cf4d46
MCC		 2077/*
2078 * r820t frontend operations and tuner attach code
2079 *
2080 * All driver locks and i2c control are only in this part of the code
2081 */
2082
2083static int r820t_init(struct dvb_frontend *fe)
2084{
2085 struct r820t_priv *priv = fe->tuner_priv;
2086 int rc;
2087
2088 tuner_dbg("%s:\n", __func__);
2089
2090 mutex_lock(&priv->lock);
2091 if (fe->ops.i2c_gate_ctrl)
2092 fe->ops.i2c_gate_ctrl(fe, 1);
2093
2094 rc = r820t_imr_callibrate(priv);
2095 if (rc < 0)
2096 goto err;
2097
2098 /* Initialize registers */
2099 rc = r820t_write(priv, 0x05,
2100 r820t_init_array, sizeof(r820t_init_array));
a80abc58 2101
a80abc58
MCC		 2102err:
2103 if (fe->ops.i2c_gate_ctrl)
2104 fe->ops.i2c_gate_ctrl(fe, 0);
7a5ef30d 2105 mutex_unlock(&priv->lock);
a80abc58 2106
7a5ef30d
MCC		 2107 if (rc < 0)
2108 tuner_dbg("%s: failed=%d\n", __func__, rc);
a80abc58
MCC		 2109 return rc;
2110}
2111
2112static int r820t_sleep(struct dvb_frontend *fe)
2113{
2114 struct r820t_priv *priv = fe->tuner_priv;
2115 int rc;
2116
2117 tuner_dbg("%s:\n", __func__);
2118
7a5ef30d 2119 mutex_lock(&priv->lock);
a80abc58
MCC		 2120 if (fe->ops.i2c_gate_ctrl)
2121 fe->ops.i2c_gate_ctrl(fe, 1);
2122
a80abc58 2123 rc = r820t_standby(priv);
a80abc58
MCC		 2124
2125 if (fe->ops.i2c_gate_ctrl)
2126 fe->ops.i2c_gate_ctrl(fe, 0);
7a5ef30d 2127 mutex_unlock(&priv->lock);
a80abc58
MCC		 2128
2129 tuner_dbg("%s: failed=%d\n", __func__, rc);
2130 return rc;
2131}
2132
2133static int r820t_set_analog_freq(struct dvb_frontend *fe,
2134 struct analog_parameters *p)
2135{
2136 struct r820t_priv *priv = fe->tuner_priv;
2137 unsigned bw;
7a5ef30d 2138 int rc;
a80abc58
MCC		 2139
2140 tuner_dbg("%s called\n", __func__);
2141
2142 /* if std is not defined, choose one */
2143 if (!p->std)
2144 p->std = V4L2_STD_MN;
2145
2146 if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC))
2147 bw = 6;
2148 else
2149 bw = 8;
2150
7a5ef30d
MCC		 2151 mutex_lock(&priv->lock);
2152 if (fe->ops.i2c_gate_ctrl)
2153 fe->ops.i2c_gate_ctrl(fe, 1);
2154
2155 rc = generic_set_freq(fe, 62500l * p->frequency, bw,
2156 V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED);
2157
2158 if (fe->ops.i2c_gate_ctrl)
2159 fe->ops.i2c_gate_ctrl(fe, 0);
2160 mutex_unlock(&priv->lock);
2161
2162 return rc;
a80abc58
MCC		 2163}
2164
2165static int r820t_set_params(struct dvb_frontend *fe)
2166{
2167 struct r820t_priv *priv = fe->tuner_priv;
2168 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2169 int rc;
2170 unsigned bw;
2171
2172 tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
2173 __func__, c->delivery_system, c->frequency, c->bandwidth_hz);
2174
7a5ef30d 2175 mutex_lock(&priv->lock);
a80abc58
MCC		 2176 if (fe->ops.i2c_gate_ctrl)
2177 fe->ops.i2c_gate_ctrl(fe, 1);
2178
2179 bw = (c->bandwidth_hz + 500000) / 1000000;
2180 if (!bw)
2181 bw = 8;
2182
2183 rc = generic_set_freq(fe, c->frequency, bw,
2184 V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system);
2185
2186 if (fe->ops.i2c_gate_ctrl)
2187 fe->ops.i2c_gate_ctrl(fe, 0);
7a5ef30d 2188 mutex_unlock(&priv->lock);
a80abc58
MCC		 2189
2190 if (rc)
2191 tuner_dbg("%s: failed=%d\n", __func__, rc);
2192 return rc;
2193}
2194
2195static int r820t_signal(struct dvb_frontend *fe, u16 *strength)
2196{
2197 struct r820t_priv *priv = fe->tuner_priv;
f8fde0e0 2198 int rc = 0;
a80abc58 2199
7a5ef30d
MCC		 2200 mutex_lock(&priv->lock);
2201 if (fe->ops.i2c_gate_ctrl)
2202 fe->ops.i2c_gate_ctrl(fe, 1);
2203
f8fde0e0
MCC		 2204 if (priv->has_lock) {
2205 rc = r820t_read_gain(priv);
2206 if (rc < 0)
7a5ef30d 2207 goto err;
f8fde0e0
MCC		 2208
2209 /* A higher gain at LNA means a lower signal strength */
2210 *strength = (45 - rc) << 4 | 0xff;
75c1819e
MCC		 2211 if (*strength == 0xff)
2212 *strength = 0;
f8fde0e0 2213 } else {
a80abc58 2214 *strength = 0;
f8fde0e0
MCC		 2215 }
2216
7a5ef30d
MCC		 2217err:
2218 if (fe->ops.i2c_gate_ctrl)
2219 fe->ops.i2c_gate_ctrl(fe, 0);
2220 mutex_unlock(&priv->lock);
2221
f8fde0e0
MCC		 2222 tuner_dbg("%s: %s, gain=%d strength=%d\n",
2223 __func__,
2224 priv->has_lock ? "PLL locked" : "no signal",
2225 rc, *strength);
a80abc58
MCC		 2226
2227 return 0;
2228}
2229
2230static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
2231{
2232 struct r820t_priv *priv = fe->tuner_priv;
2233
2234 tuner_dbg("%s:\n", __func__);
2235
2236 *frequency = priv->int_freq;
2237
2238 return 0;
2239}
2240
2241static int r820t_release(struct dvb_frontend *fe)
2242{
2243 struct r820t_priv *priv = fe->tuner_priv;
2244
2245 tuner_dbg("%s:\n", __func__);
2246
2247 mutex_lock(&r820t_list_mutex);
2248
2249 if (priv)
2250 hybrid_tuner_release_state(priv);
2251
2252 mutex_unlock(&r820t_list_mutex);
2253
2254 fe->tuner_priv = NULL;
2255
2256 kfree(fe->tuner_priv);
2257
2258 return 0;
2259}
2260
2261static const struct dvb_tuner_ops r820t_tuner_ops = {
2262 .info = {
2263 .name = "Rafael Micro R820T",
2264 .frequency_min = 42000000,
2265 .frequency_max = 1002000000,
2266 },
2267 .init = r820t_init,
2268 .release = r820t_release,
2269 .sleep = r820t_sleep,
2270 .set_params = r820t_set_params,
2271 .set_analog_params = r820t_set_analog_freq,
2272 .get_if_frequency = r820t_get_if_frequency,
2273 .get_rf_strength = r820t_signal,
2274};
2275
2276struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
2277 struct i2c_adapter *i2c,
2278 const struct r820t_config *cfg)
2279{
2280 struct r820t_priv *priv;
2281 int rc = -ENODEV;
2282 u8 data[5];
2283 int instance;
2284
2285 mutex_lock(&r820t_list_mutex);
2286
2287 instance = hybrid_tuner_request_state(struct r820t_priv, priv,
2288 hybrid_tuner_instance_list,
2289 i2c, cfg->i2c_addr,
2290 "r820t");
2291 switch (instance) {
2292 case 0:
2293 /* memory allocation failure */
2294 goto err_no_gate;
2295 break;
2296 case 1:
2297 /* new tuner instance */
2298 priv->cfg = cfg;
2299
2300 mutex_init(&priv->lock);
2301
2302 fe->tuner_priv = priv;
2303 break;
2304 case 2:
2305 /* existing tuner instance */
2306 fe->tuner_priv = priv;
2307 break;
2308 }
2309
2310 memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops, sizeof(r820t_tuner_ops));
2311
2312 if (fe->ops.i2c_gate_ctrl)
2313 fe->ops.i2c_gate_ctrl(fe, 1);
2314
2315 /* check if the tuner is there */
226471a1 2316 rc = r820t_read(priv, 0x00, data, sizeof(data));
a80abc58
MCC		 2317 if (rc < 0)
2318 goto err;
2319
2320 rc = r820t_sleep(fe);
2321 if (rc < 0)
2322 goto err;
2323
2324 tuner_info("Rafael Micro r820t successfully identified\n");
2325
2326 fe->tuner_priv = priv;
2327 memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops,
2328 sizeof(struct dvb_tuner_ops));
2329
2330 if (fe->ops.i2c_gate_ctrl)
2331 fe->ops.i2c_gate_ctrl(fe, 0);
2332
2333 mutex_unlock(&r820t_list_mutex);
2334
2335 return fe;
2336err:
2337 if (fe->ops.i2c_gate_ctrl)
2338 fe->ops.i2c_gate_ctrl(fe, 0);
2339
2340err_no_gate:
2341 mutex_unlock(&r820t_list_mutex);
2342
2343 tuner_info("%s: failed=%d\n", __func__, rc);
2344 r820t_release(fe);
2345 return NULL;
2346}
2347EXPORT_SYMBOL_GPL(r820t_attach);
2348
2349MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
2350MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2351MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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