Commit | Line | Data |
---|---|---|
5200401a | 1 | /* |
d0058645 RP |
2 | * tm6000-stds.c - driver for TM5600/TM6000/TM6010 USB video capture devices |
3 | * | |
37e59f87 | 4 | * Copyright (C) 2007 Mauro Carvalho Chehab |
d0058645 RP |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation version 2 | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
5200401a MCC |
18 | */ |
19 | ||
20 | #include <linux/module.h> | |
21 | #include <linux/kernel.h> | |
22 | #include "tm6000.h" | |
23 | #include "tm6000-regs.h" | |
24 | ||
3d1a51db | 25 | static unsigned int tm6010_a_mode; |
886a3c0b SR |
26 | module_param(tm6010_a_mode, int, 0644); |
27 | MODULE_PARM_DESC(tm6010_a_mode, "set tm6010 sif audio mode"); | |
0f6040e8 | 28 | |
5200401a MCC |
29 | struct tm6000_reg_settings { |
30 | unsigned char req; | |
31 | unsigned char reg; | |
32 | unsigned char value; | |
33 | }; | |
34 | ||
5200401a MCC |
35 | |
36 | struct tm6000_std_settings { | |
37 | v4l2_std_id id; | |
c0fa65ff TR |
38 | struct tm6000_reg_settings *common; |
39 | }; | |
40 | ||
41 | static struct tm6000_reg_settings composite_pal_m[] = { | |
42 | { TM6010_REQ07_R3F_RESET, 0x01 }, | |
43 | { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x04 }, | |
44 | { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, | |
45 | { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, | |
46 | { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 }, | |
47 | { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, | |
48 | { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, | |
49 | { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83 }, | |
50 | { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a }, | |
51 | { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0 }, | |
52 | { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, | |
53 | { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, | |
54 | { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, | |
55 | { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, | |
56 | { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, | |
57 | { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x20 }, | |
58 | { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 }, | |
59 | { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c }, | |
60 | { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, | |
61 | { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 }, | |
62 | { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, | |
63 | { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc }, | |
64 | { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, | |
65 | { TM6010_REQ07_R3F_RESET, 0x00 }, | |
66 | { 0, 0, 0 } | |
67 | }; | |
68 | ||
69 | static struct tm6000_reg_settings composite_pal_nc[] = { | |
70 | { TM6010_REQ07_R3F_RESET, 0x01 }, | |
71 | { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x36 }, | |
72 | { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, | |
73 | { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, | |
74 | { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02 }, | |
75 | { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, | |
76 | { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, | |
77 | { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91 }, | |
78 | { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f }, | |
79 | { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c }, | |
80 | { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, | |
81 | { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, | |
82 | { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, | |
83 | { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, | |
84 | { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c }, | |
85 | { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c }, | |
86 | { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 }, | |
87 | { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c }, | |
88 | { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, | |
89 | { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 }, | |
90 | { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, | |
91 | { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc }, | |
92 | { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, | |
93 | { TM6010_REQ07_R3F_RESET, 0x00 }, | |
94 | { 0, 0, 0 } | |
95 | }; | |
96 | ||
97 | static struct tm6000_reg_settings composite_pal[] = { | |
98 | { TM6010_REQ07_R3F_RESET, 0x01 }, | |
99 | { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x32 }, | |
100 | { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, | |
101 | { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, | |
102 | { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02 }, | |
103 | { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, | |
104 | { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25 }, | |
105 | { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5 }, | |
106 | { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63 }, | |
107 | { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50 }, | |
108 | { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, | |
109 | { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, | |
110 | { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, | |
111 | { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, | |
112 | { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c }, | |
113 | { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c }, | |
114 | { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 }, | |
115 | { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c }, | |
116 | { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, | |
117 | { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 }, | |
118 | { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, | |
119 | { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc }, | |
120 | { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, | |
121 | { TM6010_REQ07_R3F_RESET, 0x00 }, | |
122 | { 0, 0, 0 } | |
123 | }; | |
124 | ||
125 | static struct tm6000_reg_settings composite_secam[] = { | |
126 | { TM6010_REQ07_R3F_RESET, 0x01 }, | |
127 | { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x38 }, | |
128 | { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, | |
129 | { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, | |
130 | { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02 }, | |
131 | { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, | |
132 | { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24 }, | |
133 | { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92 }, | |
134 | { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8 }, | |
135 | { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed }, | |
136 | { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, | |
137 | { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, | |
138 | { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, | |
139 | { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, | |
140 | { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c }, | |
141 | { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c }, | |
142 | { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 }, | |
143 | { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c }, | |
144 | { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18 }, | |
145 | { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 }, | |
146 | { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xff }, | |
147 | { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, | |
148 | { TM6010_REQ07_R3F_RESET, 0x00 }, | |
149 | { 0, 0, 0 } | |
150 | }; | |
151 | ||
152 | static struct tm6000_reg_settings composite_ntsc[] = { | |
153 | { TM6010_REQ07_R3F_RESET, 0x01 }, | |
154 | { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 }, | |
155 | { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f }, | |
156 | { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, | |
157 | { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 }, | |
158 | { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, | |
159 | { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, | |
160 | { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b }, | |
161 | { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 }, | |
162 | { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 }, | |
163 | { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, | |
164 | { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, | |
165 | { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, | |
166 | { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, | |
167 | { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, | |
168 | { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 }, | |
169 | { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 }, | |
170 | { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c }, | |
171 | { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, | |
172 | { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 }, | |
173 | { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, | |
174 | { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd }, | |
175 | { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, | |
176 | { TM6010_REQ07_R3F_RESET, 0x00 }, | |
177 | { 0, 0, 0 } | |
5200401a MCC |
178 | }; |
179 | ||
180 | static struct tm6000_std_settings composite_stds[] = { | |
c0fa65ff TR |
181 | { .id = V4L2_STD_PAL_M, .common = composite_pal_m, }, |
182 | { .id = V4L2_STD_PAL_Nc, .common = composite_pal_nc, }, | |
183 | { .id = V4L2_STD_PAL, .common = composite_pal, }, | |
184 | { .id = V4L2_STD_SECAM, .common = composite_secam, }, | |
185 | { .id = V4L2_STD_NTSC, .common = composite_ntsc, }, | |
5200401a MCC |
186 | }; |
187 | ||
c0fa65ff TR |
188 | static struct tm6000_reg_settings svideo_pal_m[] = { |
189 | { TM6010_REQ07_R3F_RESET, 0x01 }, | |
190 | { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x05 }, | |
191 | { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, | |
192 | { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, | |
193 | { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04 }, | |
194 | { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, | |
195 | { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, | |
196 | { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83 }, | |
197 | { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a }, | |
198 | { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0 }, | |
199 | { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, | |
200 | { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, | |
201 | { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, | |
202 | { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, | |
203 | { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, | |
204 | { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 }, | |
205 | { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 }, | |
206 | { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c }, | |
207 | { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, | |
208 | { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 }, | |
209 | { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, | |
210 | { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc }, | |
211 | { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, | |
212 | { TM6010_REQ07_R3F_RESET, 0x00 }, | |
213 | { 0, 0, 0 } | |
5200401a MCC |
214 | }; |
215 | ||
c0fa65ff TR |
216 | static struct tm6000_reg_settings svideo_pal_nc[] = { |
217 | { TM6010_REQ07_R3F_RESET, 0x01 }, | |
218 | { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x37 }, | |
219 | { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, | |
220 | { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, | |
221 | { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04 }, | |
222 | { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, | |
223 | { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, | |
224 | { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91 }, | |
225 | { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f }, | |
226 | { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c }, | |
227 | { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, | |
228 | { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, | |
229 | { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, | |
230 | { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, | |
231 | { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, | |
232 | { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 }, | |
233 | { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 }, | |
234 | { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c }, | |
235 | { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, | |
236 | { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 }, | |
237 | { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, | |
238 | { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc }, | |
239 | { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, | |
240 | { TM6010_REQ07_R3F_RESET, 0x00 }, | |
241 | { 0, 0, 0 } | |
242 | }; | |
243 | ||
244 | static struct tm6000_reg_settings svideo_pal[] = { | |
245 | { TM6010_REQ07_R3F_RESET, 0x01 }, | |
246 | { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x33 }, | |
247 | { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, | |
248 | { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, | |
249 | { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04 }, | |
250 | { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x30 }, | |
251 | { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25 }, | |
252 | { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5 }, | |
253 | { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63 }, | |
254 | { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50 }, | |
255 | { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, | |
256 | { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, | |
257 | { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, | |
258 | { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, | |
259 | { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c }, | |
260 | { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2a }, | |
261 | { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 }, | |
262 | { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c }, | |
263 | { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, | |
264 | { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 }, | |
265 | { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, | |
266 | { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc }, | |
267 | { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, | |
268 | { TM6010_REQ07_R3F_RESET, 0x00 }, | |
269 | { 0, 0, 0 } | |
270 | }; | |
271 | ||
272 | static struct tm6000_reg_settings svideo_secam[] = { | |
273 | { TM6010_REQ07_R3F_RESET, 0x01 }, | |
274 | { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x39 }, | |
275 | { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, | |
276 | { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, | |
277 | { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x03 }, | |
278 | { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, | |
279 | { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24 }, | |
280 | { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92 }, | |
281 | { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8 }, | |
282 | { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed }, | |
283 | { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, | |
284 | { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, | |
285 | { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, | |
286 | { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, | |
287 | { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c }, | |
288 | { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2a }, | |
289 | { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 }, | |
290 | { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c }, | |
291 | { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18 }, | |
292 | { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 }, | |
293 | { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xff }, | |
294 | { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, | |
295 | { TM6010_REQ07_R3F_RESET, 0x00 }, | |
296 | { 0, 0, 0 } | |
297 | }; | |
298 | ||
299 | static struct tm6000_reg_settings svideo_ntsc[] = { | |
300 | { TM6010_REQ07_R3F_RESET, 0x01 }, | |
301 | { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x01 }, | |
302 | { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f }, | |
303 | { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, | |
304 | { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x03 }, | |
305 | { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x30 }, | |
306 | { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0x8b }, | |
307 | { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, | |
308 | { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b }, | |
309 | { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 }, | |
310 | { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 }, | |
311 | { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, | |
312 | { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, | |
313 | { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, | |
314 | { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, | |
315 | { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, | |
316 | { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 }, | |
317 | { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 }, | |
318 | { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c }, | |
319 | { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, | |
320 | { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 }, | |
321 | { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, | |
322 | { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd }, | |
323 | { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, | |
324 | { TM6010_REQ07_R3F_RESET, 0x00 }, | |
325 | { 0, 0, 0 } | |
326 | }; | |
327 | ||
328 | static struct tm6000_std_settings svideo_stds[] = { | |
329 | { .id = V4L2_STD_PAL_M, .common = svideo_pal_m, }, | |
330 | { .id = V4L2_STD_PAL_Nc, .common = svideo_pal_nc, }, | |
331 | { .id = V4L2_STD_PAL, .common = svideo_pal, }, | |
332 | { .id = V4L2_STD_SECAM, .common = svideo_secam, }, | |
333 | { .id = V4L2_STD_NTSC, .common = svideo_ntsc, }, | |
334 | }; | |
709944ea | 335 | |
0f6040e8 | 336 | static int tm6000_set_audio_std(struct tm6000_core *dev) |
709944ea | 337 | { |
421d1b70 | 338 | uint8_t areg_02 = 0x04; /* GC1 Fixed gain 0dB */ |
886a3c0b | 339 | uint8_t areg_05 = 0x01; /* Auto 4.5 = M Japan, Auto 6.5 = DK */ |
421d1b70 | 340 | uint8_t areg_06 = 0x02; /* Auto de-emphasis, mannual channel mode */ |
421d1b70 | 341 | |
8aff8ba9 DB |
342 | if (dev->radio) { |
343 | tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x00); | |
344 | tm6000_set_reg(dev, TM6010_REQ08_R02_A_FIX_GAIN_CTRL, 0x04); | |
345 | tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00); | |
346 | tm6000_set_reg(dev, TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0x80); | |
347 | tm6000_set_reg(dev, TM6010_REQ08_R05_A_STANDARD_MOD, 0x0c); | |
886a3c0b SR |
348 | /* set mono or stereo */ |
349 | if (dev->amode == V4L2_TUNER_MODE_MONO) | |
350 | tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x00); | |
351 | else if (dev->amode == V4L2_TUNER_MODE_STEREO) | |
352 | tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x02); | |
8aff8ba9 DB |
353 | tm6000_set_reg(dev, TM6010_REQ08_R09_A_MAIN_VOL, 0x18); |
354 | tm6000_set_reg(dev, TM6010_REQ08_R0C_A_ASD_THRES2, 0x0a); | |
355 | tm6000_set_reg(dev, TM6010_REQ08_R0D_A_AMD_THRES, 0x40); | |
886a3c0b | 356 | tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe); |
8aff8ba9 DB |
357 | tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13); |
358 | tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80); | |
f009a946 | 359 | tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0xff); |
8aff8ba9 DB |
360 | return 0; |
361 | } | |
362 | ||
32f6f3ac MCC |
363 | /* |
364 | * STD/MN shouldn't be affected by tm6010_a_mode, as there's just one | |
365 | * audio standard for each V4L2_STD type. | |
366 | */ | |
367 | if ((dev->norm & V4L2_STD_NTSC) == V4L2_STD_NTSC_M_KR) { | |
368 | areg_05 |= 0x04; | |
369 | } else if ((dev->norm & V4L2_STD_NTSC) == V4L2_STD_NTSC_M_JP) { | |
370 | areg_05 |= 0x43; | |
371 | } else if (dev->norm & V4L2_STD_MN) { | |
372 | areg_05 |= 0x22; | |
373 | } else switch (tm6010_a_mode) { | |
886a3c0b SR |
374 | /* auto */ |
375 | case 0: | |
32f6f3ac | 376 | if ((dev->norm & V4L2_STD_SECAM) == V4L2_STD_SECAM_L) |
886a3c0b | 377 | areg_05 |= 0x00; |
32f6f3ac | 378 | else /* Other PAL/SECAM standards */ |
886a3c0b | 379 | areg_05 |= 0x10; |
421d1b70 | 380 | break; |
886a3c0b SR |
381 | /* A2 */ |
382 | case 1: | |
32f6f3ac | 383 | if (dev->norm & V4L2_STD_DK) |
886a3c0b | 384 | areg_05 = 0x09; |
32f6f3ac MCC |
385 | else |
386 | areg_05 = 0x05; | |
421d1b70 | 387 | break; |
886a3c0b SR |
388 | /* NICAM */ |
389 | case 2: | |
32f6f3ac | 390 | if (dev->norm & V4L2_STD_DK) { |
886a3c0b | 391 | areg_05 = 0x06; |
32f6f3ac | 392 | } else if (dev->norm & V4L2_STD_PAL_I) { |
886a3c0b | 393 | areg_05 = 0x08; |
32f6f3ac | 394 | } else if (dev->norm & V4L2_STD_SECAM_L) { |
886a3c0b SR |
395 | areg_05 = 0x0a; |
396 | areg_02 = 0x02; | |
32f6f3ac MCC |
397 | } else { |
398 | areg_05 = 0x07; | |
886a3c0b | 399 | } |
709944ea | 400 | break; |
886a3c0b SR |
401 | /* other */ |
402 | case 3: | |
32f6f3ac | 403 | if (dev->norm & V4L2_STD_DK) { |
886a3c0b | 404 | areg_05 = 0x0b; |
32f6f3ac | 405 | } else { |
886a3c0b | 406 | areg_05 = 0x02; |
886a3c0b | 407 | } |
8aff8ba9 | 408 | break; |
709944ea | 409 | } |
421d1b70 | 410 | |
421d1b70 DB |
411 | tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x00); |
412 | tm6000_set_reg(dev, TM6010_REQ08_R02_A_FIX_GAIN_CTRL, areg_02); | |
413 | tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00); | |
414 | tm6000_set_reg(dev, TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0xa0); | |
415 | tm6000_set_reg(dev, TM6010_REQ08_R05_A_STANDARD_MOD, areg_05); | |
416 | tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, areg_06); | |
417 | tm6000_set_reg(dev, TM6010_REQ08_R07_A_LEFT_VOL, 0x00); | |
418 | tm6000_set_reg(dev, TM6010_REQ08_R08_A_RIGHT_VOL, 0x00); | |
419 | tm6000_set_reg(dev, TM6010_REQ08_R09_A_MAIN_VOL, 0x08); | |
420 | tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, 0x91); | |
421 | tm6000_set_reg(dev, TM6010_REQ08_R0B_A_ASD_THRES1, 0x20); | |
422 | tm6000_set_reg(dev, TM6010_REQ08_R0C_A_ASD_THRES2, 0x12); | |
423 | tm6000_set_reg(dev, TM6010_REQ08_R0D_A_AMD_THRES, 0x20); | |
424 | tm6000_set_reg(dev, TM6010_REQ08_R0E_A_MONO_THRES1, 0xf0); | |
425 | tm6000_set_reg(dev, TM6010_REQ08_R0F_A_MONO_THRES2, 0x80); | |
426 | tm6000_set_reg(dev, TM6010_REQ08_R10_A_MUTE_THRES1, 0xc0); | |
427 | tm6000_set_reg(dev, TM6010_REQ08_R11_A_MUTE_THRES2, 0x80); | |
428 | tm6000_set_reg(dev, TM6010_REQ08_R12_A_AGC_U, 0x12); | |
429 | tm6000_set_reg(dev, TM6010_REQ08_R13_A_AGC_ERR_T, 0xfe); | |
430 | tm6000_set_reg(dev, TM6010_REQ08_R14_A_AGC_GAIN_INIT, 0x20); | |
431 | tm6000_set_reg(dev, TM6010_REQ08_R15_A_AGC_STEP_THR, 0x14); | |
432 | tm6000_set_reg(dev, TM6010_REQ08_R16_A_AGC_GAIN_MAX, 0xfe); | |
433 | tm6000_set_reg(dev, TM6010_REQ08_R17_A_AGC_GAIN_MIN, 0x01); | |
434 | tm6000_set_reg(dev, TM6010_REQ08_R18_A_TR_CTRL, 0xa0); | |
435 | tm6000_set_reg(dev, TM6010_REQ08_R19_A_FH_2FH_GAIN, 0x32); | |
436 | tm6000_set_reg(dev, TM6010_REQ08_R1A_A_NICAM_SER_MAX, 0x64); | |
437 | tm6000_set_reg(dev, TM6010_REQ08_R1B_A_NICAM_SER_MIN, 0x20); | |
438 | tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1c, 0x00); | |
439 | tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1d, 0x00); | |
440 | tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13); | |
441 | tm6000_set_reg(dev, TM6010_REQ08_R1F_A_TEST_INTF_SEL, 0x00); | |
442 | tm6000_set_reg(dev, TM6010_REQ08_R20_A_TEST_PIN_SEL, 0x00); | |
421d1b70 DB |
443 | tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80); |
444 | ||
709944ea MCC |
445 | return 0; |
446 | } | |
447 | ||
5200401a MCC |
448 | void tm6000_get_std_res(struct tm6000_core *dev) |
449 | { | |
450 | /* Currently, those are the only supported resoltions */ | |
52e0a72a | 451 | if (dev->norm & V4L2_STD_525_60) |
5200401a | 452 | dev->height = 480; |
52e0a72a | 453 | else |
5200401a | 454 | dev->height = 576; |
52e0a72a | 455 | |
5200401a MCC |
456 | dev->width = 720; |
457 | } | |
458 | ||
c0fa65ff | 459 | static int tm6000_load_std(struct tm6000_core *dev, struct tm6000_reg_settings *set) |
5200401a MCC |
460 | { |
461 | int i, rc; | |
462 | ||
463 | /* Load board's initialization table */ | |
c0fa65ff | 464 | for (i = 0; set[i].req; i++) { |
5200401a MCC |
465 | rc = tm6000_set_reg(dev, set[i].req, set[i].reg, set[i].value); |
466 | if (rc < 0) { | |
467 | printk(KERN_ERR "Error %i while setting " | |
468 | "req %d, reg %d to value %d\n", | |
469 | rc, set[i].req, set[i].reg, set[i].value); | |
470 | return rc; | |
471 | } | |
472 | } | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
0f6040e8 | 477 | int tm6000_set_standard(struct tm6000_core *dev) |
5200401a | 478 | { |
3fd02b44 | 479 | struct tm6000_input *input; |
5200401a | 480 | int i, rc = 0; |
0f6040e8 SR |
481 | u8 reg_07_fe = 0x8a; |
482 | u8 reg_08_f1 = 0xfc; | |
483 | u8 reg_08_e2 = 0xf0; | |
484 | u8 reg_08_e6 = 0x0f; | |
5200401a | 485 | |
5200401a MCC |
486 | tm6000_get_std_res(dev); |
487 | ||
3fd02b44 TR |
488 | if (!dev->radio) |
489 | input = &dev->vinput[dev->input]; | |
490 | else | |
491 | input = &dev->rinput; | |
0f6040e8 SR |
492 | |
493 | if (dev->dev_type == TM6010) { | |
3fd02b44 | 494 | switch (input->vmux) { |
0f6040e8 SR |
495 | case TM6000_VMUX_VIDEO_A: |
496 | tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4); | |
497 | tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1); | |
498 | tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0); | |
499 | tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2); | |
500 | tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe8); | |
501 | reg_07_fe |= 0x01; | |
502 | break; | |
503 | case TM6000_VMUX_VIDEO_B: | |
504 | tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8); | |
505 | tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1); | |
506 | tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0); | |
507 | tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2); | |
508 | tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe8); | |
509 | reg_07_fe |= 0x01; | |
510 | break; | |
511 | case TM6000_VMUX_VIDEO_AB: | |
512 | tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc); | |
513 | tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8); | |
514 | reg_08_e6 = 0x00; | |
515 | tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2); | |
516 | tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0); | |
517 | tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2); | |
518 | tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe0); | |
519 | break; | |
520 | default: | |
521 | break; | |
5200401a | 522 | } |
3fd02b44 | 523 | switch (input->amux) { |
0f6040e8 SR |
524 | case TM6000_AMUX_ADC1: |
525 | tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, | |
526 | 0x00, 0x0f); | |
32f6f3ac MCC |
527 | /* Mux overflow workaround */ |
528 | tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL, | |
529 | 0x10, 0xf0); | |
0f6040e8 SR |
530 | break; |
531 | case TM6000_AMUX_ADC2: | |
532 | tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, | |
533 | 0x08, 0x0f); | |
32f6f3ac MCC |
534 | /* Mux overflow workaround */ |
535 | tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL, | |
536 | 0x10, 0xf0); | |
0f6040e8 SR |
537 | break; |
538 | case TM6000_AMUX_SIF1: | |
539 | reg_08_e2 |= 0x02; | |
540 | reg_08_e6 = 0x08; | |
541 | reg_07_fe |= 0x40; | |
542 | reg_08_f1 |= 0x02; | |
543 | tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3); | |
544 | tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, | |
545 | 0x02, 0x0f); | |
32f6f3ac MCC |
546 | /* Mux overflow workaround */ |
547 | tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL, | |
548 | 0x30, 0xf0); | |
0f6040e8 SR |
549 | break; |
550 | case TM6000_AMUX_SIF2: | |
551 | reg_08_e2 |= 0x02; | |
552 | reg_08_e6 = 0x08; | |
553 | reg_07_fe |= 0x40; | |
554 | reg_08_f1 |= 0x02; | |
555 | tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf7); | |
556 | tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, | |
557 | 0x02, 0x0f); | |
32f6f3ac MCC |
558 | /* Mux overflow workaround */ |
559 | tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL, | |
560 | 0x30, 0xf0); | |
0f6040e8 SR |
561 | break; |
562 | default: | |
563 | break; | |
564 | } | |
565 | tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, reg_08_e2); | |
566 | tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, reg_08_e6); | |
567 | tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, reg_08_f1); | |
568 | tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, reg_07_fe); | |
569 | } else { | |
3fd02b44 | 570 | switch (input->vmux) { |
0f6040e8 SR |
571 | case TM6000_VMUX_VIDEO_A: |
572 | tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10); | |
573 | tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00); | |
574 | tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x0f); | |
575 | tm6000_set_reg(dev, | |
3fd02b44 | 576 | REQ_03_SET_GET_MCU_PIN, input->v_gpio, 0); |
0f6040e8 SR |
577 | break; |
578 | case TM6000_VMUX_VIDEO_B: | |
579 | tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x00); | |
580 | tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00); | |
581 | tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x0f); | |
582 | tm6000_set_reg(dev, | |
3fd02b44 | 583 | REQ_03_SET_GET_MCU_PIN, input->v_gpio, 0); |
0f6040e8 SR |
584 | break; |
585 | case TM6000_VMUX_VIDEO_AB: | |
586 | tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10); | |
587 | tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x10); | |
588 | tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x00); | |
589 | tm6000_set_reg(dev, | |
3fd02b44 | 590 | REQ_03_SET_GET_MCU_PIN, input->v_gpio, 1); |
0f6040e8 SR |
591 | break; |
592 | default: | |
593 | break; | |
594 | } | |
3fd02b44 | 595 | switch (input->amux) { |
0f6040e8 SR |
596 | case TM6000_AMUX_ADC1: |
597 | tm6000_set_reg_mask(dev, | |
598 | TM6000_REQ07_REB_VADC_AADC_MODE, 0x00, 0x0f); | |
599 | break; | |
600 | case TM6000_AMUX_ADC2: | |
601 | tm6000_set_reg_mask(dev, | |
602 | TM6000_REQ07_REB_VADC_AADC_MODE, 0x04, 0x0f); | |
603 | break; | |
604 | default: | |
605 | break; | |
606 | } | |
607 | } | |
3fd02b44 | 608 | if (input->type == TM6000_INPUT_SVIDEO) { |
5200401a | 609 | for (i = 0; i < ARRAY_SIZE(svideo_stds); i++) { |
0f6040e8 | 610 | if (dev->norm & svideo_stds[i].id) { |
c0fa65ff | 611 | rc = tm6000_load_std(dev, svideo_stds[i].common); |
5200401a MCC |
612 | goto ret; |
613 | } | |
614 | } | |
615 | return -EINVAL; | |
0f6040e8 | 616 | } else { |
5200401a | 617 | for (i = 0; i < ARRAY_SIZE(composite_stds); i++) { |
0f6040e8 | 618 | if (dev->norm & composite_stds[i].id) { |
c0fa65ff | 619 | rc = tm6000_load_std(dev, composite_stds[i].common); |
5200401a MCC |
620 | goto ret; |
621 | } | |
622 | } | |
623 | return -EINVAL; | |
624 | } | |
625 | ||
626 | ret: | |
627 | if (rc < 0) | |
628 | return rc; | |
629 | ||
0f6040e8 | 630 | if ((dev->dev_type == TM6010) && |
3fd02b44 TR |
631 | ((input->amux == TM6000_AMUX_SIF1) || |
632 | (input->amux == TM6000_AMUX_SIF2))) | |
0f6040e8 SR |
633 | tm6000_set_audio_std(dev); |
634 | ||
5200401a MCC |
635 | msleep(40); |
636 | ||
637 | return 0; | |
638 | } |