Commit | Line | Data |
---|---|---|
1c1e45d1 HV |
1 | /* |
2 | * cx18 ADEC audio functions | |
3 | * | |
4 | * Derived from cx25840-core.c | |
5 | * | |
6 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> | |
1ed9dcc8 | 7 | * Copyright (C) 2008 Andy Walls <awalls@radix.net> |
1c1e45d1 HV |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version 2 | |
12 | * of the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
22 | * 02110-1301, USA. | |
23 | */ | |
24 | ||
1a267046 | 25 | #include <media/v4l2-chip-ident.h> |
1c1e45d1 | 26 | #include "cx18-driver.h" |
b1526421 | 27 | #include "cx18-io.h" |
1a267046 | 28 | #include "cx18-cards.h" |
1c1e45d1 HV |
29 | |
30 | int cx18_av_write(struct cx18 *cx, u16 addr, u8 value) | |
31 | { | |
b1526421 | 32 | u32 reg = 0xc40000 + (addr & ~3); |
1c1e45d1 HV |
33 | u32 mask = 0xff; |
34 | int shift = (addr & 3) * 8; | |
b1526421 | 35 | u32 x = cx18_read_reg(cx, reg); |
1c1e45d1 HV |
36 | |
37 | x = (x & ~(mask << shift)) | ((u32)value << shift); | |
b1526421 | 38 | cx18_write_reg(cx, x, reg); |
1c1e45d1 HV |
39 | return 0; |
40 | } | |
41 | ||
ced07371 AW |
42 | int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask) |
43 | { | |
44 | u32 reg = 0xc40000 + (addr & ~3); | |
45 | int shift = (addr & 3) * 8; | |
46 | u32 x = cx18_read_reg(cx, reg); | |
47 | ||
48 | x = (x & ~((u32)0xff << shift)) | ((u32)value << shift); | |
49 | cx18_write_reg_expect(cx, x, reg, | |
50 | ((u32)eval << shift), ((u32)mask << shift)); | |
51 | return 0; | |
52 | } | |
53 | ||
1c1e45d1 HV |
54 | int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value) |
55 | { | |
b1526421 | 56 | cx18_write_reg(cx, value, 0xc40000 + addr); |
1c1e45d1 HV |
57 | return 0; |
58 | } | |
59 | ||
ced07371 AW |
60 | int |
61 | cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask) | |
62 | { | |
63 | cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask); | |
64 | return 0; | |
65 | } | |
66 | ||
d267d851 AW |
67 | int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value) |
68 | { | |
69 | cx18_write_reg_noretry(cx, value, 0xc40000 + addr); | |
70 | return 0; | |
71 | } | |
72 | ||
1c1e45d1 HV |
73 | u8 cx18_av_read(struct cx18 *cx, u16 addr) |
74 | { | |
b1526421 | 75 | u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3)); |
1c1e45d1 HV |
76 | int shift = (addr & 3) * 8; |
77 | ||
78 | return (x >> shift) & 0xff; | |
79 | } | |
80 | ||
81 | u32 cx18_av_read4(struct cx18 *cx, u16 addr) | |
82 | { | |
b1526421 | 83 | return cx18_read_reg(cx, 0xc40000 + addr); |
1c1e45d1 HV |
84 | } |
85 | ||
86 | int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask, | |
87 | u8 or_value) | |
88 | { | |
89 | return cx18_av_write(cx, addr, | |
90 | (cx18_av_read(cx, addr) & and_mask) | | |
91 | or_value); | |
92 | } | |
93 | ||
94 | int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask, | |
95 | u32 or_value) | |
96 | { | |
97 | return cx18_av_write4(cx, addr, | |
98 | (cx18_av_read4(cx, addr) & and_mask) | | |
99 | or_value); | |
100 | } | |
101 | ||
f4672dff | 102 | static int cx18_av_init(struct v4l2_subdev *sd, u32 val) |
1c1e45d1 | 103 | { |
f4672dff AW |
104 | struct cx18 *cx = v4l2_get_subdevdata(sd); |
105 | ||
106 | /* | |
107 | * The crystal freq used in calculations in this driver will be | |
108 | * 28.636360 MHz. | |
109 | * Aim to run the PLLs' VCOs near 400 MHz to minimze errors. | |
110 | */ | |
111 | ||
112 | /* | |
113 | * VDCLK Integer = 0x0f, Post Divider = 0x04 | |
114 | * AIMCLK Integer = 0x0e, Post Divider = 0x16 | |
115 | */ | |
116 | cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f); | |
117 | ||
118 | /* VDCLK Fraction = 0x2be2fe */ | |
119 | /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */ | |
120 | cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe); | |
121 | ||
122 | /* AIMCLK Fraction = 0x05227ad */ | |
123 | /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/ | |
124 | cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad); | |
125 | ||
126 | /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */ | |
127 | cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56); | |
128 | return 0; | |
129 | } | |
130 | ||
131 | static void cx18_av_initialize(struct v4l2_subdev *sd) | |
132 | { | |
133 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
134 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1c1e45d1 HV |
135 | u32 v; |
136 | ||
137 | cx18_av_loadfw(cx); | |
138 | /* Stop 8051 code execution */ | |
ced07371 AW |
139 | cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000, |
140 | 0x03000000, 0x13000000); | |
1c1e45d1 HV |
141 | |
142 | /* initallize the PLL by toggling sleep bit */ | |
143 | v = cx18_av_read4(cx, CXADEC_HOST_REG1); | |
ced07371 AW |
144 | /* enable sleep mode - register appears to be read only... */ |
145 | cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe); | |
1c1e45d1 | 146 | /* disable sleep mode */ |
ced07371 AW |
147 | cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe, |
148 | v & 0xfffe, 0xffff); | |
1c1e45d1 HV |
149 | |
150 | /* initialize DLLs */ | |
151 | v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF; | |
152 | /* disable FLD */ | |
153 | cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v); | |
154 | /* enable FLD */ | |
155 | cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100); | |
156 | ||
157 | v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF; | |
158 | /* disable FLD */ | |
159 | cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v); | |
160 | /* enable FLD */ | |
161 | cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100); | |
162 | ||
163 | /* set analog bias currents. Set Vreg to 1.20V. */ | |
164 | cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802); | |
165 | ||
166 | v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1; | |
167 | /* enable TUNE_FIL_RST */ | |
ced07371 | 168 | cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F); |
1c1e45d1 | 169 | /* disable TUNE_FIL_RST */ |
ced07371 AW |
170 | cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, |
171 | v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F); | |
1c1e45d1 HV |
172 | |
173 | /* enable 656 output */ | |
174 | cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00); | |
175 | ||
176 | /* video output drive strength */ | |
177 | cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2); | |
178 | ||
179 | /* reset video */ | |
180 | cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000); | |
181 | cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0); | |
182 | ||
f4672dff AW |
183 | /* |
184 | * Disable Video Auto-config of the Analog Front End and Video PLL. | |
185 | * | |
186 | * Since we only use BT.656 pixel mode, which works for both 525 and 625 | |
187 | * line systems, it's just easier for us to set registers | |
188 | * 0x102 (CXADEC_CHIP_CTRL), 0x104-0x106 (CXADEC_AFE_CTRL), | |
189 | * 0x108-0x109 (CXADEC_PLL_CTRL1), and 0x10c-0x10f (CXADEC_VID_PLL_FRAC) | |
190 | * ourselves, than to run around cleaning up after the auto-config. | |
191 | * | |
192 | * (Note: my CX23418 chip doesn't seem to let the ACFG_DIS bit | |
193 | * get set to 1, but OTOH, it doesn't seem to do AFE and VID PLL | |
194 | * autoconfig either.) | |
195 | * | |
196 | * As a default, also turn off Dual mode for ADC2 and set ADC2 to CH3. | |
197 | */ | |
198 | cx18_av_and_or4(cx, CXADEC_CHIP_CTRL, 0xFFFBFFFF, 0x00120000); | |
199 | ||
200 | /* Setup the Video and and Aux/Audio PLLs */ | |
201 | cx18_av_init(sd, 0); | |
202 | ||
1c1e45d1 HV |
203 | /* set video to auto-detect */ |
204 | /* Clear bits 11-12 to enable slow locking mode. Set autodetect mode */ | |
205 | /* set the comb notch = 1 */ | |
206 | cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800); | |
207 | ||
208 | /* Enable wtw_en in CRUSH_CTRL (Set bit 22) */ | |
209 | /* Enable maj_sel in CRUSH_CTRL (Set bit 20) */ | |
210 | cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000); | |
211 | ||
212 | /* Set VGA_TRACK_RANGE to 0x20 */ | |
213 | cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000); | |
214 | ||
302df970 AW |
215 | /* |
216 | * Initial VBI setup | |
217 | * VIP-1.1, 10 bit mode, enable Raw, disable sliced, | |
812b1f9d AW |
218 | * don't clamp raw samples when codes are in use, 1 byte user D-words, |
219 | * IDID0 has line #, RP code V bit transition on VBLANK, data during | |
302df970 AW |
220 | * blanking intervals |
221 | */ | |
812b1f9d | 222 | cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e); |
1c1e45d1 HV |
223 | |
224 | /* Set the video input. | |
225 | The setting in MODE_CTRL gets lost when we do the above setup */ | |
226 | /* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */ | |
227 | /* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */ | |
228 | ||
f4672dff AW |
229 | /* |
230 | * Analog Front End (AFE) | |
231 | * Default to luma on ch1/ADC1, chroma on ch2/ADC2, SIF on ch3/ADC2 | |
232 | * bypass_ch[1-3] use filter | |
233 | * droop_comp_ch[1-3] disable | |
234 | * clamp_en_ch[1-3] disable | |
235 | * aud_in_sel ADC2 | |
236 | * luma_in_sel ADC1 | |
237 | * chroma_in_sel ADC2 | |
238 | * clamp_sel_ch[2-3] midcode | |
239 | * clamp_sel_ch1 video decoder | |
240 | * vga_sel_ch3 audio decoder | |
241 | * vga_sel_ch[1-2] video decoder | |
242 | * half_bw_ch[1-3] disable | |
243 | * +12db_ch[1-3] disable | |
244 | */ | |
245 | cx18_av_and_or4(cx, CXADEC_AFE_CTRL, 0xFF000000, 0x00005D00); | |
1c1e45d1 HV |
246 | |
247 | /* if(dwEnable && dw3DCombAvailable) { */ | |
248 | /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */ | |
249 | /* } else { */ | |
250 | /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */ | |
251 | /* } */ | |
252 | cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F); | |
ca130eef HV |
253 | state->default_volume = 228 - cx18_av_read(cx, 0x8d4); |
254 | state->default_volume = ((state->default_volume / 2) + 23) << 9; | |
1c1e45d1 HV |
255 | } |
256 | ||
1a267046 AW |
257 | static int cx18_av_reset(struct v4l2_subdev *sd, u32 val) |
258 | { | |
f4672dff | 259 | cx18_av_initialize(sd); |
cc26b076 HV |
260 | return 0; |
261 | } | |
fa3e7036 | 262 | |
cc26b076 HV |
263 | static int cx18_av_load_fw(struct v4l2_subdev *sd) |
264 | { | |
265 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
cc26b076 HV |
266 | |
267 | if (!state->is_initialized) { | |
268 | /* initialize on first use */ | |
269 | state->is_initialized = 1; | |
f4672dff | 270 | cx18_av_initialize(sd); |
1a267046 AW |
271 | } |
272 | return 0; | |
273 | } | |
1c1e45d1 | 274 | |
03b52c36 HV |
275 | void cx18_av_std_setup(struct cx18 *cx) |
276 | { | |
277 | struct cx18_av_state *state = &cx->av_state; | |
6246d4e1 | 278 | struct v4l2_subdev *sd = &state->sd; |
03b52c36 HV |
279 | v4l2_std_id std = state->std; |
280 | int hblank, hactive, burst, vblank, vactive, sc; | |
281 | int vblank656, src_decimation; | |
282 | int luma_lpf, uv_lpf, comb; | |
283 | u32 pll_int, pll_frac, pll_post; | |
284 | ||
285 | /* datasheet startup, step 8d */ | |
286 | if (std & ~V4L2_STD_NTSC) | |
287 | cx18_av_write(cx, 0x49f, 0x11); | |
288 | else | |
289 | cx18_av_write(cx, 0x49f, 0x14); | |
290 | ||
5ab74052 AW |
291 | /* |
292 | * Note: At the end of a field, there are 3 sets of half line duration | |
293 | * (double horizontal rate) pulses: | |
294 | * | |
295 | * 5 (625) or 6 (525) half-lines to blank for the vertical retrace | |
296 | * 5 (625) or 6 (525) vertical sync pulses of half line duration | |
297 | * 5 (625) or 6 (525) half-lines of equalization pulses | |
298 | */ | |
03b52c36 | 299 | if (std & V4L2_STD_625_50) { |
5ab74052 AW |
300 | /* |
301 | * The following relationships of half line counts should hold: | |
302 | * 625 = vblank656 + vactive + postvactive | |
303 | * 10 = vblank656 - vblank = vsync pulses + equalization pulses | |
304 | * | |
305 | * vblank656: half lines after line 625/mid-313 of blanked video | |
306 | * vblank: half lines, after line 5/317, of blanked video | |
307 | * vactive: half lines of active video | |
308 | * postvactive: 5 half lines after the end of active video | |
309 | * | |
310 | * As far as I can tell: | |
311 | * vblank656 starts counting from the falling edge of the first | |
312 | * vsync pulse (start of line 1 or mid-313) | |
313 | * vblank starts counting from the after the 5 vsync pulses and | |
314 | * 5 or 4 equalization pulses (start of line 6 or 318) | |
315 | * | |
316 | * For 625 line systems the driver will extract VBI information | |
317 | * from lines 6-23 and lines 318-335 (but the slicer can only | |
318 | * handle 17 lines, not the 18 in the vblank region). | |
319 | */ | |
320 | vblank656 = 46; /* lines 1 - 23 & 313 - 335 */ | |
321 | vblank = 36; /* lines 6 - 23 & 318 - 335 */ | |
322 | vactive = 574; /* lines 24 - 310 & 336 - 622 */ | |
323 | ||
324 | /* | |
325 | * For a 13.5 Mpps clock and 15,625 Hz line rate, a line is | |
326 | * is 864 pixels = 720 active + 144 blanking. ITU-R BT.601 | |
327 | * specifies 12 luma clock periods or ~ 0.9 * 13.5 Mpps after | |
328 | * the end of active video to start a horizontal line, so that | |
329 | * leaves 132 pixels of hblank to ignore. | |
330 | */ | |
03b52c36 HV |
331 | hblank = 132; |
332 | hactive = 720; | |
03b52c36 | 333 | |
5ab74052 | 334 | burst = 93; |
03b52c36 | 335 | luma_lpf = 2; |
5ab74052 | 336 | src_decimation = 0x21f; |
03b52c36 HV |
337 | if (std & V4L2_STD_PAL) { |
338 | uv_lpf = 1; | |
339 | comb = 0x20; | |
340 | sc = 688739; | |
341 | } else if (std == V4L2_STD_PAL_Nc) { | |
342 | uv_lpf = 1; | |
343 | comb = 0x20; | |
344 | sc = 556453; | |
345 | } else { /* SECAM */ | |
346 | uv_lpf = 0; | |
347 | comb = 0; | |
348 | sc = 672351; | |
349 | } | |
350 | } else { | |
812b1f9d AW |
351 | /* |
352 | * The following relationships of half line counts should hold: | |
5ab74052 AW |
353 | * 525 = prevsync + vblank656 + vactive |
354 | * 12 = vblank656 - vblank = vsync pulses + equalization pulses | |
812b1f9d | 355 | * |
5ab74052 | 356 | * prevsync: 6 half-lines before the vsync pulses |
af7c58b1 AW |
357 | * vblank656: half lines, after line 3/mid-266, of blanked video |
358 | * vblank: half lines, after line 9/272, of blanked video | |
5ab74052 | 359 | * vactive: half lines of active video |
812b1f9d | 360 | * |
af7c58b1 | 361 | * As far as I can tell: |
812b1f9d | 362 | * vblank656 starts counting from the falling edge of the first |
af7c58b1 | 363 | * vsync pulse (start of line 4 or mid-266) |
812b1f9d | 364 | * vblank starts counting from the after the 6 vsync pulses and |
af7c58b1 | 365 | * 6 or 5 equalization pulses (start of line 10 or 272) |
812b1f9d AW |
366 | * |
367 | * For 525 line systems the driver will extract VBI information | |
af7c58b1 | 368 | * from lines 10-21 and lines 273-284. |
812b1f9d | 369 | */ |
af7c58b1 AW |
370 | vblank656 = 38; /* lines 4 - 22 & 266 - 284 */ |
371 | vblank = 26; /* lines 10 - 22 & 272 - 284 */ | |
372 | vactive = 481; /* lines 23 - 263 & 285 - 525 */ | |
812b1f9d | 373 | |
af7c58b1 AW |
374 | /* |
375 | * For a 13.5 Mpps clock and 15,734.26 Hz line rate, a line is | |
376 | * is 858 pixels = 720 active + 138 blanking. The Hsync leading | |
377 | * edge should happen 1.2 us * 13.5 Mpps ~= 16 pixels after the | |
378 | * end of active video, leaving 122 pixels of hblank to ignore | |
379 | * before active video starts. | |
380 | */ | |
03b52c36 HV |
381 | hactive = 720; |
382 | hblank = 122; | |
03b52c36 HV |
383 | luma_lpf = 1; |
384 | uv_lpf = 1; | |
03b52c36 HV |
385 | |
386 | src_decimation = 0x21f; | |
387 | if (std == V4L2_STD_PAL_60) { | |
388 | burst = 0x5b; | |
389 | luma_lpf = 2; | |
390 | comb = 0x20; | |
391 | sc = 688739; | |
392 | } else if (std == V4L2_STD_PAL_M) { | |
393 | burst = 0x61; | |
394 | comb = 0x20; | |
395 | sc = 555452; | |
396 | } else { | |
397 | burst = 0x5b; | |
398 | comb = 0x66; | |
399 | sc = 556063; | |
400 | } | |
401 | } | |
402 | ||
403 | /* DEBUG: Displays configured PLL frequency */ | |
404 | pll_int = cx18_av_read(cx, 0x108); | |
405 | pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff; | |
406 | pll_post = cx18_av_read(cx, 0x109); | |
6246d4e1 AW |
407 | CX18_DEBUG_INFO_DEV(sd, "PLL regs = int: %u, frac: %u, post: %u\n", |
408 | pll_int, pll_frac, pll_post); | |
03b52c36 HV |
409 | |
410 | if (pll_post) { | |
f4167342 | 411 | int fin, fsc, pll; |
03b52c36 | 412 | |
55d81aa5 | 413 | pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25; |
03b52c36 | 414 | pll /= pll_post; |
6246d4e1 AW |
415 | CX18_DEBUG_INFO_DEV(sd, "PLL = %d.%06d MHz\n", |
416 | pll / 1000000, pll % 1000000); | |
417 | CX18_DEBUG_INFO_DEV(sd, "PLL/8 = %d.%06d MHz\n", | |
418 | pll / 8000000, (pll / 8) % 1000000); | |
03b52c36 HV |
419 | |
420 | fin = ((u64)src_decimation * pll) >> 12; | |
6246d4e1 AW |
421 | CX18_DEBUG_INFO_DEV(sd, "ADC Sampling freq = %d.%06d MHz\n", |
422 | fin / 1000000, fin % 1000000); | |
03b52c36 HV |
423 | |
424 | fsc = (((u64)sc) * pll) >> 24L; | |
6246d4e1 AW |
425 | CX18_DEBUG_INFO_DEV(sd, |
426 | "Chroma sub-carrier freq = %d.%06d MHz\n", | |
427 | fsc / 1000000, fsc % 1000000); | |
428 | ||
429 | CX18_DEBUG_INFO_DEV(sd, "hblank %i, hactive %i, vblank %i, " | |
430 | "vactive %i, vblank656 %i, src_dec %i, " | |
431 | "burst 0x%02x, luma_lpf %i, uv_lpf %i, " | |
432 | "comb 0x%02x, sc 0x%06x\n", | |
433 | hblank, hactive, vblank, vactive, vblank656, | |
434 | src_decimation, burst, luma_lpf, uv_lpf, | |
435 | comb, sc); | |
03b52c36 HV |
436 | } |
437 | ||
438 | /* Sets horizontal blanking delay and active lines */ | |
439 | cx18_av_write(cx, 0x470, hblank); | |
440 | cx18_av_write(cx, 0x471, 0xff & (((hblank >> 8) & 0x3) | | |
441 | (hactive << 4))); | |
442 | cx18_av_write(cx, 0x472, hactive >> 4); | |
443 | ||
444 | /* Sets burst gate delay */ | |
445 | cx18_av_write(cx, 0x473, burst); | |
446 | ||
447 | /* Sets vertical blanking delay and active duration */ | |
448 | cx18_av_write(cx, 0x474, vblank); | |
449 | cx18_av_write(cx, 0x475, 0xff & (((vblank >> 8) & 0x3) | | |
450 | (vactive << 4))); | |
451 | cx18_av_write(cx, 0x476, vactive >> 4); | |
452 | cx18_av_write(cx, 0x477, vblank656); | |
453 | ||
454 | /* Sets src decimation rate */ | |
455 | cx18_av_write(cx, 0x478, 0xff & src_decimation); | |
456 | cx18_av_write(cx, 0x479, 0xff & (src_decimation >> 8)); | |
457 | ||
458 | /* Sets Luma and UV Low pass filters */ | |
459 | cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30)); | |
460 | ||
461 | /* Enables comb filters */ | |
462 | cx18_av_write(cx, 0x47b, comb); | |
463 | ||
464 | /* Sets SC Step*/ | |
465 | cx18_av_write(cx, 0x47c, sc); | |
466 | cx18_av_write(cx, 0x47d, 0xff & sc >> 8); | |
467 | cx18_av_write(cx, 0x47e, 0xff & sc >> 16); | |
468 | ||
03b52c36 | 469 | if (std & V4L2_STD_625_50) { |
812b1f9d AW |
470 | state->slicer_line_delay = 1; |
471 | state->slicer_line_offset = (6 + state->slicer_line_delay - 2); | |
03b52c36 | 472 | } else { |
812b1f9d AW |
473 | state->slicer_line_delay = 0; |
474 | state->slicer_line_offset = (10 + state->slicer_line_delay - 2); | |
03b52c36 | 475 | } |
812b1f9d | 476 | cx18_av_write(cx, 0x47f, state->slicer_line_delay); |
03b52c36 HV |
477 | } |
478 | ||
1c1e45d1 HV |
479 | static void input_change(struct cx18 *cx) |
480 | { | |
481 | struct cx18_av_state *state = &cx->av_state; | |
482 | v4l2_std_id std = state->std; | |
ced07371 | 483 | u8 v; |
1c1e45d1 HV |
484 | |
485 | /* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */ | |
c1738904 HV |
486 | cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11); |
487 | cx18_av_and_or(cx, 0x401, ~0x60, 0); | |
488 | cx18_av_and_or(cx, 0x401, ~0x60, 0x60); | |
1c1e45d1 HV |
489 | |
490 | if (std & V4L2_STD_525_60) { | |
491 | if (std == V4L2_STD_NTSC_M_JP) { | |
492 | /* Japan uses EIAJ audio standard */ | |
ced07371 AW |
493 | cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff); |
494 | cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f); | |
1c1e45d1 HV |
495 | } else if (std == V4L2_STD_NTSC_M_KR) { |
496 | /* South Korea uses A2 audio standard */ | |
ced07371 AW |
497 | cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff); |
498 | cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); | |
1c1e45d1 HV |
499 | } else { |
500 | /* Others use the BTSC audio standard */ | |
ced07371 AW |
501 | cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff); |
502 | cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f); | |
1c1e45d1 | 503 | } |
1c1e45d1 HV |
504 | } else if (std & V4L2_STD_PAL) { |
505 | /* Follow tuner change procedure for PAL */ | |
ced07371 AW |
506 | cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff); |
507 | cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); | |
1c1e45d1 HV |
508 | } else if (std & V4L2_STD_SECAM) { |
509 | /* Select autodetect for SECAM */ | |
ced07371 AW |
510 | cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff); |
511 | cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); | |
1c1e45d1 HV |
512 | } |
513 | ||
ced07371 AW |
514 | v = cx18_av_read(cx, 0x803); |
515 | if (v & 0x10) { | |
1c1e45d1 | 516 | /* restart audio decoder microcontroller */ |
ced07371 AW |
517 | v &= ~0x10; |
518 | cx18_av_write_expect(cx, 0x803, v, v, 0x1f); | |
519 | v |= 0x10; | |
520 | cx18_av_write_expect(cx, 0x803, v, v, 0x1f); | |
1c1e45d1 HV |
521 | } |
522 | } | |
523 | ||
1a267046 AW |
524 | static int cx18_av_s_frequency(struct v4l2_subdev *sd, |
525 | struct v4l2_frequency *freq) | |
526 | { | |
527 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
528 | input_change(cx); | |
529 | return 0; | |
530 | } | |
531 | ||
1c1e45d1 HV |
532 | static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input, |
533 | enum cx18_av_audio_input aud_input) | |
534 | { | |
535 | struct cx18_av_state *state = &cx->av_state; | |
6246d4e1 | 536 | struct v4l2_subdev *sd = &state->sd; |
f4672dff AW |
537 | |
538 | enum analog_signal_type { | |
539 | NONE, CVBS, Y, C, SIF, Pb, Pr | |
540 | } ch[3] = {NONE, NONE, NONE}; | |
541 | ||
542 | u8 afe_mux_cfg; | |
543 | u8 adc2_cfg; | |
544 | u32 afe_cfg; | |
545 | int i; | |
1c1e45d1 | 546 | |
6246d4e1 AW |
547 | CX18_DEBUG_INFO_DEV(sd, "decoder set video input %d, audio input %d\n", |
548 | vid_input, aud_input); | |
1c1e45d1 | 549 | |
f4672dff AW |
550 | if (vid_input >= CX18_AV_COMPOSITE1 && |
551 | vid_input <= CX18_AV_COMPOSITE8) { | |
552 | afe_mux_cfg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1); | |
553 | ch[0] = CVBS; | |
1c1e45d1 HV |
554 | } else { |
555 | int luma = vid_input & 0xf0; | |
556 | int chroma = vid_input & 0xf00; | |
557 | ||
558 | if ((vid_input & ~0xff0) || | |
559 | luma < CX18_AV_SVIDEO_LUMA1 || | |
45270a15 | 560 | luma > CX18_AV_SVIDEO_LUMA8 || |
1c1e45d1 HV |
561 | chroma < CX18_AV_SVIDEO_CHROMA4 || |
562 | chroma > CX18_AV_SVIDEO_CHROMA8) { | |
6246d4e1 AW |
563 | CX18_ERR_DEV(sd, "0x%04x is not a valid video input!\n", |
564 | vid_input); | |
1c1e45d1 HV |
565 | return -EINVAL; |
566 | } | |
f4672dff AW |
567 | afe_mux_cfg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4); |
568 | ch[0] = Y; | |
1c1e45d1 | 569 | if (chroma >= CX18_AV_SVIDEO_CHROMA7) { |
f4672dff AW |
570 | afe_mux_cfg &= 0x3f; |
571 | afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2; | |
572 | ch[2] = C; | |
1c1e45d1 | 573 | } else { |
f4672dff AW |
574 | afe_mux_cfg &= 0xcf; |
575 | afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4; | |
576 | ch[1] = C; | |
1c1e45d1 HV |
577 | } |
578 | } | |
f4672dff | 579 | /* TODO: LeadTek WinFast DVR3100 H & WinFast PVR2100 can do Y/Pb/Pr */ |
1c1e45d1 HV |
580 | |
581 | switch (aud_input) { | |
81cb727d HV |
582 | case CX18_AV_AUDIO_SERIAL1: |
583 | case CX18_AV_AUDIO_SERIAL2: | |
1c1e45d1 HV |
584 | /* do nothing, use serial audio input */ |
585 | break; | |
f4672dff AW |
586 | case CX18_AV_AUDIO4: |
587 | afe_mux_cfg &= ~0x30; | |
588 | ch[1] = SIF; | |
589 | break; | |
590 | case CX18_AV_AUDIO5: | |
591 | afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x10; | |
592 | ch[1] = SIF; | |
593 | break; | |
594 | case CX18_AV_AUDIO6: | |
595 | afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x20; | |
596 | ch[1] = SIF; | |
597 | break; | |
598 | case CX18_AV_AUDIO7: | |
599 | afe_mux_cfg &= ~0xc0; | |
600 | ch[2] = SIF; | |
601 | break; | |
602 | case CX18_AV_AUDIO8: | |
603 | afe_mux_cfg = (afe_mux_cfg & ~0xc0) | 0x40; | |
604 | ch[2] = SIF; | |
605 | break; | |
1c1e45d1 HV |
606 | |
607 | default: | |
6246d4e1 AW |
608 | CX18_ERR_DEV(sd, "0x%04x is not a valid audio input!\n", |
609 | aud_input); | |
1c1e45d1 HV |
610 | return -EINVAL; |
611 | } | |
612 | ||
f4672dff AW |
613 | /* Set up analog front end multiplexers */ |
614 | cx18_av_write_expect(cx, 0x103, afe_mux_cfg, afe_mux_cfg, 0xf7); | |
1c1e45d1 | 615 | /* Set INPUT_MODE to Composite (0) or S-Video (1) */ |
f4672dff | 616 | cx18_av_and_or(cx, 0x401, ~0x6, ch[0] == CVBS ? 0 : 0x02); |
ced07371 | 617 | |
1c1e45d1 | 618 | /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */ |
f4672dff AW |
619 | adc2_cfg = cx18_av_read(cx, 0x102); |
620 | if (ch[2] == NONE) | |
621 | adc2_cfg &= ~0x2; /* No sig on CH3, set ADC2 to CH2 for input */ | |
ced07371 | 622 | else |
f4672dff AW |
623 | adc2_cfg |= 0x2; /* Signal on CH3, set ADC2 to CH3 for input */ |
624 | ||
1c1e45d1 | 625 | /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */ |
f4672dff AW |
626 | if (ch[1] != NONE && ch[2] != NONE) |
627 | adc2_cfg |= 0x4; /* Set dual mode */ | |
1c1e45d1 | 628 | else |
f4672dff AW |
629 | adc2_cfg &= ~0x4; /* Clear dual mode */ |
630 | cx18_av_write_expect(cx, 0x102, adc2_cfg, adc2_cfg, 0x17); | |
631 | ||
632 | /* Configure the analog front end */ | |
633 | afe_cfg = cx18_av_read4(cx, CXADEC_AFE_CTRL); | |
634 | afe_cfg &= 0xff000000; | |
635 | afe_cfg |= 0x00005000; /* CHROMA_IN, AUD_IN: ADC2; LUMA_IN: ADC1 */ | |
636 | if (ch[1] != NONE && ch[2] != NONE) | |
637 | afe_cfg |= 0x00000030; /* half_bw_ch[2-3] since in dual mode */ | |
638 | ||
639 | for (i = 0; i < 3; i++) { | |
640 | switch (ch[i]) { | |
641 | default: | |
642 | case NONE: | |
643 | /* CLAMP_SEL = Fixed to midcode clamp level */ | |
644 | afe_cfg |= (0x00000200 << i); | |
645 | break; | |
646 | case CVBS: | |
647 | case Y: | |
648 | if (i > 0) | |
649 | afe_cfg |= 0x00002000; /* LUMA_IN_SEL: ADC2 */ | |
650 | break; | |
651 | case C: | |
652 | case Pb: | |
653 | case Pr: | |
654 | /* CLAMP_SEL = Fixed to midcode clamp level */ | |
655 | afe_cfg |= (0x00000200 << i); | |
656 | if (i == 0 && ch[i] == C) | |
657 | afe_cfg &= ~0x00001000; /* CHROMA_IN_SEL ADC1 */ | |
658 | break; | |
659 | case SIF: | |
660 | /* | |
661 | * VGA_GAIN_SEL = Audio Decoder | |
662 | * CLAMP_SEL = Fixed to midcode clamp level | |
663 | */ | |
664 | afe_cfg |= (0x00000240 << i); | |
665 | if (i == 0) | |
666 | afe_cfg &= ~0x00004000; /* AUD_IN_SEL ADC1 */ | |
667 | break; | |
668 | } | |
669 | } | |
ced07371 | 670 | |
f4672dff | 671 | cx18_av_write4(cx, CXADEC_AFE_CTRL, afe_cfg); |
1c1e45d1 HV |
672 | |
673 | state->vid_input = vid_input; | |
674 | state->aud_input = aud_input; | |
675 | cx18_av_audio_set_path(cx); | |
676 | input_change(cx); | |
677 | return 0; | |
678 | } | |
679 | ||
1a267046 | 680 | static int cx18_av_s_video_routing(struct v4l2_subdev *sd, |
5325b427 | 681 | u32 input, u32 output, u32 config) |
1a267046 AW |
682 | { |
683 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
684 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
5325b427 | 685 | return set_input(cx, input, state->aud_input); |
1a267046 | 686 | } |
1c1e45d1 | 687 | |
1a267046 | 688 | static int cx18_av_s_audio_routing(struct v4l2_subdev *sd, |
5325b427 | 689 | u32 input, u32 output, u32 config) |
1c1e45d1 | 690 | { |
1a267046 AW |
691 | struct cx18_av_state *state = to_cx18_av_state(sd); |
692 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
5325b427 | 693 | return set_input(cx, state->vid_input, input); |
1a267046 AW |
694 | } |
695 | ||
696 | static int cx18_av_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt) | |
697 | { | |
698 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
699 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
700 | u8 vpres; | |
701 | u8 mode; | |
702 | int val = 0; | |
703 | ||
704 | if (state->radio) | |
705 | return 0; | |
706 | ||
707 | vpres = cx18_av_read(cx, 0x40e) & 0x20; | |
708 | vt->signal = vpres ? 0xffff : 0x0; | |
709 | ||
710 | vt->capability |= | |
711 | V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 | | |
712 | V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP; | |
713 | ||
714 | mode = cx18_av_read(cx, 0x804); | |
715 | ||
716 | /* get rxsubchans and audmode */ | |
717 | if ((mode & 0xf) == 1) | |
718 | val |= V4L2_TUNER_SUB_STEREO; | |
719 | else | |
720 | val |= V4L2_TUNER_SUB_MONO; | |
721 | ||
722 | if (mode == 2 || mode == 4) | |
723 | val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2; | |
724 | ||
725 | if (mode & 0x10) | |
726 | val |= V4L2_TUNER_SUB_SAP; | |
727 | ||
728 | vt->rxsubchans = val; | |
729 | vt->audmode = state->audmode; | |
730 | return 0; | |
731 | } | |
732 | ||
733 | static int cx18_av_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt) | |
734 | { | |
735 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
736 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
737 | u8 v; | |
738 | ||
739 | if (state->radio) | |
740 | return 0; | |
741 | ||
742 | v = cx18_av_read(cx, 0x809); | |
743 | v &= ~0xf; | |
744 | ||
745 | switch (vt->audmode) { | |
746 | case V4L2_TUNER_MODE_MONO: | |
747 | /* mono -> mono | |
748 | stereo -> mono | |
749 | bilingual -> lang1 */ | |
750 | break; | |
751 | case V4L2_TUNER_MODE_STEREO: | |
752 | case V4L2_TUNER_MODE_LANG1: | |
753 | /* mono -> mono | |
754 | stereo -> stereo | |
755 | bilingual -> lang1 */ | |
756 | v |= 0x4; | |
757 | break; | |
758 | case V4L2_TUNER_MODE_LANG1_LANG2: | |
759 | /* mono -> mono | |
760 | stereo -> stereo | |
761 | bilingual -> lang1/lang2 */ | |
762 | v |= 0x7; | |
763 | break; | |
764 | case V4L2_TUNER_MODE_LANG2: | |
765 | /* mono -> mono | |
766 | stereo -> stereo | |
767 | bilingual -> lang2 */ | |
768 | v |= 0x1; | |
769 | break; | |
770 | default: | |
771 | return -EINVAL; | |
772 | } | |
773 | cx18_av_write_expect(cx, 0x809, v, v, 0xff); | |
774 | state->audmode = vt->audmode; | |
775 | return 0; | |
776 | } | |
777 | ||
778 | static int cx18_av_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) | |
779 | { | |
780 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
781 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
782 | ||
1c1e45d1 HV |
783 | u8 fmt = 0; /* zero is autodetect */ |
784 | u8 pal_m = 0; | |
785 | ||
1a267046 AW |
786 | if (state->radio == 0 && state->std == norm) |
787 | return 0; | |
788 | ||
789 | state->radio = 0; | |
790 | state->std = norm; | |
791 | ||
1c1e45d1 HV |
792 | /* First tests should be against specific std */ |
793 | if (state->std == V4L2_STD_NTSC_M_JP) { | |
794 | fmt = 0x2; | |
795 | } else if (state->std == V4L2_STD_NTSC_443) { | |
796 | fmt = 0x3; | |
797 | } else if (state->std == V4L2_STD_PAL_M) { | |
798 | pal_m = 1; | |
799 | fmt = 0x5; | |
800 | } else if (state->std == V4L2_STD_PAL_N) { | |
801 | fmt = 0x6; | |
802 | } else if (state->std == V4L2_STD_PAL_Nc) { | |
803 | fmt = 0x7; | |
804 | } else if (state->std == V4L2_STD_PAL_60) { | |
805 | fmt = 0x8; | |
806 | } else { | |
807 | /* Then, test against generic ones */ | |
808 | if (state->std & V4L2_STD_NTSC) | |
809 | fmt = 0x1; | |
810 | else if (state->std & V4L2_STD_PAL) | |
811 | fmt = 0x4; | |
812 | else if (state->std & V4L2_STD_SECAM) | |
813 | fmt = 0xc; | |
814 | } | |
815 | ||
6246d4e1 | 816 | CX18_DEBUG_INFO_DEV(sd, "changing video std to fmt %i\n", fmt); |
1c1e45d1 HV |
817 | |
818 | /* Follow step 9 of section 3.16 in the cx18_av datasheet. | |
819 | Without this PAL may display a vertical ghosting effect. | |
820 | This happens for example with the Yuan MPC622. */ | |
821 | if (fmt >= 4 && fmt < 8) { | |
822 | /* Set format to NTSC-M */ | |
c1738904 | 823 | cx18_av_and_or(cx, 0x400, ~0xf, 1); |
1c1e45d1 HV |
824 | /* Turn off LCOMB */ |
825 | cx18_av_and_or(cx, 0x47b, ~6, 0); | |
826 | } | |
c1738904 HV |
827 | cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20); |
828 | cx18_av_and_or(cx, 0x403, ~0x3, pal_m); | |
03b52c36 | 829 | cx18_av_std_setup(cx); |
1c1e45d1 HV |
830 | input_change(cx); |
831 | return 0; | |
832 | } | |
833 | ||
1a267046 AW |
834 | static int cx18_av_s_radio(struct v4l2_subdev *sd) |
835 | { | |
836 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
837 | state->radio = 1; | |
838 | return 0; | |
839 | } | |
1c1e45d1 | 840 | |
1a267046 | 841 | static int cx18_av_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
1c1e45d1 | 842 | { |
1a267046 AW |
843 | struct cx18 *cx = v4l2_get_subdevdata(sd); |
844 | ||
1c1e45d1 HV |
845 | switch (ctrl->id) { |
846 | case V4L2_CID_BRIGHTNESS: | |
847 | if (ctrl->value < 0 || ctrl->value > 255) { | |
6246d4e1 AW |
848 | CX18_ERR_DEV(sd, "invalid brightness setting %d\n", |
849 | ctrl->value); | |
1c1e45d1 HV |
850 | return -ERANGE; |
851 | } | |
852 | ||
853 | cx18_av_write(cx, 0x414, ctrl->value - 128); | |
854 | break; | |
855 | ||
856 | case V4L2_CID_CONTRAST: | |
857 | if (ctrl->value < 0 || ctrl->value > 127) { | |
6246d4e1 AW |
858 | CX18_ERR_DEV(sd, "invalid contrast setting %d\n", |
859 | ctrl->value); | |
1c1e45d1 HV |
860 | return -ERANGE; |
861 | } | |
862 | ||
863 | cx18_av_write(cx, 0x415, ctrl->value << 1); | |
864 | break; | |
865 | ||
866 | case V4L2_CID_SATURATION: | |
867 | if (ctrl->value < 0 || ctrl->value > 127) { | |
6246d4e1 AW |
868 | CX18_ERR_DEV(sd, "invalid saturation setting %d\n", |
869 | ctrl->value); | |
1c1e45d1 HV |
870 | return -ERANGE; |
871 | } | |
872 | ||
873 | cx18_av_write(cx, 0x420, ctrl->value << 1); | |
874 | cx18_av_write(cx, 0x421, ctrl->value << 1); | |
875 | break; | |
876 | ||
877 | case V4L2_CID_HUE: | |
de6476f5 | 878 | if (ctrl->value < -128 || ctrl->value > 127) { |
6246d4e1 AW |
879 | CX18_ERR_DEV(sd, "invalid hue setting %d\n", |
880 | ctrl->value); | |
1c1e45d1 HV |
881 | return -ERANGE; |
882 | } | |
883 | ||
884 | cx18_av_write(cx, 0x422, ctrl->value); | |
885 | break; | |
886 | ||
887 | case V4L2_CID_AUDIO_VOLUME: | |
888 | case V4L2_CID_AUDIO_BASS: | |
889 | case V4L2_CID_AUDIO_TREBLE: | |
890 | case V4L2_CID_AUDIO_BALANCE: | |
891 | case V4L2_CID_AUDIO_MUTE: | |
41c129a8 | 892 | return cx18_av_audio_s_ctrl(cx, ctrl); |
1c1e45d1 HV |
893 | |
894 | default: | |
895 | return -EINVAL; | |
896 | } | |
1c1e45d1 HV |
897 | return 0; |
898 | } | |
899 | ||
1a267046 | 900 | static int cx18_av_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
1c1e45d1 | 901 | { |
1a267046 AW |
902 | struct cx18 *cx = v4l2_get_subdevdata(sd); |
903 | ||
1c1e45d1 HV |
904 | switch (ctrl->id) { |
905 | case V4L2_CID_BRIGHTNESS: | |
906 | ctrl->value = (s8)cx18_av_read(cx, 0x414) + 128; | |
907 | break; | |
908 | case V4L2_CID_CONTRAST: | |
909 | ctrl->value = cx18_av_read(cx, 0x415) >> 1; | |
910 | break; | |
911 | case V4L2_CID_SATURATION: | |
912 | ctrl->value = cx18_av_read(cx, 0x420) >> 1; | |
913 | break; | |
914 | case V4L2_CID_HUE: | |
915 | ctrl->value = (s8)cx18_av_read(cx, 0x422); | |
916 | break; | |
917 | case V4L2_CID_AUDIO_VOLUME: | |
918 | case V4L2_CID_AUDIO_BASS: | |
919 | case V4L2_CID_AUDIO_TREBLE: | |
920 | case V4L2_CID_AUDIO_BALANCE: | |
921 | case V4L2_CID_AUDIO_MUTE: | |
41c129a8 | 922 | return cx18_av_audio_g_ctrl(cx, ctrl); |
1c1e45d1 HV |
923 | default: |
924 | return -EINVAL; | |
925 | } | |
1c1e45d1 HV |
926 | return 0; |
927 | } | |
928 | ||
1a267046 AW |
929 | static int cx18_av_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc) |
930 | { | |
931 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
932 | ||
933 | switch (qc->id) { | |
934 | case V4L2_CID_BRIGHTNESS: | |
935 | return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); | |
936 | case V4L2_CID_CONTRAST: | |
937 | case V4L2_CID_SATURATION: | |
938 | return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64); | |
939 | case V4L2_CID_HUE: | |
940 | return v4l2_ctrl_query_fill(qc, -128, 127, 1, 0); | |
941 | default: | |
942 | break; | |
943 | } | |
944 | ||
945 | switch (qc->id) { | |
946 | case V4L2_CID_AUDIO_VOLUME: | |
947 | return v4l2_ctrl_query_fill(qc, 0, 65535, | |
948 | 65535 / 100, state->default_volume); | |
949 | case V4L2_CID_AUDIO_MUTE: | |
950 | return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); | |
951 | case V4L2_CID_AUDIO_BALANCE: | |
952 | case V4L2_CID_AUDIO_BASS: | |
953 | case V4L2_CID_AUDIO_TREBLE: | |
954 | return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768); | |
955 | default: | |
956 | return -EINVAL; | |
957 | } | |
958 | return -EINVAL; | |
959 | } | |
1c1e45d1 | 960 | |
1a267046 | 961 | static int cx18_av_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt) |
1c1e45d1 | 962 | { |
1a267046 AW |
963 | struct cx18 *cx = v4l2_get_subdevdata(sd); |
964 | ||
41c129a8 | 965 | return cx18_av_vbi_g_fmt(cx, fmt); |
1c1e45d1 HV |
966 | } |
967 | ||
1a267046 | 968 | static int cx18_av_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt) |
1c1e45d1 | 969 | { |
1a267046 AW |
970 | struct cx18_av_state *state = to_cx18_av_state(sd); |
971 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
972 | ||
1c1e45d1 HV |
973 | struct v4l2_pix_format *pix; |
974 | int HSC, VSC, Vsrc, Hsrc, filter, Vlines; | |
975 | int is_50Hz = !(state->std & V4L2_STD_525_60); | |
976 | ||
977 | switch (fmt->type) { | |
978 | case V4L2_BUF_TYPE_VIDEO_CAPTURE: | |
979 | pix = &(fmt->fmt.pix); | |
980 | ||
981 | Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4; | |
982 | Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4; | |
983 | ||
984 | Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4; | |
985 | Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4; | |
986 | ||
72401b7a AW |
987 | /* |
988 | * This adjustment reflects the excess of vactive, set in | |
989 | * cx18_av_std_setup(), above standard values: | |
990 | * | |
991 | * 480 + 1 for 60 Hz systems | |
5ab74052 | 992 | * 576 - 2 for 50 Hz systems |
72401b7a | 993 | */ |
5ab74052 | 994 | Vlines = pix->height + (is_50Hz ? -2 : 1); |
1c1e45d1 | 995 | |
72401b7a AW |
996 | /* |
997 | * Invalid height and width scaling requests are: | |
998 | * 1. width less than 1/16 of the source width | |
999 | * 2. width greater than the source width | |
1000 | * 3. height less than 1/8 of the source height | |
1001 | * 4. height greater than the source height | |
1002 | */ | |
1c1e45d1 HV |
1003 | if ((pix->width * 16 < Hsrc) || (Hsrc < pix->width) || |
1004 | (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) { | |
6246d4e1 AW |
1005 | CX18_ERR_DEV(sd, "%dx%d is not a valid size!\n", |
1006 | pix->width, pix->height); | |
1c1e45d1 HV |
1007 | return -ERANGE; |
1008 | } | |
1009 | ||
1010 | HSC = (Hsrc * (1 << 20)) / pix->width - (1 << 20); | |
1011 | VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9)); | |
1012 | VSC &= 0x1fff; | |
1013 | ||
1014 | if (pix->width >= 385) | |
1015 | filter = 0; | |
1016 | else if (pix->width > 192) | |
1017 | filter = 1; | |
1018 | else if (pix->width > 96) | |
1019 | filter = 2; | |
1020 | else | |
1021 | filter = 3; | |
1022 | ||
6246d4e1 AW |
1023 | CX18_DEBUG_INFO_DEV(sd, |
1024 | "decoder set size %dx%d -> scale %ux%u\n", | |
1025 | pix->width, pix->height, HSC, VSC); | |
1c1e45d1 HV |
1026 | |
1027 | /* HSCALE=HSC */ | |
1028 | cx18_av_write(cx, 0x418, HSC & 0xff); | |
1029 | cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff); | |
1030 | cx18_av_write(cx, 0x41a, HSC >> 16); | |
1031 | /* VSCALE=VSC */ | |
1032 | cx18_av_write(cx, 0x41c, VSC & 0xff); | |
1033 | cx18_av_write(cx, 0x41d, VSC >> 8); | |
1034 | /* VS_INTRLACE=1 VFILT=filter */ | |
1035 | cx18_av_write(cx, 0x41e, 0x8 | filter); | |
1036 | break; | |
1037 | ||
1038 | case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: | |
41c129a8 | 1039 | return cx18_av_vbi_s_fmt(cx, fmt); |
1c1e45d1 HV |
1040 | |
1041 | case V4L2_BUF_TYPE_VBI_CAPTURE: | |
41c129a8 | 1042 | return cx18_av_vbi_s_fmt(cx, fmt); |
1c1e45d1 HV |
1043 | |
1044 | default: | |
1045 | return -EINVAL; | |
1046 | } | |
1c1e45d1 HV |
1047 | return 0; |
1048 | } | |
1049 | ||
1a267046 | 1050 | static int cx18_av_s_stream(struct v4l2_subdev *sd, int enable) |
e474200d | 1051 | { |
1a267046 | 1052 | struct cx18 *cx = v4l2_get_subdevdata(sd); |
1c1e45d1 | 1053 | |
6246d4e1 | 1054 | CX18_DEBUG_INFO_DEV(sd, "%s output\n", enable ? "enable" : "disable"); |
1a267046 | 1055 | if (enable) { |
1c1e45d1 HV |
1056 | cx18_av_write(cx, 0x115, 0x8c); |
1057 | cx18_av_write(cx, 0x116, 0x07); | |
1a267046 | 1058 | } else { |
1c1e45d1 HV |
1059 | cx18_av_write(cx, 0x115, 0x00); |
1060 | cx18_av_write(cx, 0x116, 0x00); | |
1c1e45d1 | 1061 | } |
1c1e45d1 HV |
1062 | return 0; |
1063 | } | |
1064 | ||
1c1e45d1 HV |
1065 | static void log_video_status(struct cx18 *cx) |
1066 | { | |
1067 | static const char *const fmt_strs[] = { | |
1068 | "0x0", | |
1069 | "NTSC-M", "NTSC-J", "NTSC-4.43", | |
1070 | "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60", | |
1071 | "0x9", "0xA", "0xB", | |
1072 | "SECAM", | |
1073 | "0xD", "0xE", "0xF" | |
1074 | }; | |
1075 | ||
1076 | struct cx18_av_state *state = &cx->av_state; | |
6246d4e1 | 1077 | struct v4l2_subdev *sd = &state->sd; |
1c1e45d1 HV |
1078 | u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf; |
1079 | u8 gen_stat1 = cx18_av_read(cx, 0x40d); | |
1080 | u8 gen_stat2 = cx18_av_read(cx, 0x40e); | |
1081 | int vid_input = state->vid_input; | |
1082 | ||
6246d4e1 AW |
1083 | CX18_INFO_DEV(sd, "Video signal: %spresent\n", |
1084 | (gen_stat2 & 0x20) ? "" : "not "); | |
1085 | CX18_INFO_DEV(sd, "Detected format: %s\n", | |
1086 | fmt_strs[gen_stat1 & 0xf]); | |
1c1e45d1 | 1087 | |
6246d4e1 AW |
1088 | CX18_INFO_DEV(sd, "Specified standard: %s\n", |
1089 | vidfmt_sel ? fmt_strs[vidfmt_sel] | |
1090 | : "automatic detection"); | |
1c1e45d1 HV |
1091 | |
1092 | if (vid_input >= CX18_AV_COMPOSITE1 && | |
1093 | vid_input <= CX18_AV_COMPOSITE8) { | |
6246d4e1 AW |
1094 | CX18_INFO_DEV(sd, "Specified video input: Composite %d\n", |
1095 | vid_input - CX18_AV_COMPOSITE1 + 1); | |
1c1e45d1 | 1096 | } else { |
6246d4e1 AW |
1097 | CX18_INFO_DEV(sd, "Specified video input: " |
1098 | "S-Video (Luma In%d, Chroma In%d)\n", | |
1099 | (vid_input & 0xf0) >> 4, | |
1100 | (vid_input & 0xf00) >> 8); | |
1c1e45d1 HV |
1101 | } |
1102 | ||
6246d4e1 AW |
1103 | CX18_INFO_DEV(sd, "Specified audioclock freq: %d Hz\n", |
1104 | state->audclk_freq); | |
1c1e45d1 HV |
1105 | } |
1106 | ||
1c1e45d1 HV |
1107 | static void log_audio_status(struct cx18 *cx) |
1108 | { | |
1109 | struct cx18_av_state *state = &cx->av_state; | |
6246d4e1 | 1110 | struct v4l2_subdev *sd = &state->sd; |
1c1e45d1 | 1111 | u8 download_ctl = cx18_av_read(cx, 0x803); |
63b8c709 HV |
1112 | u8 mod_det_stat0 = cx18_av_read(cx, 0x804); |
1113 | u8 mod_det_stat1 = cx18_av_read(cx, 0x805); | |
1c1e45d1 HV |
1114 | u8 audio_config = cx18_av_read(cx, 0x808); |
1115 | u8 pref_mode = cx18_av_read(cx, 0x809); | |
1116 | u8 afc0 = cx18_av_read(cx, 0x80b); | |
1117 | u8 mute_ctl = cx18_av_read(cx, 0x8d3); | |
1118 | int aud_input = state->aud_input; | |
1119 | char *p; | |
1120 | ||
1121 | switch (mod_det_stat0) { | |
1122 | case 0x00: p = "mono"; break; | |
1123 | case 0x01: p = "stereo"; break; | |
1124 | case 0x02: p = "dual"; break; | |
1125 | case 0x04: p = "tri"; break; | |
1126 | case 0x10: p = "mono with SAP"; break; | |
1127 | case 0x11: p = "stereo with SAP"; break; | |
1128 | case 0x12: p = "dual with SAP"; break; | |
1129 | case 0x14: p = "tri with SAP"; break; | |
1130 | case 0xfe: p = "forced mode"; break; | |
63b8c709 | 1131 | default: p = "not defined"; break; |
1c1e45d1 | 1132 | } |
6246d4e1 | 1133 | CX18_INFO_DEV(sd, "Detected audio mode: %s\n", p); |
1c1e45d1 HV |
1134 | |
1135 | switch (mod_det_stat1) { | |
63b8c709 | 1136 | case 0x00: p = "not defined"; break; |
1c1e45d1 HV |
1137 | case 0x01: p = "EIAJ"; break; |
1138 | case 0x02: p = "A2-M"; break; | |
1139 | case 0x03: p = "A2-BG"; break; | |
1140 | case 0x04: p = "A2-DK1"; break; | |
1141 | case 0x05: p = "A2-DK2"; break; | |
1142 | case 0x06: p = "A2-DK3"; break; | |
1143 | case 0x07: p = "A1 (6.0 MHz FM Mono)"; break; | |
1144 | case 0x08: p = "AM-L"; break; | |
1145 | case 0x09: p = "NICAM-BG"; break; | |
1146 | case 0x0a: p = "NICAM-DK"; break; | |
1147 | case 0x0b: p = "NICAM-I"; break; | |
1148 | case 0x0c: p = "NICAM-L"; break; | |
1149 | case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break; | |
63b8c709 HV |
1150 | case 0x0e: p = "IF FM Radio"; break; |
1151 | case 0x0f: p = "BTSC"; break; | |
1152 | case 0x10: p = "detected chrominance"; break; | |
1153 | case 0xfd: p = "unknown audio standard"; break; | |
1154 | case 0xfe: p = "forced audio standard"; break; | |
1c1e45d1 | 1155 | case 0xff: p = "no detected audio standard"; break; |
63b8c709 | 1156 | default: p = "not defined"; break; |
1c1e45d1 | 1157 | } |
6246d4e1 AW |
1158 | CX18_INFO_DEV(sd, "Detected audio standard: %s\n", p); |
1159 | CX18_INFO_DEV(sd, "Audio muted: %s\n", | |
1160 | (mute_ctl & 0x2) ? "yes" : "no"); | |
1161 | CX18_INFO_DEV(sd, "Audio microcontroller: %s\n", | |
1162 | (download_ctl & 0x10) ? "running" : "stopped"); | |
1c1e45d1 HV |
1163 | |
1164 | switch (audio_config >> 4) { | |
63b8c709 HV |
1165 | case 0x00: p = "undefined"; break; |
1166 | case 0x01: p = "BTSC"; break; | |
1167 | case 0x02: p = "EIAJ"; break; | |
1168 | case 0x03: p = "A2-M"; break; | |
1169 | case 0x04: p = "A2-BG"; break; | |
1170 | case 0x05: p = "A2-DK1"; break; | |
1171 | case 0x06: p = "A2-DK2"; break; | |
1172 | case 0x07: p = "A2-DK3"; break; | |
1173 | case 0x08: p = "A1 (6.0 MHz FM Mono)"; break; | |
1174 | case 0x09: p = "AM-L"; break; | |
1175 | case 0x0a: p = "NICAM-BG"; break; | |
1176 | case 0x0b: p = "NICAM-DK"; break; | |
1177 | case 0x0c: p = "NICAM-I"; break; | |
1178 | case 0x0d: p = "NICAM-L"; break; | |
1179 | case 0x0e: p = "FM radio"; break; | |
1c1e45d1 | 1180 | case 0x0f: p = "automatic detection"; break; |
63b8c709 | 1181 | default: p = "undefined"; break; |
1c1e45d1 | 1182 | } |
6246d4e1 | 1183 | CX18_INFO_DEV(sd, "Configured audio standard: %s\n", p); |
1c1e45d1 HV |
1184 | |
1185 | if ((audio_config >> 4) < 0xF) { | |
1186 | switch (audio_config & 0xF) { | |
1187 | case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break; | |
1188 | case 0x01: p = "MONO2 (LANGUAGE B)"; break; | |
1189 | case 0x02: p = "MONO3 (STEREO forced MONO)"; break; | |
1190 | case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break; | |
1191 | case 0x04: p = "STEREO"; break; | |
63b8c709 HV |
1192 | case 0x05: p = "DUAL1 (AC)"; break; |
1193 | case 0x06: p = "DUAL2 (BC)"; break; | |
1194 | case 0x07: p = "DUAL3 (AB)"; break; | |
1c1e45d1 HV |
1195 | default: p = "undefined"; |
1196 | } | |
6246d4e1 | 1197 | CX18_INFO_DEV(sd, "Configured audio mode: %s\n", p); |
1c1e45d1 HV |
1198 | } else { |
1199 | switch (audio_config & 0xF) { | |
1200 | case 0x00: p = "BG"; break; | |
1201 | case 0x01: p = "DK1"; break; | |
1202 | case 0x02: p = "DK2"; break; | |
1203 | case 0x03: p = "DK3"; break; | |
1204 | case 0x04: p = "I"; break; | |
1205 | case 0x05: p = "L"; break; | |
1206 | case 0x06: p = "BTSC"; break; | |
1207 | case 0x07: p = "EIAJ"; break; | |
1208 | case 0x08: p = "A2-M"; break; | |
63b8c709 HV |
1209 | case 0x09: p = "FM Radio (4.5 MHz)"; break; |
1210 | case 0x0a: p = "FM Radio (5.5 MHz)"; break; | |
1211 | case 0x0b: p = "S-Video"; break; | |
1c1e45d1 | 1212 | case 0x0f: p = "automatic standard and mode detection"; break; |
63b8c709 | 1213 | default: p = "undefined"; break; |
1c1e45d1 | 1214 | } |
6246d4e1 | 1215 | CX18_INFO_DEV(sd, "Configured audio system: %s\n", p); |
1c1e45d1 HV |
1216 | } |
1217 | ||
1218 | if (aud_input) | |
6246d4e1 AW |
1219 | CX18_INFO_DEV(sd, "Specified audio input: Tuner (In%d)\n", |
1220 | aud_input); | |
1c1e45d1 | 1221 | else |
6246d4e1 | 1222 | CX18_INFO_DEV(sd, "Specified audio input: External\n"); |
1c1e45d1 HV |
1223 | |
1224 | switch (pref_mode & 0xf) { | |
1225 | case 0: p = "mono/language A"; break; | |
1226 | case 1: p = "language B"; break; | |
1227 | case 2: p = "language C"; break; | |
1228 | case 3: p = "analog fallback"; break; | |
1229 | case 4: p = "stereo"; break; | |
1230 | case 5: p = "language AC"; break; | |
1231 | case 6: p = "language BC"; break; | |
1232 | case 7: p = "language AB"; break; | |
63b8c709 | 1233 | default: p = "undefined"; break; |
1c1e45d1 | 1234 | } |
6246d4e1 | 1235 | CX18_INFO_DEV(sd, "Preferred audio mode: %s\n", p); |
1c1e45d1 HV |
1236 | |
1237 | if ((audio_config & 0xf) == 0xf) { | |
63b8c709 | 1238 | switch ((afc0 >> 3) & 0x1) { |
1c1e45d1 HV |
1239 | case 0: p = "system DK"; break; |
1240 | case 1: p = "system L"; break; | |
1241 | } | |
6246d4e1 | 1242 | CX18_INFO_DEV(sd, "Selected 65 MHz format: %s\n", p); |
1c1e45d1 | 1243 | |
63b8c709 HV |
1244 | switch (afc0 & 0x7) { |
1245 | case 0: p = "Chroma"; break; | |
1246 | case 1: p = "BTSC"; break; | |
1247 | case 2: p = "EIAJ"; break; | |
1248 | case 3: p = "A2-M"; break; | |
1249 | case 4: p = "autodetect"; break; | |
1250 | default: p = "undefined"; break; | |
1c1e45d1 | 1251 | } |
6246d4e1 | 1252 | CX18_INFO_DEV(sd, "Selected 45 MHz format: %s\n", p); |
1c1e45d1 HV |
1253 | } |
1254 | } | |
1a267046 AW |
1255 | |
1256 | static int cx18_av_log_status(struct v4l2_subdev *sd) | |
1257 | { | |
1258 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1259 | log_video_status(cx); | |
1260 | log_audio_status(cx); | |
1261 | return 0; | |
1262 | } | |
1263 | ||
1264 | static inline int cx18_av_dbg_match(const struct v4l2_dbg_match *match) | |
1265 | { | |
1266 | return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 1; | |
1267 | } | |
1268 | ||
1269 | static int cx18_av_g_chip_ident(struct v4l2_subdev *sd, | |
1270 | struct v4l2_dbg_chip_ident *chip) | |
1271 | { | |
fa3e7036 AW |
1272 | struct cx18_av_state *state = to_cx18_av_state(sd); |
1273 | ||
1a267046 | 1274 | if (cx18_av_dbg_match(&chip->match)) { |
fa3e7036 AW |
1275 | chip->ident = state->id; |
1276 | chip->revision = state->rev; | |
1a267046 AW |
1277 | } |
1278 | return 0; | |
1279 | } | |
1280 | ||
1281 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
1282 | static int cx18_av_g_register(struct v4l2_subdev *sd, | |
1283 | struct v4l2_dbg_register *reg) | |
1284 | { | |
1285 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1286 | ||
1287 | if (!cx18_av_dbg_match(®->match)) | |
1288 | return -EINVAL; | |
1289 | if ((reg->reg & 0x3) != 0) | |
1290 | return -EINVAL; | |
1291 | if (!capable(CAP_SYS_ADMIN)) | |
1292 | return -EPERM; | |
1293 | reg->size = 4; | |
1294 | reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc); | |
1295 | return 0; | |
1296 | } | |
1297 | ||
1298 | static int cx18_av_s_register(struct v4l2_subdev *sd, | |
1299 | struct v4l2_dbg_register *reg) | |
1300 | { | |
1301 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1302 | ||
1303 | if (!cx18_av_dbg_match(®->match)) | |
1304 | return -EINVAL; | |
1305 | if ((reg->reg & 0x3) != 0) | |
1306 | return -EINVAL; | |
1307 | if (!capable(CAP_SYS_ADMIN)) | |
1308 | return -EPERM; | |
1309 | cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val); | |
1310 | return 0; | |
1311 | } | |
1312 | #endif | |
1313 | ||
1314 | static const struct v4l2_subdev_core_ops cx18_av_general_ops = { | |
1315 | .g_chip_ident = cx18_av_g_chip_ident, | |
1316 | .log_status = cx18_av_log_status, | |
fa3e7036 | 1317 | .init = cx18_av_init, |
cc26b076 | 1318 | .load_fw = cx18_av_load_fw, |
1a267046 AW |
1319 | .reset = cx18_av_reset, |
1320 | .queryctrl = cx18_av_queryctrl, | |
1321 | .g_ctrl = cx18_av_g_ctrl, | |
1322 | .s_ctrl = cx18_av_s_ctrl, | |
f41737ec | 1323 | .s_std = cx18_av_s_std, |
1a267046 AW |
1324 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1325 | .g_register = cx18_av_g_register, | |
1326 | .s_register = cx18_av_s_register, | |
1327 | #endif | |
1328 | }; | |
1329 | ||
1330 | static const struct v4l2_subdev_tuner_ops cx18_av_tuner_ops = { | |
1331 | .s_radio = cx18_av_s_radio, | |
1332 | .s_frequency = cx18_av_s_frequency, | |
1333 | .g_tuner = cx18_av_g_tuner, | |
1334 | .s_tuner = cx18_av_s_tuner, | |
1a267046 AW |
1335 | }; |
1336 | ||
1337 | static const struct v4l2_subdev_audio_ops cx18_av_audio_ops = { | |
1338 | .s_clock_freq = cx18_av_s_clock_freq, | |
1339 | .s_routing = cx18_av_s_audio_routing, | |
1340 | }; | |
1341 | ||
1342 | static const struct v4l2_subdev_video_ops cx18_av_video_ops = { | |
1343 | .s_routing = cx18_av_s_video_routing, | |
1344 | .decode_vbi_line = cx18_av_decode_vbi_line, | |
1345 | .s_stream = cx18_av_s_stream, | |
1346 | .g_fmt = cx18_av_g_fmt, | |
1347 | .s_fmt = cx18_av_s_fmt, | |
1348 | }; | |
1349 | ||
1350 | static const struct v4l2_subdev_ops cx18_av_ops = { | |
1351 | .core = &cx18_av_general_ops, | |
1352 | .tuner = &cx18_av_tuner_ops, | |
1353 | .audio = &cx18_av_audio_ops, | |
1354 | .video = &cx18_av_video_ops, | |
1355 | }; | |
1356 | ||
ff2a2001 | 1357 | int cx18_av_probe(struct cx18 *cx) |
1a267046 | 1358 | { |
fa3e7036 | 1359 | struct cx18_av_state *state = &cx->av_state; |
ff2a2001 | 1360 | struct v4l2_subdev *sd; |
fa3e7036 AW |
1361 | |
1362 | state->rev = cx18_av_read4(cx, CXADEC_CHIP_CTRL) & 0xffff; | |
1363 | state->id = ((state->rev >> 4) == CXADEC_CHIP_TYPE_MAKO) | |
1364 | ? V4L2_IDENT_CX23418_843 : V4L2_IDENT_UNKNOWN; | |
1365 | ||
1366 | state->vid_input = CX18_AV_COMPOSITE7; | |
1367 | state->aud_input = CX18_AV_AUDIO8; | |
1368 | state->audclk_freq = 48000; | |
1369 | state->audmode = V4L2_TUNER_MODE_LANG1; | |
1370 | state->slicer_line_delay = 0; | |
1371 | state->slicer_line_offset = (10 + state->slicer_line_delay - 2); | |
1372 | ||
ff2a2001 AW |
1373 | sd = &state->sd; |
1374 | v4l2_subdev_init(sd, &cx18_av_ops); | |
1375 | v4l2_set_subdevdata(sd, cx); | |
1376 | snprintf(sd->name, sizeof(sd->name), | |
6246d4e1 | 1377 | "%s %03x", cx->v4l2_dev.name, (state->rev >> 4)); |
ff2a2001 AW |
1378 | sd->grp_id = CX18_HW_418_AV; |
1379 | return v4l2_device_register_subdev(&cx->v4l2_dev, sd); | |
1a267046 | 1380 | } |