Commit | Line | Data |
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1c1e45d1 HV |
1 | /* |
2 | * cx18 interrupt handling | |
3 | * | |
4 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA | |
19 | * 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include "cx18-driver.h" | |
b1526421 | 23 | #include "cx18-io.h" |
1c1e45d1 HV |
24 | #include "cx18-firmware.h" |
25 | #include "cx18-fileops.h" | |
26 | #include "cx18-queue.h" | |
27 | #include "cx18-irq.h" | |
28 | #include "cx18-ioctl.h" | |
29 | #include "cx18-mailbox.h" | |
30 | #include "cx18-vbi.h" | |
31 | #include "cx18-scb.h" | |
1d6782bd AW |
32 | #include "cx18-dvb.h" |
33 | ||
34 | void cx18_work_handler(struct work_struct *work) | |
35 | { | |
36 | struct cx18 *cx = container_of(work, struct cx18, work); | |
1d6782bd AW |
37 | if (test_and_clear_bit(CX18_F_I_WORK_HANDLER_DVB, &cx->i_flags)) |
38 | cx18_dvb_work_handler(cx); | |
39 | } | |
1c1e45d1 | 40 | |
72c2d6d3 | 41 | static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb, int rpu) |
1c1e45d1 HV |
42 | { |
43 | u32 handle = mb->args[0]; | |
44 | struct cx18_stream *s = NULL; | |
45 | struct cx18_buffer *buf; | |
46 | u32 off; | |
47 | int i; | |
48 | int id; | |
49 | ||
50 | for (i = 0; i < CX18_MAX_STREAMS; i++) { | |
51 | s = &cx->streams[i]; | |
52 | if ((handle == s->handle) && (s->dvb.enabled)) | |
53 | break; | |
54 | if (s->v4l2dev && handle == s->handle) | |
55 | break; | |
56 | } | |
57 | if (i == CX18_MAX_STREAMS) { | |
e86a93dc AW |
58 | CX18_WARN("Got DMA done notification for unknown/inactive" |
59 | " handle %d\n", handle); | |
1c1e45d1 HV |
60 | mb->error = CXERR_NOT_OPEN; |
61 | mb->cmd = 0; | |
72c2d6d3 | 62 | cx18_mb_ack(cx, mb, rpu); |
1c1e45d1 HV |
63 | return; |
64 | } | |
65 | ||
66 | off = mb->args[1]; | |
67 | if (mb->args[2] != 1) | |
68 | CX18_WARN("Ack struct = %d for %s\n", | |
69 | mb->args[2], s->name); | |
b1526421 AW |
70 | id = cx18_read_enc(cx, off); |
71 | buf = cx18_queue_get_buf_irq(s, id, cx18_read_enc(cx, off + 4)); | |
1c1e45d1 HV |
72 | CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, id); |
73 | if (buf) { | |
74 | cx18_buf_sync_for_cpu(s, buf); | |
75 | if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) { | |
1d6782bd | 76 | CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n", |
1c1e45d1 HV |
77 | buf->bytesused); |
78 | ||
1d6782bd AW |
79 | set_bit(CX18_F_I_WORK_HANDLER_DVB, &cx->i_flags); |
80 | set_bit(CX18_F_I_HAVE_WORK, &cx->i_flags); | |
1c1e45d1 HV |
81 | } else |
82 | set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags); | |
83 | } else { | |
84 | CX18_WARN("Could not find buf %d for stream %s\n", | |
b1526421 | 85 | cx18_read_enc(cx, off), s->name); |
1c1e45d1 HV |
86 | } |
87 | mb->error = 0; | |
88 | mb->cmd = 0; | |
72c2d6d3 | 89 | cx18_mb_ack(cx, mb, rpu); |
1c1e45d1 HV |
90 | wake_up(&cx->dma_waitq); |
91 | if (s->id != -1) | |
92 | wake_up(&s->waitq); | |
93 | } | |
94 | ||
72c2d6d3 | 95 | static void epu_debug(struct cx18 *cx, struct cx18_mailbox *mb, int rpu) |
1c1e45d1 HV |
96 | { |
97 | char str[256] = { 0 }; | |
98 | char *p; | |
99 | ||
100 | if (mb->args[1]) { | |
b1526421 AW |
101 | cx18_setup_page(cx, mb->args[1]); |
102 | cx18_memcpy_fromio(cx, str, cx->enc_mem + mb->args[1], 252); | |
1c1e45d1 HV |
103 | str[252] = 0; |
104 | } | |
72c2d6d3 | 105 | cx18_mb_ack(cx, mb, rpu); |
1c1e45d1 HV |
106 | CX18_DEBUG_INFO("%x %s\n", mb->args[0], str); |
107 | p = strchr(str, '.'); | |
108 | if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str) | |
109 | CX18_INFO("FW version: %s\n", p - 1); | |
110 | } | |
111 | ||
465f8a80 | 112 | static void epu_cmd(struct cx18 *cx, u32 sw1) |
1c1e45d1 HV |
113 | { |
114 | struct cx18_mailbox mb; | |
115 | ||
116 | if (sw1 & IRQ_CPU_TO_EPU) { | |
b1526421 | 117 | cx18_memcpy_fromio(cx, &mb, &cx->scb->cpu2epu_mb, sizeof(mb)); |
1c1e45d1 HV |
118 | mb.error = 0; |
119 | ||
120 | switch (mb.cmd) { | |
121 | case CX18_EPU_DMA_DONE: | |
72c2d6d3 | 122 | epu_dma_done(cx, &mb, CPU); |
1c1e45d1 HV |
123 | break; |
124 | case CX18_EPU_DEBUG: | |
72c2d6d3 | 125 | epu_debug(cx, &mb, CPU); |
1c1e45d1 HV |
126 | break; |
127 | default: | |
465f8a80 AW |
128 | CX18_WARN("Unknown CPU_TO_EPU mailbox command %#08x\n", |
129 | mb.cmd); | |
1c1e45d1 HV |
130 | break; |
131 | } | |
132 | } | |
465f8a80 AW |
133 | |
134 | if (sw1 & IRQ_APU_TO_EPU) { | |
135 | cx18_memcpy_fromio(cx, &mb, &cx->scb->apu2epu_mb, sizeof(mb)); | |
136 | CX18_WARN("Unknown APU_TO_EPU mailbox command %#08x\n", mb.cmd); | |
137 | } | |
465f8a80 AW |
138 | } |
139 | ||
140 | static void xpu_ack(struct cx18 *cx, u32 sw2) | |
141 | { | |
142 | if (sw2 & IRQ_CPU_TO_EPU_ACK) | |
143 | wake_up(&cx->mb_cpu_waitq); | |
144 | if (sw2 & IRQ_APU_TO_EPU_ACK) | |
145 | wake_up(&cx->mb_apu_waitq); | |
1c1e45d1 HV |
146 | } |
147 | ||
148 | irqreturn_t cx18_irq_handler(int irq, void *dev_id) | |
149 | { | |
150 | struct cx18 *cx = (struct cx18 *)dev_id; | |
151 | u32 sw1, sw1_mask; | |
152 | u32 sw2, sw2_mask; | |
153 | u32 hw2, hw2_mask; | |
154 | ||
465f8a80 | 155 | sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); |
b1526421 | 156 | sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask; |
465f8a80 | 157 | sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); |
f056d29e AW |
158 | sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask; |
159 | hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI); | |
160 | hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask; | |
1c1e45d1 | 161 | |
f056d29e AW |
162 | if (sw1) |
163 | cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1); | |
164 | if (sw2) | |
165 | cx18_write_reg_expect(cx, sw2, SW2_INT_STATUS, ~sw2, sw2); | |
166 | if (hw2) | |
167 | cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2); | |
1c1e45d1 HV |
168 | |
169 | if (sw1 || sw2 || hw2) | |
170 | CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2); | |
171 | ||
172 | /* To do: interrupt-based I2C handling | |
465f8a80 | 173 | if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) { |
1c1e45d1 HV |
174 | } |
175 | */ | |
176 | ||
465f8a80 AW |
177 | if (sw2) |
178 | xpu_ack(cx, sw2); | |
1c1e45d1 HV |
179 | |
180 | if (sw1) | |
465f8a80 | 181 | epu_cmd(cx, sw1); |
1c1e45d1 | 182 | |
1d6782bd | 183 | if (test_and_clear_bit(CX18_F_I_HAVE_WORK, &cx->i_flags)) |
f68d0cf5 | 184 | schedule_work(&cx->work); |
1d6782bd | 185 | |
f056d29e | 186 | return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE; |
1c1e45d1 | 187 | } |