Commit | Line | Data |
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1c1e45d1 HV |
1 | /* |
2 | * cx18 mailbox functions | |
3 | * | |
4 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> | |
1ed9dcc8 | 5 | * Copyright (C) 2008 Andy Walls <awalls@radix.net> |
1c1e45d1 HV |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA | |
20 | * 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <stdarg.h> | |
24 | ||
25 | #include "cx18-driver.h" | |
b1526421 | 26 | #include "cx18-io.h" |
1c1e45d1 HV |
27 | #include "cx18-scb.h" |
28 | #include "cx18-irq.h" | |
29 | #include "cx18-mailbox.h" | |
ee2d64f5 AW |
30 | #include "cx18-queue.h" |
31 | #include "cx18-streams.h" | |
32 | ||
33 | static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" }; | |
1c1e45d1 HV |
34 | |
35 | #define API_FAST (1 << 2) /* Short timeout */ | |
36 | #define API_SLOW (1 << 3) /* Additional 300ms timeout */ | |
37 | ||
1c1e45d1 HV |
38 | struct cx18_api_info { |
39 | u32 cmd; | |
40 | u8 flags; /* Flags, see above */ | |
41 | u8 rpu; /* Processing unit */ | |
42 | const char *name; /* The name of the command */ | |
43 | }; | |
44 | ||
45 | #define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x } | |
46 | ||
47 | static const struct cx18_api_info api_info[] = { | |
48 | /* MPEG encoder API */ | |
49 | API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0), | |
50 | API_ENTRY(CPU, CX18_EPU_DEBUG, 0), | |
51 | API_ENTRY(CPU, CX18_CREATE_TASK, 0), | |
52 | API_ENTRY(CPU, CX18_DESTROY_TASK, 0), | |
53 | API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW), | |
54 | API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW), | |
55 | API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0), | |
56 | API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0), | |
57 | API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0), | |
58 | API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0), | |
59 | API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0), | |
60 | API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0), | |
61 | API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0), | |
62 | API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0), | |
63 | API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0), | |
64 | API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0), | |
65 | API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0), | |
66 | API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0), | |
67 | API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0), | |
68 | API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0), | |
69 | API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0), | |
70 | API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW), | |
71 | API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0), | |
72 | API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0), | |
73 | API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0), | |
74 | API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0), | |
75 | API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0), | |
76 | API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0), | |
77 | API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0), | |
78 | API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0), | |
79 | API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0), | |
80 | API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0), | |
81 | API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0), | |
82 | API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0), | |
83 | API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0), | |
84 | API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST), | |
4e6b6104 | 85 | API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW), |
350145a4 AW |
86 | API_ENTRY(APU, CX18_APU_START, 0), |
87 | API_ENTRY(APU, CX18_APU_STOP, 0), | |
fd6b9c97 AW |
88 | API_ENTRY(APU, CX18_APU_RESETAI, 0), |
89 | API_ENTRY(CPU, CX18_CPU_DEBUG_PEEK32, 0), | |
1c1e45d1 HV |
90 | API_ENTRY(0, 0, 0), |
91 | }; | |
92 | ||
93 | static const struct cx18_api_info *find_api_info(u32 cmd) | |
94 | { | |
95 | int i; | |
96 | ||
97 | for (i = 0; api_info[i].cmd; i++) | |
98 | if (api_info[i].cmd == cmd) | |
99 | return &api_info[i]; | |
100 | return NULL; | |
101 | } | |
102 | ||
50299994 AW |
103 | /* Call with buf of n*11+1 bytes */ |
104 | static char *u32arr2hex(u32 data[], int n, char *buf) | |
ee2d64f5 | 105 | { |
ee2d64f5 AW |
106 | char *p; |
107 | int i; | |
108 | ||
50299994 AW |
109 | for (i = 0, p = buf; i < n; i++, p += 11) { |
110 | /* kernel snprintf() appends '\0' always */ | |
111 | snprintf(p, 12, " %#010x", data[i]); | |
112 | } | |
113 | *p = '\0'; | |
114 | return buf; | |
115 | } | |
116 | ||
117 | static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name) | |
118 | { | |
119 | char argstr[MAX_MB_ARGUMENTS*11+1]; | |
120 | ||
ee2d64f5 AW |
121 | if (!(cx18_debug & CX18_DBGFLG_API)) |
122 | return; | |
123 | ||
ee2d64f5 | 124 | CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s" |
50299994 AW |
125 | "\n", name, mb->request, mb->ack, mb->cmd, mb->error, |
126 | u32arr2hex(mb->args, MAX_MB_ARGUMENTS, argstr)); | |
ee2d64f5 AW |
127 | } |
128 | ||
129 | ||
130 | /* | |
131 | * Functions that run in a work_queue work handling context | |
132 | */ | |
133 | ||
deed75ed | 134 | static void epu_dma_done(struct cx18 *cx, struct cx18_in_work_order *order) |
ee2d64f5 | 135 | { |
bca11a57 | 136 | u32 handle, mdl_ack_count, id; |
ee2d64f5 AW |
137 | struct cx18_mailbox *mb; |
138 | struct cx18_mdl_ack *mdl_ack; | |
139 | struct cx18_stream *s; | |
140 | struct cx18_buffer *buf; | |
141 | int i; | |
142 | ||
143 | mb = &order->mb; | |
144 | handle = mb->args[0]; | |
145 | s = cx18_handle_to_stream(cx, handle); | |
146 | ||
147 | if (s == NULL) { | |
148 | CX18_WARN("Got DMA done notification for unknown/inactive" | |
bca11a57 AW |
149 | " handle %d, %s mailbox seq no %d\n", handle, |
150 | (order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) ? | |
151 | "stale" : "good", mb->request); | |
ee2d64f5 AW |
152 | return; |
153 | } | |
154 | ||
155 | mdl_ack_count = mb->args[2]; | |
156 | mdl_ack = order->mdl_ack; | |
157 | for (i = 0; i < mdl_ack_count; i++, mdl_ack++) { | |
bca11a57 AW |
158 | id = mdl_ack->id; |
159 | /* | |
160 | * Simple integrity check for processing a stale (and possibly | |
161 | * inconsistent mailbox): make sure the buffer id is in the | |
162 | * valid range for the stream. | |
163 | * | |
164 | * We go through the trouble of dealing with stale mailboxes | |
165 | * because most of the time, the mailbox data is still valid and | |
166 | * unchanged (and in practice the firmware ping-pongs the | |
167 | * two mdl_ack buffers so mdl_acks are not stale). | |
168 | * | |
169 | * There are occasions when we get a half changed mailbox, | |
170 | * which this check catches for a handle & id mismatch. If the | |
171 | * handle and id do correspond, the worst case is that we | |
172 | * completely lost the old buffer, but pick up the new buffer | |
173 | * early (but the new mdl_ack is guaranteed to be good in this | |
174 | * case as the firmware wouldn't point us to a new mdl_ack until | |
175 | * it's filled in). | |
176 | * | |
177 | * cx18_queue_get buf() will detect the lost buffers | |
abb096de | 178 | * and send them back to q_free for fw rotation eventually. |
bca11a57 AW |
179 | */ |
180 | if ((order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) && | |
181 | !(id >= s->mdl_offset && | |
182 | id < (s->mdl_offset + s->buffers))) { | |
183 | CX18_WARN("Fell behind! Ignoring stale mailbox with " | |
184 | " inconsistent data. Lost buffer for mailbox " | |
185 | "seq no %d\n", mb->request); | |
186 | break; | |
187 | } | |
188 | buf = cx18_queue_get_buf(s, id, mdl_ack->data_used); | |
abb096de | 189 | |
bca11a57 | 190 | CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, id); |
ee2d64f5 AW |
191 | if (buf == NULL) { |
192 | CX18_WARN("Could not find buf %d for stream %s\n", | |
bca11a57 | 193 | id, s->name); |
abb096de AW |
194 | /* Put as many buffers as possible back into fw use */ |
195 | cx18_stream_load_fw_queue(s); | |
ee2d64f5 AW |
196 | continue; |
197 | } | |
198 | ||
ee2d64f5 AW |
199 | if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) { |
200 | CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n", | |
201 | buf->bytesused); | |
ee2d64f5 AW |
202 | dvb_dmx_swfilter(&s->dvb.demux, buf->buf, |
203 | buf->bytesused); | |
abb096de AW |
204 | } |
205 | /* Put as many buffers as possible back into fw use */ | |
206 | cx18_stream_load_fw_queue(s); | |
207 | /* Put back TS buffer, since it was removed from all queues */ | |
208 | if (s->type == CX18_ENC_STREAM_TYPE_TS) | |
66c2a6b0 | 209 | cx18_stream_put_buf_fw(s, buf); |
ee2d64f5 AW |
210 | } |
211 | wake_up(&cx->dma_waitq); | |
212 | if (s->id != -1) | |
213 | wake_up(&s->waitq); | |
214 | } | |
215 | ||
deed75ed | 216 | static void epu_debug(struct cx18 *cx, struct cx18_in_work_order *order) |
ee2d64f5 AW |
217 | { |
218 | char *p; | |
219 | char *str = order->str; | |
220 | ||
221 | CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str); | |
222 | p = strchr(str, '.'); | |
223 | if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str) | |
224 | CX18_INFO("FW version: %s\n", p - 1); | |
225 | } | |
226 | ||
deed75ed | 227 | static void epu_cmd(struct cx18 *cx, struct cx18_in_work_order *order) |
ee2d64f5 AW |
228 | { |
229 | switch (order->rpu) { | |
230 | case CPU: | |
231 | { | |
232 | switch (order->mb.cmd) { | |
233 | case CX18_EPU_DMA_DONE: | |
234 | epu_dma_done(cx, order); | |
235 | break; | |
236 | case CX18_EPU_DEBUG: | |
237 | epu_debug(cx, order); | |
238 | break; | |
239 | default: | |
240 | CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n", | |
241 | order->mb.cmd); | |
242 | break; | |
243 | } | |
244 | break; | |
245 | } | |
246 | case APU: | |
247 | CX18_WARN("Unknown APU to EPU mailbox command %#0x\n", | |
248 | order->mb.cmd); | |
249 | break; | |
250 | default: | |
251 | break; | |
252 | } | |
253 | } | |
254 | ||
255 | static | |
deed75ed | 256 | void free_in_work_order(struct cx18 *cx, struct cx18_in_work_order *order) |
ee2d64f5 AW |
257 | { |
258 | atomic_set(&order->pending, 0); | |
259 | } | |
260 | ||
deed75ed | 261 | void cx18_in_work_handler(struct work_struct *work) |
ee2d64f5 | 262 | { |
deed75ed AW |
263 | struct cx18_in_work_order *order = |
264 | container_of(work, struct cx18_in_work_order, work); | |
ee2d64f5 AW |
265 | struct cx18 *cx = order->cx; |
266 | epu_cmd(cx, order); | |
deed75ed | 267 | free_in_work_order(cx, order); |
ee2d64f5 AW |
268 | } |
269 | ||
270 | ||
271 | /* | |
272 | * Functions that run in an interrupt handling context | |
273 | */ | |
274 | ||
deed75ed | 275 | static void mb_ack_irq(struct cx18 *cx, struct cx18_in_work_order *order) |
1c1e45d1 | 276 | { |
990c81c8 | 277 | struct cx18_mailbox __iomem *ack_mb; |
ee2d64f5 | 278 | u32 ack_irq, req; |
1c1e45d1 | 279 | |
ee2d64f5 | 280 | switch (order->rpu) { |
1c1e45d1 HV |
281 | case APU: |
282 | ack_irq = IRQ_EPU_TO_APU_ACK; | |
283 | ack_mb = &cx->scb->apu2epu_mb; | |
284 | break; | |
285 | case CPU: | |
286 | ack_irq = IRQ_EPU_TO_CPU_ACK; | |
287 | ack_mb = &cx->scb->cpu2epu_mb; | |
288 | break; | |
289 | default: | |
72c2d6d3 | 290 | CX18_WARN("Unhandled RPU (%d) for command %x ack\n", |
ee2d64f5 AW |
291 | order->rpu, order->mb.cmd); |
292 | return; | |
1c1e45d1 HV |
293 | } |
294 | ||
ee2d64f5 AW |
295 | req = order->mb.request; |
296 | /* Don't ack if the RPU has gotten impatient and timed us out */ | |
297 | if (req != cx18_readl(cx, &ack_mb->request) || | |
72a4f808 | 298 | req == cx18_readl(cx, &ack_mb->ack)) { |
bca11a57 AW |
299 | CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our " |
300 | "incoming %s to EPU mailbox (sequence no. %u) " | |
301 | "while processing\n", | |
302 | rpu_str[order->rpu], rpu_str[order->rpu], req); | |
72a4f808 | 303 | order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC; |
ee2d64f5 | 304 | return; |
72a4f808 | 305 | } |
ee2d64f5 | 306 | cx18_writel(cx, req, &ack_mb->ack); |
f056d29e | 307 | cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq); |
ee2d64f5 AW |
308 | return; |
309 | } | |
310 | ||
deed75ed | 311 | static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order) |
ee2d64f5 AW |
312 | { |
313 | u32 handle, mdl_ack_offset, mdl_ack_count; | |
314 | struct cx18_mailbox *mb; | |
315 | ||
316 | mb = &order->mb; | |
317 | handle = mb->args[0]; | |
318 | mdl_ack_offset = mb->args[1]; | |
319 | mdl_ack_count = mb->args[2]; | |
320 | ||
321 | if (handle == CX18_INVALID_TASK_HANDLE || | |
322 | mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) { | |
72a4f808 | 323 | if ((order->flags & CX18_F_EWO_MB_STALE) == 0) |
ee2d64f5 AW |
324 | mb_ack_irq(cx, order); |
325 | return -1; | |
326 | } | |
327 | ||
328 | cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset, | |
329 | sizeof(struct cx18_mdl_ack) * mdl_ack_count); | |
72a4f808 AW |
330 | |
331 | if ((order->flags & CX18_F_EWO_MB_STALE) == 0) | |
ee2d64f5 AW |
332 | mb_ack_irq(cx, order); |
333 | return 1; | |
334 | } | |
335 | ||
336 | static | |
deed75ed | 337 | int epu_debug_irq(struct cx18 *cx, struct cx18_in_work_order *order) |
ee2d64f5 AW |
338 | { |
339 | u32 str_offset; | |
340 | char *str = order->str; | |
341 | ||
342 | str[0] = '\0'; | |
343 | str_offset = order->mb.args[1]; | |
344 | if (str_offset) { | |
345 | cx18_setup_page(cx, str_offset); | |
346 | cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252); | |
347 | str[252] = '\0'; | |
348 | cx18_setup_page(cx, SCB_OFFSET); | |
349 | } | |
350 | ||
72a4f808 | 351 | if ((order->flags & CX18_F_EWO_MB_STALE) == 0) |
ee2d64f5 AW |
352 | mb_ack_irq(cx, order); |
353 | ||
354 | return str_offset ? 1 : 0; | |
355 | } | |
356 | ||
357 | static inline | |
deed75ed | 358 | int epu_cmd_irq(struct cx18 *cx, struct cx18_in_work_order *order) |
ee2d64f5 AW |
359 | { |
360 | int ret = -1; | |
361 | ||
362 | switch (order->rpu) { | |
363 | case CPU: | |
364 | { | |
365 | switch (order->mb.cmd) { | |
366 | case CX18_EPU_DMA_DONE: | |
72a4f808 | 367 | ret = epu_dma_done_irq(cx, order); |
ee2d64f5 AW |
368 | break; |
369 | case CX18_EPU_DEBUG: | |
72a4f808 | 370 | ret = epu_debug_irq(cx, order); |
ee2d64f5 AW |
371 | break; |
372 | default: | |
373 | CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n", | |
374 | order->mb.cmd); | |
375 | break; | |
376 | } | |
377 | break; | |
378 | } | |
379 | case APU: | |
380 | CX18_WARN("Unknown APU to EPU mailbox command %#0x\n", | |
381 | order->mb.cmd); | |
382 | break; | |
383 | default: | |
384 | break; | |
385 | } | |
386 | return ret; | |
1c1e45d1 HV |
387 | } |
388 | ||
ee2d64f5 | 389 | static inline |
deed75ed | 390 | struct cx18_in_work_order *alloc_in_work_order_irq(struct cx18 *cx) |
ee2d64f5 AW |
391 | { |
392 | int i; | |
deed75ed | 393 | struct cx18_in_work_order *order = NULL; |
ee2d64f5 | 394 | |
deed75ed | 395 | for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++) { |
ee2d64f5 AW |
396 | /* |
397 | * We only need "pending" atomic to inspect its contents, | |
398 | * and need not do a check and set because: | |
399 | * 1. Any work handler thread only clears "pending" and only | |
400 | * on one, particular work order at a time, per handler thread. | |
401 | * 2. "pending" is only set here, and we're serialized because | |
402 | * we're called in an IRQ handler context. | |
403 | */ | |
deed75ed AW |
404 | if (atomic_read(&cx->in_work_order[i].pending) == 0) { |
405 | order = &cx->in_work_order[i]; | |
ee2d64f5 AW |
406 | atomic_set(&order->pending, 1); |
407 | break; | |
408 | } | |
409 | } | |
410 | return order; | |
411 | } | |
412 | ||
413 | void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu) | |
414 | { | |
415 | struct cx18_mailbox __iomem *mb; | |
416 | struct cx18_mailbox *order_mb; | |
deed75ed | 417 | struct cx18_in_work_order *order; |
ee2d64f5 AW |
418 | int submit; |
419 | ||
420 | switch (rpu) { | |
421 | case CPU: | |
422 | mb = &cx->scb->cpu2epu_mb; | |
423 | break; | |
424 | case APU: | |
425 | mb = &cx->scb->apu2epu_mb; | |
426 | break; | |
427 | default: | |
428 | return; | |
429 | } | |
430 | ||
deed75ed | 431 | order = alloc_in_work_order_irq(cx); |
ee2d64f5 AW |
432 | if (order == NULL) { |
433 | CX18_WARN("Unable to find blank work order form to schedule " | |
434 | "incoming mailbox command processing\n"); | |
435 | return; | |
436 | } | |
437 | ||
72a4f808 | 438 | order->flags = 0; |
ee2d64f5 AW |
439 | order->rpu = rpu; |
440 | order_mb = &order->mb; | |
d6c7e5f8 AW |
441 | |
442 | /* mb->cmd and mb->args[0] through mb->args[2] */ | |
443 | cx18_memcpy_fromio(cx, &order_mb->cmd, &mb->cmd, 4 * sizeof(u32)); | |
444 | /* mb->request and mb->ack. N.B. we want to read mb->ack last */ | |
445 | cx18_memcpy_fromio(cx, &order_mb->request, &mb->request, | |
446 | 2 * sizeof(u32)); | |
ee2d64f5 AW |
447 | |
448 | if (order_mb->request == order_mb->ack) { | |
bca11a57 AW |
449 | CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our " |
450 | "incoming %s to EPU mailbox (sequence no. %u)" | |
451 | "\n", | |
452 | rpu_str[rpu], rpu_str[rpu], order_mb->request); | |
50299994 AW |
453 | if (cx18_debug & CX18_DBGFLG_WARN) |
454 | dump_mb(cx, order_mb, "incoming"); | |
72a4f808 | 455 | order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT; |
ee2d64f5 AW |
456 | } |
457 | ||
458 | /* | |
459 | * Individual EPU command processing is responsible for ack-ing | |
460 | * a non-stale mailbox as soon as possible | |
461 | */ | |
72a4f808 | 462 | submit = epu_cmd_irq(cx, order); |
ee2d64f5 | 463 | if (submit > 0) { |
deed75ed | 464 | queue_work(cx->in_work_queue, &order->work); |
ee2d64f5 AW |
465 | } |
466 | } | |
467 | ||
468 | ||
469 | /* | |
470 | * Functions called from a non-interrupt, non work_queue context | |
471 | */ | |
472 | ||
1c1e45d1 HV |
473 | static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[]) |
474 | { | |
475 | const struct cx18_api_info *info = find_api_info(cmd); | |
ac504417 | 476 | u32 state, irq, req, ack, err; |
990c81c8 | 477 | struct cx18_mailbox __iomem *mb; |
ac504417 | 478 | u32 __iomem *xpu_state; |
1c1e45d1 | 479 | wait_queue_head_t *waitq; |
72c2d6d3 | 480 | struct mutex *mb_lock; |
5f0a3cfc | 481 | unsigned long int t0, timeout, ret; |
1c1e45d1 | 482 | int i; |
50299994 | 483 | char argstr[MAX_MB_ARGUMENTS*11+1]; |
5f0a3cfc | 484 | DEFINE_WAIT(w); |
1c1e45d1 HV |
485 | |
486 | if (info == NULL) { | |
487 | CX18_WARN("unknown cmd %x\n", cmd); | |
488 | return -EINVAL; | |
489 | } | |
490 | ||
50299994 AW |
491 | if (cx18_debug & CX18_DBGFLG_API) { /* only call u32arr2hex if needed */ |
492 | if (cmd == CX18_CPU_DE_SET_MDL) { | |
493 | if (cx18_debug & CX18_DBGFLG_HIGHVOL) | |
494 | CX18_DEBUG_HI_API("%s\tcmd %#010x args%s\n", | |
495 | info->name, cmd, | |
496 | u32arr2hex(data, args, argstr)); | |
497 | } else | |
498 | CX18_DEBUG_API("%s\tcmd %#010x args%s\n", | |
499 | info->name, cmd, | |
500 | u32arr2hex(data, args, argstr)); | |
501 | } | |
72c2d6d3 AW |
502 | |
503 | switch (info->rpu) { | |
504 | case APU: | |
505 | waitq = &cx->mb_apu_waitq; | |
506 | mb_lock = &cx->epu2apu_mb_lock; | |
ac504417 AW |
507 | irq = IRQ_EPU_TO_APU; |
508 | mb = &cx->scb->epu2apu_mb; | |
509 | xpu_state = &cx->scb->apu_state; | |
72c2d6d3 AW |
510 | break; |
511 | case CPU: | |
512 | waitq = &cx->mb_cpu_waitq; | |
513 | mb_lock = &cx->epu2cpu_mb_lock; | |
ac504417 AW |
514 | irq = IRQ_EPU_TO_CPU; |
515 | mb = &cx->scb->epu2cpu_mb; | |
516 | xpu_state = &cx->scb->cpu_state; | |
72c2d6d3 AW |
517 | break; |
518 | default: | |
519 | CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu); | |
520 | return -EINVAL; | |
521 | } | |
522 | ||
523 | mutex_lock(mb_lock); | |
ac504417 AW |
524 | /* |
525 | * Wait for an in-use mailbox to complete | |
526 | * | |
527 | * If the XPU is responding with Ack's, the mailbox shouldn't be in | |
528 | * a busy state, since we serialize access to it on our end. | |
529 | * | |
530 | * If the wait for ack after sending a previous command was interrupted | |
531 | * by a signal, we may get here and find a busy mailbox. After waiting, | |
532 | * mark it "not busy" from our end, if the XPU hasn't ack'ed it still. | |
533 | */ | |
534 | state = cx18_readl(cx, xpu_state); | |
535 | req = cx18_readl(cx, &mb->request); | |
2bb49f1b | 536 | timeout = msecs_to_jiffies(10); |
ac504417 AW |
537 | ret = wait_event_timeout(*waitq, |
538 | (ack = cx18_readl(cx, &mb->ack)) == req, | |
330c6ec8 | 539 | timeout); |
ac504417 AW |
540 | if (req != ack) { |
541 | /* waited long enough, make the mbox "not busy" from our end */ | |
542 | cx18_writel(cx, req, &mb->ack); | |
543 | CX18_ERR("mbox was found stuck busy when setting up for %s; " | |
544 | "clearing busy and trying to proceed\n", info->name); | |
330c6ec8 | 545 | } else if (ret != timeout) |
2bb49f1b AW |
546 | CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n", |
547 | jiffies_to_msecs(timeout-ret)); | |
ac504417 AW |
548 | |
549 | /* Build the outgoing mailbox */ | |
550 | req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1; | |
1c1e45d1 | 551 | |
b1526421 | 552 | cx18_writel(cx, cmd, &mb->cmd); |
1c1e45d1 | 553 | for (i = 0; i < args; i++) |
b1526421 AW |
554 | cx18_writel(cx, data[i], &mb->args[i]); |
555 | cx18_writel(cx, 0, &mb->error); | |
556 | cx18_writel(cx, req, &mb->request); | |
ac504417 | 557 | cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */ |
1c1e45d1 | 558 | |
330c6ec8 AW |
559 | /* |
560 | * Notify the XPU and wait for it to send an Ack back | |
330c6ec8 | 561 | */ |
2bb49f1b | 562 | timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20); |
ac504417 AW |
563 | |
564 | CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n", | |
565 | irq, info->name); | |
5f0a3cfc AW |
566 | |
567 | /* So we don't miss the wakeup, prepare to wait before notifying fw */ | |
568 | prepare_to_wait(waitq, &w, TASK_UNINTERRUPTIBLE); | |
f056d29e | 569 | cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq); |
1c1e45d1 | 570 | |
5f0a3cfc AW |
571 | t0 = jiffies; |
572 | ack = cx18_readl(cx, &mb->ack); | |
573 | if (ack != req) { | |
574 | schedule_timeout(timeout); | |
575 | ret = jiffies - t0; | |
576 | ack = cx18_readl(cx, &mb->ack); | |
577 | } else { | |
578 | ret = jiffies - t0; | |
579 | } | |
580 | ||
581 | finish_wait(waitq, &w); | |
2bb49f1b | 582 | |
5f0a3cfc | 583 | if (req != ack) { |
72c2d6d3 | 584 | mutex_unlock(mb_lock); |
5f0a3cfc AW |
585 | if (ret >= timeout) { |
586 | /* Timed out */ | |
587 | CX18_DEBUG_WARN("sending %s timed out waiting %d msecs " | |
588 | "for RPU acknowledgement\n", | |
589 | info->name, jiffies_to_msecs(ret)); | |
590 | } else { | |
591 | CX18_DEBUG_WARN("woken up before mailbox ack was ready " | |
592 | "after submitting %s to RPU. only " | |
593 | "waited %d msecs on req %u but awakened" | |
594 | " with unmatched ack %u\n", | |
595 | info->name, | |
596 | jiffies_to_msecs(ret), | |
597 | req, ack); | |
598 | } | |
1c1e45d1 | 599 | return -EINVAL; |
330c6ec8 AW |
600 | } |
601 | ||
5f0a3cfc AW |
602 | if (ret >= timeout) |
603 | CX18_DEBUG_WARN("failed to be awakened upon RPU acknowledgment " | |
604 | "sending %s; timed out waiting %d msecs\n", | |
605 | info->name, jiffies_to_msecs(ret)); | |
606 | else | |
330c6ec8 | 607 | CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n", |
5f0a3cfc | 608 | jiffies_to_msecs(ret), info->name); |
72c2d6d3 | 609 | |
ac504417 | 610 | /* Collect data returned by the XPU */ |
1c1e45d1 | 611 | for (i = 0; i < MAX_MB_ARGUMENTS; i++) |
b1526421 AW |
612 | data[i] = cx18_readl(cx, &mb->args[i]); |
613 | err = cx18_readl(cx, &mb->error); | |
72c2d6d3 | 614 | mutex_unlock(mb_lock); |
ac504417 AW |
615 | |
616 | /* | |
617 | * Wait for XPU to perform extra actions for the caller in some cases. | |
618 | * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all buffers | |
619 | * back in a burst shortly thereafter | |
620 | */ | |
72c2d6d3 | 621 | if (info->flags & API_SLOW) |
1c1e45d1 | 622 | cx18_msleep_timeout(300, 0); |
ac504417 | 623 | |
1c1e45d1 HV |
624 | if (err) |
625 | CX18_DEBUG_API("mailbox error %08x for command %s\n", err, | |
626 | info->name); | |
627 | return err ? -EIO : 0; | |
628 | } | |
629 | ||
630 | int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[]) | |
631 | { | |
ac504417 | 632 | return cx18_api_call(cx, cmd, args, data); |
1c1e45d1 HV |
633 | } |
634 | ||
635 | static int cx18_set_filter_param(struct cx18_stream *s) | |
636 | { | |
637 | struct cx18 *cx = s->cx; | |
638 | u32 mode; | |
639 | int ret; | |
640 | ||
641 | mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0); | |
642 | ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4, | |
643 | s->handle, 1, mode, cx->spatial_strength); | |
644 | mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0); | |
645 | ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4, | |
646 | s->handle, 0, mode, cx->temporal_strength); | |
647 | ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4, | |
648 | s->handle, 2, cx->filter_mode >> 2, 0); | |
649 | return ret; | |
650 | } | |
651 | ||
652 | int cx18_api_func(void *priv, u32 cmd, int in, int out, | |
653 | u32 data[CX2341X_MBOX_MAX_DATA]) | |
654 | { | |
50b86bac AW |
655 | struct cx18_api_func_private *api_priv = priv; |
656 | struct cx18 *cx = api_priv->cx; | |
657 | struct cx18_stream *s = api_priv->s; | |
1c1e45d1 HV |
658 | |
659 | switch (cmd) { | |
660 | case CX2341X_ENC_SET_OUTPUT_PORT: | |
661 | return 0; | |
662 | case CX2341X_ENC_SET_FRAME_RATE: | |
663 | return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6, | |
664 | s->handle, 0, 0, 0, 0, data[0]); | |
665 | case CX2341X_ENC_SET_FRAME_SIZE: | |
666 | return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3, | |
667 | s->handle, data[1], data[0]); | |
668 | case CX2341X_ENC_SET_STREAM_TYPE: | |
669 | return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2, | |
670 | s->handle, data[0]); | |
671 | case CX2341X_ENC_SET_ASPECT_RATIO: | |
672 | return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2, | |
673 | s->handle, data[0]); | |
674 | ||
675 | case CX2341X_ENC_SET_GOP_PROPERTIES: | |
676 | return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3, | |
677 | s->handle, data[0], data[1]); | |
678 | case CX2341X_ENC_SET_GOP_CLOSURE: | |
679 | return 0; | |
680 | case CX2341X_ENC_SET_AUDIO_PROPERTIES: | |
681 | return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2, | |
682 | s->handle, data[0]); | |
683 | case CX2341X_ENC_MUTE_AUDIO: | |
684 | return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2, | |
685 | s->handle, data[0]); | |
686 | case CX2341X_ENC_SET_BIT_RATE: | |
687 | return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5, | |
688 | s->handle, data[0], data[1], data[2], data[3]); | |
689 | case CX2341X_ENC_MUTE_VIDEO: | |
690 | return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, | |
691 | s->handle, data[0]); | |
692 | case CX2341X_ENC_SET_FRAME_DROP_RATE: | |
693 | return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2, | |
694 | s->handle, data[0]); | |
695 | case CX2341X_ENC_MISC: | |
696 | return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4, | |
697 | s->handle, data[0], data[1], data[2]); | |
698 | case CX2341X_ENC_SET_DNR_FILTER_MODE: | |
699 | cx->filter_mode = (data[0] & 3) | (data[1] << 2); | |
700 | return cx18_set_filter_param(s); | |
701 | case CX2341X_ENC_SET_DNR_FILTER_PROPS: | |
702 | cx->spatial_strength = data[0]; | |
703 | cx->temporal_strength = data[1]; | |
704 | return cx18_set_filter_param(s); | |
705 | case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE: | |
706 | return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3, | |
707 | s->handle, data[0], data[1]); | |
708 | case CX2341X_ENC_SET_CORING_LEVELS: | |
709 | return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5, | |
710 | s->handle, data[0], data[1], data[2], data[3]); | |
711 | } | |
712 | CX18_WARN("Unknown cmd %x\n", cmd); | |
713 | return 0; | |
714 | } | |
715 | ||
716 | int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS], | |
717 | u32 cmd, int args, ...) | |
718 | { | |
719 | va_list ap; | |
720 | int i; | |
721 | ||
722 | va_start(ap, args); | |
723 | for (i = 0; i < args; i++) | |
724 | data[i] = va_arg(ap, u32); | |
725 | va_end(ap); | |
726 | return cx18_api(cx, cmd, args, data); | |
727 | } | |
728 | ||
729 | int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...) | |
730 | { | |
731 | u32 data[MAX_MB_ARGUMENTS]; | |
732 | va_list ap; | |
733 | int i; | |
734 | ||
735 | if (cx == NULL) { | |
736 | CX18_ERR("cx == NULL (cmd=%x)\n", cmd); | |
737 | return 0; | |
738 | } | |
739 | if (args > MAX_MB_ARGUMENTS) { | |
740 | CX18_ERR("args too big (cmd=%x)\n", cmd); | |
741 | args = MAX_MB_ARGUMENTS; | |
742 | } | |
743 | va_start(ap, args); | |
744 | for (i = 0; i < args; i++) | |
745 | data[i] = va_arg(ap, u32); | |
746 | va_end(ap); | |
747 | return cx18_api(cx, cmd, args, data); | |
748 | } |