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V4L/DVB (9803): cx18: Increment version number due to siginificant buffering changes
[deliverable/linux.git] / drivers / media / video / cx18 / cx18-mailbox.c
CommitLineData
1c1e45d1
HV		 1/*
2 * cx18 mailbox functions
3 *
4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
1ed9dcc8 5 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
1c1e45d1
HV		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20 * 02111-1307 USA
21 */
22
23#include <stdarg.h>
24
25#include "cx18-driver.h"
b1526421 26#include "cx18-io.h"
1c1e45d1
HV		 27#include "cx18-scb.h"
28#include "cx18-irq.h"
29#include "cx18-mailbox.h"
ee2d64f5
AW		 30#include "cx18-queue.h"
31#include "cx18-streams.h"
32
33static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
1c1e45d1
HV		 34
35#define API_FAST (1 << 2) /* Short timeout */
36#define API_SLOW (1 << 3) /* Additional 300ms timeout */
37
1c1e45d1
HV		 38struct cx18_api_info {
39 u32 cmd;
40 u8 flags; /* Flags, see above */
41 u8 rpu; /* Processing unit */
42 const char *name; /* The name of the command */
43};
44
45#define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
46
47static const struct cx18_api_info api_info[] = {
48 /* MPEG encoder API */
49 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
50 API_ENTRY(CPU, CX18_EPU_DEBUG, 0),
51 API_ENTRY(CPU, CX18_CREATE_TASK, 0),
52 API_ENTRY(CPU, CX18_DESTROY_TASK, 0),
53 API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW),
54 API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW),
55 API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0),
56 API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0),
57 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
58 API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0),
59 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0),
60 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0),
61 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0),
62 API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0),
63 API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0),
64 API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0),
65 API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0),
66 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0),
67 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0),
68 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0),
69 API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0),
70 API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW),
71 API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0),
72 API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0),
73 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0),
74 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0),
75 API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0),
76 API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0),
77 API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0),
78 API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0),
79 API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0),
80 API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0),
81 API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0),
82 API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0),
83 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0),
84 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST),
81cb727d 85 API_ENTRY(CPU, CX18_APU_RESETAI, API_FAST),
4e6b6104 86 API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW),
1c1e45d1
HV		 87 API_ENTRY(0, 0, 0),
88};
89
90static const struct cx18_api_info *find_api_info(u32 cmd)
91{
92 int i;
93
94 for (i = 0; api_info[i].cmd; i++)
95 if (api_info[i].cmd == cmd)
96 return &api_info[i];
97 return NULL;
98}
99
ee2d64f5
AW		 100static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
101{
102 char argstr[MAX_MB_ARGUMENTS*11+1];
103 char *p;
104 int i;
105
106 if (!(cx18_debug & CX18_DBGFLG_API))
107 return;
108
109 for (i = 0, p = argstr; i < MAX_MB_ARGUMENTS; i++, p += 11) {
110 /* kernel snprintf() appends '\0' always */
111 snprintf(p, 12, " %#010x", mb->args[i]);
112 }
113 CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s"
114 "\n", name, mb->request, mb->ack, mb->cmd, mb->error, argstr);
115}
116
117
118/*
119 * Functions that run in a work_queue work handling context
120 */
121
122static void epu_dma_done(struct cx18 *cx, struct cx18_epu_work_order *order)
123{
bca11a57 124 u32 handle, mdl_ack_count, id;
ee2d64f5
AW		 125 struct cx18_mailbox *mb;
126 struct cx18_mdl_ack *mdl_ack;
127 struct cx18_stream *s;
128 struct cx18_buffer *buf;
129 int i;
130
131 mb = &order->mb;
132 handle = mb->args[0];
133 s = cx18_handle_to_stream(cx, handle);
134
135 if (s == NULL) {
136 CX18_WARN("Got DMA done notification for unknown/inactive"
bca11a57
AW		 137 " handle %d, %s mailbox seq no %d\n", handle,
138 (order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) ?
139 "stale" : "good", mb->request);
ee2d64f5
AW		 140 return;
141 }
142
143 mdl_ack_count = mb->args[2];
144 mdl_ack = order->mdl_ack;
145 for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
bca11a57
AW		 146 id = mdl_ack->id;
147 /*
148 * Simple integrity check for processing a stale (and possibly
149 * inconsistent mailbox): make sure the buffer id is in the
150 * valid range for the stream.
151 *
152 * We go through the trouble of dealing with stale mailboxes
153 * because most of the time, the mailbox data is still valid and
154 * unchanged (and in practice the firmware ping-pongs the
155 * two mdl_ack buffers so mdl_acks are not stale).
156 *
157 * There are occasions when we get a half changed mailbox,
158 * which this check catches for a handle & id mismatch. If the
159 * handle and id do correspond, the worst case is that we
160 * completely lost the old buffer, but pick up the new buffer
161 * early (but the new mdl_ack is guaranteed to be good in this
162 * case as the firmware wouldn't point us to a new mdl_ack until
163 * it's filled in).
164 *
165 * cx18_queue_get buf() will detect the lost buffers
166 * and put them back in rotation eventually.
167 */
168 if ((order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) &&
169 !(id >= s->mdl_offset &&
170 id < (s->mdl_offset + s->buffers))) {
171 CX18_WARN("Fell behind! Ignoring stale mailbox with "
172 " inconsistent data. Lost buffer for mailbox "
173 "seq no %d\n", mb->request);
174 break;
175 }
176 buf = cx18_queue_get_buf(s, id, mdl_ack->data_used);
177 CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, id);
ee2d64f5
AW		 178 if (buf == NULL) {
179 CX18_WARN("Could not find buf %d for stream %s\n",
bca11a57 180 id, s->name);
ee2d64f5
AW		 181 continue;
182 }
183
184 cx18_buf_sync_for_cpu(s, buf);
185 if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) {
186 CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n",
187 buf->bytesused);
188
189 dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
190 buf->bytesused);
191
66c2a6b0 192 cx18_stream_put_buf_fw(s, buf);
ee2d64f5
AW		 193 } else
194 set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags);
195 }
196 wake_up(&cx->dma_waitq);
197 if (s->id != -1)
198 wake_up(&s->waitq);
199}
200
201static void epu_debug(struct cx18 *cx, struct cx18_epu_work_order *order)
202{
203 char *p;
204 char *str = order->str;
205
206 CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
207 p = strchr(str, '.');
208 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
209 CX18_INFO("FW version: %s\n", p - 1);
210}
211
212static void epu_cmd(struct cx18 *cx, struct cx18_epu_work_order *order)
213{
214 switch (order->rpu) {
215 case CPU:
216 {
217 switch (order->mb.cmd) {
218 case CX18_EPU_DMA_DONE:
219 epu_dma_done(cx, order);
220 break;
221 case CX18_EPU_DEBUG:
222 epu_debug(cx, order);
223 break;
224 default:
225 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
226 order->mb.cmd);
227 break;
228 }
229 break;
230 }
231 case APU:
232 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
233 order->mb.cmd);
234 break;
235 default:
236 break;
237 }
238}
239
240static
241void free_epu_work_order(struct cx18 *cx, struct cx18_epu_work_order *order)
242{
243 atomic_set(&order->pending, 0);
244}
245
246void cx18_epu_work_handler(struct work_struct *work)
247{
248 struct cx18_epu_work_order *order =
249 container_of(work, struct cx18_epu_work_order, work);
250 struct cx18 *cx = order->cx;
251 epu_cmd(cx, order);
252 free_epu_work_order(cx, order);
253}
254
255
256/*
257 * Functions that run in an interrupt handling context
258 */
259
72a4f808 260static void mb_ack_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
1c1e45d1 261{
990c81c8 262 struct cx18_mailbox __iomem *ack_mb;
ee2d64f5 263 u32 ack_irq, req;
1c1e45d1 264
ee2d64f5 265 switch (order->rpu) {
1c1e45d1
HV		 266 case APU:
267 ack_irq = IRQ_EPU_TO_APU_ACK;
268 ack_mb = &cx->scb->apu2epu_mb;
269 break;
270 case CPU:
271 ack_irq = IRQ_EPU_TO_CPU_ACK;
272 ack_mb = &cx->scb->cpu2epu_mb;
273 break;
274 default:
72c2d6d3 275 CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
ee2d64f5
AW		 276 order->rpu, order->mb.cmd);
277 return;
1c1e45d1
HV		 278 }
279
ee2d64f5
AW		 280 req = order->mb.request;
281 /* Don't ack if the RPU has gotten impatient and timed us out */
282 if (req != cx18_readl(cx, &ack_mb->request) ||
72a4f808 283 req == cx18_readl(cx, &ack_mb->ack)) {
bca11a57
AW		 284 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
285 "incoming %s to EPU mailbox (sequence no. %u) "
286 "while processing\n",
287 rpu_str[order->rpu], rpu_str[order->rpu], req);
72a4f808 288 order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
ee2d64f5 289 return;
72a4f808 290 }
ee2d64f5 291 cx18_writel(cx, req, &ack_mb->ack);
f056d29e 292 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
ee2d64f5
AW		 293 return;
294}
295
72a4f808 296static int epu_dma_done_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
ee2d64f5
AW		 297{
298 u32 handle, mdl_ack_offset, mdl_ack_count;
299 struct cx18_mailbox *mb;
300
301 mb = &order->mb;
302 handle = mb->args[0];
303 mdl_ack_offset = mb->args[1];
304 mdl_ack_count = mb->args[2];
305
306 if (handle == CX18_INVALID_TASK_HANDLE ||
307 mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
72a4f808 308 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
ee2d64f5
AW		 309 mb_ack_irq(cx, order);
310 return -1;
311 }
312
313 cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset,
314 sizeof(struct cx18_mdl_ack) * mdl_ack_count);
72a4f808
AW		 315
316 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
ee2d64f5
AW		 317 mb_ack_irq(cx, order);
318 return 1;
319}
320
321static
72a4f808 322int epu_debug_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
ee2d64f5
AW		 323{
324 u32 str_offset;
325 char *str = order->str;
326
327 str[0] = '\0';
328 str_offset = order->mb.args[1];
329 if (str_offset) {
330 cx18_setup_page(cx, str_offset);
331 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
332 str[252] = '\0';
333 cx18_setup_page(cx, SCB_OFFSET);
334 }
335
72a4f808 336 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
ee2d64f5
AW		 337 mb_ack_irq(cx, order);
338
339 return str_offset ? 1 : 0;
340}
341
342static inline
72a4f808 343int epu_cmd_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
ee2d64f5
AW		 344{
345 int ret = -1;
346
347 switch (order->rpu) {
348 case CPU:
349 {
350 switch (order->mb.cmd) {
351 case CX18_EPU_DMA_DONE:
72a4f808 352 ret = epu_dma_done_irq(cx, order);
ee2d64f5
AW		 353 break;
354 case CX18_EPU_DEBUG:
72a4f808 355 ret = epu_debug_irq(cx, order);
ee2d64f5
AW		 356 break;
357 default:
358 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
359 order->mb.cmd);
360 break;
361 }
362 break;
363 }
364 case APU:
365 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
366 order->mb.cmd);
367 break;
368 default:
369 break;
370 }
371 return ret;
1c1e45d1
HV		 372}
373
ee2d64f5
AW		 374static inline
375struct cx18_epu_work_order *alloc_epu_work_order_irq(struct cx18 *cx)
376{
377 int i;
378 struct cx18_epu_work_order *order = NULL;
379
380 for (i = 0; i < CX18_MAX_EPU_WORK_ORDERS; i++) {
381 /*
382 * We only need "pending" atomic to inspect its contents,
383 * and need not do a check and set because:
384 * 1. Any work handler thread only clears "pending" and only
385 * on one, particular work order at a time, per handler thread.
386 * 2. "pending" is only set here, and we're serialized because
387 * we're called in an IRQ handler context.
388 */
389 if (atomic_read(&cx->epu_work_order[i].pending) == 0) {
390 order = &cx->epu_work_order[i];
391 atomic_set(&order->pending, 1);
392 break;
393 }
394 }
395 return order;
396}
397
398void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
399{
400 struct cx18_mailbox __iomem *mb;
401 struct cx18_mailbox *order_mb;
402 struct cx18_epu_work_order *order;
ee2d64f5
AW		 403 int submit;
404
405 switch (rpu) {
406 case CPU:
407 mb = &cx->scb->cpu2epu_mb;
408 break;
409 case APU:
410 mb = &cx->scb->apu2epu_mb;
411 break;
412 default:
413 return;
414 }
415
416 order = alloc_epu_work_order_irq(cx);
417 if (order == NULL) {
418 CX18_WARN("Unable to find blank work order form to schedule "
419 "incoming mailbox command processing\n");
420 return;
421 }
422
72a4f808 423 order->flags = 0;
ee2d64f5
AW		 424 order->rpu = rpu;
425 order_mb = &order->mb;
d6c7e5f8
AW		 426
427 /* mb->cmd and mb->args[0] through mb->args[2] */
428 cx18_memcpy_fromio(cx, &order_mb->cmd, &mb->cmd, 4 * sizeof(u32));
429 /* mb->request and mb->ack. N.B. we want to read mb->ack last */
430 cx18_memcpy_fromio(cx, &order_mb->request, &mb->request,
431 2 * sizeof(u32));
ee2d64f5
AW		 432
433 if (order_mb->request == order_mb->ack) {
bca11a57
AW		 434 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
435 "incoming %s to EPU mailbox (sequence no. %u)"
436 "\n",
437 rpu_str[rpu], rpu_str[rpu], order_mb->request);
ee2d64f5 438 dump_mb(cx, order_mb, "incoming");
72a4f808 439 order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
ee2d64f5
AW		 440 }
441
442 /*
443 * Individual EPU command processing is responsible for ack-ing
444 * a non-stale mailbox as soon as possible
445 */
72a4f808 446 submit = epu_cmd_irq(cx, order);
ee2d64f5 447 if (submit > 0) {
572bfea7 448 queue_work(cx->work_queue, &order->work);
ee2d64f5
AW		 449 }
450}
451
452
453/*
454 * Functions called from a non-interrupt, non work_queue context
455 */
456
1c1e45d1
HV		 457static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
458{
459 const struct cx18_api_info *info = find_api_info(cmd);
ac504417 460 u32 state, irq, req, ack, err;
990c81c8 461 struct cx18_mailbox __iomem *mb;
ac504417 462 u32 __iomem *xpu_state;
1c1e45d1 463 wait_queue_head_t *waitq;
72c2d6d3 464 struct mutex *mb_lock;
330c6ec8 465 long int timeout, ret;
1c1e45d1
HV		 466 int i;
467
468 if (info == NULL) {
469 CX18_WARN("unknown cmd %x\n", cmd);
470 return -EINVAL;
471 }
472
473 if (cmd == CX18_CPU_DE_SET_MDL)
474 CX18_DEBUG_HI_API("%s\n", info->name);
475 else
476 CX18_DEBUG_API("%s\n", info->name);
72c2d6d3
AW		 477
478 switch (info->rpu) {
479 case APU:
480 waitq = &cx->mb_apu_waitq;
481 mb_lock = &cx->epu2apu_mb_lock;
ac504417
AW		 482 irq = IRQ_EPU_TO_APU;
483 mb = &cx->scb->epu2apu_mb;
484 xpu_state = &cx->scb->apu_state;
72c2d6d3
AW		 485 break;
486 case CPU:
487 waitq = &cx->mb_cpu_waitq;
488 mb_lock = &cx->epu2cpu_mb_lock;
ac504417
AW		 489 irq = IRQ_EPU_TO_CPU;
490 mb = &cx->scb->epu2cpu_mb;
491 xpu_state = &cx->scb->cpu_state;
72c2d6d3
AW		 492 break;
493 default:
494 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
495 return -EINVAL;
496 }
497
498 mutex_lock(mb_lock);
ac504417
AW		 499 /*
500 * Wait for an in-use mailbox to complete
501 *
502 * If the XPU is responding with Ack's, the mailbox shouldn't be in
503 * a busy state, since we serialize access to it on our end.
504 *
505 * If the wait for ack after sending a previous command was interrupted
506 * by a signal, we may get here and find a busy mailbox. After waiting,
507 * mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
508 */
509 state = cx18_readl(cx, xpu_state);
510 req = cx18_readl(cx, &mb->request);
2bb49f1b 511 timeout = msecs_to_jiffies(10);
ac504417
AW		 512 ret = wait_event_timeout(*waitq,
513 (ack = cx18_readl(cx, &mb->ack)) == req,
330c6ec8 514 timeout);
ac504417
AW		 515 if (req != ack) {
516 /* waited long enough, make the mbox "not busy" from our end */
517 cx18_writel(cx, req, &mb->ack);
518 CX18_ERR("mbox was found stuck busy when setting up for %s; "
519 "clearing busy and trying to proceed\n", info->name);
330c6ec8 520 } else if (ret != timeout)
2bb49f1b
AW		 521 CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n",
522 jiffies_to_msecs(timeout-ret));
ac504417
AW		 523
524 /* Build the outgoing mailbox */
525 req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
1c1e45d1 526
b1526421 527 cx18_writel(cx, cmd, &mb->cmd);
1c1e45d1 528 for (i = 0; i < args; i++)
b1526421
AW		 529 cx18_writel(cx, data[i], &mb->args[i]);
530 cx18_writel(cx, 0, &mb->error);
531 cx18_writel(cx, req, &mb->request);
ac504417 532 cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
1c1e45d1 533
330c6ec8
AW		 534 /*
535 * Notify the XPU and wait for it to send an Ack back
330c6ec8 536 */
2bb49f1b 537 timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20);
ac504417
AW		 538
539 CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
540 irq, info->name);
f056d29e 541 cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
1c1e45d1 542
330c6ec8 543 ret = wait_event_timeout(
72c2d6d3
AW		 544 *waitq,
545 cx18_readl(cx, &mb->ack) == cx18_readl(cx, &mb->request),
330c6ec8 546 timeout);
2bb49f1b 547
ac504417 548 if (ret == 0) {
72c2d6d3 549 /* Timed out */
72c2d6d3 550 mutex_unlock(mb_lock);
ec984f43
AW		 551 CX18_DEBUG_WARN("sending %s timed out waiting %d msecs for RPU "
552 "acknowledgement\n",
553 info->name, jiffies_to_msecs(timeout));
1c1e45d1 554 return -EINVAL;
330c6ec8
AW		 555 }
556
330c6ec8
AW		 557 if (ret != timeout)
558 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
2bb49f1b 559 jiffies_to_msecs(timeout-ret), info->name);
72c2d6d3 560
ac504417 561 /* Collect data returned by the XPU */
1c1e45d1 562 for (i = 0; i < MAX_MB_ARGUMENTS; i++)
b1526421
AW		 563 data[i] = cx18_readl(cx, &mb->args[i]);
564 err = cx18_readl(cx, &mb->error);
72c2d6d3 565 mutex_unlock(mb_lock);
ac504417
AW		 566
567 /*
568 * Wait for XPU to perform extra actions for the caller in some cases.
569 * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all buffers
570 * back in a burst shortly thereafter
571 */
72c2d6d3 572 if (info->flags & API_SLOW)
1c1e45d1 573 cx18_msleep_timeout(300, 0);
ac504417 574
1c1e45d1
HV		 575 if (err)
576 CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
577 info->name);
578 return err ? -EIO : 0;
579}
580
581int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
582{
ac504417 583 return cx18_api_call(cx, cmd, args, data);
1c1e45d1
HV		 584}
585
586static int cx18_set_filter_param(struct cx18_stream *s)
587{
588 struct cx18 *cx = s->cx;
589 u32 mode;
590 int ret;
591
592 mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
593 ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
594 s->handle, 1, mode, cx->spatial_strength);
595 mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
596 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
597 s->handle, 0, mode, cx->temporal_strength);
598 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
599 s->handle, 2, cx->filter_mode >> 2, 0);
600 return ret;
601}
602
603int cx18_api_func(void *priv, u32 cmd, int in, int out,
604 u32 data[CX2341X_MBOX_MAX_DATA])
605{
606 struct cx18 *cx = priv;
607 struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_MPG];
608
609 switch (cmd) {
610 case CX2341X_ENC_SET_OUTPUT_PORT:
611 return 0;
612 case CX2341X_ENC_SET_FRAME_RATE:
613 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
614 s->handle, 0, 0, 0, 0, data[0]);
615 case CX2341X_ENC_SET_FRAME_SIZE:
616 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
617 s->handle, data[1], data[0]);
618 case CX2341X_ENC_SET_STREAM_TYPE:
619 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
620 s->handle, data[0]);
621 case CX2341X_ENC_SET_ASPECT_RATIO:
622 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
623 s->handle, data[0]);
624
625 case CX2341X_ENC_SET_GOP_PROPERTIES:
626 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
627 s->handle, data[0], data[1]);
628 case CX2341X_ENC_SET_GOP_CLOSURE:
629 return 0;
630 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
631 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
632 s->handle, data[0]);
633 case CX2341X_ENC_MUTE_AUDIO:
634 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
635 s->handle, data[0]);
636 case CX2341X_ENC_SET_BIT_RATE:
637 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
638 s->handle, data[0], data[1], data[2], data[3]);
639 case CX2341X_ENC_MUTE_VIDEO:
640 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
641 s->handle, data[0]);
642 case CX2341X_ENC_SET_FRAME_DROP_RATE:
643 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
644 s->handle, data[0]);
645 case CX2341X_ENC_MISC:
646 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
647 s->handle, data[0], data[1], data[2]);
648 case CX2341X_ENC_SET_DNR_FILTER_MODE:
649 cx->filter_mode = (data[0] & 3) | (data[1] << 2);
650 return cx18_set_filter_param(s);
651 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
652 cx->spatial_strength = data[0];
653 cx->temporal_strength = data[1];
654 return cx18_set_filter_param(s);
655 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
656 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
657 s->handle, data[0], data[1]);
658 case CX2341X_ENC_SET_CORING_LEVELS:
659 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
660 s->handle, data[0], data[1], data[2], data[3]);
661 }
662 CX18_WARN("Unknown cmd %x\n", cmd);
663 return 0;
664}
665
666int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
667 u32 cmd, int args, ...)
668{
669 va_list ap;
670 int i;
671
672 va_start(ap, args);
673 for (i = 0; i < args; i++)
674 data[i] = va_arg(ap, u32);
675 va_end(ap);
676 return cx18_api(cx, cmd, args, data);
677}
678
679int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
680{
681 u32 data[MAX_MB_ARGUMENTS];
682 va_list ap;
683 int i;
684
685 if (cx == NULL) {
686 CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
687 return 0;
688 }
689 if (args > MAX_MB_ARGUMENTS) {
690 CX18_ERR("args too big (cmd=%x)\n", cmd);
691 args = MAX_MB_ARGUMENTS;
692 }
693 va_start(ap, args);
694 for (i = 0; i < args; i++)
695 data[i] = va_arg(ap, u32);
696 va_end(ap);
697 return cx18_api(cx, cmd, args, data);
698}
Linux kernel - Deliverables
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