Commit | Line | Data |
---|---|---|
b1b81f1d ST |
1 | /* |
2 | * | |
3 | * Support for a cx23417 mpeg encoder via cx23885 host port. | |
4 | * | |
f8de18d4 | 5 | * (c) 2004 Jelle Foks <jelle@foks.us> |
b1b81f1d | 6 | * (c) 2004 Gerd Knorr <kraxel@bytesex.org> |
6d897616 | 7 | * (c) 2008 Steven Toth <stoth@linuxtv.org> |
b1b81f1d ST |
8 | * - CX23885/7/8 support |
9 | * | |
631dd1a8 | 10 | * Includes parts from the ivtv driver <http://sourceforge.net/projects/ivtv/> |
b1b81f1d ST |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | */ | |
26 | ||
27 | #include <linux/module.h> | |
28 | #include <linux/moduleparam.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/fs.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/device.h> | |
33 | #include <linux/firmware.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
b1b81f1d | 35 | #include <media/v4l2-common.h> |
35ea11ff | 36 | #include <media/v4l2-ioctl.h> |
b1b81f1d ST |
37 | #include <media/cx2341x.h> |
38 | ||
39 | #include "cx23885.h" | |
74618244 | 40 | #include "cx23885-ioctl.h" |
b1b81f1d ST |
41 | |
42 | #define CX23885_FIRM_IMAGE_SIZE 376836 | |
43 | #define CX23885_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw" | |
44 | ||
45 | static unsigned int mpegbufs = 32; | |
46 | module_param(mpegbufs, int, 0644); | |
47 | MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32"); | |
48 | static unsigned int mpeglines = 32; | |
49 | module_param(mpeglines, int, 0644); | |
50 | MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32"); | |
51 | static unsigned int mpeglinesize = 512; | |
52 | module_param(mpeglinesize, int, 0644); | |
53 | MODULE_PARM_DESC(mpeglinesize, | |
54 | "number of bytes in each line of an MPEG buffer, range 512-1024"); | |
55 | ||
56 | static unsigned int v4l_debug; | |
57 | module_param(v4l_debug, int, 0644); | |
58 | MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages"); | |
59 | ||
60 | #define dprintk(level, fmt, arg...)\ | |
61 | do { if (v4l_debug >= level) \ | |
ca4e771f MK |
62 | printk(KERN_DEBUG "%s: " fmt, \ |
63 | (dev) ? dev->name : "cx23885[?]", ## arg); \ | |
b1b81f1d ST |
64 | } while (0) |
65 | ||
66 | static struct cx23885_tvnorm cx23885_tvnorms[] = { | |
67 | { | |
68 | .name = "NTSC-M", | |
69 | .id = V4L2_STD_NTSC_M, | |
70 | }, { | |
71 | .name = "NTSC-JP", | |
72 | .id = V4L2_STD_NTSC_M_JP, | |
73 | }, { | |
74 | .name = "PAL-BG", | |
75 | .id = V4L2_STD_PAL_BG, | |
76 | }, { | |
77 | .name = "PAL-DK", | |
78 | .id = V4L2_STD_PAL_DK, | |
79 | }, { | |
80 | .name = "PAL-I", | |
81 | .id = V4L2_STD_PAL_I, | |
82 | }, { | |
83 | .name = "PAL-M", | |
84 | .id = V4L2_STD_PAL_M, | |
85 | }, { | |
86 | .name = "PAL-N", | |
87 | .id = V4L2_STD_PAL_N, | |
88 | }, { | |
89 | .name = "PAL-Nc", | |
90 | .id = V4L2_STD_PAL_Nc, | |
91 | }, { | |
92 | .name = "PAL-60", | |
93 | .id = V4L2_STD_PAL_60, | |
94 | }, { | |
95 | .name = "SECAM-L", | |
96 | .id = V4L2_STD_SECAM_L, | |
97 | }, { | |
98 | .name = "SECAM-DK", | |
99 | .id = V4L2_STD_SECAM_DK, | |
100 | } | |
101 | }; | |
102 | ||
103 | /* ------------------------------------------------------------------ */ | |
104 | enum cx23885_capture_type { | |
105 | CX23885_MPEG_CAPTURE, | |
106 | CX23885_RAW_CAPTURE, | |
107 | CX23885_RAW_PASSTHRU_CAPTURE | |
108 | }; | |
109 | enum cx23885_capture_bits { | |
110 | CX23885_RAW_BITS_NONE = 0x00, | |
111 | CX23885_RAW_BITS_YUV_CAPTURE = 0x01, | |
112 | CX23885_RAW_BITS_PCM_CAPTURE = 0x02, | |
113 | CX23885_RAW_BITS_VBI_CAPTURE = 0x04, | |
114 | CX23885_RAW_BITS_PASSTHRU_CAPTURE = 0x08, | |
115 | CX23885_RAW_BITS_TO_HOST_CAPTURE = 0x10 | |
116 | }; | |
117 | enum cx23885_capture_end { | |
118 | CX23885_END_AT_GOP, /* stop at the end of gop, generate irq */ | |
119 | CX23885_END_NOW, /* stop immediately, no irq */ | |
120 | }; | |
121 | enum cx23885_framerate { | |
122 | CX23885_FRAMERATE_NTSC_30, /* NTSC: 30fps */ | |
123 | CX23885_FRAMERATE_PAL_25 /* PAL: 25fps */ | |
124 | }; | |
125 | enum cx23885_stream_port { | |
126 | CX23885_OUTPUT_PORT_MEMORY, | |
127 | CX23885_OUTPUT_PORT_STREAMING, | |
128 | CX23885_OUTPUT_PORT_SERIAL | |
129 | }; | |
130 | enum cx23885_data_xfer_status { | |
131 | CX23885_MORE_BUFFERS_FOLLOW, | |
132 | CX23885_LAST_BUFFER, | |
133 | }; | |
134 | enum cx23885_picture_mask { | |
135 | CX23885_PICTURE_MASK_NONE, | |
136 | CX23885_PICTURE_MASK_I_FRAMES, | |
137 | CX23885_PICTURE_MASK_I_P_FRAMES = 0x3, | |
138 | CX23885_PICTURE_MASK_ALL_FRAMES = 0x7, | |
139 | }; | |
140 | enum cx23885_vbi_mode_bits { | |
141 | CX23885_VBI_BITS_SLICED, | |
142 | CX23885_VBI_BITS_RAW, | |
143 | }; | |
144 | enum cx23885_vbi_insertion_bits { | |
145 | CX23885_VBI_BITS_INSERT_IN_XTENSION_USR_DATA, | |
146 | CX23885_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1, | |
147 | CX23885_VBI_BITS_SEPARATE_STREAM = 0x2 << 1, | |
148 | CX23885_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1, | |
149 | CX23885_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1, | |
150 | }; | |
151 | enum cx23885_dma_unit { | |
152 | CX23885_DMA_BYTES, | |
153 | CX23885_DMA_FRAMES, | |
154 | }; | |
155 | enum cx23885_dma_transfer_status_bits { | |
156 | CX23885_DMA_TRANSFER_BITS_DONE = 0x01, | |
157 | CX23885_DMA_TRANSFER_BITS_ERROR = 0x04, | |
158 | CX23885_DMA_TRANSFER_BITS_LL_ERROR = 0x10, | |
159 | }; | |
160 | enum cx23885_pause { | |
161 | CX23885_PAUSE_ENCODING, | |
162 | CX23885_RESUME_ENCODING, | |
163 | }; | |
164 | enum cx23885_copyright { | |
165 | CX23885_COPYRIGHT_OFF, | |
166 | CX23885_COPYRIGHT_ON, | |
167 | }; | |
168 | enum cx23885_notification_type { | |
169 | CX23885_NOTIFICATION_REFRESH, | |
170 | }; | |
171 | enum cx23885_notification_status { | |
172 | CX23885_NOTIFICATION_OFF, | |
173 | CX23885_NOTIFICATION_ON, | |
174 | }; | |
175 | enum cx23885_notification_mailbox { | |
176 | CX23885_NOTIFICATION_NO_MAILBOX = -1, | |
177 | }; | |
178 | enum cx23885_field1_lines { | |
179 | CX23885_FIELD1_SAA7114 = 0x00EF, /* 239 */ | |
180 | CX23885_FIELD1_SAA7115 = 0x00F0, /* 240 */ | |
181 | CX23885_FIELD1_MICRONAS = 0x0105, /* 261 */ | |
182 | }; | |
183 | enum cx23885_field2_lines { | |
184 | CX23885_FIELD2_SAA7114 = 0x00EF, /* 239 */ | |
185 | CX23885_FIELD2_SAA7115 = 0x00F0, /* 240 */ | |
186 | CX23885_FIELD2_MICRONAS = 0x0106, /* 262 */ | |
187 | }; | |
188 | enum cx23885_custom_data_type { | |
189 | CX23885_CUSTOM_EXTENSION_USR_DATA, | |
190 | CX23885_CUSTOM_PRIVATE_PACKET, | |
191 | }; | |
192 | enum cx23885_mute { | |
193 | CX23885_UNMUTE, | |
194 | CX23885_MUTE, | |
195 | }; | |
196 | enum cx23885_mute_video_mask { | |
197 | CX23885_MUTE_VIDEO_V_MASK = 0x0000FF00, | |
198 | CX23885_MUTE_VIDEO_U_MASK = 0x00FF0000, | |
199 | CX23885_MUTE_VIDEO_Y_MASK = 0xFF000000, | |
200 | }; | |
201 | enum cx23885_mute_video_shift { | |
202 | CX23885_MUTE_VIDEO_V_SHIFT = 8, | |
203 | CX23885_MUTE_VIDEO_U_SHIFT = 16, | |
204 | CX23885_MUTE_VIDEO_Y_SHIFT = 24, | |
205 | }; | |
206 | ||
207 | /* defines below are from ivtv-driver.h */ | |
208 | #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF | |
209 | ||
210 | /* Firmware API commands */ | |
211 | #define IVTV_API_STD_TIMEOUT 500 | |
212 | ||
213 | /* Registers */ | |
214 | /* IVTV_REG_OFFSET */ | |
215 | #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8) | |
216 | #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC) | |
217 | #define IVTV_REG_SPU (0x9050) | |
218 | #define IVTV_REG_HW_BLOCKS (0x9054) | |
219 | #define IVTV_REG_VPU (0x9058) | |
220 | #define IVTV_REG_APU (0xA064) | |
221 | ||
222 | /**** Bit definitions for MC417_RWD and MC417_OEN registers *** | |
223 | bits 31-16 | |
224 | +-----------+ | |
225 | | Reserved | | |
226 | +-----------+ | |
227 | bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 | |
228 | +-------+-------+-------+-------+-------+-------+-------+-------+ | |
229 | | MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0| | |
230 | +-------+-------+-------+-------+-------+-------+-------+-------+ | |
231 | bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 | |
232 | +-------+-------+-------+-------+-------+-------+-------+-------+ | |
233 | |MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0| | |
234 | +-------+-------+-------+-------+-------+-------+-------+-------+ | |
235 | ***/ | |
236 | #define MC417_MIWR 0x8000 | |
237 | #define MC417_MIRD 0x4000 | |
238 | #define MC417_MICS 0x2000 | |
239 | #define MC417_MIRDY 0x1000 | |
240 | #define MC417_MIADDR 0x0F00 | |
241 | #define MC417_MIDATA 0x00FF | |
242 | ||
243 | /* MIADDR* nibble definitions */ | |
244 | #define MCI_MEMORY_DATA_BYTE0 0x000 | |
245 | #define MCI_MEMORY_DATA_BYTE1 0x100 | |
246 | #define MCI_MEMORY_DATA_BYTE2 0x200 | |
247 | #define MCI_MEMORY_DATA_BYTE3 0x300 | |
248 | #define MCI_MEMORY_ADDRESS_BYTE2 0x400 | |
249 | #define MCI_MEMORY_ADDRESS_BYTE1 0x500 | |
250 | #define MCI_MEMORY_ADDRESS_BYTE0 0x600 | |
251 | #define MCI_REGISTER_DATA_BYTE0 0x800 | |
252 | #define MCI_REGISTER_DATA_BYTE1 0x900 | |
253 | #define MCI_REGISTER_DATA_BYTE2 0xA00 | |
254 | #define MCI_REGISTER_DATA_BYTE3 0xB00 | |
255 | #define MCI_REGISTER_ADDRESS_BYTE0 0xC00 | |
256 | #define MCI_REGISTER_ADDRESS_BYTE1 0xD00 | |
257 | #define MCI_REGISTER_MODE 0xE00 | |
258 | ||
259 | /* Read and write modes */ | |
260 | #define MCI_MODE_REGISTER_READ 0 | |
261 | #define MCI_MODE_REGISTER_WRITE 1 | |
262 | #define MCI_MODE_MEMORY_READ 0 | |
263 | #define MCI_MODE_MEMORY_WRITE 0x40 | |
264 | ||
265 | /*** Bit definitions for MC417_CTL register **** | |
266 | bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0 | |
267 | +--------+-------------+--------+--------------+------------+ | |
268 | |Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN| | |
269 | +--------+-------------+--------+--------------+------------+ | |
270 | ***/ | |
271 | #define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030) | |
272 | #define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006) | |
273 | #define MC417_UART_GPIO_EN 0x00000001 | |
274 | ||
275 | /* Values for speed control */ | |
276 | #define MC417_SPD_CTL_SLOW 0x1 | |
277 | #define MC417_SPD_CTL_MEDIUM 0x0 | |
278 | #define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */ | |
279 | ||
280 | /* Values for GPIO select */ | |
281 | #define MC417_GPIO_SEL_GPIO3 0x3 | |
282 | #define MC417_GPIO_SEL_GPIO2 0x2 | |
283 | #define MC417_GPIO_SEL_GPIO1 0x1 | |
284 | #define MC417_GPIO_SEL_GPIO0 0x0 | |
285 | ||
286 | void cx23885_mc417_init(struct cx23885_dev *dev) | |
287 | { | |
288 | u32 regval; | |
289 | ||
290 | dprintk(2, "%s()\n", __func__); | |
291 | ||
292 | /* Configure MC417_CTL register to defaults. */ | |
293 | regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) | | |
294 | MC417_GPIO_SEL(MC417_GPIO_SEL_GPIO3) | | |
295 | MC417_UART_GPIO_EN; | |
296 | cx_write(MC417_CTL, regval); | |
297 | ||
298 | /* Configure MC417_OEN to defaults. */ | |
299 | regval = MC417_MIRDY; | |
300 | cx_write(MC417_OEN, regval); | |
301 | ||
302 | /* Configure MC417_RWD to defaults. */ | |
303 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS; | |
304 | cx_write(MC417_RWD, regval); | |
305 | } | |
306 | ||
307 | static int mc417_wait_ready(struct cx23885_dev *dev) | |
308 | { | |
309 | u32 mi_ready; | |
310 | unsigned long timeout = jiffies + msecs_to_jiffies(1); | |
311 | ||
312 | for (;;) { | |
313 | mi_ready = cx_read(MC417_RWD) & MC417_MIRDY; | |
314 | if (mi_ready != 0) | |
315 | return 0; | |
316 | if (time_after(jiffies, timeout)) | |
317 | return -1; | |
318 | udelay(1); | |
319 | } | |
320 | } | |
321 | ||
74618244 | 322 | int mc417_register_write(struct cx23885_dev *dev, u16 address, u32 value) |
b1b81f1d ST |
323 | { |
324 | u32 regval; | |
325 | ||
326 | /* Enable MC417 GPIO outputs except for MC417_MIRDY, | |
327 | * which is an input. | |
328 | */ | |
329 | cx_write(MC417_OEN, MC417_MIRDY); | |
330 | ||
331 | /* Write data byte 0 */ | |
332 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 | | |
333 | (value & 0x000000FF); | |
334 | cx_write(MC417_RWD, regval); | |
335 | ||
336 | /* Transition CS/WR to effect write transaction across bus. */ | |
337 | regval |= MC417_MICS | MC417_MIWR; | |
338 | cx_write(MC417_RWD, regval); | |
339 | ||
340 | /* Write data byte 1 */ | |
341 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 | | |
342 | ((value >> 8) & 0x000000FF); | |
343 | cx_write(MC417_RWD, regval); | |
344 | regval |= MC417_MICS | MC417_MIWR; | |
345 | cx_write(MC417_RWD, regval); | |
346 | ||
347 | /* Write data byte 2 */ | |
348 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 | | |
349 | ((value >> 16) & 0x000000FF); | |
350 | cx_write(MC417_RWD, regval); | |
351 | regval |= MC417_MICS | MC417_MIWR; | |
352 | cx_write(MC417_RWD, regval); | |
353 | ||
354 | /* Write data byte 3 */ | |
355 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 | | |
356 | ((value >> 24) & 0x000000FF); | |
357 | cx_write(MC417_RWD, regval); | |
358 | regval |= MC417_MICS | MC417_MIWR; | |
359 | cx_write(MC417_RWD, regval); | |
360 | ||
361 | /* Write address byte 0 */ | |
362 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 | | |
363 | (address & 0xFF); | |
364 | cx_write(MC417_RWD, regval); | |
365 | regval |= MC417_MICS | MC417_MIWR; | |
366 | cx_write(MC417_RWD, regval); | |
367 | ||
368 | /* Write address byte 1 */ | |
369 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 | | |
370 | ((address >> 8) & 0xFF); | |
371 | cx_write(MC417_RWD, regval); | |
372 | regval |= MC417_MICS | MC417_MIWR; | |
373 | cx_write(MC417_RWD, regval); | |
374 | ||
375 | /* Indicate that this is a write. */ | |
376 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE | | |
377 | MCI_MODE_REGISTER_WRITE; | |
378 | cx_write(MC417_RWD, regval); | |
379 | regval |= MC417_MICS | MC417_MIWR; | |
380 | cx_write(MC417_RWD, regval); | |
381 | ||
382 | /* Wait for the trans to complete (MC417_MIRDY asserted). */ | |
383 | return mc417_wait_ready(dev); | |
384 | } | |
385 | ||
74618244 | 386 | int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value) |
b1b81f1d ST |
387 | { |
388 | int retval; | |
389 | u32 regval; | |
390 | u32 tempval; | |
391 | u32 dataval; | |
392 | ||
393 | /* Enable MC417 GPIO outputs except for MC417_MIRDY, | |
394 | * which is an input. | |
395 | */ | |
396 | cx_write(MC417_OEN, MC417_MIRDY); | |
397 | ||
398 | /* Write address byte 0 */ | |
399 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 | | |
400 | ((address & 0x00FF)); | |
401 | cx_write(MC417_RWD, regval); | |
402 | regval |= MC417_MICS | MC417_MIWR; | |
403 | cx_write(MC417_RWD, regval); | |
404 | ||
405 | /* Write address byte 1 */ | |
406 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 | | |
407 | ((address >> 8) & 0xFF); | |
408 | cx_write(MC417_RWD, regval); | |
409 | regval |= MC417_MICS | MC417_MIWR; | |
410 | cx_write(MC417_RWD, regval); | |
411 | ||
412 | /* Indicate that this is a register read. */ | |
413 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE | | |
414 | MCI_MODE_REGISTER_READ; | |
415 | cx_write(MC417_RWD, regval); | |
416 | regval |= MC417_MICS | MC417_MIWR; | |
417 | cx_write(MC417_RWD, regval); | |
418 | ||
419 | /* Wait for the trans to complete (MC417_MIRDY asserted). */ | |
420 | retval = mc417_wait_ready(dev); | |
421 | ||
422 | /* switch the DAT0-7 GPIO[10:3] to input mode */ | |
423 | cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA); | |
424 | ||
425 | /* Read data byte 0 */ | |
426 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0; | |
427 | cx_write(MC417_RWD, regval); | |
428 | ||
429 | /* Transition RD to effect read transaction across bus. | |
430 | * Transtion 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)? | |
431 | * Should it be 0x9000 -> 0xF000 (also why is RDY being set, its | |
432 | * input only...) | |
433 | */ | |
434 | regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0; | |
435 | cx_write(MC417_RWD, regval); | |
436 | ||
437 | /* Collect byte */ | |
438 | tempval = cx_read(MC417_RWD); | |
439 | dataval = tempval & 0x000000FF; | |
440 | ||
441 | /* Bring CS and RD high. */ | |
442 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
443 | cx_write(MC417_RWD, regval); | |
444 | ||
445 | /* Read data byte 1 */ | |
446 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1; | |
447 | cx_write(MC417_RWD, regval); | |
448 | regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1; | |
449 | cx_write(MC417_RWD, regval); | |
450 | tempval = cx_read(MC417_RWD); | |
451 | dataval |= ((tempval & 0x000000FF) << 8); | |
452 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
453 | cx_write(MC417_RWD, regval); | |
454 | ||
455 | /* Read data byte 2 */ | |
456 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2; | |
457 | cx_write(MC417_RWD, regval); | |
458 | regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2; | |
459 | cx_write(MC417_RWD, regval); | |
460 | tempval = cx_read(MC417_RWD); | |
461 | dataval |= ((tempval & 0x000000FF) << 16); | |
462 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
463 | cx_write(MC417_RWD, regval); | |
464 | ||
465 | /* Read data byte 3 */ | |
466 | regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3; | |
467 | cx_write(MC417_RWD, regval); | |
468 | regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3; | |
469 | cx_write(MC417_RWD, regval); | |
470 | tempval = cx_read(MC417_RWD); | |
471 | dataval |= ((tempval & 0x000000FF) << 24); | |
472 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
473 | cx_write(MC417_RWD, regval); | |
474 | ||
475 | *value = dataval; | |
476 | ||
477 | return retval; | |
478 | } | |
479 | ||
480 | int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value) | |
481 | { | |
482 | u32 regval; | |
483 | ||
484 | /* Enable MC417 GPIO outputs except for MC417_MIRDY, | |
485 | * which is an input. | |
486 | */ | |
487 | cx_write(MC417_OEN, MC417_MIRDY); | |
488 | ||
489 | /* Write data byte 0 */ | |
490 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 | | |
491 | (value & 0x000000FF); | |
492 | cx_write(MC417_RWD, regval); | |
493 | ||
494 | /* Transition CS/WR to effect write transaction across bus. */ | |
495 | regval |= MC417_MICS | MC417_MIWR; | |
496 | cx_write(MC417_RWD, regval); | |
497 | ||
498 | /* Write data byte 1 */ | |
499 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 | | |
500 | ((value >> 8) & 0x000000FF); | |
501 | cx_write(MC417_RWD, regval); | |
502 | regval |= MC417_MICS | MC417_MIWR; | |
503 | cx_write(MC417_RWD, regval); | |
504 | ||
505 | /* Write data byte 2 */ | |
506 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 | | |
507 | ((value >> 16) & 0x000000FF); | |
508 | cx_write(MC417_RWD, regval); | |
509 | regval |= MC417_MICS | MC417_MIWR; | |
510 | cx_write(MC417_RWD, regval); | |
511 | ||
512 | /* Write data byte 3 */ | |
513 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 | | |
514 | ((value >> 24) & 0x000000FF); | |
515 | cx_write(MC417_RWD, regval); | |
516 | regval |= MC417_MICS | MC417_MIWR; | |
517 | cx_write(MC417_RWD, regval); | |
518 | ||
519 | /* Write address byte 2 */ | |
520 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 | | |
521 | MCI_MODE_MEMORY_WRITE | ((address >> 16) & 0x3F); | |
522 | cx_write(MC417_RWD, regval); | |
523 | regval |= MC417_MICS | MC417_MIWR; | |
524 | cx_write(MC417_RWD, regval); | |
525 | ||
526 | /* Write address byte 1 */ | |
527 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 | | |
528 | ((address >> 8) & 0xFF); | |
529 | cx_write(MC417_RWD, regval); | |
530 | regval |= MC417_MICS | MC417_MIWR; | |
531 | cx_write(MC417_RWD, regval); | |
532 | ||
533 | /* Write address byte 0 */ | |
534 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 | | |
535 | (address & 0xFF); | |
536 | cx_write(MC417_RWD, regval); | |
537 | regval |= MC417_MICS | MC417_MIWR; | |
538 | cx_write(MC417_RWD, regval); | |
539 | ||
540 | /* Wait for the trans to complete (MC417_MIRDY asserted). */ | |
541 | return mc417_wait_ready(dev); | |
542 | } | |
543 | ||
544 | int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value) | |
545 | { | |
546 | int retval; | |
547 | u32 regval; | |
548 | u32 tempval; | |
549 | u32 dataval; | |
550 | ||
551 | /* Enable MC417 GPIO outputs except for MC417_MIRDY, | |
552 | * which is an input. | |
553 | */ | |
554 | cx_write(MC417_OEN, MC417_MIRDY); | |
555 | ||
556 | /* Write address byte 2 */ | |
557 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 | | |
558 | MCI_MODE_MEMORY_READ | ((address >> 16) & 0x3F); | |
559 | cx_write(MC417_RWD, regval); | |
560 | regval |= MC417_MICS | MC417_MIWR; | |
561 | cx_write(MC417_RWD, regval); | |
562 | ||
563 | /* Write address byte 1 */ | |
564 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 | | |
565 | ((address >> 8) & 0xFF); | |
566 | cx_write(MC417_RWD, regval); | |
567 | regval |= MC417_MICS | MC417_MIWR; | |
568 | cx_write(MC417_RWD, regval); | |
569 | ||
570 | /* Write address byte 0 */ | |
571 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 | | |
572 | (address & 0xFF); | |
573 | cx_write(MC417_RWD, regval); | |
574 | regval |= MC417_MICS | MC417_MIWR; | |
575 | cx_write(MC417_RWD, regval); | |
576 | ||
577 | /* Wait for the trans to complete (MC417_MIRDY asserted). */ | |
578 | retval = mc417_wait_ready(dev); | |
579 | ||
580 | /* switch the DAT0-7 GPIO[10:3] to input mode */ | |
581 | cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA); | |
582 | ||
583 | /* Read data byte 3 */ | |
584 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3; | |
585 | cx_write(MC417_RWD, regval); | |
586 | ||
587 | /* Transition RD to effect read transaction across bus. */ | |
588 | regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3; | |
589 | cx_write(MC417_RWD, regval); | |
590 | ||
591 | /* Collect byte */ | |
592 | tempval = cx_read(MC417_RWD); | |
593 | dataval = ((tempval & 0x000000FF) << 24); | |
594 | ||
595 | /* Bring CS and RD high. */ | |
596 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
597 | cx_write(MC417_RWD, regval); | |
598 | ||
599 | /* Read data byte 2 */ | |
600 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2; | |
601 | cx_write(MC417_RWD, regval); | |
602 | regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2; | |
603 | cx_write(MC417_RWD, regval); | |
604 | tempval = cx_read(MC417_RWD); | |
605 | dataval |= ((tempval & 0x000000FF) << 16); | |
606 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
607 | cx_write(MC417_RWD, regval); | |
608 | ||
609 | /* Read data byte 1 */ | |
610 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1; | |
611 | cx_write(MC417_RWD, regval); | |
612 | regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1; | |
613 | cx_write(MC417_RWD, regval); | |
614 | tempval = cx_read(MC417_RWD); | |
615 | dataval |= ((tempval & 0x000000FF) << 8); | |
616 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
617 | cx_write(MC417_RWD, regval); | |
618 | ||
619 | /* Read data byte 0 */ | |
620 | regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0; | |
621 | cx_write(MC417_RWD, regval); | |
622 | regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0; | |
623 | cx_write(MC417_RWD, regval); | |
624 | tempval = cx_read(MC417_RWD); | |
625 | dataval |= (tempval & 0x000000FF); | |
626 | regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; | |
627 | cx_write(MC417_RWD, regval); | |
628 | ||
629 | *value = dataval; | |
630 | ||
631 | return retval; | |
632 | } | |
633 | ||
f659c513 ST |
634 | void mc417_gpio_set(struct cx23885_dev *dev, u32 mask) |
635 | { | |
636 | u32 val; | |
637 | ||
638 | /* Set the gpio value */ | |
639 | mc417_register_read(dev, 0x900C, &val); | |
640 | val |= (mask & 0x000ffff); | |
641 | mc417_register_write(dev, 0x900C, val); | |
642 | } | |
643 | ||
644 | void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask) | |
645 | { | |
646 | u32 val; | |
647 | ||
648 | /* Clear the gpio value */ | |
649 | mc417_register_read(dev, 0x900C, &val); | |
650 | val &= ~(mask & 0x0000ffff); | |
651 | mc417_register_write(dev, 0x900C, val); | |
652 | } | |
653 | ||
654 | void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput) | |
655 | { | |
656 | u32 val; | |
657 | ||
658 | /* Enable GPIO direction bits */ | |
659 | mc417_register_read(dev, 0x9020, &val); | |
660 | if (asoutput) | |
661 | val |= (mask & 0x0000ffff); | |
662 | else | |
663 | val &= ~(mask & 0x0000ffff); | |
664 | ||
665 | mc417_register_write(dev, 0x9020, val); | |
666 | } | |
b1b81f1d ST |
667 | /* ------------------------------------------------------------------ */ |
668 | ||
669 | /* MPEG encoder API */ | |
d45b9b8a | 670 | static char *cmd_to_str(int cmd) |
b1b81f1d ST |
671 | { |
672 | switch (cmd) { | |
673 | case CX2341X_ENC_PING_FW: | |
674 | return "PING_FW"; | |
675 | case CX2341X_ENC_START_CAPTURE: | |
676 | return "START_CAPTURE"; | |
677 | case CX2341X_ENC_STOP_CAPTURE: | |
678 | return "STOP_CAPTURE"; | |
679 | case CX2341X_ENC_SET_AUDIO_ID: | |
680 | return "SET_AUDIO_ID"; | |
681 | case CX2341X_ENC_SET_VIDEO_ID: | |
682 | return "SET_VIDEO_ID"; | |
683 | case CX2341X_ENC_SET_PCR_ID: | |
26ee91ef | 684 | return "SET_PCR_ID"; |
b1b81f1d ST |
685 | case CX2341X_ENC_SET_FRAME_RATE: |
686 | return "SET_FRAME_RATE"; | |
687 | case CX2341X_ENC_SET_FRAME_SIZE: | |
688 | return "SET_FRAME_SIZE"; | |
689 | case CX2341X_ENC_SET_BIT_RATE: | |
690 | return "SET_BIT_RATE"; | |
691 | case CX2341X_ENC_SET_GOP_PROPERTIES: | |
692 | return "SET_GOP_PROPERTIES"; | |
693 | case CX2341X_ENC_SET_ASPECT_RATIO: | |
694 | return "SET_ASPECT_RATIO"; | |
695 | case CX2341X_ENC_SET_DNR_FILTER_MODE: | |
26ee91ef | 696 | return "SET_DNR_FILTER_MODE"; |
b1b81f1d ST |
697 | case CX2341X_ENC_SET_DNR_FILTER_PROPS: |
698 | return "SET_DNR_FILTER_PROPS"; | |
699 | case CX2341X_ENC_SET_CORING_LEVELS: | |
700 | return "SET_CORING_LEVELS"; | |
701 | case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE: | |
702 | return "SET_SPATIAL_FILTER_TYPE"; | |
703 | case CX2341X_ENC_SET_VBI_LINE: | |
704 | return "SET_VBI_LINE"; | |
705 | case CX2341X_ENC_SET_STREAM_TYPE: | |
706 | return "SET_STREAM_TYPE"; | |
707 | case CX2341X_ENC_SET_OUTPUT_PORT: | |
708 | return "SET_OUTPUT_PORT"; | |
709 | case CX2341X_ENC_SET_AUDIO_PROPERTIES: | |
710 | return "SET_AUDIO_PROPERTIES"; | |
711 | case CX2341X_ENC_HALT_FW: | |
712 | return "HALT_FW"; | |
713 | case CX2341X_ENC_GET_VERSION: | |
714 | return "GET_VERSION"; | |
715 | case CX2341X_ENC_SET_GOP_CLOSURE: | |
716 | return "SET_GOP_CLOSURE"; | |
717 | case CX2341X_ENC_GET_SEQ_END: | |
718 | return "GET_SEQ_END"; | |
719 | case CX2341X_ENC_SET_PGM_INDEX_INFO: | |
720 | return "SET_PGM_INDEX_INFO"; | |
721 | case CX2341X_ENC_SET_VBI_CONFIG: | |
722 | return "SET_VBI_CONFIG"; | |
723 | case CX2341X_ENC_SET_DMA_BLOCK_SIZE: | |
724 | return "SET_DMA_BLOCK_SIZE"; | |
725 | case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10: | |
726 | return "GET_PREV_DMA_INFO_MB_10"; | |
727 | case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9: | |
728 | return "GET_PREV_DMA_INFO_MB_9"; | |
729 | case CX2341X_ENC_SCHED_DMA_TO_HOST: | |
730 | return "SCHED_DMA_TO_HOST"; | |
731 | case CX2341X_ENC_INITIALIZE_INPUT: | |
732 | return "INITIALIZE_INPUT"; | |
733 | case CX2341X_ENC_SET_FRAME_DROP_RATE: | |
734 | return "SET_FRAME_DROP_RATE"; | |
735 | case CX2341X_ENC_PAUSE_ENCODER: | |
736 | return "PAUSE_ENCODER"; | |
737 | case CX2341X_ENC_REFRESH_INPUT: | |
738 | return "REFRESH_INPUT"; | |
739 | case CX2341X_ENC_SET_COPYRIGHT: | |
740 | return "SET_COPYRIGHT"; | |
741 | case CX2341X_ENC_SET_EVENT_NOTIFICATION: | |
742 | return "SET_EVENT_NOTIFICATION"; | |
743 | case CX2341X_ENC_SET_NUM_VSYNC_LINES: | |
744 | return "SET_NUM_VSYNC_LINES"; | |
745 | case CX2341X_ENC_SET_PLACEHOLDER: | |
746 | return "SET_PLACEHOLDER"; | |
747 | case CX2341X_ENC_MUTE_VIDEO: | |
748 | return "MUTE_VIDEO"; | |
749 | case CX2341X_ENC_MUTE_AUDIO: | |
750 | return "MUTE_AUDIO"; | |
751 | case CX2341X_ENC_MISC: | |
752 | return "MISC"; | |
753 | default: | |
754 | return "UNKNOWN"; | |
755 | } | |
756 | } | |
757 | ||
758 | static int cx23885_mbox_func(void *priv, | |
759 | u32 command, | |
760 | int in, | |
761 | int out, | |
762 | u32 data[CX2341X_MBOX_MAX_DATA]) | |
763 | { | |
764 | struct cx23885_dev *dev = priv; | |
765 | unsigned long timeout; | |
766 | u32 value, flag, retval = 0; | |
767 | int i; | |
768 | ||
769 | dprintk(3, "%s: command(0x%X) = %s\n", __func__, command, | |
770 | cmd_to_str(command)); | |
771 | ||
772 | /* this may not be 100% safe if we can't read any memory location | |
773 | without side effects */ | |
774 | mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value); | |
775 | if (value != 0x12345678) { | |
776 | printk(KERN_ERR | |
777 | "Firmware and/or mailbox pointer not initialized " | |
778 | "or corrupted, signature = 0x%x, cmd = %s\n", value, | |
779 | cmd_to_str(command)); | |
780 | return -1; | |
781 | } | |
782 | ||
783 | /* This read looks at 32 bits, but flag is only 8 bits. | |
784 | * Seems we also bail if CMD or TIMEOUT bytes are set??? | |
785 | */ | |
786 | mc417_memory_read(dev, dev->cx23417_mailbox, &flag); | |
787 | if (flag) { | |
788 | printk(KERN_ERR "ERROR: Mailbox appears to be in use " | |
789 | "(%x), cmd = %s\n", flag, cmd_to_str(command)); | |
790 | return -1; | |
791 | } | |
792 | ||
793 | flag |= 1; /* tell 'em we're working on it */ | |
794 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); | |
795 | ||
796 | /* write command + args + fill remaining with zeros */ | |
797 | /* command code */ | |
798 | mc417_memory_write(dev, dev->cx23417_mailbox + 1, command); | |
799 | mc417_memory_write(dev, dev->cx23417_mailbox + 3, | |
800 | IVTV_API_STD_TIMEOUT); /* timeout */ | |
801 | for (i = 0; i < in; i++) { | |
802 | mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]); | |
803 | dprintk(3, "API Input %d = %d\n", i, data[i]); | |
804 | } | |
805 | for (; i < CX2341X_MBOX_MAX_DATA; i++) | |
806 | mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0); | |
807 | ||
808 | flag |= 3; /* tell 'em we're done writing */ | |
809 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); | |
810 | ||
811 | /* wait for firmware to handle the API command */ | |
812 | timeout = jiffies + msecs_to_jiffies(10); | |
813 | for (;;) { | |
814 | mc417_memory_read(dev, dev->cx23417_mailbox, &flag); | |
815 | if (0 != (flag & 4)) | |
816 | break; | |
817 | if (time_after(jiffies, timeout)) { | |
818 | printk(KERN_ERR "ERROR: API Mailbox timeout\n"); | |
819 | return -1; | |
820 | } | |
821 | udelay(10); | |
822 | } | |
823 | ||
824 | /* read output values */ | |
825 | for (i = 0; i < out; i++) { | |
826 | mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i); | |
827 | dprintk(3, "API Output %d = %d\n", i, data[i]); | |
828 | } | |
829 | ||
830 | mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval); | |
831 | dprintk(3, "API result = %d\n", retval); | |
832 | ||
833 | flag = 0; | |
834 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); | |
835 | ||
836 | return retval; | |
837 | } | |
838 | ||
839 | /* We don't need to call the API often, so using just one | |
840 | * mailbox will probably suffice | |
841 | */ | |
842 | static int cx23885_api_cmd(struct cx23885_dev *dev, | |
843 | u32 command, | |
844 | u32 inputcnt, | |
845 | u32 outputcnt, | |
846 | ...) | |
847 | { | |
848 | u32 data[CX2341X_MBOX_MAX_DATA]; | |
849 | va_list vargs; | |
850 | int i, err; | |
851 | ||
852 | dprintk(3, "%s() cmds = 0x%08x\n", __func__, command); | |
853 | ||
854 | va_start(vargs, outputcnt); | |
855 | for (i = 0; i < inputcnt; i++) | |
856 | data[i] = va_arg(vargs, int); | |
857 | ||
858 | err = cx23885_mbox_func(dev, command, inputcnt, outputcnt, data); | |
859 | for (i = 0; i < outputcnt; i++) { | |
860 | int *vptr = va_arg(vargs, int *); | |
861 | *vptr = data[i]; | |
862 | } | |
863 | va_end(vargs); | |
864 | ||
865 | return err; | |
866 | } | |
867 | ||
868 | static int cx23885_find_mailbox(struct cx23885_dev *dev) | |
869 | { | |
870 | u32 signature[4] = { | |
871 | 0x12345678, 0x34567812, 0x56781234, 0x78123456 | |
872 | }; | |
873 | int signaturecnt = 0; | |
874 | u32 value; | |
875 | int i; | |
876 | ||
877 | dprintk(2, "%s()\n", __func__); | |
878 | ||
879 | for (i = 0; i < CX23885_FIRM_IMAGE_SIZE; i++) { | |
880 | mc417_memory_read(dev, i, &value); | |
881 | if (value == signature[signaturecnt]) | |
882 | signaturecnt++; | |
883 | else | |
884 | signaturecnt = 0; | |
885 | if (4 == signaturecnt) { | |
886 | dprintk(1, "Mailbox signature found at 0x%x\n", i+1); | |
887 | return i+1; | |
888 | } | |
889 | } | |
890 | printk(KERN_ERR "Mailbox signature values not found!\n"); | |
891 | return -1; | |
892 | } | |
893 | ||
894 | static int cx23885_load_firmware(struct cx23885_dev *dev) | |
895 | { | |
896 | static const unsigned char magic[8] = { | |
897 | 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa | |
898 | }; | |
899 | const struct firmware *firmware; | |
900 | int i, retval = 0; | |
901 | u32 value = 0; | |
902 | u32 gpio_output = 0; | |
182d29f3 | 903 | u32 gpio_value; |
b1b81f1d ST |
904 | u32 checksum = 0; |
905 | u32 *dataptr; | |
906 | ||
907 | dprintk(2, "%s()\n", __func__); | |
908 | ||
909 | /* Save GPIO settings before reset of APU */ | |
910 | retval |= mc417_memory_read(dev, 0x9020, &gpio_output); | |
182d29f3 | 911 | retval |= mc417_memory_read(dev, 0x900C, &gpio_value); |
b1b81f1d ST |
912 | |
913 | retval = mc417_register_write(dev, | |
914 | IVTV_REG_VPU, 0xFFFFFFED); | |
915 | retval |= mc417_register_write(dev, | |
916 | IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST); | |
917 | retval |= mc417_register_write(dev, | |
918 | IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800); | |
919 | retval |= mc417_register_write(dev, | |
920 | IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A); | |
921 | retval |= mc417_register_write(dev, | |
922 | IVTV_REG_APU, 0); | |
923 | ||
924 | if (retval != 0) { | |
925 | printk(KERN_ERR "%s: Error with mc417_register_write\n", | |
926 | __func__); | |
927 | return -1; | |
928 | } | |
929 | ||
930 | retval = request_firmware(&firmware, CX23885_FIRM_IMAGE_NAME, | |
931 | &dev->pci->dev); | |
932 | ||
933 | if (retval != 0) { | |
934 | printk(KERN_ERR | |
935 | "ERROR: Hotplug firmware request failed (%s).\n", | |
d35ed627 | 936 | CX23885_FIRM_IMAGE_NAME); |
b1b81f1d ST |
937 | printk(KERN_ERR "Please fix your hotplug setup, the board will " |
938 | "not work without firmware loaded!\n"); | |
939 | return -1; | |
940 | } | |
941 | ||
942 | if (firmware->size != CX23885_FIRM_IMAGE_SIZE) { | |
943 | printk(KERN_ERR "ERROR: Firmware size mismatch " | |
944 | "(have %zd, expected %d)\n", | |
945 | firmware->size, CX23885_FIRM_IMAGE_SIZE); | |
946 | release_firmware(firmware); | |
947 | return -1; | |
948 | } | |
949 | ||
950 | if (0 != memcmp(firmware->data, magic, 8)) { | |
951 | printk(KERN_ERR | |
952 | "ERROR: Firmware magic mismatch, wrong file?\n"); | |
953 | release_firmware(firmware); | |
954 | return -1; | |
955 | } | |
956 | ||
957 | /* transfer to the chip */ | |
958 | dprintk(2, "Loading firmware ...\n"); | |
959 | dataptr = (u32 *)firmware->data; | |
960 | for (i = 0; i < (firmware->size >> 2); i++) { | |
961 | value = *dataptr; | |
962 | checksum += ~value; | |
963 | if (mc417_memory_write(dev, i, value) != 0) { | |
964 | printk(KERN_ERR "ERROR: Loading firmware failed!\n"); | |
965 | release_firmware(firmware); | |
966 | return -1; | |
967 | } | |
968 | dataptr++; | |
969 | } | |
970 | ||
971 | /* read back to verify with the checksum */ | |
972 | dprintk(1, "Verifying firmware ...\n"); | |
973 | for (i--; i >= 0; i--) { | |
974 | if (mc417_memory_read(dev, i, &value) != 0) { | |
975 | printk(KERN_ERR "ERROR: Reading firmware failed!\n"); | |
976 | release_firmware(firmware); | |
977 | return -1; | |
978 | } | |
979 | checksum -= ~value; | |
980 | } | |
981 | if (checksum) { | |
982 | printk(KERN_ERR | |
983 | "ERROR: Firmware load failed (checksum mismatch).\n"); | |
984 | release_firmware(firmware); | |
985 | return -1; | |
986 | } | |
987 | release_firmware(firmware); | |
988 | dprintk(1, "Firmware upload successful.\n"); | |
989 | ||
990 | retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS, | |
991 | IVTV_CMD_HW_BLOCKS_RST); | |
992 | ||
f659c513 ST |
993 | /* F/W power up disturbs the GPIOs, restore state */ |
994 | retval |= mc417_register_write(dev, 0x9020, gpio_output); | |
182d29f3 | 995 | retval |= mc417_register_write(dev, 0x900C, gpio_value); |
b1b81f1d ST |
996 | |
997 | retval |= mc417_register_read(dev, IVTV_REG_VPU, &value); | |
998 | retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8); | |
999 | ||
182d29f3 ST |
1000 | /* Hardcoded GPIO's here */ |
1001 | retval |= mc417_register_write(dev, 0x9020, 0x4000); | |
1002 | retval |= mc417_register_write(dev, 0x900C, 0x4000); | |
1003 | ||
1004 | mc417_register_read(dev, 0x9020, &gpio_output); | |
1005 | mc417_register_read(dev, 0x900C, &gpio_value); | |
1006 | ||
b1b81f1d ST |
1007 | if (retval < 0) |
1008 | printk(KERN_ERR "%s: Error with mc417_register_write\n", | |
1009 | __func__); | |
1010 | return 0; | |
1011 | } | |
1012 | ||
1013 | void cx23885_417_check_encoder(struct cx23885_dev *dev) | |
1014 | { | |
1015 | u32 status, seq; | |
1016 | ||
1017 | status = seq = 0; | |
1018 | cx23885_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq); | |
1019 | dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq); | |
1020 | } | |
1021 | ||
1022 | static void cx23885_codec_settings(struct cx23885_dev *dev) | |
1023 | { | |
1024 | dprintk(1, "%s()\n", __func__); | |
1025 | ||
38e3d7ce ST |
1026 | /* Dynamically change the height based on video standard */ |
1027 | if (dev->encodernorm.id & V4L2_STD_525_60) | |
1028 | dev->ts1.height = 480; | |
1029 | else | |
1030 | dev->ts1.height = 576; | |
1031 | ||
b1b81f1d ST |
1032 | /* assign frame size */ |
1033 | cx23885_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0, | |
1034 | dev->ts1.height, dev->ts1.width); | |
1035 | ||
1036 | dev->mpeg_params.width = dev->ts1.width; | |
1037 | dev->mpeg_params.height = dev->ts1.height; | |
1038 | dev->mpeg_params.is_50hz = | |
1039 | (dev->encodernorm.id & V4L2_STD_625_50) != 0; | |
1040 | ||
1041 | cx2341x_update(dev, cx23885_mbox_func, NULL, &dev->mpeg_params); | |
1042 | ||
1043 | cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1); | |
1044 | cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1); | |
1045 | } | |
1046 | ||
9c9c3d07 | 1047 | static int cx23885_initialize_codec(struct cx23885_dev *dev, int startencoder) |
b1b81f1d ST |
1048 | { |
1049 | int version; | |
1050 | int retval; | |
1051 | u32 i, data[7]; | |
1052 | ||
1053 | dprintk(1, "%s()\n", __func__); | |
1054 | ||
1055 | retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */ | |
1056 | if (retval < 0) { | |
1057 | dprintk(2, "%s() PING OK\n", __func__); | |
1058 | retval = cx23885_load_firmware(dev); | |
1059 | if (retval < 0) { | |
1060 | printk(KERN_ERR "%s() f/w load failed\n", __func__); | |
1061 | return retval; | |
1062 | } | |
f347535a | 1063 | retval = cx23885_find_mailbox(dev); |
1064 | if (retval < 0) { | |
b1b81f1d ST |
1065 | printk(KERN_ERR "%s() mailbox < 0, error\n", |
1066 | __func__); | |
1067 | return -1; | |
1068 | } | |
f347535a | 1069 | dev->cx23417_mailbox = retval; |
b1b81f1d ST |
1070 | retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); |
1071 | if (retval < 0) { | |
1072 | printk(KERN_ERR | |
1073 | "ERROR: cx23417 firmware ping failed!\n"); | |
1074 | return -1; | |
1075 | } | |
1076 | retval = cx23885_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1, | |
1077 | &version); | |
1078 | if (retval < 0) { | |
1079 | printk(KERN_ERR "ERROR: cx23417 firmware get encoder :" | |
1080 | "version failed!\n"); | |
1081 | return -1; | |
1082 | } | |
1083 | dprintk(1, "cx23417 firmware version is 0x%08x\n", version); | |
1084 | msleep(200); | |
1085 | } | |
1086 | ||
1087 | cx23885_codec_settings(dev); | |
1088 | msleep(60); | |
1089 | ||
1090 | cx23885_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0, | |
1091 | CX23885_FIELD1_SAA7115, CX23885_FIELD2_SAA7115); | |
1092 | cx23885_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0, | |
1093 | CX23885_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1094 | 0, 0); | |
1095 | ||
1096 | /* Setup to capture VBI */ | |
1097 | data[0] = 0x0001BD00; | |
1098 | data[1] = 1; /* frames per interrupt */ | |
1099 | data[2] = 4; /* total bufs */ | |
1100 | data[3] = 0x91559155; /* start codes */ | |
1101 | data[4] = 0x206080C0; /* stop codes */ | |
1102 | data[5] = 6; /* lines */ | |
1103 | data[6] = 64; /* BPL */ | |
1104 | ||
1105 | cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1], | |
1106 | data[2], data[3], data[4], data[5], data[6]); | |
1107 | ||
1108 | for (i = 2; i <= 24; i++) { | |
1109 | int valid; | |
1110 | ||
1111 | valid = ((i >= 19) && (i <= 21)); | |
1112 | cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i, | |
1113 | valid, 0 , 0, 0); | |
1114 | cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, | |
1115 | i | 0x80000000, valid, 0, 0, 0); | |
1116 | } | |
1117 | ||
1118 | cx23885_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX23885_UNMUTE); | |
1119 | msleep(60); | |
1120 | ||
1121 | /* initialize the video input */ | |
1122 | cx23885_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0); | |
1123 | msleep(60); | |
1124 | ||
1125 | /* Enable VIP style pixel invalidation so we work with scaled mode */ | |
1126 | mc417_memory_write(dev, 2120, 0x00000080); | |
1127 | ||
1128 | /* start capturing to the host interface */ | |
9c9c3d07 ST |
1129 | if (startencoder) { |
1130 | cx23885_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0, | |
1131 | CX23885_MPEG_CAPTURE, CX23885_RAW_BITS_NONE); | |
1132 | msleep(10); | |
1133 | } | |
b1b81f1d ST |
1134 | |
1135 | return 0; | |
1136 | } | |
1137 | ||
1138 | /* ------------------------------------------------------------------ */ | |
1139 | ||
1140 | static int bb_buf_setup(struct videobuf_queue *q, | |
1141 | unsigned int *count, unsigned int *size) | |
1142 | { | |
1143 | struct cx23885_fh *fh = q->priv_data; | |
1144 | ||
1145 | fh->dev->ts1.ts_packet_size = mpeglinesize; | |
1146 | fh->dev->ts1.ts_packet_count = mpeglines; | |
1147 | ||
1148 | *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count; | |
1149 | *count = mpegbufs; | |
1150 | ||
1151 | return 0; | |
1152 | } | |
1153 | ||
1154 | static int bb_buf_prepare(struct videobuf_queue *q, | |
1155 | struct videobuf_buffer *vb, enum v4l2_field field) | |
1156 | { | |
1157 | struct cx23885_fh *fh = q->priv_data; | |
1158 | return cx23885_buf_prepare(q, &fh->dev->ts1, | |
1159 | (struct cx23885_buffer *)vb, | |
1160 | field); | |
1161 | } | |
1162 | ||
1163 | static void bb_buf_queue(struct videobuf_queue *q, | |
1164 | struct videobuf_buffer *vb) | |
1165 | { | |
1166 | struct cx23885_fh *fh = q->priv_data; | |
1167 | cx23885_buf_queue(&fh->dev->ts1, (struct cx23885_buffer *)vb); | |
1168 | } | |
1169 | ||
1170 | static void bb_buf_release(struct videobuf_queue *q, | |
1171 | struct videobuf_buffer *vb) | |
1172 | { | |
1173 | cx23885_free_buffer(q, (struct cx23885_buffer *)vb); | |
1174 | } | |
1175 | ||
1176 | static struct videobuf_queue_ops cx23885_qops = { | |
1177 | .buf_setup = bb_buf_setup, | |
1178 | .buf_prepare = bb_buf_prepare, | |
1179 | .buf_queue = bb_buf_queue, | |
1180 | .buf_release = bb_buf_release, | |
1181 | }; | |
1182 | ||
1183 | /* ------------------------------------------------------------------ */ | |
1184 | ||
1185 | static const u32 *ctrl_classes[] = { | |
1186 | cx2341x_mpeg_ctrls, | |
1187 | NULL | |
1188 | }; | |
1189 | ||
1190 | static int cx23885_queryctrl(struct cx23885_dev *dev, | |
1191 | struct v4l2_queryctrl *qctrl) | |
1192 | { | |
1193 | qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id); | |
1194 | if (qctrl->id == 0) | |
1195 | return -EINVAL; | |
1196 | ||
1197 | /* MPEG V4L2 controls */ | |
1198 | if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl)) | |
1199 | qctrl->flags |= V4L2_CTRL_FLAG_DISABLED; | |
1200 | ||
1201 | return 0; | |
1202 | } | |
1203 | ||
1204 | static int cx23885_querymenu(struct cx23885_dev *dev, | |
1205 | struct v4l2_querymenu *qmenu) | |
1206 | { | |
1207 | struct v4l2_queryctrl qctrl; | |
1208 | ||
1209 | qctrl.id = qmenu->id; | |
1210 | cx23885_queryctrl(dev, &qctrl); | |
1211 | return v4l2_ctrl_query_menu(qmenu, &qctrl, | |
e0e31cdb | 1212 | cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id)); |
b1b81f1d ST |
1213 | } |
1214 | ||
09b3bc22 ST |
1215 | static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *id) |
1216 | { | |
1217 | struct cx23885_fh *fh = file->private_data; | |
1218 | struct cx23885_dev *dev = fh->dev; | |
1219 | ||
1220 | call_all(dev, core, g_std, id); | |
1221 | ||
1222 | return 0; | |
1223 | } | |
1224 | ||
305519c9 | 1225 | static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id) |
b1b81f1d | 1226 | { |
305519c9 DSL |
1227 | struct cx23885_fh *fh = file->private_data; |
1228 | struct cx23885_dev *dev = fh->dev; | |
1229 | unsigned int i; | |
b1b81f1d | 1230 | |
305519c9 DSL |
1231 | for (i = 0; i < ARRAY_SIZE(cx23885_tvnorms); i++) |
1232 | if (*id & cx23885_tvnorms[i].id) | |
1233 | break; | |
1234 | if (i == ARRAY_SIZE(cx23885_tvnorms)) | |
1235 | return -EINVAL; | |
1236 | dev->encodernorm = cx23885_tvnorms[i]; | |
09b3bc22 ST |
1237 | |
1238 | /* Have the drier core notify the subdevices */ | |
1239 | mutex_lock(&dev->lock); | |
1240 | cx23885_set_tvnorm(dev, *id); | |
1241 | mutex_unlock(&dev->lock); | |
1242 | ||
305519c9 DSL |
1243 | return 0; |
1244 | } | |
b1b81f1d | 1245 | |
305519c9 | 1246 | static int vidioc_enum_input(struct file *file, void *priv, |
09b3bc22 | 1247 | struct v4l2_input *i) |
305519c9 | 1248 | { |
09b3bc22 ST |
1249 | struct cx23885_dev *dev = ((struct cx23885_fh *)priv)->dev; |
1250 | dprintk(1, "%s()\n", __func__); | |
1251 | return cx23885_enum_input(dev, i); | |
305519c9 | 1252 | } |
b1b81f1d | 1253 | |
305519c9 DSL |
1254 | static int vidioc_g_input(struct file *file, void *priv, unsigned int *i) |
1255 | { | |
09b3bc22 | 1256 | return cx23885_get_input(file, priv, i); |
305519c9 | 1257 | } |
b1b81f1d | 1258 | |
305519c9 DSL |
1259 | static int vidioc_s_input(struct file *file, void *priv, unsigned int i) |
1260 | { | |
09b3bc22 | 1261 | return cx23885_set_input(file, priv, i); |
305519c9 | 1262 | } |
b1b81f1d | 1263 | |
305519c9 DSL |
1264 | static int vidioc_g_tuner(struct file *file, void *priv, |
1265 | struct v4l2_tuner *t) | |
1266 | { | |
1267 | struct cx23885_fh *fh = file->private_data; | |
1268 | struct cx23885_dev *dev = fh->dev; | |
b1b81f1d | 1269 | |
305519c9 DSL |
1270 | if (UNSET == dev->tuner_type) |
1271 | return -EINVAL; | |
1272 | if (0 != t->index) | |
1273 | return -EINVAL; | |
305519c9 | 1274 | strcpy(t->name, "Television"); |
0d5a19f1 | 1275 | call_all(dev, tuner, g_tuner, t); |
b1b81f1d | 1276 | |
305519c9 | 1277 | dprintk(1, "VIDIOC_G_TUNER: tuner type %d\n", t->type); |
b1b81f1d | 1278 | |
305519c9 DSL |
1279 | return 0; |
1280 | } | |
b1b81f1d | 1281 | |
305519c9 DSL |
1282 | static int vidioc_s_tuner(struct file *file, void *priv, |
1283 | struct v4l2_tuner *t) | |
1284 | { | |
1285 | struct cx23885_fh *fh = file->private_data; | |
1286 | struct cx23885_dev *dev = fh->dev; | |
1287 | ||
1288 | if (UNSET == dev->tuner_type) | |
1289 | return -EINVAL; | |
1290 | ||
1291 | /* Update the A/V core */ | |
0d5a19f1 | 1292 | call_all(dev, tuner, s_tuner, t); |
305519c9 DSL |
1293 | |
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | static int vidioc_g_frequency(struct file *file, void *priv, | |
1298 | struct v4l2_frequency *f) | |
1299 | { | |
1300 | struct cx23885_fh *fh = file->private_data; | |
1301 | struct cx23885_dev *dev = fh->dev; | |
1302 | ||
305519c9 DSL |
1303 | if (UNSET == dev->tuner_type) |
1304 | return -EINVAL; | |
1305 | f->type = V4L2_TUNER_ANALOG_TV; | |
1306 | f->frequency = dev->freq; | |
1307 | ||
0d5a19f1 | 1308 | call_all(dev, tuner, g_frequency, f); |
305519c9 DSL |
1309 | |
1310 | return 0; | |
1311 | } | |
1312 | ||
1313 | static int vidioc_s_frequency(struct file *file, void *priv, | |
09b3bc22 | 1314 | struct v4l2_frequency *f) |
305519c9 | 1315 | { |
09b3bc22 ST |
1316 | return cx23885_set_frequency(file, priv, f); |
1317 | } | |
305519c9 | 1318 | |
09b3bc22 ST |
1319 | static int vidioc_g_ctrl(struct file *file, void *priv, |
1320 | struct v4l2_control *ctl) | |
1321 | { | |
1322 | struct cx23885_dev *dev = ((struct cx23885_fh *)priv)->dev; | |
b1b81f1d | 1323 | |
09b3bc22 | 1324 | return cx23885_get_control(dev, ctl); |
b1b81f1d ST |
1325 | } |
1326 | ||
305519c9 | 1327 | static int vidioc_s_ctrl(struct file *file, void *priv, |
09b3bc22 | 1328 | struct v4l2_control *ctl) |
305519c9 | 1329 | { |
09b3bc22 | 1330 | struct cx23885_dev *dev = ((struct cx23885_fh *)priv)->dev; |
305519c9 | 1331 | |
09b3bc22 | 1332 | return cx23885_set_control(dev, ctl); |
305519c9 DSL |
1333 | } |
1334 | ||
1335 | static int vidioc_querycap(struct file *file, void *priv, | |
1336 | struct v4l2_capability *cap) | |
b1b81f1d ST |
1337 | { |
1338 | struct cx23885_fh *fh = file->private_data; | |
1339 | struct cx23885_dev *dev = fh->dev; | |
1340 | struct cx23885_tsport *tsport = &dev->ts1; | |
1341 | ||
b084307c | 1342 | strlcpy(cap->driver, dev->name, sizeof(cap->driver)); |
305519c9 DSL |
1343 | strlcpy(cap->card, cx23885_boards[tsport->dev->board].name, |
1344 | sizeof(cap->card)); | |
1345 | sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); | |
305519c9 DSL |
1346 | cap->capabilities = |
1347 | V4L2_CAP_VIDEO_CAPTURE | | |
1348 | V4L2_CAP_READWRITE | | |
1349 | V4L2_CAP_STREAMING | | |
1350 | 0; | |
1351 | if (UNSET != dev->tuner_type) | |
1352 | cap->capabilities |= V4L2_CAP_TUNER; | |
b1b81f1d | 1353 | |
305519c9 DSL |
1354 | return 0; |
1355 | } | |
b1b81f1d | 1356 | |
305519c9 DSL |
1357 | static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, |
1358 | struct v4l2_fmtdesc *f) | |
1359 | { | |
f29816bc | 1360 | if (f->index != 0) |
305519c9 | 1361 | return -EINVAL; |
b1b81f1d | 1362 | |
305519c9 | 1363 | strlcpy(f->description, "MPEG", sizeof(f->description)); |
305519c9 | 1364 | f->pixelformat = V4L2_PIX_FMT_MPEG; |
b1b81f1d | 1365 | |
305519c9 DSL |
1366 | return 0; |
1367 | } | |
b1b81f1d | 1368 | |
305519c9 DSL |
1369 | static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, |
1370 | struct v4l2_format *f) | |
1371 | { | |
1372 | struct cx23885_fh *fh = file->private_data; | |
1373 | struct cx23885_dev *dev = fh->dev; | |
b1b81f1d | 1374 | |
305519c9 DSL |
1375 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
1376 | f->fmt.pix.bytesperline = 0; | |
1377 | f->fmt.pix.sizeimage = | |
1378 | dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; | |
1379 | f->fmt.pix.colorspace = 0; | |
1380 | f->fmt.pix.width = dev->ts1.width; | |
1381 | f->fmt.pix.height = dev->ts1.height; | |
1382 | f->fmt.pix.field = fh->mpegq.field; | |
1383 | dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n", | |
1384 | dev->ts1.width, dev->ts1.height, fh->mpegq.field); | |
1385 | return 0; | |
1386 | } | |
b1b81f1d | 1387 | |
305519c9 DSL |
1388 | static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, |
1389 | struct v4l2_format *f) | |
1390 | { | |
1391 | struct cx23885_fh *fh = file->private_data; | |
1392 | struct cx23885_dev *dev = fh->dev; | |
b1b81f1d | 1393 | |
305519c9 DSL |
1394 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
1395 | f->fmt.pix.bytesperline = 0; | |
1396 | f->fmt.pix.sizeimage = | |
1397 | dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; | |
305519c9 DSL |
1398 | f->fmt.pix.colorspace = 0; |
1399 | dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n", | |
1400 | dev->ts1.width, dev->ts1.height, fh->mpegq.field); | |
1401 | return 0; | |
1402 | } | |
b1b81f1d | 1403 | |
305519c9 DSL |
1404 | static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, |
1405 | struct v4l2_format *f) | |
1406 | { | |
1407 | struct cx23885_fh *fh = file->private_data; | |
1408 | struct cx23885_dev *dev = fh->dev; | |
b1b81f1d | 1409 | |
305519c9 DSL |
1410 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
1411 | f->fmt.pix.bytesperline = 0; | |
1412 | f->fmt.pix.sizeimage = | |
1413 | dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; | |
1414 | f->fmt.pix.colorspace = 0; | |
1415 | dprintk(1, "VIDIOC_S_FMT: w: %d, h: %d, f: %d\n", | |
1416 | f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field); | |
1417 | return 0; | |
1418 | } | |
b1b81f1d | 1419 | |
305519c9 DSL |
1420 | static int vidioc_reqbufs(struct file *file, void *priv, |
1421 | struct v4l2_requestbuffers *p) | |
1422 | { | |
1423 | struct cx23885_fh *fh = file->private_data; | |
b1b81f1d | 1424 | |
305519c9 DSL |
1425 | return videobuf_reqbufs(&fh->mpegq, p); |
1426 | } | |
1427 | ||
1428 | static int vidioc_querybuf(struct file *file, void *priv, | |
1429 | struct v4l2_buffer *p) | |
1430 | { | |
1431 | struct cx23885_fh *fh = file->private_data; | |
1432 | ||
1433 | return videobuf_querybuf(&fh->mpegq, p); | |
1434 | } | |
1435 | ||
1436 | static int vidioc_qbuf(struct file *file, void *priv, | |
1437 | struct v4l2_buffer *p) | |
1438 | { | |
1439 | struct cx23885_fh *fh = file->private_data; | |
1440 | ||
1441 | return videobuf_qbuf(&fh->mpegq, p); | |
1442 | } | |
1443 | ||
1444 | static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b) | |
1445 | { | |
1446 | struct cx23885_fh *fh = priv; | |
1447 | ||
1448 | return videobuf_dqbuf(&fh->mpegq, b, file->f_flags & O_NONBLOCK); | |
1449 | } | |
1450 | ||
1451 | ||
1452 | static int vidioc_streamon(struct file *file, void *priv, | |
1453 | enum v4l2_buf_type i) | |
1454 | { | |
1455 | struct cx23885_fh *fh = file->private_data; | |
1456 | ||
1457 | return videobuf_streamon(&fh->mpegq); | |
1458 | } | |
1459 | ||
1460 | static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) | |
1461 | { | |
1462 | struct cx23885_fh *fh = file->private_data; | |
1463 | ||
1464 | return videobuf_streamoff(&fh->mpegq); | |
1465 | } | |
1466 | ||
1467 | static int vidioc_g_ext_ctrls(struct file *file, void *priv, | |
1468 | struct v4l2_ext_controls *f) | |
1469 | { | |
1470 | struct cx23885_fh *fh = priv; | |
1471 | struct cx23885_dev *dev = fh->dev; | |
1472 | ||
1473 | if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG) | |
1474 | return -EINVAL; | |
1475 | return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS); | |
1476 | } | |
1477 | ||
1478 | static int vidioc_s_ext_ctrls(struct file *file, void *priv, | |
1479 | struct v4l2_ext_controls *f) | |
1480 | { | |
1481 | struct cx23885_fh *fh = priv; | |
1482 | struct cx23885_dev *dev = fh->dev; | |
1483 | struct cx2341x_mpeg_params p; | |
1484 | int err; | |
1485 | ||
1486 | if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG) | |
1487 | return -EINVAL; | |
1488 | ||
1489 | p = dev->mpeg_params; | |
1490 | err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_S_EXT_CTRLS); | |
1491 | ||
1492 | if (err == 0) { | |
1493 | err = cx2341x_update(dev, cx23885_mbox_func, | |
1494 | &dev->mpeg_params, &p); | |
1495 | dev->mpeg_params = p; | |
b1b81f1d | 1496 | } |
305519c9 DSL |
1497 | return err; |
1498 | } | |
1499 | ||
1500 | static int vidioc_try_ext_ctrls(struct file *file, void *priv, | |
1501 | struct v4l2_ext_controls *f) | |
1502 | { | |
1503 | struct cx23885_fh *fh = priv; | |
1504 | struct cx23885_dev *dev = fh->dev; | |
1505 | struct cx2341x_mpeg_params p; | |
1506 | int err; | |
1507 | ||
1508 | if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG) | |
1509 | return -EINVAL; | |
1510 | ||
1511 | p = dev->mpeg_params; | |
1512 | err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS); | |
1513 | return err; | |
1514 | } | |
1515 | ||
1516 | static int vidioc_log_status(struct file *file, void *priv) | |
1517 | { | |
1518 | struct cx23885_fh *fh = priv; | |
1519 | struct cx23885_dev *dev = fh->dev; | |
1520 | char name[32 + 2]; | |
1521 | ||
1522 | snprintf(name, sizeof(name), "%s/2", dev->name); | |
1523 | printk(KERN_INFO | |
1524 | "%s/2: ============ START LOG STATUS ============\n", | |
1525 | dev->name); | |
0d5a19f1 | 1526 | call_all(dev, core, log_status); |
305519c9 DSL |
1527 | cx2341x_log_status(&dev->mpeg_params, name); |
1528 | printk(KERN_INFO | |
1529 | "%s/2: ============= END LOG STATUS =============\n", | |
1530 | dev->name); | |
b1b81f1d ST |
1531 | return 0; |
1532 | } | |
1533 | ||
305519c9 DSL |
1534 | static int vidioc_querymenu(struct file *file, void *priv, |
1535 | struct v4l2_querymenu *a) | |
1536 | { | |
1537 | struct cx23885_fh *fh = priv; | |
1538 | struct cx23885_dev *dev = fh->dev; | |
1539 | ||
1540 | return cx23885_querymenu(dev, a); | |
1541 | } | |
1542 | ||
1543 | static int vidioc_queryctrl(struct file *file, void *priv, | |
1544 | struct v4l2_queryctrl *c) | |
b1b81f1d | 1545 | { |
305519c9 DSL |
1546 | struct cx23885_fh *fh = priv; |
1547 | struct cx23885_dev *dev = fh->dev; | |
1548 | ||
1549 | return cx23885_queryctrl(dev, c); | |
b1b81f1d ST |
1550 | } |
1551 | ||
bec43661 | 1552 | static int mpeg_open(struct file *file) |
b1b81f1d | 1553 | { |
63b0d5ad | 1554 | struct cx23885_dev *dev = video_drvdata(file); |
b1b81f1d ST |
1555 | struct cx23885_fh *fh; |
1556 | ||
1557 | dprintk(2, "%s()\n", __func__); | |
1558 | ||
b1b81f1d ST |
1559 | /* allocate + initialize per filehandle data */ |
1560 | fh = kzalloc(sizeof(*fh), GFP_KERNEL); | |
0edf2e5e | 1561 | if (!fh) |
b1b81f1d | 1562 | return -ENOMEM; |
63b0d5ad | 1563 | |
b1b81f1d ST |
1564 | file->private_data = fh; |
1565 | fh->dev = dev; | |
1566 | ||
1567 | videobuf_queue_sg_init(&fh->mpegq, &cx23885_qops, | |
1568 | &dev->pci->dev, &dev->ts1.slock, | |
1569 | V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
1570 | V4L2_FIELD_INTERLACED, | |
1571 | sizeof(struct cx23885_buffer), | |
08bff03e | 1572 | fh, NULL); |
b1b81f1d ST |
1573 | return 0; |
1574 | } | |
1575 | ||
bec43661 | 1576 | static int mpeg_release(struct file *file) |
b1b81f1d ST |
1577 | { |
1578 | struct cx23885_fh *fh = file->private_data; | |
1579 | struct cx23885_dev *dev = fh->dev; | |
1580 | ||
1581 | dprintk(2, "%s()\n", __func__); | |
1582 | ||
1583 | /* FIXME: Review this crap */ | |
1584 | /* Shut device down on last close */ | |
1585 | if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) { | |
1586 | if (atomic_dec_return(&dev->v4l_reader_count) == 0) { | |
1587 | /* stop mpeg capture */ | |
1588 | cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0, | |
1589 | CX23885_END_NOW, CX23885_MPEG_CAPTURE, | |
1590 | CX23885_RAW_BITS_NONE); | |
1591 | ||
1592 | msleep(500); | |
1593 | cx23885_417_check_encoder(dev); | |
1594 | ||
1595 | cx23885_cancel_buffers(&fh->dev->ts1); | |
1596 | } | |
1597 | } | |
1598 | ||
1599 | if (fh->mpegq.streaming) | |
1600 | videobuf_streamoff(&fh->mpegq); | |
1601 | if (fh->mpegq.reading) | |
1602 | videobuf_read_stop(&fh->mpegq); | |
1603 | ||
1604 | videobuf_mmap_free(&fh->mpegq); | |
1605 | file->private_data = NULL; | |
1606 | kfree(fh); | |
1607 | ||
1608 | return 0; | |
1609 | } | |
1610 | ||
1611 | static ssize_t mpeg_read(struct file *file, char __user *data, | |
1612 | size_t count, loff_t *ppos) | |
1613 | { | |
1614 | struct cx23885_fh *fh = file->private_data; | |
1615 | struct cx23885_dev *dev = fh->dev; | |
1616 | ||
1617 | dprintk(2, "%s()\n", __func__); | |
1618 | ||
1619 | /* Deal w/ A/V decoder * and mpeg encoder sync issues. */ | |
1620 | /* Start mpeg encoder on first read. */ | |
1621 | if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) { | |
1622 | if (atomic_inc_return(&dev->v4l_reader_count) == 1) { | |
9c9c3d07 | 1623 | if (cx23885_initialize_codec(dev, 1) < 0) |
b1b81f1d ST |
1624 | return -EINVAL; |
1625 | } | |
1626 | } | |
1627 | ||
1628 | return videobuf_read_stream(&fh->mpegq, data, count, ppos, 0, | |
1629 | file->f_flags & O_NONBLOCK); | |
1630 | } | |
1631 | ||
1632 | static unsigned int mpeg_poll(struct file *file, | |
1633 | struct poll_table_struct *wait) | |
1634 | { | |
1635 | struct cx23885_fh *fh = file->private_data; | |
1636 | struct cx23885_dev *dev = fh->dev; | |
1637 | ||
1638 | dprintk(2, "%s\n", __func__); | |
1639 | ||
1640 | return videobuf_poll_stream(file, &fh->mpegq, wait); | |
1641 | } | |
1642 | ||
1643 | static int mpeg_mmap(struct file *file, struct vm_area_struct *vma) | |
1644 | { | |
1645 | struct cx23885_fh *fh = file->private_data; | |
1646 | struct cx23885_dev *dev = fh->dev; | |
1647 | ||
1648 | dprintk(2, "%s()\n", __func__); | |
1649 | ||
1650 | return videobuf_mmap_mapper(&fh->mpegq, vma); | |
1651 | } | |
1652 | ||
bec43661 | 1653 | static struct v4l2_file_operations mpeg_fops = { |
b1b81f1d ST |
1654 | .owner = THIS_MODULE, |
1655 | .open = mpeg_open, | |
1656 | .release = mpeg_release, | |
1657 | .read = mpeg_read, | |
1658 | .poll = mpeg_poll, | |
1659 | .mmap = mpeg_mmap, | |
12a34cc8 | 1660 | .ioctl = video_ioctl2, |
b1b81f1d ST |
1661 | }; |
1662 | ||
a399810c | 1663 | static const struct v4l2_ioctl_ops mpeg_ioctl_ops = { |
09b3bc22 ST |
1664 | .vidioc_querystd = vidioc_g_std, |
1665 | .vidioc_g_std = vidioc_g_std, | |
305519c9 DSL |
1666 | .vidioc_s_std = vidioc_s_std, |
1667 | .vidioc_enum_input = vidioc_enum_input, | |
1668 | .vidioc_g_input = vidioc_g_input, | |
1669 | .vidioc_s_input = vidioc_s_input, | |
1670 | .vidioc_g_tuner = vidioc_g_tuner, | |
1671 | .vidioc_s_tuner = vidioc_s_tuner, | |
1672 | .vidioc_g_frequency = vidioc_g_frequency, | |
1673 | .vidioc_s_frequency = vidioc_s_frequency, | |
1674 | .vidioc_s_ctrl = vidioc_s_ctrl, | |
09b3bc22 | 1675 | .vidioc_g_ctrl = vidioc_g_ctrl, |
305519c9 DSL |
1676 | .vidioc_querycap = vidioc_querycap, |
1677 | .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, | |
1678 | .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, | |
1679 | .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, | |
1680 | .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, | |
1681 | .vidioc_reqbufs = vidioc_reqbufs, | |
1682 | .vidioc_querybuf = vidioc_querybuf, | |
1683 | .vidioc_qbuf = vidioc_qbuf, | |
1684 | .vidioc_dqbuf = vidioc_dqbuf, | |
1685 | .vidioc_streamon = vidioc_streamon, | |
1686 | .vidioc_streamoff = vidioc_streamoff, | |
1687 | .vidioc_g_ext_ctrls = vidioc_g_ext_ctrls, | |
1688 | .vidioc_s_ext_ctrls = vidioc_s_ext_ctrls, | |
1689 | .vidioc_try_ext_ctrls = vidioc_try_ext_ctrls, | |
1690 | .vidioc_log_status = vidioc_log_status, | |
1691 | .vidioc_querymenu = vidioc_querymenu, | |
1692 | .vidioc_queryctrl = vidioc_queryctrl, | |
74618244 AW |
1693 | .vidioc_g_chip_ident = cx23885_g_chip_ident, |
1694 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
1695 | .vidioc_g_register = cx23885_g_register, | |
1696 | .vidioc_s_register = cx23885_s_register, | |
1697 | #endif | |
b1b81f1d ST |
1698 | }; |
1699 | ||
a399810c HV |
1700 | static struct video_device cx23885_mpeg_template = { |
1701 | .name = "cx23885", | |
a399810c HV |
1702 | .fops = &mpeg_fops, |
1703 | .ioctl_ops = &mpeg_ioctl_ops, | |
6655be0f MK |
1704 | .tvnorms = CX23885_NORMS, |
1705 | .current_norm = V4L2_STD_NTSC_M, | |
a399810c HV |
1706 | }; |
1707 | ||
b1b81f1d ST |
1708 | void cx23885_417_unregister(struct cx23885_dev *dev) |
1709 | { | |
1710 | dprintk(1, "%s()\n", __func__); | |
1711 | ||
1712 | if (dev->v4l_device) { | |
f0813b4c | 1713 | if (video_is_registered(dev->v4l_device)) |
b1b81f1d ST |
1714 | video_unregister_device(dev->v4l_device); |
1715 | else | |
1716 | video_device_release(dev->v4l_device); | |
1717 | dev->v4l_device = NULL; | |
1718 | } | |
1719 | } | |
1720 | ||
1721 | static struct video_device *cx23885_video_dev_alloc( | |
1722 | struct cx23885_tsport *tsport, | |
1723 | struct pci_dev *pci, | |
1724 | struct video_device *template, | |
1725 | char *type) | |
1726 | { | |
1727 | struct video_device *vfd; | |
1728 | struct cx23885_dev *dev = tsport->dev; | |
1729 | ||
1730 | dprintk(1, "%s()\n", __func__); | |
1731 | ||
1732 | vfd = video_device_alloc(); | |
1733 | if (NULL == vfd) | |
1734 | return NULL; | |
1735 | *vfd = *template; | |
9def5ed7 ST |
1736 | snprintf(vfd->name, sizeof(vfd->name), "%s (%s)", |
1737 | cx23885_boards[tsport->dev->board].name, type); | |
5e85e732 | 1738 | vfd->parent = &pci->dev; |
b1b81f1d ST |
1739 | vfd->release = video_device_release; |
1740 | return vfd; | |
1741 | } | |
1742 | ||
1743 | int cx23885_417_register(struct cx23885_dev *dev) | |
1744 | { | |
1745 | /* FIXME: Port1 hardcoded here */ | |
1746 | int err = -ENODEV; | |
1747 | struct cx23885_tsport *tsport = &dev->ts1; | |
1748 | ||
1749 | dprintk(1, "%s()\n", __func__); | |
1750 | ||
1751 | if (cx23885_boards[dev->board].portb != CX23885_MPEG_ENCODER) | |
1752 | return err; | |
1753 | ||
1754 | /* Set default TV standard */ | |
1755 | dev->encodernorm = cx23885_tvnorms[0]; | |
1756 | ||
1757 | if (dev->encodernorm.id & V4L2_STD_525_60) | |
1758 | tsport->height = 480; | |
1759 | else | |
1760 | tsport->height = 576; | |
1761 | ||
1762 | tsport->width = 720; | |
1763 | cx2341x_fill_defaults(&dev->mpeg_params); | |
1764 | ||
1765 | dev->mpeg_params.port = CX2341X_PORT_SERIAL; | |
1766 | ||
1767 | /* Allocate and initialize V4L video device */ | |
1768 | dev->v4l_device = cx23885_video_dev_alloc(tsport, | |
1769 | dev->pci, &cx23885_mpeg_template, "mpeg"); | |
63b0d5ad | 1770 | video_set_drvdata(dev->v4l_device, dev); |
b1b81f1d ST |
1771 | err = video_register_device(dev->v4l_device, |
1772 | VFL_TYPE_GRABBER, -1); | |
1773 | if (err < 0) { | |
1774 | printk(KERN_INFO "%s: can't register mpeg device\n", dev->name); | |
1775 | return err; | |
1776 | } | |
1777 | ||
38c7c036 LP |
1778 | printk(KERN_INFO "%s: registered device %s [mpeg]\n", |
1779 | dev->name, video_device_node_name(dev->v4l_device)); | |
b1b81f1d | 1780 | |
9c9c3d07 ST |
1781 | /* ST: Configure the encoder paramaters, but don't begin |
1782 | * encoding, this resolves an issue where the first time the | |
1783 | * encoder is started video can be choppy. | |
1784 | */ | |
1785 | cx23885_initialize_codec(dev, 0); | |
1786 | ||
b1b81f1d ST |
1787 | return 0; |
1788 | } |