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V4L/DVB: cx23885, cx25840: Report the actual length of an IR Rx timeout event
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23888-ir.c
CommitLineData
29f8a0a5
AW		 1/*
2 * Driver for the Conexant CX23885/7/8 PCIe bridge
3 *
4 * CX23888 Integrated Consumer Infrared Controller
5 *
6afdeaf8 6 * Copyright (C) 2009 Andy Walls <awalls@md.metrocast.net>
29f8a0a5
AW		 7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * 02110-1301, USA.
22 */
23
1a0b9d89 24#include <linux/kfifo.h>
5a0e3ad6 25#include <linux/slab.h>
1a0b9d89 26
29f8a0a5
AW		 27#include <media/v4l2-device.h>
28#include <media/v4l2-chip-ident.h>
29
30#include "cx23885.h"
31
1a0b9d89
AW		 32static unsigned int ir_888_debug;
33module_param(ir_888_debug, int, 0644);
34MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]");
35
29f8a0a5
AW		 36#define CX23888_IR_REG_BASE 0x170000
37/*
38 * These CX23888 register offsets have a straightforward one to one mapping
39 * to the CX23885 register offsets of 0x200 through 0x218
40 */
41#define CX23888_IR_CNTRL_REG 0x170000
1a0b9d89
AW		 42#define CNTRL_WIN_3_3 0x00000000
43#define CNTRL_WIN_4_3 0x00000001
44#define CNTRL_WIN_3_4 0x00000002
45#define CNTRL_WIN_4_4 0x00000003
46#define CNTRL_WIN 0x00000003
47#define CNTRL_EDG_NONE 0x00000000
48#define CNTRL_EDG_FALL 0x00000004
49#define CNTRL_EDG_RISE 0x00000008
50#define CNTRL_EDG_BOTH 0x0000000C
51#define CNTRL_EDG 0x0000000C
52#define CNTRL_DMD 0x00000010
53#define CNTRL_MOD 0x00000020
54#define CNTRL_RFE 0x00000040
55#define CNTRL_TFE 0x00000080
56#define CNTRL_RXE 0x00000100
57#define CNTRL_TXE 0x00000200
58#define CNTRL_RIC 0x00000400
59#define CNTRL_TIC 0x00000800
60#define CNTRL_CPL 0x00001000
61#define CNTRL_LBM 0x00002000
62#define CNTRL_R 0x00004000
5a28d9a3
AW		 63/* CX23888 specific control flag */
64#define CNTRL_IVO 0x00008000
1a0b9d89 65
29f8a0a5 66#define CX23888_IR_TXCLK_REG 0x170004
1a0b9d89
AW		 67#define TXCLK_TCD 0x0000FFFF
68
29f8a0a5 69#define CX23888_IR_RXCLK_REG 0x170008
1a0b9d89
AW		 70#define RXCLK_RCD 0x0000FFFF
71
29f8a0a5 72#define CX23888_IR_CDUTY_REG 0x17000C
1a0b9d89
AW		 73#define CDUTY_CDC 0x0000000F
74
29f8a0a5 75#define CX23888_IR_STATS_REG 0x170010
1a0b9d89
AW		 76#define STATS_RTO 0x00000001
77#define STATS_ROR 0x00000002
78#define STATS_RBY 0x00000004
79#define STATS_TBY 0x00000008
80#define STATS_RSR 0x00000010
81#define STATS_TSR 0x00000020
82
29f8a0a5 83#define CX23888_IR_IRQEN_REG 0x170014
1a0b9d89
AW		 84#define IRQEN_RTE 0x00000001
85#define IRQEN_ROE 0x00000002
86#define IRQEN_RSE 0x00000010
87#define IRQEN_TSE 0x00000020
88
29f8a0a5 89#define CX23888_IR_FILTR_REG 0x170018
1a0b9d89
AW		 90#define FILTR_LPF 0x0000FFFF
91
29f8a0a5
AW		 92/* This register doesn't follow the pattern; it's 0x23C on a CX23885 */
93#define CX23888_IR_FIFO_REG 0x170040
1a0b9d89
AW		 94#define FIFO_RXTX 0x0000FFFF
95#define FIFO_RXTX_LVL 0x00010000
96#define FIFO_RXTX_RTO 0x0001FFFF
97#define FIFO_RX_NDV 0x00020000
98#define FIFO_RX_DEPTH 8
99#define FIFO_TX_DEPTH 8
29f8a0a5
AW		 100
101/* CX23888 unique registers */
102#define CX23888_IR_SEEDP_REG 0x17001C
103#define CX23888_IR_TIMOL_REG 0x170020
104#define CX23888_IR_WAKE0_REG 0x170024
105#define CX23888_IR_WAKE1_REG 0x170028
106#define CX23888_IR_WAKE2_REG 0x17002C
107#define CX23888_IR_MASK0_REG 0x170030
108#define CX23888_IR_MASK1_REG 0x170034
109#define CX23888_IR_MAKS2_REG 0x170038
110#define CX23888_IR_DPIPG_REG 0x17003C
111#define CX23888_IR_LEARN_REG 0x170044
112
1a0b9d89 113#define CX23888_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */
928213aa 114#define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ / 2)
1a0b9d89
AW		 115
116#define CX23888_IR_RX_KFIFO_SIZE (512 * sizeof(u32))
117#define CX23888_IR_TX_KFIFO_SIZE (512 * sizeof(u32))
29f8a0a5
AW		 118
119struct cx23888_ir_state {
120 struct v4l2_subdev sd;
121 struct cx23885_dev *dev;
122 u32 id;
123 u32 rev;
1a0b9d89
AW		 124
125 struct v4l2_subdev_ir_parameters rx_params;
126 struct mutex rx_params_lock;
127 atomic_t rxclk_divider;
128 atomic_t rx_invert;
129
7801edb0 130 struct kfifo rx_kfifo;
1a0b9d89
AW		 131 spinlock_t rx_kfifo_lock;
132
133 struct v4l2_subdev_ir_parameters tx_params;
134 struct mutex tx_params_lock;
135 atomic_t txclk_divider;
29f8a0a5
AW		 136};
137
138static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd)
139{
140 return v4l2_get_subdevdata(sd);
141}
142
1a0b9d89
AW		 143/*
144 * IR register block read and write functions
145 */
146static
147inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value)
29f8a0a5 148{
1a0b9d89
AW		 149 cx_write(addr, value);
150 return 0;
151}
152
153static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr)
154{
155 return cx_read(addr);
156}
29f8a0a5 157
1a0b9d89
AW		 158static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr,
159 u32 and_mask, u32 or_value)
160{
161 cx_andor(addr, ~and_mask, or_value);
29f8a0a5
AW		 162 return 0;
163}
164
1a0b9d89
AW		 165/*
166 * Rx and Tx Clock Divider register computations
167 *
168 * Note the largest clock divider value of 0xffff corresponds to:
169 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
170 * which fits in 21 bits, so we'll use unsigned int for time arguments.
171 */
172static inline u16 count_to_clock_divider(unsigned int d)
29f8a0a5 173{
928213aa 174 if (d > RXCLK_RCD + 1)
1a0b9d89
AW		 175 d = RXCLK_RCD;
176 else if (d < 2)
177 d = 1;
178 else
179 d--;
180 return (u16) d;
181}
182
183static inline u16 ns_to_clock_divider(unsigned int ns)
184{
185 return count_to_clock_divider(
928213aa 186 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
1a0b9d89
AW		 187}
188
189static inline unsigned int clock_divider_to_ns(unsigned int divider)
190{
191 /* Period of the Rx or Tx clock in ns */
192 return DIV_ROUND_CLOSEST((divider + 1) * 1000,
928213aa 193 CX23888_IR_REFCLK_FREQ / 1000000);
1a0b9d89
AW		 194}
195
196static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
197{
198 return count_to_clock_divider(
199 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16));
200}
201
202static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
203{
204 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
205}
206
207static inline u16 freq_to_clock_divider(unsigned int freq,
208 unsigned int rollovers)
209{
210 return count_to_clock_divider(
211 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * rollovers));
212}
213
214static inline unsigned int clock_divider_to_freq(unsigned int divider,
215 unsigned int rollovers)
216{
217 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ,
218 (divider + 1) * rollovers);
219}
220
221/*
222 * Low Pass Filter register calculations
223 *
224 * Note the largest count value of 0xffff corresponds to:
225 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
226 * which fits in 21 bits, so we'll use unsigned int for time arguments.
227 */
228static inline u16 count_to_lpf_count(unsigned int d)
229{
230 if (d > FILTR_LPF)
231 d = FILTR_LPF;
232 else if (d < 4)
233 d = 0;
234 return (u16) d;
235}
236
237static inline u16 ns_to_lpf_count(unsigned int ns)
238{
239 return count_to_lpf_count(
928213aa 240 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
1a0b9d89
AW		 241}
242
243static inline unsigned int lpf_count_to_ns(unsigned int count)
244{
245 /* Duration of the Low Pass Filter rejection window in ns */
928213aa
AW		 246 return DIV_ROUND_CLOSEST(count * 1000,
247 CX23888_IR_REFCLK_FREQ / 1000000);
1a0b9d89
AW		 248}
249
250static inline unsigned int lpf_count_to_us(unsigned int count)
251{
252 /* Duration of the Low Pass Filter rejection window in us */
928213aa 253 return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000);
1a0b9d89
AW		 254}
255
256/*
257 * FIFO register pulse width count compuations
258 */
259static u32 clock_divider_to_resolution(u16 divider)
260{
261 /*
262 * Resolution is the duration of 1 tick of the readable portion of
263 * of the pulse width counter as read from the FIFO. The two lsb's are
264 * not readable, hence the << 2. This function returns ns.
265 */
266 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
928213aa 267 CX23888_IR_REFCLK_FREQ / 1000000);
1a0b9d89
AW		 268}
269
270static u64 pulse_width_count_to_ns(u16 count, u16 divider)
271{
272 u64 n;
273 u32 rem;
274
275 /*
276 * The 2 lsb's of the pulse width timer count are not readable, hence
277 * the (count << 2) | 0x3
278 */
279 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
928213aa
AW		 280 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */
281 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
1a0b9d89
AW		 282 n++;
283 return n;
284}
285
286static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
287{
288 u64 n;
289 u32 rem;
290
291 /*
292 * The 2 lsb's of the pulse width timer count are not readable, hence
293 * the (count << 2) | 0x3
294 */
928213aa
AW		 295 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
296 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
297 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
1a0b9d89
AW		 298 n++;
299 return (unsigned int) n;
300}
301
302/*
303 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
304 *
305 * The total pulse clock count is an 18 bit pulse width timer count as the most
306 * significant part and (up to) 16 bit clock divider count as a modulus.
307 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
308 * width timer count's least significant bit.
309 */
310static u64 ns_to_pulse_clocks(u32 ns)
311{
312 u64 clocks;
313 u32 rem;
928213aa 314 clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */
1a0b9d89 315 rem = do_div(clocks, 1000); /* /1000 = cycles */
928213aa 316 if (rem >= 1000 / 2)
1a0b9d89
AW		 317 clocks++;
318 return clocks;
319}
320
321static u16 pulse_clocks_to_clock_divider(u64 count)
322{
323 u32 rem;
324
325 rem = do_div(count, (FIFO_RXTX << 2) | 0x3);
326
327 /* net result needs to be rounded down and decremented by 1 */
928213aa 328 if (count > RXCLK_RCD + 1)
1a0b9d89
AW		 329 count = RXCLK_RCD;
330 else if (count < 2)
331 count = 1;
332 else
333 count--;
334 return (u16) count;
335}
336
337/*
338 * IR Control Register helpers
339 */
340enum tx_fifo_watermark {
341 TX_FIFO_HALF_EMPTY = 0,
342 TX_FIFO_EMPTY = CNTRL_TIC,
343};
344
345enum rx_fifo_watermark {
346 RX_FIFO_HALF_FULL = 0,
347 RX_FIFO_NOT_EMPTY = CNTRL_RIC,
348};
349
350static inline void control_tx_irq_watermark(struct cx23885_dev *dev,
351 enum tx_fifo_watermark level)
352{
353 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level);
354}
355
356static inline void control_rx_irq_watermark(struct cx23885_dev *dev,
357 enum rx_fifo_watermark level)
358{
359 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level);
360}
361
362static inline void control_tx_enable(struct cx23885_dev *dev, bool enable)
363{
364 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
365 enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
366}
367
368static inline void control_rx_enable(struct cx23885_dev *dev, bool enable)
369{
370 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
371 enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
372}
373
374static inline void control_tx_modulation_enable(struct cx23885_dev *dev,
375 bool enable)
376{
377 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD,
378 enable ? CNTRL_MOD : 0);
379}
380
381static inline void control_rx_demodulation_enable(struct cx23885_dev *dev,
382 bool enable)
383{
384 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD,
385 enable ? CNTRL_DMD : 0);
386}
387
388static inline void control_rx_s_edge_detection(struct cx23885_dev *dev,
389 u32 edge_types)
390{
391 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
392 edge_types & CNTRL_EDG_BOTH);
393}
394
395static void control_rx_s_carrier_window(struct cx23885_dev *dev,
396 unsigned int carrier,
397 unsigned int *carrier_range_low,
398 unsigned int *carrier_range_high)
399{
400 u32 v;
401 unsigned int c16 = carrier * 16;
402
403 if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
404 v = CNTRL_WIN_3_4;
405 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
406 } else {
407 v = CNTRL_WIN_3_3;
408 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
409 }
410
411 if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
412 v |= CNTRL_WIN_4_3;
413 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
414 } else {
415 v |= CNTRL_WIN_3_3;
416 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
417 }
418 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v);
419}
420
421static inline void control_tx_polarity_invert(struct cx23885_dev *dev,
422 bool invert)
423{
424 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL,
425 invert ? CNTRL_CPL : 0);
426}
427
5a28d9a3
AW		 428static inline void control_tx_level_invert(struct cx23885_dev *dev,
429 bool invert)
430{
431 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_IVO,
432 invert ? CNTRL_IVO : 0);
433}
434
1a0b9d89
AW		 435/*
436 * IR Rx & Tx Clock Register helpers
437 */
438static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev,
439 unsigned int freq,
440 u16 *divider)
441{
442 *divider = carrier_freq_to_clock_divider(freq);
443 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
444 return clock_divider_to_carrier_freq(*divider);
445}
446
447static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev,
448 unsigned int freq,
449 u16 *divider)
450{
451 *divider = carrier_freq_to_clock_divider(freq);
452 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
453 return clock_divider_to_carrier_freq(*divider);
454}
455
456static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
457 u16 *divider)
458{
459 u64 pulse_clocks;
460
461 if (ns > V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS)
462 ns = V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS;
463 pulse_clocks = ns_to_pulse_clocks(ns);
464 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
465 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
466 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
467}
468
469static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
470 u16 *divider)
471{
472 u64 pulse_clocks;
473
474 if (ns > V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS)
475 ns = V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS;
476 pulse_clocks = ns_to_pulse_clocks(ns);
477 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
478 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
479 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
480}
481
482/*
483 * IR Tx Carrier Duty Cycle register helpers
484 */
485static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev,
486 unsigned int duty_cycle)
487{
488 u32 n;
489 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
490 if (n != 0)
491 n--;
492 if (n > 15)
493 n = 15;
494 cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n);
928213aa 495 return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
1a0b9d89
AW		 496}
497
498/*
499 * IR Filter Register helpers
500 */
501static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns)
502{
503 u32 count = ns_to_lpf_count(min_width_ns);
504 cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count);
505 return lpf_count_to_ns(count);
506}
507
508/*
509 * IR IRQ Enable Register helpers
510 */
511static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask)
512{
513 mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
514 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG,
515 ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
516}
517
518static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask)
519{
520 mask &= IRQEN_TSE;
521 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask);
522}
523
524/*
525 * V4L2 Subdevice IR Ops
526 */
527static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status,
528 bool *handled)
529{
530 struct cx23888_ir_state *state = to_state(sd);
531 struct cx23885_dev *dev = state->dev;
7801edb0 532 unsigned long flags;
1a0b9d89
AW		 533
534 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
535 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
536 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
537
538 u32 rx_data[FIFO_RX_DEPTH];
539 int i, j, k;
540 u32 events, v;
541 int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
542
543 tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
544 rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
545 rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
546 ror = stats & STATS_ROR; /* Rx FIFO Over Run */
547
548 tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
549 rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */
550 rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
551 roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
552
553 *handled = false;
554 v4l2_dbg(2, ir_888_debug, sd, "IRQ Status: %s %s %s %s %s %s\n",
555 tsr ? "tsr" : " ", rsr ? "rsr" : " ",
556 rto ? "rto" : " ", ror ? "ror" : " ",
557 stats & STATS_TBY ? "tby" : " ",
558 stats & STATS_RBY ? "rby" : " ");
559
560 v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n",
561 tse ? "tse" : " ", rse ? "rse" : " ",
562 rte ? "rte" : " ", roe ? "roe" : " ");
563
564 /*
565 * Transmitter interrupt service
566 */
567 if (tse && tsr) {
568 /*
569 * TODO:
570 * Check the watermark threshold setting
571 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
572 * Push the data to the hardware FIFO.
573 * If there was nothing more to send in the tx_kfifo, disable
574 * the TSR IRQ and notify the v4l2_device.
575 * If there was something in the tx_kfifo, check the tx_kfifo
576 * level and notify the v4l2_device, if it is low.
577 */
578 /* For now, inhibit TSR interrupt until Tx is implemented */
579 irqenable_tx(dev, 0);
580 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
581 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
582 *handled = true;
583 }
584
585 /*
586 * Receiver interrupt service
587 */
588 kror = 0;
589 if ((rse && rsr) || (rte && rto)) {
590 /*
591 * Receive data on RSR to clear the STATS_RSR.
592 * Receive data on RTO, since we may not have yet hit the RSR
593 * watermark when we receive the RTO.
594 */
595 for (i = 0, v = FIFO_RX_NDV;
596 (v & FIFO_RX_NDV) && !kror; i = 0) {
597 for (j = 0;
598 (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
599 v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG);
600 rx_data[i++] = v & ~FIFO_RX_NDV;
601 }
602 if (i == 0)
603 break;
604 j = i * sizeof(u32);
7801edb0
SS		 605 k = kfifo_in_locked(&state->rx_kfifo,
606 (unsigned char *) rx_data, j,
607 &state->rx_kfifo_lock);
1a0b9d89
AW		 608 if (k != j)
609 kror++; /* rx_kfifo over run */
610 }
611 *handled = true;
612 }
613
614 events = 0;
615 v = 0;
616 if (kror) {
617 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
618 v4l2_err(sd, "IR receiver software FIFO overrun\n");
619 }
620 if (roe && ror) {
621 /*
622 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
623 * the Rx FIFO Over Run status (STATS_ROR)
624 */
625 v |= CNTRL_RFE;
626 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
627 v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
628 }
629 if (rte && rto) {
630 /*
631 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
632 * the Rx Pulse Width Timer Time Out (STATS_RTO)
633 */
634 v |= CNTRL_RXE;
635 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
636 }
637 if (v) {
638 /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
639 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v);
640 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl);
641 *handled = true;
642 }
7801edb0
SS		 643
644 spin_lock_irqsave(&state->rx_kfifo_lock, flags);
645 if (kfifo_len(&state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2)
1a0b9d89 646 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
7801edb0 647 spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
1a0b9d89
AW		 648
649 if (events)
650 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
29f8a0a5
AW		 651 return 0;
652}
653
1a0b9d89
AW		 654/* Receiver */
655static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
656 ssize_t *num)
29f8a0a5 657{
1a0b9d89
AW		 658 struct cx23888_ir_state *state = to_state(sd);
659 bool invert = (bool) atomic_read(&state->rx_invert);
660 u16 divider = (u16) atomic_read(&state->rxclk_divider);
661
662 unsigned int i, n;
663 u32 *p;
664 u32 u, v;
665
666 n = count / sizeof(u32) * sizeof(u32);
667 if (n == 0) {
668 *num = 0;
669 return 0;
670 }
671
7801edb0 672 n = kfifo_out_locked(&state->rx_kfifo, buf, n, &state->rx_kfifo_lock);
1a0b9d89
AW		 673
674 n /= sizeof(u32);
675 *num = n * sizeof(u32);
676
677 for (p = (u32 *) buf, i = 0; i < n; p++, i++) {
2560d94e 678
1a0b9d89 679 if ((*p & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
2560d94e
AW		 680 /* Assume RTO was because of no IR light input */
681 u = 0;
1a0b9d89 682 v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n");
2560d94e
AW		 683 } else {
684 u = (*p & FIFO_RXTX_LVL)
685 ? V4L2_SUBDEV_IR_PULSE_LEVEL_MASK : 0;
686 if (invert)
687 u = u ? 0 : V4L2_SUBDEV_IR_PULSE_LEVEL_MASK;
1a0b9d89
AW		 688 }
689
1a0b9d89
AW		 690 v = (u32) pulse_width_count_to_ns((u16) (*p & FIFO_RXTX),
691 divider);
692 if (v >= V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS)
693 v = V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS - 1;
694
695 *p = u | v;
696
697 v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns %s\n",
698 v, u ? "mark" : "space");
699 }
700 return 0;
29f8a0a5
AW		 701}
702
1a0b9d89
AW		 703static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd,
704 struct v4l2_subdev_ir_parameters *p)
29f8a0a5 705{
1a0b9d89
AW		 706 struct cx23888_ir_state *state = to_state(sd);
707 mutex_lock(&state->rx_params_lock);
708 memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters));
709 mutex_unlock(&state->rx_params_lock);
710 return 0;
29f8a0a5
AW		 711}
712
1a0b9d89 713static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd)
29f8a0a5 714{
1a0b9d89
AW		 715 struct cx23888_ir_state *state = to_state(sd);
716 struct cx23885_dev *dev = state->dev;
717
718 mutex_lock(&state->rx_params_lock);
719
720 /* Disable or slow down all IR Rx circuits and counters */
721 irqenable_rx(dev, 0);
722 control_rx_enable(dev, false);
723 control_rx_demodulation_enable(dev, false);
724 control_rx_s_edge_detection(dev, CNTRL_EDG_NONE);
725 filter_rx_s_min_width(dev, 0);
726 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD);
727
728 state->rx_params.shutdown = true;
729
730 mutex_unlock(&state->rx_params_lock);
731 return 0;
29f8a0a5
AW		 732}
733
1a0b9d89
AW		 734static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd,
735 struct v4l2_subdev_ir_parameters *p)
29f8a0a5 736{
1a0b9d89
AW		 737 struct cx23888_ir_state *state = to_state(sd);
738 struct cx23885_dev *dev = state->dev;
739 struct v4l2_subdev_ir_parameters *o = &state->rx_params;
740 u16 rxclk_divider;
741
742 if (p->shutdown)
743 return cx23888_ir_rx_shutdown(sd);
744
745 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
746 return -ENOSYS;
747
748 mutex_lock(&state->rx_params_lock);
749
750 o->shutdown = p->shutdown;
751
752 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
753
754 o->bytes_per_data_element = p->bytes_per_data_element = sizeof(u32);
755
756 /* Before we tweak the hardware, we have to disable the receiver */
757 irqenable_rx(dev, 0);
758 control_rx_enable(dev, false);
759
760 control_rx_demodulation_enable(dev, p->modulation);
761 o->modulation = p->modulation;
762
763 if (p->modulation) {
764 p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq,
765 &rxclk_divider);
766
767 o->carrier_freq = p->carrier_freq;
768
769 o->duty_cycle = p->duty_cycle = 50;
770
771 control_rx_s_carrier_window(dev, p->carrier_freq,
772 &p->carrier_range_lower,
773 &p->carrier_range_upper);
774 o->carrier_range_lower = p->carrier_range_lower;
775 o->carrier_range_upper = p->carrier_range_upper;
ceb152ad
AW		 776
777 p->max_pulse_width =
778 (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
1a0b9d89
AW		 779 } else {
780 p->max_pulse_width =
781 rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width,
782 &rxclk_divider);
1a0b9d89 783 }
ceb152ad 784 o->max_pulse_width = p->max_pulse_width;
1a0b9d89
AW		 785 atomic_set(&state->rxclk_divider, rxclk_divider);
786
787 p->noise_filter_min_width =
788 filter_rx_s_min_width(dev, p->noise_filter_min_width);
789 o->noise_filter_min_width = p->noise_filter_min_width;
790
791 p->resolution = clock_divider_to_resolution(rxclk_divider);
792 o->resolution = p->resolution;
793
794 /* FIXME - make this dependent on resolution for better performance */
795 control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL);
796
797 control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH);
798
5a28d9a3
AW		 799 o->invert_level = p->invert_level;
800 atomic_set(&state->rx_invert, p->invert_level);
1a0b9d89
AW		 801
802 o->interrupt_enable = p->interrupt_enable;
803 o->enable = p->enable;
804 if (p->enable) {
7801edb0
SS		 805 unsigned long flags;
806
807 spin_lock_irqsave(&state->rx_kfifo_lock, flags);
808 kfifo_reset(&state->rx_kfifo);
809 /* reset tx_fifo too if there is one... */
810 spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
1a0b9d89
AW		 811 if (p->interrupt_enable)
812 irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
813 control_rx_enable(dev, p->enable);
814 }
815
816 mutex_unlock(&state->rx_params_lock);
817 return 0;
818}
819
820/* Transmitter */
821static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
822 ssize_t *num)
823{
824 struct cx23888_ir_state *state = to_state(sd);
825 struct cx23885_dev *dev = state->dev;
826 /* For now enable the Tx FIFO Service interrupt & pretend we did work */
827 irqenable_tx(dev, IRQEN_TSE);
828 *num = count;
829 return 0;
830}
831
832static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd,
833 struct v4l2_subdev_ir_parameters *p)
834{
835 struct cx23888_ir_state *state = to_state(sd);
836 mutex_lock(&state->tx_params_lock);
837 memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters));
838 mutex_unlock(&state->tx_params_lock);
29f8a0a5
AW		 839 return 0;
840}
841
1a0b9d89
AW		 842static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd)
843{
844 struct cx23888_ir_state *state = to_state(sd);
845 struct cx23885_dev *dev = state->dev;
846
847 mutex_lock(&state->tx_params_lock);
848
849 /* Disable or slow down all IR Tx circuits and counters */
850 irqenable_tx(dev, 0);
851 control_tx_enable(dev, false);
852 control_tx_modulation_enable(dev, false);
853 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD);
854
855 state->tx_params.shutdown = true;
856
857 mutex_unlock(&state->tx_params_lock);
858 return 0;
859}
860
861static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd,
862 struct v4l2_subdev_ir_parameters *p)
863{
864 struct cx23888_ir_state *state = to_state(sd);
865 struct cx23885_dev *dev = state->dev;
866 struct v4l2_subdev_ir_parameters *o = &state->tx_params;
867 u16 txclk_divider;
868
869 if (p->shutdown)
870 return cx23888_ir_tx_shutdown(sd);
871
872 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
873 return -ENOSYS;
874
875 mutex_lock(&state->tx_params_lock);
876
877 o->shutdown = p->shutdown;
878
879 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
880
881 o->bytes_per_data_element = p->bytes_per_data_element = sizeof(u32);
882
883 /* Before we tweak the hardware, we have to disable the transmitter */
884 irqenable_tx(dev, 0);
885 control_tx_enable(dev, false);
886
887 control_tx_modulation_enable(dev, p->modulation);
888 o->modulation = p->modulation;
889
890 if (p->modulation) {
891 p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq,
892 &txclk_divider);
893 o->carrier_freq = p->carrier_freq;
894
895 p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle);
896 o->duty_cycle = p->duty_cycle;
ceb152ad
AW		 897
898 p->max_pulse_width =
899 (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
1a0b9d89
AW		 900 } else {
901 p->max_pulse_width =
902 txclk_tx_s_max_pulse_width(dev, p->max_pulse_width,
903 &txclk_divider);
1a0b9d89 904 }
ceb152ad 905 o->max_pulse_width = p->max_pulse_width;
1a0b9d89
AW		 906 atomic_set(&state->txclk_divider, txclk_divider);
907
908 p->resolution = clock_divider_to_resolution(txclk_divider);
909 o->resolution = p->resolution;
910
911 /* FIXME - make this dependent on resolution for better performance */
912 control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY);
913
5a28d9a3
AW		 914 control_tx_polarity_invert(dev, p->invert_carrier_sense);
915 o->invert_carrier_sense = p->invert_carrier_sense;
916
917 control_tx_level_invert(dev, p->invert_level);
918 o->invert_level = p->invert_level;
1a0b9d89
AW		 919
920 o->interrupt_enable = p->interrupt_enable;
921 o->enable = p->enable;
922 if (p->enable) {
1a0b9d89
AW		 923 if (p->interrupt_enable)
924 irqenable_tx(dev, IRQEN_TSE);
925 control_tx_enable(dev, p->enable);
926 }
927
928 mutex_unlock(&state->tx_params_lock);
929 return 0;
930}
931
932
933/*
934 * V4L2 Subdevice Core Ops
935 */
29f8a0a5
AW		 936static int cx23888_ir_log_status(struct v4l2_subdev *sd)
937{
938 struct cx23888_ir_state *state = to_state(sd);
939 struct cx23885_dev *dev = state->dev;
1a0b9d89
AW		 940 char *s;
941 int i, j;
942
943 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
944 u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD;
945 u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD;
946 u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC;
947 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
948 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
949 u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF;
950
951 v4l2_info(sd, "IR Receiver:\n");
952 v4l2_info(sd, "\tEnabled: %s\n",
953 cntrl & CNTRL_RXE ? "yes" : "no");
954 v4l2_info(sd, "\tDemodulation from a carrier: %s\n",
955 cntrl & CNTRL_DMD ? "enabled" : "disabled");
956 v4l2_info(sd, "\tFIFO: %s\n",
957 cntrl & CNTRL_RFE ? "enabled" : "disabled");
958 switch (cntrl & CNTRL_EDG) {
959 case CNTRL_EDG_NONE:
960 s = "disabled";
961 break;
962 case CNTRL_EDG_FALL:
963 s = "falling edge";
964 break;
965 case CNTRL_EDG_RISE:
966 s = "rising edge";
967 break;
968 case CNTRL_EDG_BOTH:
969 s = "rising & falling edges";
970 break;
971 default:
972 s = "??? edge";
973 break;
974 }
975 v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s);
976 v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
977 cntrl & CNTRL_R ? "not loaded" : "overflow marker");
978 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
979 cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
980 v4l2_info(sd, "\tLoopback mode: %s\n",
981 cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
982 if (cntrl & CNTRL_DMD) {
983 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n",
984 clock_divider_to_carrier_freq(rxclk));
985 switch (cntrl & CNTRL_WIN) {
986 case CNTRL_WIN_3_3:
987 i = 3;
988 j = 3;
989 break;
990 case CNTRL_WIN_4_3:
991 i = 4;
992 j = 3;
993 break;
994 case CNTRL_WIN_3_4:
995 i = 3;
996 j = 4;
997 break;
998 case CNTRL_WIN_4_4:
999 i = 4;
1000 j = 4;
1001 break;
1002 default:
1003 i = 0;
1004 j = 0;
1005 break;
1006 }
1007 v4l2_info(sd, "\tNext carrier edge window: 16 clocks "
1008 "-%1d/+%1d, %u to %u Hz\n", i, j,
1009 clock_divider_to_freq(rxclk, 16 + j),
1010 clock_divider_to_freq(rxclk, 16 - i));
1a0b9d89 1011 }
ceb152ad
AW		 1012 v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n",
1013 pulse_width_count_to_us(FIFO_RXTX, rxclk),
1014 pulse_width_count_to_ns(FIFO_RXTX, rxclk));
1a0b9d89
AW		 1015 v4l2_info(sd, "\tLow pass filter: %s\n",
1016 filtr ? "enabled" : "disabled");
1017 if (filtr)
1018 v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, "
1019 "%u ns\n",
1020 lpf_count_to_us(filtr),
1021 lpf_count_to_ns(filtr));
1022 v4l2_info(sd, "\tPulse width timer timed-out: %s\n",
1023 stats & STATS_RTO ? "yes" : "no");
1024 v4l2_info(sd, "\tPulse width timer time-out intr: %s\n",
1025 irqen & IRQEN_RTE ? "enabled" : "disabled");
1026 v4l2_info(sd, "\tFIFO overrun: %s\n",
1027 stats & STATS_ROR ? "yes" : "no");
1028 v4l2_info(sd, "\tFIFO overrun interrupt: %s\n",
1029 irqen & IRQEN_ROE ? "enabled" : "disabled");
1030 v4l2_info(sd, "\tBusy: %s\n",
1031 stats & STATS_RBY ? "yes" : "no");
1032 v4l2_info(sd, "\tFIFO service requested: %s\n",
1033 stats & STATS_RSR ? "yes" : "no");
1034 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1035 irqen & IRQEN_RSE ? "enabled" : "disabled");
1036
1037 v4l2_info(sd, "IR Transmitter:\n");
1038 v4l2_info(sd, "\tEnabled: %s\n",
1039 cntrl & CNTRL_TXE ? "yes" : "no");
1040 v4l2_info(sd, "\tModulation onto a carrier: %s\n",
1041 cntrl & CNTRL_MOD ? "enabled" : "disabled");
1042 v4l2_info(sd, "\tFIFO: %s\n",
1043 cntrl & CNTRL_TFE ? "enabled" : "disabled");
1044 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1045 cntrl & CNTRL_TIC ? "not empty" : "half full or less");
5a28d9a3
AW		 1046 v4l2_info(sd, "\tOutput pin level inversion %s\n",
1047 cntrl & CNTRL_IVO ? "yes" : "no");
1048 v4l2_info(sd, "\tCarrier polarity: %s\n",
1049 cntrl & CNTRL_CPL ? "space:burst mark:noburst"
1050 : "space:noburst mark:burst");
1a0b9d89
AW		 1051 if (cntrl & CNTRL_MOD) {
1052 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
1053 clock_divider_to_carrier_freq(txclk));
1054 v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n",
1055 cduty + 1);
1a0b9d89 1056 }
ceb152ad
AW		 1057 v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n",
1058 pulse_width_count_to_us(FIFO_RXTX, txclk),
1059 pulse_width_count_to_ns(FIFO_RXTX, txclk));
1a0b9d89
AW		 1060 v4l2_info(sd, "\tBusy: %s\n",
1061 stats & STATS_TBY ? "yes" : "no");
1062 v4l2_info(sd, "\tFIFO service requested: %s\n",
1063 stats & STATS_TSR ? "yes" : "no");
1064 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1065 irqen & IRQEN_TSE ? "enabled" : "disabled");
1066
29f8a0a5
AW		 1067 return 0;
1068}
1069
1070static inline int cx23888_ir_dbg_match(const struct v4l2_dbg_match *match)
1071{
1072 return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 2;
1073}
1074
1075static int cx23888_ir_g_chip_ident(struct v4l2_subdev *sd,
1076 struct v4l2_dbg_chip_ident *chip)
1077{
1078 struct cx23888_ir_state *state = to_state(sd);
1079
1080 if (cx23888_ir_dbg_match(&chip->match)) {
1081 chip->ident = state->id;
1082 chip->revision = state->rev;
1083 }
1084 return 0;
1085}
1086
1087#ifdef CONFIG_VIDEO_ADV_DEBUG
1088static int cx23888_ir_g_register(struct v4l2_subdev *sd,
1089 struct v4l2_dbg_register *reg)
1090{
1091 struct cx23888_ir_state *state = to_state(sd);
1092 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1093
1094 if (!cx23888_ir_dbg_match(&reg->match))
1095 return -EINVAL;
1096 if ((addr & 0x3) != 0)
1097 return -EINVAL;
1098 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1099 return -EINVAL;
1100 if (!capable(CAP_SYS_ADMIN))
1101 return -EPERM;
1102 reg->size = 4;
1103 reg->val = cx23888_ir_read4(state->dev, addr);
1104 return 0;
1105}
1106
1107static int cx23888_ir_s_register(struct v4l2_subdev *sd,
1108 struct v4l2_dbg_register *reg)
1109{
1110 struct cx23888_ir_state *state = to_state(sd);
1111 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1112
1113 if (!cx23888_ir_dbg_match(&reg->match))
1114 return -EINVAL;
1115 if ((addr & 0x3) != 0)
1116 return -EINVAL;
1117 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1118 return -EINVAL;
1119 if (!capable(CAP_SYS_ADMIN))
1120 return -EPERM;
1121 cx23888_ir_write4(state->dev, addr, reg->val);
1122 return 0;
1123}
1124#endif
1125
1126static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = {
1127 .g_chip_ident = cx23888_ir_g_chip_ident,
1128 .log_status = cx23888_ir_log_status,
1129#ifdef CONFIG_VIDEO_ADV_DEBUG
1130 .g_register = cx23888_ir_g_register,
1131 .s_register = cx23888_ir_s_register,
1132#endif
260e689b 1133 .interrupt_service_routine = cx23888_ir_irq_handler,
29f8a0a5
AW		 1134};
1135
1a0b9d89 1136static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = {
1a0b9d89
AW		 1137 .rx_read = cx23888_ir_rx_read,
1138 .rx_g_parameters = cx23888_ir_rx_g_parameters,
1139 .rx_s_parameters = cx23888_ir_rx_s_parameters,
1140
1141 .tx_write = cx23888_ir_tx_write,
1142 .tx_g_parameters = cx23888_ir_tx_g_parameters,
1143 .tx_s_parameters = cx23888_ir_tx_s_parameters,
1144};
1145
29f8a0a5
AW		 1146static const struct v4l2_subdev_ops cx23888_ir_controller_ops = {
1147 .core = &cx23888_ir_core_ops,
1a0b9d89
AW		 1148 .ir = &cx23888_ir_ir_ops,
1149};
1150
1151static const struct v4l2_subdev_ir_parameters default_rx_params = {
1152 .bytes_per_data_element = sizeof(u32),
1153 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1154
1155 .enable = false,
1156 .interrupt_enable = false,
1157 .shutdown = true,
1158
1159 .modulation = true,
1160 .carrier_freq = 36000, /* 36 kHz - RC-5, RC-6, and RC-6A carrier */
1161
1162 /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1163 /* RC-6A: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1164 .noise_filter_min_width = 333333, /* ns */
1165 .carrier_range_lower = 35000,
1166 .carrier_range_upper = 37000,
5a28d9a3 1167 .invert_level = false,
1a0b9d89
AW		 1168};
1169
1170static const struct v4l2_subdev_ir_parameters default_tx_params = {
1171 .bytes_per_data_element = sizeof(u32),
1172 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1173
1174 .enable = false,
1175 .interrupt_enable = false,
1176 .shutdown = true,
1177
1178 .modulation = true,
1179 .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1180 .duty_cycle = 25, /* 25 % - RC-5 carrier */
5a28d9a3
AW		 1181 .invert_level = false,
1182 .invert_carrier_sense = false,
29f8a0a5
AW		 1183};
1184
1185int cx23888_ir_probe(struct cx23885_dev *dev)
1186{
1187 struct cx23888_ir_state *state;
1188 struct v4l2_subdev *sd;
1a0b9d89
AW		 1189 struct v4l2_subdev_ir_parameters default_params;
1190 int ret;
29f8a0a5
AW		 1191
1192 state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL);
1193 if (state == NULL)
1194 return -ENOMEM;
1195
1a0b9d89 1196 spin_lock_init(&state->rx_kfifo_lock);
7801edb0 1197 if (kfifo_alloc(&state->rx_kfifo, CX23888_IR_RX_KFIFO_SIZE, GFP_KERNEL))
1a0b9d89 1198 return -ENOMEM;
1a0b9d89 1199
29f8a0a5
AW		 1200 state->dev = dev;
1201 state->id = V4L2_IDENT_CX23888_IR;
1202 state->rev = 0;
1203 sd = &state->sd;
1204
1205 v4l2_subdev_init(sd, &cx23888_ir_controller_ops);
1206 v4l2_set_subdevdata(sd, state);
1207 /* FIXME - fix the formatting of dev->v4l2_dev.name and use it */
1208 snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name);
1209 sd->grp_id = CX23885_HW_888_IR;
1a0b9d89
AW		 1210
1211 ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd);
1212 if (ret == 0) {
1213 /*
1214 * Ensure no interrupts arrive from '888 specific conditions,
1215 * since we ignore them in this driver to have commonality with
1216 * similar IR controller cores.
1217 */
1218 cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0);
1219
1220 mutex_init(&state->rx_params_lock);
1221 memcpy(&default_params, &default_rx_params,
1222 sizeof(struct v4l2_subdev_ir_parameters));
1223 v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1224
1225 mutex_init(&state->tx_params_lock);
1226 memcpy(&default_params, &default_tx_params,
1227 sizeof(struct v4l2_subdev_ir_parameters));
1228 v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1229 } else {
7801edb0 1230 kfifo_free(&state->rx_kfifo);
1a0b9d89
AW		 1231 }
1232 return ret;
29f8a0a5
AW		 1233}
1234
1235int cx23888_ir_remove(struct cx23885_dev *dev)
1236{
1237 struct v4l2_subdev *sd;
1238 struct cx23888_ir_state *state;
1239
1240 sd = cx23885_find_hw(dev, CX23885_HW_888_IR);
1241 if (sd == NULL)
1242 return -ENODEV;
1243
1a0b9d89
AW		 1244 cx23888_ir_rx_shutdown(sd);
1245 cx23888_ir_tx_shutdown(sd);
29f8a0a5
AW		 1246
1247 state = to_state(sd);
1248 v4l2_device_unregister_subdev(sd);
7801edb0 1249 kfifo_free(&state->rx_kfifo);
29f8a0a5
AW		 1250 kfree(state);
1251 /* Nothing more to free() as state held the actual v4l2_subdev object */
1252 return 0;
1253}
Linux kernel - Deliverables
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