Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * |
3 | * device driver for Conexant 2388x based TV cards | |
4 | * MPEG Transport Stream (DVB) routines | |
5 | * | |
fc40b261 | 6 | * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au> |
1da177e4 LT |
7 | * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/fs.h> | |
28 | #include <linux/kthread.h> | |
29 | #include <linux/file.h> | |
30 | #include <linux/suspend.h> | |
31 | ||
1da177e4 LT |
32 | #include "cx88.h" |
33 | #include "dvb-pll.h" | |
5e453dc7 | 34 | #include <media/v4l2-common.h> |
41ef7c1e | 35 | |
1f10c7af AQ |
36 | #include "mt352.h" |
37 | #include "mt352_priv.h" | |
38 | #ifdef HAVE_VP3054_I2C | |
39 | # include "cx88-vp3054-i2c.h" | |
0fa14aa6 | 40 | #endif |
1f10c7af AQ |
41 | #include "zl10353.h" |
42 | #include "cx22702.h" | |
43 | #include "or51132.h" | |
44 | #include "lgdt330x.h" | |
76db93d0 | 45 | #include "lgh06xf.h" |
1f10c7af AQ |
46 | #include "nxt200x.h" |
47 | #include "cx24123.h" | |
cd20ca9f | 48 | #include "isl6421.h" |
1da177e4 LT |
49 | |
50 | MODULE_DESCRIPTION("driver for cx2388x based DVB cards"); | |
51 | MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>"); | |
52 | MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]"); | |
53 | MODULE_LICENSE("GPL"); | |
54 | ||
55 | static unsigned int debug = 0; | |
56 | module_param(debug, int, 0644); | |
57 | MODULE_PARM_DESC(debug,"enable debug messages [dvb]"); | |
58 | ||
59 | #define dprintk(level,fmt, arg...) if (debug >= level) \ | |
6c5be74c | 60 | printk(KERN_DEBUG "%s/2-dvb: " fmt, core->name, ## arg) |
1da177e4 LT |
61 | |
62 | /* ------------------------------------------------------------------ */ | |
63 | ||
64 | static int dvb_buf_setup(struct videobuf_queue *q, | |
65 | unsigned int *count, unsigned int *size) | |
66 | { | |
67 | struct cx8802_dev *dev = q->priv_data; | |
68 | ||
69 | dev->ts_packet_size = 188 * 4; | |
70 | dev->ts_packet_count = 32; | |
71 | ||
72 | *size = dev->ts_packet_size * dev->ts_packet_count; | |
73 | *count = 32; | |
74 | return 0; | |
75 | } | |
76 | ||
77 | static int dvb_buf_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb, | |
78 | enum v4l2_field field) | |
79 | { | |
80 | struct cx8802_dev *dev = q->priv_data; | |
c7b0ac05 | 81 | return cx8802_buf_prepare(q, dev, (struct cx88_buffer*)vb,field); |
1da177e4 LT |
82 | } |
83 | ||
84 | static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) | |
85 | { | |
86 | struct cx8802_dev *dev = q->priv_data; | |
87 | cx8802_buf_queue(dev, (struct cx88_buffer*)vb); | |
88 | } | |
89 | ||
90 | static void dvb_buf_release(struct videobuf_queue *q, struct videobuf_buffer *vb) | |
91 | { | |
c7b0ac05 | 92 | cx88_free_buffer(q, (struct cx88_buffer*)vb); |
1da177e4 LT |
93 | } |
94 | ||
408b664a | 95 | static struct videobuf_queue_ops dvb_qops = { |
1da177e4 LT |
96 | .buf_setup = dvb_buf_setup, |
97 | .buf_prepare = dvb_buf_prepare, | |
98 | .buf_queue = dvb_buf_queue, | |
99 | .buf_release = dvb_buf_release, | |
100 | }; | |
101 | ||
102 | /* ------------------------------------------------------------------ */ | |
3d7d027a | 103 | static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe) |
1da177e4 LT |
104 | { |
105 | static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 }; | |
106 | static u8 reset [] = { RESET, 0x80 }; | |
107 | static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | |
108 | static u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 }; | |
109 | static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 }; | |
110 | static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 }; | |
111 | ||
112 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
113 | udelay(200); | |
114 | mt352_write(fe, reset, sizeof(reset)); | |
115 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
116 | ||
117 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
118 | mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg)); | |
119 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
120 | return 0; | |
121 | } | |
122 | ||
43eabb4e CP |
123 | static int dvico_dual_demod_init(struct dvb_frontend *fe) |
124 | { | |
125 | static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 }; | |
126 | static u8 reset [] = { RESET, 0x80 }; | |
127 | static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | |
128 | static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 }; | |
129 | static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 }; | |
130 | static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 }; | |
131 | ||
132 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
133 | udelay(200); | |
134 | mt352_write(fe, reset, sizeof(reset)); | |
135 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
136 | ||
137 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
138 | mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg)); | |
139 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
140 | ||
141 | return 0; | |
142 | } | |
143 | ||
1da177e4 LT |
144 | static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe) |
145 | { | |
146 | static u8 clock_config [] = { 0x89, 0x38, 0x39 }; | |
147 | static u8 reset [] = { 0x50, 0x80 }; | |
148 | static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 }; | |
149 | static u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF, | |
f2421ca3 | 150 | 0x00, 0xFF, 0x00, 0x40, 0x40 }; |
1da177e4 LT |
151 | static u8 dntv_extra[] = { 0xB5, 0x7A }; |
152 | static u8 capt_range_cfg[] = { 0x75, 0x32 }; | |
153 | ||
154 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
155 | udelay(2000); | |
156 | mt352_write(fe, reset, sizeof(reset)); | |
157 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
158 | ||
159 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
160 | udelay(2000); | |
161 | mt352_write(fe, dntv_extra, sizeof(dntv_extra)); | |
162 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
1da177e4 | 167 | static struct mt352_config dvico_fusionhdtv = { |
f7b54b10 | 168 | .demod_address = 0x0f, |
3d7d027a | 169 | .demod_init = dvico_fusionhdtv_demod_init, |
1da177e4 LT |
170 | }; |
171 | ||
172 | static struct mt352_config dntv_live_dvbt_config = { | |
173 | .demod_address = 0x0f, | |
174 | .demod_init = dntv_live_dvbt_demod_init, | |
1da177e4 | 175 | }; |
fc40b261 | 176 | |
43eabb4e | 177 | static struct mt352_config dvico_fusionhdtv_dual = { |
f7b54b10 | 178 | .demod_address = 0x0f, |
43eabb4e | 179 | .demod_init = dvico_dual_demod_init, |
43eabb4e CP |
180 | }; |
181 | ||
fc40b261 | 182 | #ifdef HAVE_VP3054_I2C |
3d7d027a CP |
183 | static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe) |
184 | { | |
185 | static u8 clock_config [] = { 0x89, 0x38, 0x38 }; | |
186 | static u8 reset [] = { 0x50, 0x80 }; | |
187 | static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 }; | |
188 | static u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF, | |
189 | 0x00, 0xFF, 0x00, 0x40, 0x40 }; | |
190 | static u8 dntv_extra[] = { 0xB5, 0x7A }; | |
191 | static u8 capt_range_cfg[] = { 0x75, 0x32 }; | |
192 | ||
193 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
194 | udelay(2000); | |
195 | mt352_write(fe, reset, sizeof(reset)); | |
196 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
197 | ||
198 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
199 | udelay(2000); | |
200 | mt352_write(fe, dntv_extra, sizeof(dntv_extra)); | |
201 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
fc40b261 CP |
206 | static int philips_fmd1216_pll_init(struct dvb_frontend *fe) |
207 | { | |
208 | struct cx8802_dev *dev= fe->dvb->priv; | |
209 | ||
210 | /* this message is to set up ATC and ALC */ | |
211 | static u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0xa0 }; | |
212 | struct i2c_msg msg = | |
213 | { .addr = dev->core->pll_addr, .flags = 0, | |
214 | .buf = fmd1216_init, .len = sizeof(fmd1216_init) }; | |
215 | int err; | |
216 | ||
dea74869 PB |
217 | if (fe->ops.i2c_gate_ctrl) |
218 | fe->ops.i2c_gate_ctrl(fe, 1); | |
fc40b261 CP |
219 | if ((err = i2c_transfer(&dev->core->i2c_adap, &msg, 1)) != 1) { |
220 | if (err < 0) | |
221 | return err; | |
222 | else | |
223 | return -EREMOTEIO; | |
224 | } | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
f54376e2 AQ |
229 | static int dntv_live_dvbt_pro_tuner_set_params(struct dvb_frontend* fe, |
230 | struct dvb_frontend_parameters* params) | |
fc40b261 CP |
231 | { |
232 | struct cx8802_dev *dev= fe->dvb->priv; | |
f54376e2 | 233 | u8 buf[4]; |
fc40b261 CP |
234 | struct i2c_msg msg = |
235 | { .addr = dev->core->pll_addr, .flags = 0, | |
f54376e2 | 236 | .buf = buf, .len = 4 }; |
fc40b261 CP |
237 | int err; |
238 | ||
239 | /* Switch PLL to DVB mode */ | |
240 | err = philips_fmd1216_pll_init(fe); | |
241 | if (err) | |
242 | return err; | |
243 | ||
244 | /* Tune PLL */ | |
f54376e2 | 245 | dvb_pll_configure(dev->core->pll_desc, buf, |
fc40b261 CP |
246 | params->frequency, |
247 | params->u.ofdm.bandwidth); | |
dea74869 PB |
248 | if (fe->ops.i2c_gate_ctrl) |
249 | fe->ops.i2c_gate_ctrl(fe, 1); | |
fc40b261 | 250 | if ((err = i2c_transfer(&dev->core->i2c_adap, &msg, 1)) != 1) { |
f54376e2 | 251 | |
fc40b261 | 252 | printk(KERN_WARNING "cx88-dvb: %s error " |
f7b54b10 MK |
253 | "(addr %02x <- %02x, err = %i)\n", |
254 | __FUNCTION__, dev->core->pll_addr, buf[0], err); | |
fc40b261 CP |
255 | if (err < 0) |
256 | return err; | |
257 | else | |
258 | return -EREMOTEIO; | |
259 | } | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | static struct mt352_config dntv_live_dvbt_pro_config = { | |
265 | .demod_address = 0x0f, | |
266 | .no_tuner = 1, | |
3d7d027a | 267 | .demod_init = dntv_live_dvbt_pro_demod_init, |
fc40b261 CP |
268 | }; |
269 | #endif | |
1da177e4 | 270 | |
f54376e2 AQ |
271 | static int dvico_hybrid_tuner_set_params(struct dvb_frontend *fe, |
272 | struct dvb_frontend_parameters *params) | |
780dfef3 | 273 | { |
f54376e2 | 274 | u8 pllbuf[4]; |
780dfef3 CP |
275 | struct cx8802_dev *dev= fe->dvb->priv; |
276 | struct i2c_msg msg = | |
277 | { .addr = dev->core->pll_addr, .flags = 0, | |
f54376e2 | 278 | .buf = pllbuf, .len = 4 }; |
780dfef3 CP |
279 | int err; |
280 | ||
f54376e2 | 281 | dvb_pll_configure(dev->core->pll_desc, pllbuf, |
780dfef3 CP |
282 | params->frequency, |
283 | params->u.ofdm.bandwidth); | |
284 | ||
dea74869 PB |
285 | if (fe->ops.i2c_gate_ctrl) |
286 | fe->ops.i2c_gate_ctrl(fe, 1); | |
780dfef3 CP |
287 | if ((err = i2c_transfer(&dev->core->i2c_adap, &msg, 1)) != 1) { |
288 | printk(KERN_WARNING "cx88-dvb: %s error " | |
f7b54b10 MK |
289 | "(addr %02x <- %02x, err = %i)\n", |
290 | __FUNCTION__, pllbuf[0], pllbuf[1], err); | |
780dfef3 CP |
291 | if (err < 0) |
292 | return err; | |
293 | else | |
294 | return -EREMOTEIO; | |
295 | } | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | static struct zl10353_config dvico_fusionhdtv_hybrid = { | |
f7b54b10 | 301 | .demod_address = 0x0f, |
f54376e2 | 302 | .no_tuner = 1, |
780dfef3 CP |
303 | }; |
304 | ||
305 | static struct zl10353_config dvico_fusionhdtv_plus_v1_1 = { | |
f7b54b10 | 306 | .demod_address = 0x0f, |
780dfef3 | 307 | }; |
780dfef3 | 308 | |
1da177e4 LT |
309 | static struct cx22702_config connexant_refboard_config = { |
310 | .demod_address = 0x43, | |
38d84c3b | 311 | .output_mode = CX22702_SERIAL_OUTPUT, |
1da177e4 LT |
312 | }; |
313 | ||
314 | static struct cx22702_config hauppauge_novat_config = { | |
315 | .demod_address = 0x43, | |
38d84c3b | 316 | .output_mode = CX22702_SERIAL_OUTPUT, |
1da177e4 | 317 | }; |
611900c1 ST |
318 | static struct cx22702_config hauppauge_hvr1100_config = { |
319 | .demod_address = 0x63, | |
320 | .output_mode = CX22702_SERIAL_OUTPUT, | |
611900c1 | 321 | }; |
6c5be74c | 322 | static struct cx22702_config hauppauge_hvr3000_config = { |
aa481a65 ST |
323 | .demod_address = 0x63, |
324 | .output_mode = CX22702_SERIAL_OUTPUT, | |
325 | }; | |
1da177e4 | 326 | |
6c5be74c ST |
327 | static int cx88_dvb_bus_ctrl(struct dvb_frontend* fe, |
328 | int acquire) | |
329 | { | |
330 | struct cx8802_dev *dev= fe->dvb->priv; | |
331 | struct cx8802_driver *drv = NULL; | |
332 | int ret = 0; | |
333 | ||
334 | drv = cx8802_get_driver(dev, CX88_MPEG_DVB); | |
335 | if (drv) { | |
336 | if(acquire) | |
337 | ret = drv->request_acquire(drv); | |
338 | else | |
339 | ret = drv->request_release(drv); | |
340 | } | |
341 | ||
342 | return ret; | |
343 | } | |
344 | ||
345 | static struct cx22702_config hauppauge_hvr1300_config = { | |
76dc82ab | 346 | .demod_address = 0x63, |
6c5be74c | 347 | .output_mode = CX22702_SERIAL_OUTPUT, |
76dc82ab ST |
348 | }; |
349 | ||
1da177e4 LT |
350 | static int or51132_set_ts_param(struct dvb_frontend* fe, |
351 | int is_punctured) | |
352 | { | |
353 | struct cx8802_dev *dev= fe->dvb->priv; | |
354 | dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00; | |
355 | return 0; | |
356 | } | |
357 | ||
408b664a | 358 | static struct or51132_config pchdtv_hd3000 = { |
f7b54b10 MK |
359 | .demod_address = 0x15, |
360 | .set_ts_params = or51132_set_ts_param, | |
1da177e4 | 361 | }; |
1da177e4 | 362 | |
6ddcc919 | 363 | static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index) |
0ccef6db MK |
364 | { |
365 | struct cx8802_dev *dev= fe->dvb->priv; | |
366 | struct cx88_core *core = dev->core; | |
367 | ||
368 | dprintk(1, "%s: index = %d\n", __FUNCTION__, index); | |
369 | if (index == 0) | |
370 | cx_clear(MO_GP0_IO, 8); | |
371 | else | |
372 | cx_set(MO_GP0_IO, 8); | |
373 | return 0; | |
374 | } | |
375 | ||
6ddcc919 | 376 | static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured) |
f1798495 MK |
377 | { |
378 | struct cx8802_dev *dev= fe->dvb->priv; | |
379 | if (is_punctured) | |
380 | dev->ts_gen_cntrl |= 0x04; | |
381 | else | |
382 | dev->ts_gen_cntrl &= ~0x04; | |
383 | return 0; | |
384 | } | |
385 | ||
6ddcc919 | 386 | static struct lgdt330x_config fusionhdtv_3_gold = { |
f7b54b10 MK |
387 | .demod_address = 0x0e, |
388 | .demod_chip = LGDT3302, | |
389 | .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */ | |
390 | .set_ts_params = lgdt330x_set_ts_param, | |
0d723c09 | 391 | }; |
e52e98a7 MCC |
392 | |
393 | static struct lgdt330x_config fusionhdtv_5_gold = { | |
f7b54b10 MK |
394 | .demod_address = 0x0e, |
395 | .demod_chip = LGDT3303, | |
396 | .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */ | |
397 | .set_ts_params = lgdt330x_set_ts_param, | |
e52e98a7 | 398 | }; |
da215d22 RS |
399 | |
400 | static struct lgdt330x_config pchdtv_hd5500 = { | |
f7b54b10 MK |
401 | .demod_address = 0x59, |
402 | .demod_chip = LGDT3303, | |
403 | .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */ | |
404 | .set_ts_params = lgdt330x_set_ts_param, | |
da215d22 | 405 | }; |
f1798495 | 406 | |
fde6d31e KL |
407 | static int nxt200x_set_ts_param(struct dvb_frontend* fe, |
408 | int is_punctured) | |
409 | { | |
410 | struct cx8802_dev *dev= fe->dvb->priv; | |
411 | dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00; | |
412 | return 0; | |
413 | } | |
414 | ||
d4c34aa0 KL |
415 | static int nxt200x_set_pll_input(u8* buf, int input) |
416 | { | |
417 | if (input) | |
418 | buf[3] |= 0x08; | |
419 | else | |
420 | buf[3] &= ~0x08; | |
421 | return 0; | |
422 | } | |
423 | ||
fde6d31e | 424 | static struct nxt200x_config ati_hdtvwonder = { |
f7b54b10 MK |
425 | .demod_address = 0x0a, |
426 | .set_pll_input = nxt200x_set_pll_input, | |
427 | .set_ts_params = nxt200x_set_ts_param, | |
fde6d31e | 428 | }; |
fde6d31e | 429 | |
0fa14aa6 ST |
430 | static int cx24123_set_ts_param(struct dvb_frontend* fe, |
431 | int is_punctured) | |
432 | { | |
433 | struct cx8802_dev *dev= fe->dvb->priv; | |
f7b54b10 | 434 | dev->ts_gen_cntrl = 0x02; |
0fa14aa6 ST |
435 | return 0; |
436 | } | |
437 | ||
f7b54b10 MK |
438 | static int kworld_dvbs_100_set_voltage(struct dvb_frontend* fe, |
439 | fe_sec_voltage_t voltage) | |
0e0351e3 VC |
440 | { |
441 | struct cx8802_dev *dev= fe->dvb->priv; | |
442 | struct cx88_core *core = dev->core; | |
443 | ||
cd20ca9f | 444 | if (voltage == SEC_VOLTAGE_OFF) { |
f7b54b10 | 445 | cx_write(MO_GP0_IO, 0x000006fb); |
cd20ca9f AQ |
446 | } else { |
447 | cx_write(MO_GP0_IO, 0x000006f9); | |
448 | } | |
449 | ||
450 | if (core->prev_set_voltage) | |
451 | return core->prev_set_voltage(fe, voltage); | |
452 | return 0; | |
0e0351e3 VC |
453 | } |
454 | ||
f7b54b10 MK |
455 | static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe, |
456 | fe_sec_voltage_t voltage) | |
c02a34f4 SA |
457 | { |
458 | struct cx8802_dev *dev= fe->dvb->priv; | |
459 | struct cx88_core *core = dev->core; | |
460 | ||
461 | if (voltage == SEC_VOLTAGE_OFF) { | |
462 | dprintk(1,"LNB Voltage OFF\n"); | |
463 | cx_write(MO_GP0_IO, 0x0000efff); | |
464 | } | |
465 | ||
466 | if (core->prev_set_voltage) | |
467 | return core->prev_set_voltage(fe, voltage); | |
468 | return 0; | |
469 | } | |
470 | ||
471 | static struct cx24123_config geniatech_dvbs_config = { | |
f7b54b10 MK |
472 | .demod_address = 0x55, |
473 | .set_ts_params = cx24123_set_ts_param, | |
c02a34f4 SA |
474 | }; |
475 | ||
0fa14aa6 | 476 | static struct cx24123_config hauppauge_novas_config = { |
f7b54b10 MK |
477 | .demod_address = 0x55, |
478 | .set_ts_params = cx24123_set_ts_param, | |
0e0351e3 VC |
479 | }; |
480 | ||
481 | static struct cx24123_config kworld_dvbs_100_config = { | |
f7b54b10 MK |
482 | .demod_address = 0x15, |
483 | .set_ts_params = cx24123_set_ts_param, | |
ef76856d | 484 | .lnb_polarity = 1, |
0fa14aa6 | 485 | }; |
0fa14aa6 | 486 | |
1da177e4 LT |
487 | static int dvb_register(struct cx8802_dev *dev) |
488 | { | |
489 | /* init struct videobuf_dvb */ | |
490 | dev->dvb.name = dev->core->name; | |
491 | dev->ts_gen_cntrl = 0x0c; | |
492 | ||
493 | /* init frontend */ | |
494 | switch (dev->core->board) { | |
1da177e4 | 495 | case CX88_BOARD_HAUPPAUGE_DVB_T1: |
f7b54b10 MK |
496 | dev->dvb.frontend = dvb_attach(cx22702_attach, |
497 | &hauppauge_novat_config, | |
498 | &dev->core->i2c_adap); | |
f54376e2 | 499 | if (dev->dvb.frontend != NULL) { |
2bfe031d | 500 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, |
f7b54b10 MK |
501 | &dev->core->i2c_adap, |
502 | &dvb_pll_thomson_dtt759x); | |
f54376e2 | 503 | } |
1da177e4 | 504 | break; |
e057ee11 | 505 | case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1: |
1da177e4 | 506 | case CX88_BOARD_CONEXANT_DVB_T1: |
f39624fd | 507 | case CX88_BOARD_KWORLD_DVB_T_CX22702: |
2b5200a7 | 508 | case CX88_BOARD_WINFAST_DTV1000: |
f7b54b10 MK |
509 | dev->dvb.frontend = dvb_attach(cx22702_attach, |
510 | &connexant_refboard_config, | |
511 | &dev->core->i2c_adap); | |
f54376e2 | 512 | if (dev->dvb.frontend != NULL) { |
2bfe031d | 513 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60, |
f7b54b10 MK |
514 | &dev->core->i2c_adap, |
515 | &dvb_pll_thomson_dtt7579); | |
f54376e2 | 516 | } |
1da177e4 | 517 | break; |
4bd6e9d9 | 518 | case CX88_BOARD_WINFAST_DTV2000H: |
611900c1 ST |
519 | case CX88_BOARD_HAUPPAUGE_HVR1100: |
520 | case CX88_BOARD_HAUPPAUGE_HVR1100LP: | |
f7b54b10 MK |
521 | dev->dvb.frontend = dvb_attach(cx22702_attach, |
522 | &hauppauge_hvr1100_config, | |
523 | &dev->core->i2c_adap); | |
f54376e2 | 524 | if (dev->dvb.frontend != NULL) { |
2bfe031d | 525 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, |
f7b54b10 MK |
526 | &dev->core->i2c_adap, |
527 | &dvb_pll_fmd1216me); | |
f54376e2 | 528 | } |
611900c1 | 529 | break; |
780dfef3 | 530 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS: |
f7b54b10 MK |
531 | dev->dvb.frontend = dvb_attach(mt352_attach, |
532 | &dvico_fusionhdtv, | |
533 | &dev->core->i2c_adap); | |
f54376e2 | 534 | if (dev->dvb.frontend != NULL) { |
2bfe031d | 535 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60, |
c162dff6 | 536 | NULL, &dvb_pll_thomson_dtt7579); |
780dfef3 | 537 | break; |
f54376e2 | 538 | } |
780dfef3 | 539 | /* ZL10353 replaces MT352 on later cards */ |
f7b54b10 MK |
540 | dev->dvb.frontend = dvb_attach(zl10353_attach, |
541 | &dvico_fusionhdtv_plus_v1_1, | |
542 | &dev->core->i2c_adap); | |
f54376e2 | 543 | if (dev->dvb.frontend != NULL) { |
2bfe031d | 544 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60, |
c162dff6 | 545 | NULL, &dvb_pll_thomson_dtt7579); |
f54376e2 | 546 | } |
c2af3cd6 MK |
547 | break; |
548 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL: | |
c2af3cd6 MK |
549 | /* The tin box says DEE1601, but it seems to be DTT7579 |
550 | * compatible, with a slightly different MT352 AGC gain. */ | |
f7b54b10 MK |
551 | dev->dvb.frontend = dvb_attach(mt352_attach, |
552 | &dvico_fusionhdtv_dual, | |
553 | &dev->core->i2c_adap); | |
c2af3cd6 | 554 | if (dev->dvb.frontend != NULL) { |
2bfe031d | 555 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, |
c162dff6 | 556 | NULL, &dvb_pll_thomson_dtt7579); |
c2af3cd6 MK |
557 | break; |
558 | } | |
c2af3cd6 | 559 | /* ZL10353 replaces MT352 on later cards */ |
f7b54b10 MK |
560 | dev->dvb.frontend = dvb_attach(zl10353_attach, |
561 | &dvico_fusionhdtv_plus_v1_1, | |
562 | &dev->core->i2c_adap); | |
c2af3cd6 | 563 | if (dev->dvb.frontend != NULL) { |
2bfe031d | 564 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, |
c162dff6 | 565 | NULL, &dvb_pll_thomson_dtt7579); |
c2af3cd6 | 566 | } |
1da177e4 | 567 | break; |
780dfef3 | 568 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1: |
f7b54b10 MK |
569 | dev->dvb.frontend = dvb_attach(mt352_attach, |
570 | &dvico_fusionhdtv, | |
571 | &dev->core->i2c_adap); | |
f54376e2 | 572 | if (dev->dvb.frontend != NULL) { |
2bfe031d | 573 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, |
c162dff6 | 574 | NULL, &dvb_pll_lg_z201); |
f54376e2 | 575 | } |
1da177e4 LT |
576 | break; |
577 | case CX88_BOARD_KWORLD_DVB_T: | |
578 | case CX88_BOARD_DNTV_LIVE_DVB_T: | |
a82decf6 | 579 | case CX88_BOARD_ADSTECH_DVB_T_PCI: |
f7b54b10 MK |
580 | dev->dvb.frontend = dvb_attach(mt352_attach, |
581 | &dntv_live_dvbt_config, | |
582 | &dev->core->i2c_adap); | |
f54376e2 | 583 | if (dev->dvb.frontend != NULL) { |
2bfe031d | 584 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, |
c162dff6 | 585 | NULL, &dvb_pll_unknown_1); |
f54376e2 | 586 | } |
1da177e4 | 587 | break; |
fc40b261 CP |
588 | case CX88_BOARD_DNTV_LIVE_DVB_T_PRO: |
589 | #ifdef HAVE_VP3054_I2C | |
590 | dev->core->pll_addr = 0x61; | |
591 | dev->core->pll_desc = &dvb_pll_fmd1216me; | |
2bfe031d | 592 | dev->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config, |
fc40b261 | 593 | &((struct vp3054_i2c_state *)dev->card_priv)->adap); |
f54376e2 | 594 | if (dev->dvb.frontend != NULL) { |
dea74869 | 595 | dev->dvb.frontend->ops.tuner_ops.set_params = dntv_live_dvbt_pro_tuner_set_params; |
f54376e2 | 596 | } |
fc40b261 CP |
597 | #else |
598 | printk("%s: built without vp3054 support\n", dev->core->name); | |
599 | #endif | |
600 | break; | |
780dfef3 CP |
601 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID: |
602 | dev->core->pll_addr = 0x61; | |
91ae3299 | 603 | dev->core->pll_desc = &dvb_pll_thomson_fe6600; |
f7b54b10 MK |
604 | dev->dvb.frontend = dvb_attach(zl10353_attach, |
605 | &dvico_fusionhdtv_hybrid, | |
606 | &dev->core->i2c_adap); | |
f54376e2 | 607 | if (dev->dvb.frontend != NULL) { |
dea74869 | 608 | dev->dvb.frontend->ops.tuner_ops.set_params = dvico_hybrid_tuner_set_params; |
f54376e2 | 609 | } |
780dfef3 | 610 | break; |
1da177e4 | 611 | case CX88_BOARD_PCHDTV_HD3000: |
f7b54b10 MK |
612 | dev->dvb.frontend = dvb_attach(or51132_attach, |
613 | &pchdtv_hd3000, | |
614 | &dev->core->i2c_adap); | |
f54376e2 | 615 | if (dev->dvb.frontend != NULL) { |
2bfe031d | 616 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, |
f7b54b10 MK |
617 | &dev->core->i2c_adap, |
618 | &dvb_pll_thomson_dtt761x); | |
f54376e2 | 619 | } |
1da177e4 | 620 | break; |
f1798495 MK |
621 | case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q: |
622 | dev->ts_gen_cntrl = 0x08; | |
623 | { | |
624 | /* Do a hardware reset of chip before using it. */ | |
625 | struct cx88_core *core = dev->core; | |
626 | ||
627 | cx_clear(MO_GP0_IO, 1); | |
628 | mdelay(100); | |
0ccef6db | 629 | cx_set(MO_GP0_IO, 1); |
f1798495 | 630 | mdelay(200); |
0ccef6db MK |
631 | |
632 | /* Select RF connector callback */ | |
6ddcc919 | 633 | fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set; |
f7b54b10 MK |
634 | dev->dvb.frontend = dvb_attach(lgdt330x_attach, |
635 | &fusionhdtv_3_gold, | |
636 | &dev->core->i2c_adap); | |
f54376e2 | 637 | if (dev->dvb.frontend != NULL) { |
1d4bb7d3 MK |
638 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, |
639 | &dev->core->i2c_adap, | |
640 | &dvb_pll_microtune_4042); | |
f54376e2 | 641 | } |
f1798495 MK |
642 | } |
643 | break; | |
0d723c09 MK |
644 | case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T: |
645 | dev->ts_gen_cntrl = 0x08; | |
646 | { | |
647 | /* Do a hardware reset of chip before using it. */ | |
648 | struct cx88_core *core = dev->core; | |
649 | ||
650 | cx_clear(MO_GP0_IO, 1); | |
651 | mdelay(100); | |
d975872c | 652 | cx_set(MO_GP0_IO, 9); |
0d723c09 | 653 | mdelay(200); |
f7b54b10 MK |
654 | dev->dvb.frontend = dvb_attach(lgdt330x_attach, |
655 | &fusionhdtv_3_gold, | |
656 | &dev->core->i2c_adap); | |
f54376e2 | 657 | if (dev->dvb.frontend != NULL) { |
1d4bb7d3 MK |
658 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, |
659 | &dev->core->i2c_adap, | |
660 | &dvb_pll_thomson_dtt761x); | |
f54376e2 | 661 | } |
0d723c09 MK |
662 | } |
663 | break; | |
e52e98a7 MCC |
664 | case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD: |
665 | dev->ts_gen_cntrl = 0x08; | |
666 | { | |
667 | /* Do a hardware reset of chip before using it. */ | |
668 | struct cx88_core *core = dev->core; | |
669 | ||
670 | cx_clear(MO_GP0_IO, 1); | |
671 | mdelay(100); | |
672 | cx_set(MO_GP0_IO, 1); | |
673 | mdelay(200); | |
f7b54b10 MK |
674 | dev->dvb.frontend = dvb_attach(lgdt330x_attach, |
675 | &fusionhdtv_5_gold, | |
676 | &dev->core->i2c_adap); | |
f54376e2 | 677 | if (dev->dvb.frontend != NULL) { |
76db93d0 MK |
678 | dvb_attach(lgh06xf_attach, dev->dvb.frontend, |
679 | &dev->core->i2c_adap); | |
f54376e2 | 680 | } |
e52e98a7 MCC |
681 | } |
682 | break; | |
da215d22 RS |
683 | case CX88_BOARD_PCHDTV_HD5500: |
684 | dev->ts_gen_cntrl = 0x08; | |
685 | { | |
686 | /* Do a hardware reset of chip before using it. */ | |
687 | struct cx88_core *core = dev->core; | |
688 | ||
689 | cx_clear(MO_GP0_IO, 1); | |
690 | mdelay(100); | |
691 | cx_set(MO_GP0_IO, 1); | |
692 | mdelay(200); | |
f7b54b10 MK |
693 | dev->dvb.frontend = dvb_attach(lgdt330x_attach, |
694 | &pchdtv_hd5500, | |
695 | &dev->core->i2c_adap); | |
f54376e2 | 696 | if (dev->dvb.frontend != NULL) { |
76db93d0 MK |
697 | dvb_attach(lgh06xf_attach, dev->dvb.frontend, |
698 | &dev->core->i2c_adap); | |
f54376e2 | 699 | } |
da215d22 RS |
700 | } |
701 | break; | |
fde6d31e | 702 | case CX88_BOARD_ATI_HDTVWONDER: |
f7b54b10 MK |
703 | dev->dvb.frontend = dvb_attach(nxt200x_attach, |
704 | &ati_hdtvwonder, | |
705 | &dev->core->i2c_adap); | |
f54376e2 | 706 | if (dev->dvb.frontend != NULL) { |
2bfe031d | 707 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, |
4ad8eee5 | 708 | NULL, &dvb_pll_tuv1236d); |
f54376e2 | 709 | } |
0fa14aa6 | 710 | break; |
0fa14aa6 ST |
711 | case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1: |
712 | case CX88_BOARD_HAUPPAUGE_NOVASE2_S1: | |
f7b54b10 MK |
713 | dev->dvb.frontend = dvb_attach(cx24123_attach, |
714 | &hauppauge_novas_config, | |
715 | &dev->core->i2c_adap); | |
cd20ca9f | 716 | if (dev->dvb.frontend) { |
f7b54b10 MK |
717 | dvb_attach(isl6421_attach, dev->dvb.frontend, |
718 | &dev->core->i2c_adap, 0x08, 0x00, 0x00); | |
cd20ca9f | 719 | } |
0e0351e3 VC |
720 | break; |
721 | case CX88_BOARD_KWORLD_DVBS_100: | |
f7b54b10 MK |
722 | dev->dvb.frontend = dvb_attach(cx24123_attach, |
723 | &kworld_dvbs_100_config, | |
724 | &dev->core->i2c_adap); | |
cd20ca9f | 725 | if (dev->dvb.frontend) { |
dea74869 PB |
726 | dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; |
727 | dev->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage; | |
cd20ca9f | 728 | } |
fde6d31e | 729 | break; |
c02a34f4 | 730 | case CX88_BOARD_GENIATECH_DVBS: |
f7b54b10 MK |
731 | dev->dvb.frontend = dvb_attach(cx24123_attach, |
732 | &geniatech_dvbs_config, | |
733 | &dev->core->i2c_adap); | |
c02a34f4 SA |
734 | if (dev->dvb.frontend) { |
735 | dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; | |
736 | dev->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage; | |
737 | } | |
738 | break; | |
6c5be74c ST |
739 | case CX88_BOARD_HAUPPAUGE_HVR1300: |
740 | dev->dvb.frontend = dvb_attach(cx22702_attach, | |
741 | &hauppauge_hvr1300_config, | |
742 | &dev->core->i2c_adap); | |
743 | if (dev->dvb.frontend != NULL) { | |
744 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, | |
745 | &dev->core->i2c_adap, | |
746 | &dvb_pll_fmd1216me); | |
747 | } | |
748 | break; | |
749 | case CX88_BOARD_HAUPPAUGE_HVR3000: | |
750 | dev->dvb.frontend = dvb_attach(cx22702_attach, | |
751 | &hauppauge_hvr3000_config, | |
752 | &dev->core->i2c_adap); | |
753 | if (dev->dvb.frontend != NULL) { | |
754 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, | |
755 | &dev->core->i2c_adap, | |
756 | &dvb_pll_fmd1216me); | |
757 | } | |
758 | break; | |
1da177e4 | 759 | default: |
1622c3fc GK |
760 | printk("%s: The frontend of your DVB/ATSC card isn't supported yet\n", |
761 | dev->core->name); | |
1da177e4 LT |
762 | break; |
763 | } | |
764 | if (NULL == dev->dvb.frontend) { | |
765 | printk("%s: frontend initialization failed\n",dev->core->name); | |
766 | return -1; | |
767 | } | |
768 | ||
769 | if (dev->core->pll_desc) { | |
dea74869 PB |
770 | dev->dvb.frontend->ops.info.frequency_min = dev->core->pll_desc->min; |
771 | dev->dvb.frontend->ops.info.frequency_max = dev->core->pll_desc->max; | |
1da177e4 | 772 | } |
6c5be74c ST |
773 | /* Ensure all frontends negotiate bus access */ |
774 | dev->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl; | |
1da177e4 | 775 | |
93352f5c MCC |
776 | /* Put the analog decoder in standby to keep it quiet */ |
777 | cx88_call_i2c_clients (dev->core, TUNER_SET_STANDBY, NULL); | |
778 | ||
1da177e4 | 779 | /* register everything */ |
d09dbf92 | 780 | return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev); |
1da177e4 LT |
781 | } |
782 | ||
783 | /* ----------------------------------------------------------- */ | |
784 | ||
6c5be74c ST |
785 | /* CX8802 MPEG -> mini driver - We have been given the hardware */ |
786 | static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv) | |
1da177e4 | 787 | { |
6c5be74c ST |
788 | struct cx88_core *core = drv->core; |
789 | int err = 0; | |
790 | dprintk( 1, "%s\n", __FUNCTION__); | |
791 | ||
792 | switch (core->board) { | |
793 | case CX88_BOARD_HAUPPAUGE_HVR1300: | |
794 | /* We arrive here with either the cx23416 or the cx22702 | |
795 | * on the bus. Take the bus from the cx23416 and enable the | |
796 | * cx22702 demod | |
797 | */ | |
798 | cx_set(MO_GP0_IO, 0x00000080); /* cx22702 out of reset and enable */ | |
799 | cx_clear(MO_GP0_IO, 0x00000004); | |
800 | udelay(1000); | |
801 | break; | |
802 | default: | |
803 | err = -ENODEV; | |
804 | } | |
805 | return err; | |
806 | } | |
807 | ||
808 | /* CX8802 MPEG -> mini driver - We no longer have the hardware */ | |
809 | static int cx8802_dvb_advise_release(struct cx8802_driver *drv) | |
810 | { | |
811 | struct cx88_core *core = drv->core; | |
812 | int err = 0; | |
813 | dprintk( 1, "%s\n", __FUNCTION__); | |
814 | ||
815 | switch (core->board) { | |
816 | case CX88_BOARD_HAUPPAUGE_HVR1300: | |
817 | /* Do Nothing, leave the cx22702 on the bus. */ | |
818 | break; | |
819 | default: | |
820 | err = -ENODEV; | |
821 | } | |
822 | return err; | |
823 | } | |
824 | ||
825 | static int cx8802_dvb_probe(struct cx8802_driver *drv) | |
826 | { | |
827 | struct cx88_core *core = drv->core; | |
828 | struct cx8802_dev *dev = drv->core->dvbdev; | |
1da177e4 LT |
829 | int err; |
830 | ||
6c5be74c ST |
831 | dprintk( 1, "%s\n", __FUNCTION__); |
832 | dprintk( 1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n", | |
833 | core->board, | |
834 | core->name, | |
835 | core->pci_bus, | |
836 | core->pci_slot); | |
1da177e4 LT |
837 | |
838 | err = -ENODEV; | |
48d5e803 | 839 | if (!(cx88_boards[core->board].mpeg & CX88_MPEG_DVB)) |
1da177e4 LT |
840 | goto fail_core; |
841 | ||
fc40b261 CP |
842 | #ifdef HAVE_VP3054_I2C |
843 | err = vp3054_i2c_probe(dev); | |
844 | if (0 != err) | |
6c5be74c | 845 | goto fail_core; |
fc40b261 CP |
846 | #endif |
847 | ||
1da177e4 LT |
848 | /* dvb stuff */ |
849 | printk("%s/2: cx2388x based dvb card\n", core->name); | |
850 | videobuf_queue_init(&dev->dvb.dvbq, &dvb_qops, | |
851 | dev->pci, &dev->slock, | |
852 | V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
853 | V4L2_FIELD_TOP, | |
854 | sizeof(struct cx88_buffer), | |
855 | dev); | |
856 | err = dvb_register(dev); | |
6c5be74c ST |
857 | if (err != 0) |
858 | printk("%s dvb_register failed err = %d\n", __FUNCTION__, err); | |
1da177e4 | 859 | |
1da177e4 | 860 | fail_core: |
1da177e4 LT |
861 | return err; |
862 | } | |
863 | ||
6c5be74c | 864 | static int cx8802_dvb_remove(struct cx8802_driver *drv) |
1da177e4 | 865 | { |
6c5be74c | 866 | struct cx8802_dev *dev = drv->core->dvbdev; |
611900c1 | 867 | |
1da177e4 LT |
868 | /* dvb */ |
869 | videobuf_dvb_unregister(&dev->dvb); | |
870 | ||
fc40b261 CP |
871 | #ifdef HAVE_VP3054_I2C |
872 | vp3054_i2c_remove(dev); | |
873 | #endif | |
874 | ||
6c5be74c | 875 | return 0; |
1da177e4 LT |
876 | } |
877 | ||
6c5be74c ST |
878 | static struct cx8802_driver cx8802_dvb_driver = { |
879 | .type_id = CX88_MPEG_DVB, | |
880 | .hw_access = CX8802_DRVCTL_SHARED, | |
881 | .probe = cx8802_dvb_probe, | |
882 | .remove = cx8802_dvb_remove, | |
883 | .advise_acquire = cx8802_dvb_advise_acquire, | |
884 | .advise_release = cx8802_dvb_advise_release, | |
1da177e4 LT |
885 | }; |
886 | ||
887 | static int dvb_init(void) | |
888 | { | |
889 | printk(KERN_INFO "cx2388x dvb driver version %d.%d.%d loaded\n", | |
890 | (CX88_VERSION_CODE >> 16) & 0xff, | |
891 | (CX88_VERSION_CODE >> 8) & 0xff, | |
892 | CX88_VERSION_CODE & 0xff); | |
893 | #ifdef SNAPSHOT | |
894 | printk(KERN_INFO "cx2388x: snapshot date %04d-%02d-%02d\n", | |
895 | SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100); | |
896 | #endif | |
6c5be74c | 897 | return cx8802_register_driver(&cx8802_dvb_driver); |
1da177e4 LT |
898 | } |
899 | ||
900 | static void dvb_fini(void) | |
901 | { | |
6c5be74c | 902 | cx8802_unregister_driver(&cx8802_dvb_driver); |
1da177e4 LT |
903 | } |
904 | ||
905 | module_init(dvb_init); | |
906 | module_exit(dvb_fini); | |
907 | ||
908 | /* | |
909 | * Local variables: | |
910 | * c-basic-offset: 8 | |
911 | * compile-command: "make DVB=1" | |
912 | * End: | |
913 | */ |