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e8417683 MK |
1 | /* |
2 | * Copyright (C) 2008-2009 Texas Instruments Inc | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | #ifndef _ISIF_REGS_H | |
19 | #define _ISIF_REGS_H | |
20 | ||
21 | /* ISIF registers relative offsets */ | |
22 | #define SYNCEN 0x00 | |
23 | #define MODESET 0x04 | |
24 | #define HDW 0x08 | |
25 | #define VDW 0x0c | |
26 | #define PPLN 0x10 | |
27 | #define LPFR 0x14 | |
28 | #define SPH 0x18 | |
29 | #define LNH 0x1c | |
30 | #define SLV0 0x20 | |
31 | #define SLV1 0x24 | |
32 | #define LNV 0x28 | |
33 | #define CULH 0x2c | |
34 | #define CULV 0x30 | |
35 | #define HSIZE 0x34 | |
36 | #define SDOFST 0x38 | |
37 | #define CADU 0x3c | |
38 | #define CADL 0x40 | |
39 | #define LINCFG0 0x44 | |
40 | #define LINCFG1 0x48 | |
41 | #define CCOLP 0x4c | |
42 | #define CRGAIN 0x50 | |
43 | #define CGRGAIN 0x54 | |
44 | #define CGBGAIN 0x58 | |
45 | #define CBGAIN 0x5c | |
46 | #define COFSTA 0x60 | |
47 | #define FLSHCFG0 0x64 | |
48 | #define FLSHCFG1 0x68 | |
49 | #define FLSHCFG2 0x6c | |
50 | #define VDINT0 0x70 | |
51 | #define VDINT1 0x74 | |
52 | #define VDINT2 0x78 | |
53 | #define MISC 0x7c | |
54 | #define CGAMMAWD 0x80 | |
55 | #define REC656IF 0x84 | |
56 | #define CCDCFG 0x88 | |
57 | /***************************************************** | |
58 | * Defect Correction registers | |
59 | *****************************************************/ | |
60 | #define DFCCTL 0x8c | |
61 | #define VDFSATLV 0x90 | |
62 | #define DFCMEMCTL 0x94 | |
63 | #define DFCMEM0 0x98 | |
64 | #define DFCMEM1 0x9c | |
65 | #define DFCMEM2 0xa0 | |
66 | #define DFCMEM3 0xa4 | |
67 | #define DFCMEM4 0xa8 | |
68 | /**************************************************** | |
69 | * Black Clamp registers | |
70 | ****************************************************/ | |
71 | #define CLAMPCFG 0xac | |
72 | #define CLDCOFST 0xb0 | |
73 | #define CLSV 0xb4 | |
74 | #define CLHWIN0 0xb8 | |
75 | #define CLHWIN1 0xbc | |
76 | #define CLHWIN2 0xc0 | |
77 | #define CLVRV 0xc4 | |
78 | #define CLVWIN0 0xc8 | |
79 | #define CLVWIN1 0xcc | |
80 | #define CLVWIN2 0xd0 | |
81 | #define CLVWIN3 0xd4 | |
82 | /**************************************************** | |
83 | * Lense Shading Correction | |
84 | ****************************************************/ | |
85 | #define DATAHOFST 0xd8 | |
86 | #define DATAVOFST 0xdc | |
87 | #define LSCHVAL 0xe0 | |
88 | #define LSCVVAL 0xe4 | |
89 | #define TWODLSCCFG 0xe8 | |
90 | #define TWODLSCOFST 0xec | |
91 | #define TWODLSCINI 0xf0 | |
92 | #define TWODLSCGRBU 0xf4 | |
93 | #define TWODLSCGRBL 0xf8 | |
94 | #define TWODLSCGROF 0xfc | |
95 | #define TWODLSCORBU 0x100 | |
96 | #define TWODLSCORBL 0x104 | |
97 | #define TWODLSCOROF 0x108 | |
98 | #define TWODLSCIRQEN 0x10c | |
99 | #define TWODLSCIRQST 0x110 | |
100 | /**************************************************** | |
101 | * Data formatter | |
102 | ****************************************************/ | |
103 | #define FMTCFG 0x114 | |
104 | #define FMTPLEN 0x118 | |
105 | #define FMTSPH 0x11c | |
106 | #define FMTLNH 0x120 | |
107 | #define FMTSLV 0x124 | |
108 | #define FMTLNV 0x128 | |
109 | #define FMTRLEN 0x12c | |
110 | #define FMTHCNT 0x130 | |
111 | #define FMTAPTR_BASE 0x134 | |
112 | /* Below macro for addresses FMTAPTR0 - FMTAPTR15 */ | |
113 | #define FMTAPTR(i) (FMTAPTR_BASE + (i * 4)) | |
114 | #define FMTPGMVF0 0x174 | |
115 | #define FMTPGMVF1 0x178 | |
116 | #define FMTPGMAPU0 0x17c | |
117 | #define FMTPGMAPU1 0x180 | |
118 | #define FMTPGMAPS0 0x184 | |
119 | #define FMTPGMAPS1 0x188 | |
120 | #define FMTPGMAPS2 0x18c | |
121 | #define FMTPGMAPS3 0x190 | |
122 | #define FMTPGMAPS4 0x194 | |
123 | #define FMTPGMAPS5 0x198 | |
124 | #define FMTPGMAPS6 0x19c | |
125 | #define FMTPGMAPS7 0x1a0 | |
126 | /************************************************ | |
127 | * Color Space Converter | |
128 | ************************************************/ | |
129 | #define CSCCTL 0x1a4 | |
130 | #define CSCM0 0x1a8 | |
131 | #define CSCM1 0x1ac | |
132 | #define CSCM2 0x1b0 | |
133 | #define CSCM3 0x1b4 | |
134 | #define CSCM4 0x1b8 | |
135 | #define CSCM5 0x1bc | |
136 | #define CSCM6 0x1c0 | |
137 | #define CSCM7 0x1c4 | |
138 | #define OBWIN0 0x1c8 | |
139 | #define OBWIN1 0x1cc | |
140 | #define OBWIN2 0x1d0 | |
141 | #define OBWIN3 0x1d4 | |
142 | #define OBVAL0 0x1d8 | |
143 | #define OBVAL1 0x1dc | |
144 | #define OBVAL2 0x1e0 | |
145 | #define OBVAL3 0x1e4 | |
146 | #define OBVAL4 0x1e8 | |
147 | #define OBVAL5 0x1ec | |
148 | #define OBVAL6 0x1f0 | |
149 | #define OBVAL7 0x1f4 | |
150 | #define CLKCTL 0x1f8 | |
151 | ||
152 | /* Masks & Shifts below */ | |
153 | #define START_PX_HOR_MASK 0x7FFF | |
154 | #define NUM_PX_HOR_MASK 0x7FFF | |
155 | #define START_VER_ONE_MASK 0x7FFF | |
156 | #define START_VER_TWO_MASK 0x7FFF | |
157 | #define NUM_LINES_VER 0x7FFF | |
158 | ||
159 | /* gain - offset masks */ | |
160 | #define GAIN_INTEGER_SHIFT 9 | |
000f64ef | 161 | #define OFFSET_MASK 0xFFF |
e8417683 MK |
162 | #define GAIN_SDRAM_EN_SHIFT 12 |
163 | #define GAIN_IPIPE_EN_SHIFT 13 | |
164 | #define GAIN_H3A_EN_SHIFT 14 | |
165 | #define OFST_SDRAM_EN_SHIFT 8 | |
166 | #define OFST_IPIPE_EN_SHIFT 9 | |
167 | #define OFST_H3A_EN_SHIFT 10 | |
168 | #define GAIN_OFFSET_EN_MASK 0x7700 | |
169 | ||
170 | /* Culling */ | |
171 | #define CULL_PAT_EVEN_LINE_SHIFT 8 | |
172 | ||
173 | /* CCDCFG register */ | |
174 | #define ISIF_YCINSWP_RAW (0x00 << 4) | |
175 | #define ISIF_YCINSWP_YCBCR (0x01 << 4) | |
176 | #define ISIF_CCDCFG_FIDMD_LATCH_VSYNC (0x00 << 6) | |
177 | #define ISIF_CCDCFG_WENLOG_AND (0x00 << 8) | |
178 | #define ISIF_CCDCFG_TRGSEL_WEN (0x00 << 9) | |
179 | #define ISIF_CCDCFG_EXTRG_DISABLE (0x00 << 10) | |
180 | #define ISIF_LATCH_ON_VSYNC_DISABLE (0x01 << 15) | |
181 | #define ISIF_LATCH_ON_VSYNC_ENABLE (0x00 << 15) | |
182 | #define ISIF_DATA_PACK_MASK 3 | |
183 | #define ISIF_DATA_PACK16 0 | |
184 | #define ISIF_DATA_PACK12 1 | |
185 | #define ISIF_DATA_PACK8 2 | |
186 | #define ISIF_PIX_ORDER_SHIFT 11 | |
187 | #define ISIF_BW656_ENABLE (0x01 << 5) | |
188 | ||
189 | /* MODESET registers */ | |
190 | #define ISIF_VDHDOUT_INPUT (0x00 << 0) | |
191 | #define ISIF_INPUT_SHIFT 12 | |
192 | #define ISIF_RAW_INPUT_MODE 0 | |
193 | #define ISIF_FID_POL_SHIFT 4 | |
194 | #define ISIF_HD_POL_SHIFT 3 | |
195 | #define ISIF_VD_POL_SHIFT 2 | |
196 | #define ISIF_DATAPOL_NORMAL 0 | |
197 | #define ISIF_DATAPOL_SHIFT 6 | |
198 | #define ISIF_EXWEN_DISABLE 0 | |
199 | #define ISIF_EXWEN_SHIFT 5 | |
200 | #define ISIF_FRM_FMT_SHIFT 7 | |
201 | #define ISIF_DATASFT_SHIFT 8 | |
202 | #define ISIF_LPF_SHIFT 14 | |
203 | #define ISIF_LPF_MASK 1 | |
204 | ||
205 | /* GAMMAWD registers */ | |
206 | #define ISIF_ALAW_GAMA_WD_MASK 0xF | |
207 | #define ISIF_ALAW_GAMA_WD_SHIFT 1 | |
208 | #define ISIF_ALAW_ENABLE 1 | |
209 | #define ISIF_GAMMAWD_CFA_SHIFT 5 | |
210 | ||
211 | /* HSIZE registers */ | |
212 | #define ISIF_HSIZE_FLIP_MASK 1 | |
213 | #define ISIF_HSIZE_FLIP_SHIFT 12 | |
214 | ||
215 | /* MISC registers */ | |
216 | #define ISIF_DPCM_EN_SHIFT 12 | |
217 | #define ISIF_DPCM_PREDICTOR_SHIFT 13 | |
218 | ||
219 | /* Black clamp related */ | |
220 | #define ISIF_BC_MODE_COLOR_SHIFT 4 | |
221 | #define ISIF_HORZ_BC_MODE_SHIFT 1 | |
222 | #define ISIF_HORZ_BC_WIN_SEL_SHIFT 5 | |
223 | #define ISIF_HORZ_BC_PIX_LIMIT_SHIFT 6 | |
224 | #define ISIF_HORZ_BC_WIN_H_SIZE_SHIFT 8 | |
225 | #define ISIF_HORZ_BC_WIN_V_SIZE_SHIFT 12 | |
226 | #define ISIF_VERT_BC_RST_VAL_SEL_SHIFT 4 | |
227 | #define ISIF_VERT_BC_LINE_AVE_COEF_SHIFT 8 | |
228 | ||
229 | /* VDFC registers */ | |
230 | #define ISIF_VDFC_EN_SHIFT 4 | |
231 | #define ISIF_VDFC_CORR_MOD_SHIFT 5 | |
232 | #define ISIF_VDFC_CORR_WHOLE_LN_SHIFT 7 | |
233 | #define ISIF_VDFC_LEVEL_SHFT_SHIFT 8 | |
234 | #define ISIF_VDFC_POS_MASK 0x1FFF | |
235 | #define ISIF_DFCMEMCTL_DFCMARST_SHIFT 2 | |
236 | ||
237 | /* CSC registers */ | |
238 | #define ISIF_CSC_COEF_INTEG_MASK 7 | |
239 | #define ISIF_CSC_COEF_DECIMAL_MASK 0x1f | |
240 | #define ISIF_CSC_COEF_INTEG_SHIFT 5 | |
241 | #define ISIF_CSCM_MSB_SHIFT 8 | |
242 | #define ISIF_DF_CSC_SPH_MASK 0x1FFF | |
243 | #define ISIF_DF_CSC_LNH_MASK 0x1FFF | |
244 | #define ISIF_DF_CSC_SLV_MASK 0x1FFF | |
245 | #define ISIF_DF_CSC_LNV_MASK 0x1FFF | |
246 | #define ISIF_DF_NUMLINES 0x7FFF | |
247 | #define ISIF_DF_NUMPIX 0x1FFF | |
248 | ||
249 | /* Offsets for LSC/DFC/Gain */ | |
250 | #define ISIF_DATA_H_OFFSET_MASK 0x1FFF | |
251 | #define ISIF_DATA_V_OFFSET_MASK 0x1FFF | |
252 | ||
253 | /* Linearization */ | |
254 | #define ISIF_LIN_CORRSFT_SHIFT 4 | |
255 | #define ISIF_LIN_SCALE_FACT_INTEG_SHIFT 10 | |
256 | ||
257 | ||
258 | /* Pattern registers */ | |
259 | #define ISIF_PG_EN (1 << 3) | |
260 | #define ISIF_SEL_PG_SRC (3 << 4) | |
261 | #define ISIF_PG_VD_POL_SHIFT 0 | |
262 | #define ISIF_PG_HD_POL_SHIFT 1 | |
263 | ||
264 | /*random other junk*/ | |
265 | #define ISIF_SYNCEN_VDHDEN_MASK (1 << 0) | |
266 | #define ISIF_SYNCEN_WEN_MASK (1 << 1) | |
267 | #define ISIF_SYNCEN_WEN_SHIFT 1 | |
268 | ||
269 | #endif |