Commit | Line | Data |
---|---|---|
a6c2ba28 | 1 | /* |
0e7072ef | 2 | em28xx.h - driver for Empia EM2800/EM2820/2840 USB video capture devices |
a6c2ba28 | 3 | |
4 | Copyright (C) 2005 Markus Rechberger <mrechberger@gmail.com> | |
4ac97914 | 5 | Ludovico Cavedon <cavedon@sssup.it> |
2e7c6dc3 | 6 | Mauro Carvalho Chehab <mchehab@infradead.org> |
a6c2ba28 | 7 | |
8 | Based on the em2800 driver from Sascha Sommer <saschasommer@freenet.de> | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2 of the License, or | |
13 | (at your option) any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software | |
22 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
24 | ||
3acf2809 MCC |
25 | #ifndef _EM28XX_H |
26 | #define _EM28XX_H | |
a6c2ba28 | 27 | |
39a96b4c MCC |
28 | #include <linux/workqueue.h> |
29 | #include <linux/i2c.h> | |
30 | #include <linux/mutex.h> | |
cb77d010 | 31 | #include <linux/videodev2.h> |
39a96b4c | 32 | |
ad0ebb96 | 33 | #include <media/videobuf-vmalloc.h> |
f2cf250a | 34 | #include <media/v4l2-device.h> |
d5e52653 | 35 | #include <media/ir-kbd-i2c.h> |
6bda9644 | 36 | #include <media/rc-core.h> |
3aefb79a MCC |
37 | #if defined(CONFIG_VIDEO_EM28XX_DVB) || defined(CONFIG_VIDEO_EM28XX_DVB_MODULE) |
38 | #include <media/videobuf-dvb.h> | |
39 | #endif | |
3ca9c093 | 40 | #include "tuner-xc2028.h" |
82e7dbbd | 41 | #include "xc5000.h" |
2ba890ec | 42 | #include "em28xx-reg.h" |
3aefb79a MCC |
43 | |
44 | /* Boards supported by driver */ | |
45 | #define EM2800_BOARD_UNKNOWN 0 | |
46 | #define EM2820_BOARD_UNKNOWN 1 | |
47 | #define EM2820_BOARD_TERRATEC_CINERGY_250 2 | |
48 | #define EM2820_BOARD_PINNACLE_USB_2 3 | |
49 | #define EM2820_BOARD_HAUPPAUGE_WINTV_USB_2 4 | |
50 | #define EM2820_BOARD_MSI_VOX_USB_2 5 | |
51 | #define EM2800_BOARD_TERRATEC_CINERGY_200 6 | |
52 | #define EM2800_BOARD_LEADTEK_WINFAST_USBII 7 | |
53 | #define EM2800_BOARD_KWORLD_USB2800 8 | |
54 | #define EM2820_BOARD_PINNACLE_DVC_90 9 | |
55 | #define EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900 10 | |
56 | #define EM2880_BOARD_TERRATEC_HYBRID_XS 11 | |
57 | #define EM2820_BOARD_KWORLD_PVRTV2800RF 12 | |
58 | #define EM2880_BOARD_TERRATEC_PRODIGY_XS 13 | |
59 | #define EM2820_BOARD_PROLINK_PLAYTV_USB2 14 | |
60 | #define EM2800_BOARD_VGEAR_POCKETTV 15 | |
10ac6603 | 61 | #define EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950 16 |
4fd305b2 | 62 | #define EM2880_BOARD_PINNACLE_PCTV_HD_PRO 17 |
17d9d558 | 63 | #define EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2 18 |
3ed58baf | 64 | #define EM2860_BOARD_SAA711X_REFERENCE_DESIGN 19 |
e14b3658 | 65 | #define EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600 20 |
59d07f1b | 66 | #define EM2800_BOARD_GRABBEEX_USB2800 21 |
95b86a9a DSL |
67 | #define EM2750_BOARD_UNKNOWN 22 |
68 | #define EM2750_BOARD_DLCW_130 23 | |
69 | #define EM2820_BOARD_DLINK_USB_TV 24 | |
70 | #define EM2820_BOARD_GADMEI_UTV310 25 | |
71 | #define EM2820_BOARD_HERCULES_SMART_TV_USB2 26 | |
72 | #define EM2820_BOARD_PINNACLE_USB_2_FM1216ME 27 | |
73 | #define EM2820_BOARD_LEADTEK_WINFAST_USBII_DELUXE 28 | |
443fed9f | 74 | #define EM2860_BOARD_TVP5150_REFERENCE_DESIGN 29 |
95b86a9a DSL |
75 | #define EM2820_BOARD_VIDEOLOGY_20K14XUSB 30 |
76 | #define EM2821_BOARD_USBGEAR_VD204 31 | |
77 | #define EM2821_BOARD_SUPERCOMP_USB_2 32 | |
8298f2f8 | 78 | #define EM2860_BOARD_ELGATO_VIDEO_CAPTURE 33 |
95b86a9a DSL |
79 | #define EM2860_BOARD_TERRATEC_HYBRID_XS 34 |
80 | #define EM2860_BOARD_TYPHOON_DVD_MAKER 35 | |
81 | #define EM2860_BOARD_NETGMBH_CAM 36 | |
82 | #define EM2860_BOARD_GADMEI_UTV330 37 | |
83 | #define EM2861_BOARD_YAKUMO_MOVIE_MIXER 38 | |
84 | #define EM2861_BOARD_KWORLD_PVRTV_300U 39 | |
85 | #define EM2861_BOARD_PLEXTOR_PX_TV100U 40 | |
86 | #define EM2870_BOARD_KWORLD_350U 41 | |
87 | #define EM2870_BOARD_KWORLD_355U 42 | |
88 | #define EM2870_BOARD_TERRATEC_XS 43 | |
89 | #define EM2870_BOARD_TERRATEC_XS_MT2060 44 | |
90 | #define EM2870_BOARD_PINNACLE_PCTV_DVB 45 | |
91 | #define EM2870_BOARD_COMPRO_VIDEOMATE 46 | |
92 | #define EM2880_BOARD_KWORLD_DVB_305U 47 | |
93 | #define EM2880_BOARD_KWORLD_DVB_310U 48 | |
94 | #define EM2880_BOARD_MSI_DIGIVOX_AD 49 | |
95 | #define EM2880_BOARD_MSI_DIGIVOX_AD_II 50 | |
96 | #define EM2880_BOARD_TERRATEC_HYBRID_XS_FR 51 | |
97 | #define EM2881_BOARD_DNT_DA2_HYBRID 52 | |
98 | #define EM2881_BOARD_PINNACLE_HYBRID_PRO 53 | |
99 | #define EM2882_BOARD_KWORLD_VS_DVBT 54 | |
100 | #define EM2882_BOARD_TERRATEC_HYBRID_XS 55 | |
09bc1942 | 101 | #define EM2882_BOARD_PINNACLE_HYBRID_PRO_330E 56 |
6e7b9ea0 | 102 | #define EM2883_BOARD_KWORLD_HYBRID_330U 57 |
ee281b85 | 103 | #define EM2820_BOARD_COMPRO_VIDEOMATE_FORYOU 58 |
f89bc329 | 104 | #define EM2883_BOARD_HAUPPAUGE_WINTV_HVR_850 60 |
1e1addd5 | 105 | #define EM2820_BOARD_PROLINK_PLAYTV_BOX4_USB2 61 |
f7fe3e6f | 106 | #define EM2820_BOARD_GADMEI_TVR200 62 |
56ee3807 MCC |
107 | #define EM2860_BOARD_KAIOMY_TVNPC_U2 63 |
108 | #define EM2860_BOARD_EASYCAP 64 | |
f74a61e3 | 109 | #define EM2820_BOARD_IODATA_GVMVP_SZ 65 |
e5db5d44 | 110 | #define EM2880_BOARD_EMPIRE_DUAL_TV 66 |
4557af9c | 111 | #define EM2860_BOARD_TERRATEC_GRABBY 67 |
766ed64d | 112 | #define EM2860_BOARD_TERRATEC_AV350 68 |
d7de5d8f | 113 | #define EM2882_BOARD_KWORLD_ATSC_315U 69 |
19859229 | 114 | #define EM2882_BOARD_EVGA_INDTUBE 70 |
02e7804b | 115 | #define EM2820_BOARD_SILVERCREST_WEBCAM 71 |
6d888a66 | 116 | #define EM2861_BOARD_GADMEI_UTV330PLUS 72 |
285eb1a4 | 117 | #define EM2870_BOARD_REDDO_DVB_C_USB_BOX 73 |
694a101e | 118 | #define EM2800_BOARD_VC211A 74 |
7ca7ef60 | 119 | #define EM2882_BOARD_DIKOM_DK300 75 |
7e48b30a | 120 | #define EM2870_BOARD_KWORLD_A340 76 |
fec528b7 | 121 | #define EM2874_BOARD_LEADERSHIP_ISDBT 77 |
d6a5f921 | 122 | #define EM28174_BOARD_PCTV_290E 78 |
fec528b7 | 123 | #define EM2884_BOARD_TERRATEC_H5 79 |
36588715 | 124 | #define EM28174_BOARD_PCTV_460E 80 |
82e7dbbd | 125 | #define EM2884_BOARD_HAUPPAUGE_WINTV_HVR_930C 81 |
a1ed02e9 | 126 | #define EM2884_BOARD_CINERGY_HTC_STICK 82 |
4d28d3d9 | 127 | #define EM2860_BOARD_HT_VIDBOX_NW03 83 |
3553085c | 128 | #define EM2874_BOARD_MAXMEDIA_UB425_TC 84 |
fa5527cd IK |
129 | #define EM2884_BOARD_PCTV_510E 85 |
130 | #define EM2884_BOARD_PCTV_520E 86 | |
3aefb79a MCC |
131 | |
132 | /* Limits minimum and default number of buffers */ | |
133 | #define EM28XX_MIN_BUF 4 | |
134 | #define EM28XX_DEF_BUF 8 | |
a6c2ba28 | 135 | |
c4a98793 MCC |
136 | /*Limits the max URB message size */ |
137 | #define URB_MAX_CTRL_SIZE 80 | |
138 | ||
95b86a9a DSL |
139 | /* Params for validated field */ |
140 | #define EM28XX_BOARD_NOT_VALIDATED 1 | |
141 | #define EM28XX_BOARD_VALIDATED 0 | |
142 | ||
22cff7b3 DSL |
143 | /* Params for em28xx_cmd() audio */ |
144 | #define EM28XX_START_AUDIO 1 | |
145 | #define EM28XX_STOP_AUDIO 0 | |
146 | ||
596d92d5 | 147 | /* maximum number of em28xx boards */ |
3687e1e6 | 148 | #define EM28XX_MAXBOARDS 4 /*FIXME: should be bigger */ |
596d92d5 | 149 | |
a6c2ba28 | 150 | /* maximum number of frames that can be queued */ |
3acf2809 | 151 | #define EM28XX_NUM_FRAMES 5 |
a6c2ba28 | 152 | /* number of frames that get used for v4l2_read() */ |
3acf2809 | 153 | #define EM28XX_NUM_READ_FRAMES 2 |
a6c2ba28 | 154 | |
155 | /* number of buffers for isoc transfers */ | |
3acf2809 | 156 | #define EM28XX_NUM_BUFS 5 |
86d38d1e | 157 | #define EM28XX_DVB_NUM_BUFS 5 |
a6c2ba28 | 158 | |
d5e52653 | 159 | /* number of packets for each buffer |
33c02fac | 160 | windows requests only 64 packets .. so we better do the same |
d5e52653 MCC |
161 | this is what I found out for all alternate numbers there! |
162 | */ | |
33c02fac | 163 | #define EM28XX_NUM_PACKETS 64 |
86d38d1e | 164 | #define EM28XX_DVB_MAX_PACKETS 64 |
a6c2ba28 | 165 | |
3acf2809 | 166 | #define EM28XX_INTERLACED_DEFAULT 1 |
a6c2ba28 | 167 | |
168 | /* | |
169 | #define (use usbview if you want to get the other alternate number infos) | |
170 | #define | |
171 | #define alternate number 2 | |
172 | #define Endpoint Address: 82 | |
173 | Direction: in | |
174 | Attribute: 1 | |
175 | Type: Isoc | |
176 | Max Packet Size: 1448 | |
177 | Interval: 125us | |
178 | ||
179 | alternate number 7 | |
180 | ||
181 | Endpoint Address: 82 | |
182 | Direction: in | |
183 | Attribute: 1 | |
184 | Type: Isoc | |
185 | Max Packet Size: 3072 | |
186 | Interval: 125us | |
187 | */ | |
188 | ||
189 | /* time to wait when stopping the isoc transfer */ | |
a1a6ee74 NS |
190 | #define EM28XX_URB_TIMEOUT \ |
191 | msecs_to_jiffies(EM28XX_NUM_BUFS * EM28XX_NUM_PACKETS) | |
a6c2ba28 | 192 | |
596d92d5 MCC |
193 | /* time in msecs to wait for i2c writes to finish */ |
194 | #define EM2800_I2C_WRITE_TIMEOUT 20 | |
195 | ||
3aefb79a | 196 | enum em28xx_mode { |
2fe3e2ee | 197 | EM28XX_SUSPEND, |
3aefb79a MCC |
198 | EM28XX_ANALOG_MODE, |
199 | EM28XX_DIGITAL_MODE, | |
200 | }; | |
201 | ||
a6c2ba28 | 202 | |
579f72e4 AT |
203 | struct em28xx; |
204 | ||
86d38d1e | 205 | struct em28xx_usb_isoc_bufs { |
ad0ebb96 MCC |
206 | /* max packet size of isoc transaction */ |
207 | int max_pkt_size; | |
208 | ||
86d38d1e GG |
209 | /* number of packets in each buffer */ |
210 | int num_packets; | |
211 | ||
ad0ebb96 MCC |
212 | /* number of allocated urbs */ |
213 | int num_bufs; | |
214 | ||
215 | /* urb for isoc transfers */ | |
216 | struct urb **urb; | |
217 | ||
218 | /* transfer buffers for isoc transfer */ | |
219 | char **transfer_buffer; | |
86d38d1e GG |
220 | }; |
221 | ||
222 | struct em28xx_usb_isoc_ctl { | |
223 | /* isoc transfer buffers for analog mode */ | |
224 | struct em28xx_usb_isoc_bufs analog_bufs; | |
225 | ||
226 | /* isoc transfer buffers for digital mode */ | |
227 | struct em28xx_usb_isoc_bufs digital_bufs; | |
ad0ebb96 | 228 | |
ad0ebb96 | 229 | /* Stores already requested buffers */ |
28abf083 DH |
230 | struct em28xx_buffer *vid_buf; |
231 | struct em28xx_buffer *vbi_buf; | |
ad0ebb96 | 232 | |
579f72e4 AT |
233 | /* isoc urb callback */ |
234 | int (*isoc_copy) (struct em28xx *dev, struct urb *urb); | |
235 | ||
ad0ebb96 MCC |
236 | }; |
237 | ||
bddcf633 | 238 | /* Struct to enumberate video formats */ |
ad0ebb96 MCC |
239 | struct em28xx_fmt { |
240 | char *name; | |
241 | u32 fourcc; /* v4l2 format id */ | |
bddcf633 MCC |
242 | int depth; |
243 | int reg; | |
ad0ebb96 MCC |
244 | }; |
245 | ||
246 | /* buffer for one video frame */ | |
247 | struct em28xx_buffer { | |
248 | /* common v4l buffer stuff -- must be first */ | |
249 | struct videobuf_buffer vb; | |
250 | ||
a6c2ba28 | 251 | struct list_head frame; |
a6c2ba28 | 252 | int top_field; |
ad0ebb96 MCC |
253 | int receiving; |
254 | }; | |
255 | ||
256 | struct em28xx_dmaqueue { | |
257 | struct list_head active; | |
258 | struct list_head queued; | |
ad0ebb96 MCC |
259 | |
260 | wait_queue_head_t wq; | |
261 | ||
262 | /* Counters to control buffer fill */ | |
263 | int pos; | |
a6c2ba28 | 264 | }; |
265 | ||
266 | /* io methods */ | |
3acf2809 | 267 | enum em28xx_io_method { |
a6c2ba28 | 268 | IO_NONE, |
269 | IO_READ, | |
270 | IO_MMAP, | |
271 | }; | |
272 | ||
273 | /* inputs */ | |
274 | ||
3acf2809 MCC |
275 | #define MAX_EM28XX_INPUT 4 |
276 | enum enum28xx_itype { | |
277 | EM28XX_VMUX_COMPOSITE1 = 1, | |
278 | EM28XX_VMUX_COMPOSITE2, | |
279 | EM28XX_VMUX_COMPOSITE3, | |
280 | EM28XX_VMUX_COMPOSITE4, | |
281 | EM28XX_VMUX_SVIDEO, | |
282 | EM28XX_VMUX_TELEVISION, | |
283 | EM28XX_VMUX_CABLE, | |
284 | EM28XX_VMUX_DVB, | |
285 | EM28XX_VMUX_DEBUG, | |
286 | EM28XX_RADIO, | |
a6c2ba28 | 287 | }; |
288 | ||
35643943 MCC |
289 | enum em28xx_ac97_mode { |
290 | EM28XX_NO_AC97 = 0, | |
291 | EM28XX_AC97_EM202, | |
209acc02 | 292 | EM28XX_AC97_SIGMATEL, |
35643943 MCC |
293 | EM28XX_AC97_OTHER, |
294 | }; | |
295 | ||
296 | struct em28xx_audio_mode { | |
297 | enum em28xx_ac97_mode ac97; | |
298 | ||
299 | u16 ac97_feat; | |
16c7bcad | 300 | u32 ac97_vendor_id; |
35643943 MCC |
301 | |
302 | unsigned int has_audio:1; | |
303 | ||
304 | unsigned int i2s_3rates:1; | |
305 | unsigned int i2s_5rates:1; | |
5c2231c8 DH |
306 | }; |
307 | ||
5faff789 MCC |
308 | /* em28xx has two audio inputs: tuner and line in. |
309 | However, on most devices, an auxiliary AC97 codec device is used. | |
310 | The AC97 device may have several different inputs and outputs, | |
311 | depending on their model. So, it is possible to use AC97 mixer to | |
312 | address more than two different entries. | |
313 | */ | |
539c96d0 | 314 | enum em28xx_amux { |
5faff789 MCC |
315 | /* This is the only entry for em28xx tuner input */ |
316 | EM28XX_AMUX_VIDEO, /* em28xx tuner, AC97 mixer Video */ | |
317 | ||
318 | EM28XX_AMUX_LINE_IN, /* AC97 mixer Line In */ | |
319 | ||
320 | /* Some less-common mixer setups */ | |
321 | EM28XX_AMUX_VIDEO2, /* em28xx Line in, AC97 mixer Video */ | |
322 | EM28XX_AMUX_PHONE, | |
323 | EM28XX_AMUX_MIC, | |
324 | EM28XX_AMUX_CD, | |
325 | EM28XX_AMUX_AUX, | |
326 | EM28XX_AMUX_PCM_OUT, | |
539c96d0 MCC |
327 | }; |
328 | ||
35ae6f04 | 329 | enum em28xx_aout { |
8866f9cf | 330 | /* AC97 outputs */ |
e879b8eb MCC |
331 | EM28XX_AOUT_MASTER = 1 << 0, |
332 | EM28XX_AOUT_LINE = 1 << 1, | |
333 | EM28XX_AOUT_MONO = 1 << 2, | |
334 | EM28XX_AOUT_LFE = 1 << 3, | |
335 | EM28XX_AOUT_SURR = 1 << 4, | |
8866f9cf MCC |
336 | |
337 | /* PCM IN Mixer - used by AC97_RECORD_SELECT register */ | |
338 | EM28XX_AOUT_PCM_IN = 1 << 7, | |
339 | ||
340 | /* Bits 10-8 are used to indicate the PCM IN record select */ | |
341 | EM28XX_AOUT_PCM_MIC_PCM = 0 << 8, | |
342 | EM28XX_AOUT_PCM_CD = 1 << 8, | |
343 | EM28XX_AOUT_PCM_VIDEO = 2 << 8, | |
344 | EM28XX_AOUT_PCM_AUX = 3 << 8, | |
345 | EM28XX_AOUT_PCM_LINE = 4 << 8, | |
346 | EM28XX_AOUT_PCM_STEREO = 5 << 8, | |
347 | EM28XX_AOUT_PCM_MONO = 6 << 8, | |
348 | EM28XX_AOUT_PCM_PHONE = 7 << 8, | |
35ae6f04 MCC |
349 | }; |
350 | ||
32929fb4 | 351 | static inline int ac97_return_record_select(int a_out) |
8866f9cf MCC |
352 | { |
353 | return (a_out & 0x700) >> 8; | |
354 | } | |
355 | ||
122b77e5 MCC |
356 | struct em28xx_reg_seq { |
357 | int reg; | |
358 | unsigned char val, mask; | |
359 | int sleep; | |
360 | }; | |
361 | ||
3acf2809 MCC |
362 | struct em28xx_input { |
363 | enum enum28xx_itype type; | |
a6c2ba28 | 364 | unsigned int vmux; |
539c96d0 | 365 | enum em28xx_amux amux; |
35ae6f04 | 366 | enum em28xx_aout aout; |
122b77e5 | 367 | struct em28xx_reg_seq *gpio; |
a6c2ba28 | 368 | }; |
369 | ||
3acf2809 | 370 | #define INPUT(nr) (&em28xx_boards[dev->model].input[nr]) |
a6c2ba28 | 371 | |
3acf2809 | 372 | enum em28xx_decoder { |
527f09a9 | 373 | EM28XX_NODECODER = 0, |
3acf2809 | 374 | EM28XX_TVP5150, |
ec5de990 | 375 | EM28XX_SAA711X, |
527f09a9 MCC |
376 | }; |
377 | ||
378 | enum em28xx_sensor { | |
379 | EM28XX_NOSENSOR = 0, | |
02e7804b | 380 | EM28XX_MT9V011, |
b80fd2d8 | 381 | EM28XX_MT9M001, |
f2e26ae7 | 382 | EM28XX_MT9M111, |
a6c2ba28 | 383 | }; |
384 | ||
df7fa09c MCC |
385 | enum em28xx_adecoder { |
386 | EM28XX_NOADECODER = 0, | |
387 | EM28XX_TVAUDIO, | |
388 | }; | |
389 | ||
3acf2809 | 390 | struct em28xx_board { |
a6c2ba28 | 391 | char *name; |
505b6d0b | 392 | int vchannels; |
a6c2ba28 | 393 | int tuner_type; |
66767920 | 394 | int tuner_addr; |
a6c2ba28 | 395 | |
396 | /* i2c flags */ | |
397 | unsigned int tda9887_conf; | |
398 | ||
017ab4b1 | 399 | /* GPIO sequences */ |
122b77e5 | 400 | struct em28xx_reg_seq *dvb_gpio; |
2fe3e2ee | 401 | struct em28xx_reg_seq *suspend_gpio; |
017ab4b1 | 402 | struct em28xx_reg_seq *tuner_gpio; |
2bd1d9eb | 403 | struct em28xx_reg_seq *mute_gpio; |
122b77e5 | 404 | |
74f38a82 | 405 | unsigned int is_em2800:1; |
a6c2ba28 | 406 | unsigned int has_msp34xx:1; |
5add9a6f | 407 | unsigned int mts_firmware:1; |
c8793b03 | 408 | unsigned int max_range_640_480:1; |
3aefb79a | 409 | unsigned int has_dvb:1; |
a9fc52bc | 410 | unsigned int has_snapshot_button:1; |
c43221df | 411 | unsigned int is_webcam:1; |
95b86a9a | 412 | unsigned int valid:1; |
ac07bb73 | 413 | unsigned int has_ir_i2c:1; |
3abee53e | 414 | |
a2070c66 | 415 | unsigned char xclk, i2c_speed; |
f2cf250a DSL |
416 | unsigned char radio_addr; |
417 | unsigned short tvaudio_addr; | |
a2070c66 | 418 | |
3acf2809 | 419 | enum em28xx_decoder decoder; |
df7fa09c | 420 | enum em28xx_adecoder adecoder; |
a6c2ba28 | 421 | |
3acf2809 | 422 | struct em28xx_input input[MAX_EM28XX_INPUT]; |
0be43754 | 423 | struct em28xx_input radio; |
02858eed | 424 | char *ir_codes; |
a6c2ba28 | 425 | }; |
426 | ||
3acf2809 | 427 | struct em28xx_eeprom { |
a6c2ba28 | 428 | u32 id; /* 0x9567eb1a */ |
429 | u16 vendor_ID; | |
430 | u16 product_ID; | |
431 | ||
432 | u16 chip_conf; | |
433 | ||
434 | u16 board_conf; | |
435 | ||
436 | u16 string1, string2, string3; | |
437 | ||
438 | u8 string_idx_table; | |
439 | }; | |
440 | ||
441 | /* device states */ | |
3acf2809 | 442 | enum em28xx_dev_state { |
a6c2ba28 | 443 | DEV_INITIALIZED = 0x01, |
444 | DEV_DISCONNECTED = 0x02, | |
445 | DEV_MISCONFIGURED = 0x04, | |
446 | }; | |
447 | ||
6d79468d MCC |
448 | #define EM28XX_AUDIO_BUFS 5 |
449 | #define EM28XX_NUM_AUDIO_PACKETS 64 | |
450 | #define EM28XX_AUDIO_MAX_PACKET_SIZE 196 /* static value */ | |
451 | #define EM28XX_CAPTURE_STREAM_EN 1 | |
3aefb79a MCC |
452 | |
453 | /* em28xx extensions */ | |
6d79468d | 454 | #define EM28XX_AUDIO 0x10 |
3aefb79a | 455 | #define EM28XX_DVB 0x20 |
6d79468d | 456 | |
8c873d31 DH |
457 | /* em28xx resource types (used for res_get/res_lock etc */ |
458 | #define EM28XX_RESOURCE_VIDEO 0x01 | |
459 | #define EM28XX_RESOURCE_VBI 0x02 | |
460 | ||
6d79468d MCC |
461 | struct em28xx_audio { |
462 | char name[50]; | |
463 | char *transfer_buffer[EM28XX_AUDIO_BUFS]; | |
464 | struct urb *urb[EM28XX_AUDIO_BUFS]; | |
465 | struct usb_device *udev; | |
466 | unsigned int capture_transfer_done; | |
467 | struct snd_pcm_substream *capture_pcm_substream; | |
468 | ||
469 | unsigned int hwptr_done_capture; | |
470 | struct snd_card *sndcard; | |
471 | ||
c744dff2 | 472 | int users; |
6d79468d MCC |
473 | spinlock_t slock; |
474 | }; | |
475 | ||
52284c3e MCC |
476 | struct em28xx; |
477 | ||
478 | struct em28xx_fh { | |
479 | struct em28xx *dev; | |
52284c3e | 480 | int radio; |
8c873d31 | 481 | unsigned int resources; |
52284c3e MCC |
482 | |
483 | struct videobuf_queue vb_vidq; | |
28abf083 | 484 | struct videobuf_queue vb_vbiq; |
52284c3e MCC |
485 | |
486 | enum v4l2_buf_type type; | |
487 | }; | |
488 | ||
a6c2ba28 | 489 | /* main device struct */ |
3acf2809 | 490 | struct em28xx { |
a6c2ba28 | 491 | /* generic device properties */ |
492 | char name[30]; /* name (including minor) of the device */ | |
493 | int model; /* index in the device_data struct */ | |
e5589bef | 494 | int devno; /* marks the number of this device */ |
600bd7f0 | 495 | enum em28xx_chip_id chip_id; |
505b6d0b | 496 | |
4f83e7b3 MCC |
497 | int audio_ifnum; |
498 | ||
f2cf250a | 499 | struct v4l2_device v4l2_dev; |
505b6d0b MCC |
500 | struct em28xx_board board; |
501 | ||
d36bb4e7 | 502 | /* Webcam specific fields */ |
527f09a9 | 503 | enum em28xx_sensor em28xx_sensor; |
55699964 | 504 | int sensor_xres, sensor_yres; |
d36bb4e7 | 505 | int sensor_xtal; |
527f09a9 | 506 | |
c2a6b54a MCC |
507 | /* Allows progressive (e. g. non-interlaced) mode */ |
508 | int progressive; | |
509 | ||
579d3152 MCC |
510 | /* Vinmode/Vinctl used at the driver */ |
511 | int vinmode, vinctl; | |
512 | ||
d7448a8d | 513 | unsigned int has_audio_class:1; |
24a613e4 | 514 | unsigned int has_alsa_audio:1; |
4f83e7b3 | 515 | unsigned int is_audio_only:1; |
a2070c66 | 516 | |
39a96b4c MCC |
517 | /* Controls audio streaming */ |
518 | struct work_struct wq_trigger; /* Trigger to start/stop audio for alsa module */ | |
519 | atomic_t stream_started; /* stream should be running if true */ | |
520 | ||
bddcf633 MCC |
521 | struct em28xx_fmt *format; |
522 | ||
a924a499 MCC |
523 | struct em28xx_IR *ir; |
524 | ||
89b329ef MCC |
525 | /* Some older em28xx chips needs a waiting time after writing */ |
526 | unsigned int wait_after_write; | |
527 | ||
74f38a82 MCC |
528 | struct list_head devlist; |
529 | ||
9bb13a6d MCC |
530 | u32 i2s_speed; /* I2S speed for audio digital stream */ |
531 | ||
35643943 | 532 | struct em28xx_audio_mode audio_mode; |
a6c2ba28 | 533 | |
534 | int tuner_type; /* type of the tuner */ | |
535 | int tuner_addr; /* tuner address */ | |
536 | int tda9887_conf; | |
537 | /* i2c i/o */ | |
538 | struct i2c_adapter i2c_adap; | |
539 | struct i2c_client i2c_client; | |
540 | /* video for linux */ | |
541 | int users; /* user count for exclusive use */ | |
542 | struct video_device *vdev; /* video for linux device struct */ | |
7d497f8a | 543 | v4l2_std_id norm; /* selected tv norm */ |
a6c2ba28 | 544 | int ctl_freq; /* selected frequency */ |
545 | unsigned int ctl_input; /* selected input */ | |
95b86a9a | 546 | unsigned int ctl_ainput;/* selected audio input */ |
35ae6f04 | 547 | unsigned int ctl_aoutput;/* selected audio output */ |
a6c2ba28 | 548 | int mute; |
549 | int volume; | |
550 | /* frame properties */ | |
a6c2ba28 | 551 | int width; /* current frame width */ |
552 | int height; /* current frame height */ | |
d45b9b8a HV |
553 | unsigned hscale; /* horizontal scale factor (see datasheet) */ |
554 | unsigned vscale; /* vertical scale factor (see datasheet) */ | |
a6c2ba28 | 555 | int interlaced; /* 1=interlace fileds, 0=just top fileds */ |
9e31ced8 | 556 | unsigned int video_bytesread; /* Number of bytes read */ |
a6c2ba28 | 557 | |
03910cc3 | 558 | unsigned long hash; /* eeprom hash - for boards with generic ID */ |
6ea54d93 DSL |
559 | unsigned long i2c_hash; /* i2c devicelist hash - |
560 | for boards with generic ID */ | |
03910cc3 | 561 | |
9baed99e | 562 | struct em28xx_audio adev; |
6d79468d | 563 | |
a6c2ba28 | 564 | /* states */ |
3acf2809 | 565 | enum em28xx_dev_state state; |
3acf2809 | 566 | enum em28xx_io_method io; |
9e31ced8 | 567 | |
da52a55c DH |
568 | /* vbi related state tracking */ |
569 | int capture_type; | |
570 | int vbi_read; | |
571 | unsigned char cur_field; | |
66d9cbad DH |
572 | unsigned int vbi_width; |
573 | unsigned int vbi_height; /* lines per field */ | |
da52a55c | 574 | |
d7448a8d MCC |
575 | struct work_struct request_module_wk; |
576 | ||
a6c2ba28 | 577 | /* locks */ |
5a80415b | 578 | struct mutex lock; |
f2a2e491 | 579 | struct mutex ctrl_urb_lock; /* protects urb_buf */ |
d7aa8020 | 580 | /* spinlock_t queue_lock; */ |
a6c2ba28 | 581 | struct list_head inqueue, outqueue; |
582 | wait_queue_head_t open, wait_frame, wait_stream; | |
583 | struct video_device *vbi_dev; | |
0be43754 | 584 | struct video_device *radio_dev; |
a6c2ba28 | 585 | |
8c873d31 DH |
586 | /* resources in use */ |
587 | unsigned int resources; | |
588 | ||
a6c2ba28 | 589 | unsigned char eedata[256]; |
590 | ||
ad0ebb96 MCC |
591 | /* Isoc control struct */ |
592 | struct em28xx_dmaqueue vidq; | |
28abf083 | 593 | struct em28xx_dmaqueue vbiq; |
ad0ebb96 MCC |
594 | struct em28xx_usb_isoc_ctl isoc_ctl; |
595 | spinlock_t slock; | |
596 | ||
a6c2ba28 | 597 | /* usb transfer */ |
598 | struct usb_device *udev; /* the usb device */ | |
599 | int alt; /* alternate */ | |
600 | int max_pkt_size; /* max packet size of isoc transaction */ | |
9d4d9c05 MCC |
601 | int num_alt; /* Number of alternative settings */ |
602 | unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */ | |
8ab33626 HN |
603 | int dvb_alt; /* alternate for DVB */ |
604 | unsigned int dvb_max_pkt_size; /* wMaxPacketSize for DVB */ | |
c4a98793 MCC |
605 | char urb_buf[URB_MAX_CTRL_SIZE]; /* urb control msg buffer */ |
606 | ||
a6c2ba28 | 607 | /* helper funcs that call usb_control_msg */ |
6ea54d93 | 608 | int (*em28xx_write_regs) (struct em28xx *dev, u16 reg, |
a6c2ba28 | 609 | char *buf, int len); |
6ea54d93 DSL |
610 | int (*em28xx_read_reg) (struct em28xx *dev, u16 reg); |
611 | int (*em28xx_read_reg_req_len) (struct em28xx *dev, u8 req, u16 reg, | |
612 | char *buf, int len); | |
613 | int (*em28xx_write_regs_req) (struct em28xx *dev, u8 req, u16 reg, | |
a6c2ba28 | 614 | char *buf, int len); |
6ea54d93 | 615 | int (*em28xx_read_reg_req) (struct em28xx *dev, u8 req, u16 reg); |
3aefb79a MCC |
616 | |
617 | enum em28xx_mode mode; | |
618 | ||
6a1acc3b DH |
619 | /* register numbers for GPO/GPIO registers */ |
620 | u16 reg_gpo_num, reg_gpio_num; | |
621 | ||
c67ec53f MCC |
622 | /* Caches GPO and GPIO registers */ |
623 | unsigned char reg_gpo, reg_gpio; | |
624 | ||
a9fc52bc DH |
625 | /* Snapshot button */ |
626 | char snapshot_button_path[30]; /* path of the input dev */ | |
627 | struct input_dev *sbutton_input_dev; | |
628 | struct delayed_work sbutton_query_work; | |
629 | ||
3421b778 | 630 | struct em28xx_dvb *dvb; |
d2ebd0f8 MCC |
631 | |
632 | /* I2C keyboard data */ | |
d2ebd0f8 | 633 | struct IR_i2c_init_data init_data; |
a6c2ba28 | 634 | }; |
635 | ||
6d79468d MCC |
636 | struct em28xx_ops { |
637 | struct list_head next; | |
638 | char *name; | |
639 | int id; | |
640 | int (*init)(struct em28xx *); | |
641 | int (*fini)(struct em28xx *); | |
a3a048ce MCC |
642 | }; |
643 | ||
3acf2809 | 644 | /* Provided by em28xx-i2c.c */ |
fad7b958 | 645 | void em28xx_do_i2c_scan(struct em28xx *dev); |
f2cf250a DSL |
646 | int em28xx_i2c_register(struct em28xx *dev); |
647 | int em28xx_i2c_unregister(struct em28xx *dev); | |
a6c2ba28 | 648 | |
3acf2809 | 649 | /* Provided by em28xx-core.c */ |
a6c2ba28 | 650 | |
3acf2809 MCC |
651 | u32 em28xx_request_buffers(struct em28xx *dev, u32 count); |
652 | void em28xx_queue_unusedframes(struct em28xx *dev); | |
653 | void em28xx_release_buffers(struct em28xx *dev); | |
a6c2ba28 | 654 | |
3acf2809 | 655 | int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg, |
a6c2ba28 | 656 | char *buf, int len); |
3acf2809 MCC |
657 | int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg); |
658 | int em28xx_read_reg(struct em28xx *dev, u16 reg); | |
659 | int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf, | |
a6c2ba28 | 660 | int len); |
3acf2809 | 661 | int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len); |
b6972489 | 662 | int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val); |
1bad429e MCC |
663 | int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val, |
664 | u8 bitmask); | |
b6972489 | 665 | |
531c98e7 MCC |
666 | int em28xx_read_ac97(struct em28xx *dev, u8 reg); |
667 | int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val); | |
668 | ||
3acf2809 | 669 | int em28xx_audio_analog_set(struct em28xx *dev); |
35643943 | 670 | int em28xx_audio_setup(struct em28xx *dev); |
539c96d0 | 671 | |
3acf2809 MCC |
672 | int em28xx_colorlevels_set_default(struct em28xx *dev); |
673 | int em28xx_capture_start(struct em28xx *dev, int start); | |
da52a55c | 674 | int em28xx_vbi_supported(struct em28xx *dev); |
bddcf633 | 675 | int em28xx_set_outfmt(struct em28xx *dev); |
3acf2809 | 676 | int em28xx_resolution_set(struct em28xx *dev); |
3acf2809 | 677 | int em28xx_set_alternate(struct em28xx *dev); |
86d38d1e GG |
678 | int em28xx_alloc_isoc(struct em28xx *dev, enum em28xx_mode mode, |
679 | int max_packets, int num_bufs, int max_pkt_size); | |
680 | int em28xx_init_isoc(struct em28xx *dev, enum em28xx_mode mode, | |
681 | int max_packets, int num_bufs, int max_pkt_size, | |
c67ec53f | 682 | int (*isoc_copy) (struct em28xx *dev, struct urb *urb)); |
86d38d1e | 683 | void em28xx_uninit_isoc(struct em28xx *dev, enum em28xx_mode mode); |
5f5f147f | 684 | void em28xx_stop_urbs(struct em28xx *dev); |
d18e2fda | 685 | int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev); |
c67ec53f MCC |
686 | int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode); |
687 | int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio); | |
1a23f81b | 688 | void em28xx_wake_i2c(struct em28xx *dev); |
6d79468d MCC |
689 | int em28xx_register_extension(struct em28xx_ops *dev); |
690 | void em28xx_unregister_extension(struct em28xx_ops *dev); | |
1a23f81b MCC |
691 | void em28xx_init_extension(struct em28xx *dev); |
692 | void em28xx_close_extension(struct em28xx *dev); | |
693 | ||
694 | /* Provided by em28xx-video.c */ | |
1a23f81b MCC |
695 | int em28xx_register_analog_devices(struct em28xx *dev); |
696 | void em28xx_release_analog_resources(struct em28xx *dev); | |
6d79468d | 697 | |
3acf2809 | 698 | /* Provided by em28xx-cards.c */ |
6ea54d93 | 699 | extern int em2800_variant_detect(struct usb_device *udev, int model); |
a94e95b4 | 700 | extern void em28xx_pre_card_setup(struct em28xx *dev); |
3acf2809 MCC |
701 | extern void em28xx_card_setup(struct em28xx *dev); |
702 | extern struct em28xx_board em28xx_boards[]; | |
703 | extern struct usb_device_id em28xx_id_table[]; | |
704 | extern const unsigned int em28xx_bcount; | |
d7cba043 | 705 | int em28xx_tuner_callback(void *ptr, int component, int command, int arg); |
1a23f81b | 706 | void em28xx_release_resources(struct em28xx *dev); |
c8793b03 MCC |
707 | |
708 | /* Provided by em28xx-input.c */ | |
5b89ecf9 MCC |
709 | |
710 | #ifdef CONFIG_VIDEO_EM28XX_RC | |
711 | ||
a924a499 MCC |
712 | int em28xx_ir_init(struct em28xx *dev); |
713 | int em28xx_ir_fini(struct em28xx *dev); | |
714 | ||
5b89ecf9 MCC |
715 | #else |
716 | ||
5b89ecf9 MCC |
717 | static inline int em28xx_ir_init(struct em28xx *dev) { return 0; } |
718 | static inline int em28xx_ir_fini(struct em28xx *dev) { return 0; } | |
719 | ||
720 | #endif | |
721 | ||
28abf083 DH |
722 | /* Provided by em28xx-vbi.c */ |
723 | extern struct videobuf_queue_ops em28xx_vbi_qops; | |
724 | ||
a6c2ba28 | 725 | /* printk macros */ |
726 | ||
3acf2809 | 727 | #define em28xx_err(fmt, arg...) do {\ |
f85c657f | 728 | printk(KERN_ERR fmt , ##arg); } while (0) |
a6c2ba28 | 729 | |
3acf2809 | 730 | #define em28xx_errdev(fmt, arg...) do {\ |
4ac97914 | 731 | printk(KERN_ERR "%s: "fmt,\ |
f85c657f | 732 | dev->name , ##arg); } while (0) |
a6c2ba28 | 733 | |
3acf2809 | 734 | #define em28xx_info(fmt, arg...) do {\ |
4ac97914 | 735 | printk(KERN_INFO "%s: "fmt,\ |
f85c657f | 736 | dev->name , ##arg); } while (0) |
3acf2809 | 737 | #define em28xx_warn(fmt, arg...) do {\ |
4ac97914 | 738 | printk(KERN_WARNING "%s: "fmt,\ |
f85c657f | 739 | dev->name , ##arg); } while (0) |
a6c2ba28 | 740 | |
6ea54d93 | 741 | static inline int em28xx_compression_disable(struct em28xx *dev) |
a6c2ba28 | 742 | { |
743 | /* side effect of disabling scaler and mixer */ | |
2a29a0d7 | 744 | return em28xx_write_reg(dev, EM28XX_R26_COMPR, 0x00); |
a6c2ba28 | 745 | } |
746 | ||
6ea54d93 | 747 | static inline int em28xx_contrast_get(struct em28xx *dev) |
a6c2ba28 | 748 | { |
41facaa4 | 749 | return em28xx_read_reg(dev, EM28XX_R20_YGAIN) & 0x1f; |
a6c2ba28 | 750 | } |
751 | ||
6ea54d93 | 752 | static inline int em28xx_brightness_get(struct em28xx *dev) |
a6c2ba28 | 753 | { |
41facaa4 | 754 | return em28xx_read_reg(dev, EM28XX_R21_YOFFSET); |
a6c2ba28 | 755 | } |
756 | ||
6ea54d93 | 757 | static inline int em28xx_saturation_get(struct em28xx *dev) |
a6c2ba28 | 758 | { |
41facaa4 | 759 | return em28xx_read_reg(dev, EM28XX_R22_UVGAIN) & 0x1f; |
a6c2ba28 | 760 | } |
761 | ||
6ea54d93 | 762 | static inline int em28xx_u_balance_get(struct em28xx *dev) |
a6c2ba28 | 763 | { |
41facaa4 | 764 | return em28xx_read_reg(dev, EM28XX_R23_UOFFSET); |
a6c2ba28 | 765 | } |
766 | ||
6ea54d93 | 767 | static inline int em28xx_v_balance_get(struct em28xx *dev) |
a6c2ba28 | 768 | { |
41facaa4 | 769 | return em28xx_read_reg(dev, EM28XX_R24_VOFFSET); |
a6c2ba28 | 770 | } |
771 | ||
6ea54d93 | 772 | static inline int em28xx_gamma_get(struct em28xx *dev) |
a6c2ba28 | 773 | { |
41facaa4 | 774 | return em28xx_read_reg(dev, EM28XX_R14_GAMMA) & 0x3f; |
a6c2ba28 | 775 | } |
776 | ||
6ea54d93 | 777 | static inline int em28xx_contrast_set(struct em28xx *dev, s32 val) |
a6c2ba28 | 778 | { |
779 | u8 tmp = (u8) val; | |
41facaa4 | 780 | return em28xx_write_regs(dev, EM28XX_R20_YGAIN, &tmp, 1); |
a6c2ba28 | 781 | } |
782 | ||
6ea54d93 | 783 | static inline int em28xx_brightness_set(struct em28xx *dev, s32 val) |
a6c2ba28 | 784 | { |
785 | u8 tmp = (u8) val; | |
41facaa4 | 786 | return em28xx_write_regs(dev, EM28XX_R21_YOFFSET, &tmp, 1); |
a6c2ba28 | 787 | } |
788 | ||
6ea54d93 | 789 | static inline int em28xx_saturation_set(struct em28xx *dev, s32 val) |
a6c2ba28 | 790 | { |
791 | u8 tmp = (u8) val; | |
41facaa4 | 792 | return em28xx_write_regs(dev, EM28XX_R22_UVGAIN, &tmp, 1); |
a6c2ba28 | 793 | } |
794 | ||
6ea54d93 | 795 | static inline int em28xx_u_balance_set(struct em28xx *dev, s32 val) |
a6c2ba28 | 796 | { |
797 | u8 tmp = (u8) val; | |
41facaa4 | 798 | return em28xx_write_regs(dev, EM28XX_R23_UOFFSET, &tmp, 1); |
a6c2ba28 | 799 | } |
800 | ||
6ea54d93 | 801 | static inline int em28xx_v_balance_set(struct em28xx *dev, s32 val) |
a6c2ba28 | 802 | { |
803 | u8 tmp = (u8) val; | |
41facaa4 | 804 | return em28xx_write_regs(dev, EM28XX_R24_VOFFSET, &tmp, 1); |
a6c2ba28 | 805 | } |
806 | ||
6ea54d93 | 807 | static inline int em28xx_gamma_set(struct em28xx *dev, s32 val) |
a6c2ba28 | 808 | { |
809 | u8 tmp = (u8) val; | |
41facaa4 | 810 | return em28xx_write_regs(dev, EM28XX_R14_GAMMA, &tmp, 1); |
a6c2ba28 | 811 | } |
812 | ||
813 | /*FIXME: maxw should be dependent of alt mode */ | |
6ea54d93 | 814 | static inline unsigned int norm_maxw(struct em28xx *dev) |
30556b23 | 815 | { |
55699964 MCC |
816 | if (dev->board.is_webcam) |
817 | return dev->sensor_xres; | |
818 | ||
1020d13d | 819 | if (dev->board.max_range_640_480) |
7d497f8a | 820 | return 640; |
55699964 MCC |
821 | |
822 | return 720; | |
30556b23 MR |
823 | } |
824 | ||
6ea54d93 | 825 | static inline unsigned int norm_maxh(struct em28xx *dev) |
a6c2ba28 | 826 | { |
55699964 MCC |
827 | if (dev->board.is_webcam) |
828 | return dev->sensor_yres; | |
829 | ||
505b6d0b | 830 | if (dev->board.max_range_640_480) |
7d497f8a | 831 | return 480; |
55699964 MCC |
832 | |
833 | return (dev->norm & V4L2_STD_625_50) ? 576 : 480; | |
a6c2ba28 | 834 | } |
a6c2ba28 | 835 | #endif |