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V4L/DVB: ivtv: Fix race condition for queued udma transfers
[deliverable/linux.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
75212a02 27#include <media/tuner.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
d855497e
MI		 33#include "pvrusb2-eeprom.h"
34#include "pvrusb2-hdw-internal.h"
35#include "pvrusb2-encoder.h"
36#include "pvrusb2-debug.h"
8d364363 37#include "pvrusb2-fx2-cmd.h"
5f6dae80 38#include "pvrusb2-wm8775.h"
6f956512 39#include "pvrusb2-video-v4l.h"
634ba268 40#include "pvrusb2-cx2584x-v4l.h"
2a6b627f 41#include "pvrusb2-cs53l32a.h"
76891d65 42#include "pvrusb2-audio.h"
d855497e 43
1bde0289
MI		 44#define TV_MIN_FREQ 55250000L
45#define TV_MAX_FREQ 850000000L
25d8527a 46
83ce57aa
MI		 47/* This defines a minimum interval that the decoder must remain quiet
48 before we are allowed to start it running. */
49#define TIME_MSEC_DECODER_WAIT 50
50
51/* This defines a minimum interval that the encoder must remain quiet
fa98e594
MI		 52 before we are allowed to configure it. I had this originally set to
53 50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
54 things work better when it's set to 100msec. */
55#define TIME_MSEC_ENCODER_WAIT 100
83ce57aa
MI		 56
57/* This defines the minimum interval that the encoder must successfully run
58 before we consider that the encoder has run at least once since its
59 firmware has been loaded. This measurement is in important for cases
60 where we can't do something until we know that the encoder has been run
61 at least once. */
62#define TIME_MSEC_ENCODER_OK 250
63
a0fd1cb1 64static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 65static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 66
ff699e6b 67static int ctlchg;
ff699e6b 68static int procreload;
d855497e
MI		 69static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
70static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
71static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 72static int init_pause_msec;
d855497e
MI		 73
74module_param(ctlchg, int, S_IRUGO|S_IWUSR);
75MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
76module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
77MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 78module_param(procreload, int, S_IRUGO|S_IWUSR);
79MODULE_PARM_DESC(procreload,
80 "Attempt init failure recovery with firmware reload");
81module_param_array(tuner, int, NULL, 0444);
82MODULE_PARM_DESC(tuner,"specify installed tuner type");
83module_param_array(video_std, int, NULL, 0444);
84MODULE_PARM_DESC(video_std,"specify initial video standard");
85module_param_array(tolerance, int, NULL, 0444);
86MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
87
6f441ed7
MI		 88/* US Broadcast channel 3 (61.25 MHz), to help with testing */
89static int default_tv_freq = 61250000L;
5a4f5da6
MK		 90/* 104.3 MHz, a usable FM station for my area */
91static int default_radio_freq = 104300000L;
92
93module_param_named(tv_freq, default_tv_freq, int, 0444);
94MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
95module_param_named(radio_freq, default_radio_freq, int, 0444);
96MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
97
d855497e
MI		 98#define PVR2_CTL_WRITE_ENDPOINT 0x01
99#define PVR2_CTL_READ_ENDPOINT 0x81
100
101#define PVR2_GPIO_IN 0x9008
102#define PVR2_GPIO_OUT 0x900c
103#define PVR2_GPIO_DIR 0x9020
104
105#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
106
107#define PVR2_FIRMWARE_ENDPOINT 0x02
108
109/* size of a firmware chunk */
110#define FIRMWARE_CHUNK_SIZE 0x2000
111
edb9dcb8
MI		 112typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
113 struct v4l2_subdev *);
114
115static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 116 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 117 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 118 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 119 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
2a6b627f 120 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
edb9dcb8
MI		 121};
122
e9c64a78
MI		 123static const char *module_names[] = {
124 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
125 [PVR2_CLIENT_ID_CX25840] = "cx25840",
126 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
127 [PVR2_CLIENT_ID_TUNER] = "tuner",
bb65242a 128 [PVR2_CLIENT_ID_DEMOD] = "tuner",
851981a1 129 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
5f6dae80 130 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 131};
132
133
134static const unsigned char *module_i2c_addresses[] = {
135 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
bb65242a 136 [PVR2_CLIENT_ID_DEMOD] = "\x43",
1dfe6c77
MI		 137 [PVR2_CLIENT_ID_MSP3400] = "\x40",
138 [PVR2_CLIENT_ID_SAA7115] = "\x21",
ae111f76 139 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 140 [PVR2_CLIENT_ID_CX25840] = "\x44",
23334a22 141 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
e9c64a78
MI		 142};
143
144
27eab384
MI		 145static const char *ir_scheme_names[] = {
146 [PVR2_IR_SCHEME_NONE] = "none",
147 [PVR2_IR_SCHEME_29XXX] = "29xxx",
148 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
149 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
150 [PVR2_IR_SCHEME_ZILOG] = "Zilog",
151};
152
153
b30d2441
MI		 154/* Define the list of additional controls we'll dynamically construct based
155 on query of the cx2341x module. */
156struct pvr2_mpeg_ids {
157 const char *strid;
158 int id;
159};
160static const struct pvr2_mpeg_ids mpeg_ids[] = {
161 {
162 .strid = "audio_layer",
163 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
164 },{
165 .strid = "audio_bitrate",
166 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
167 },{
168 /* Already using audio_mode elsewhere :-( */
169 .strid = "mpeg_audio_mode",
170 .id = V4L2_CID_MPEG_AUDIO_MODE,
171 },{
172 .strid = "mpeg_audio_mode_extension",
173 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
174 },{
175 .strid = "audio_emphasis",
176 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
177 },{
178 .strid = "audio_crc",
179 .id = V4L2_CID_MPEG_AUDIO_CRC,
180 },{
181 .strid = "video_aspect",
182 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
183 },{
184 .strid = "video_b_frames",
185 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
186 },{
187 .strid = "video_gop_size",
188 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
189 },{
190 .strid = "video_gop_closure",
191 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 192 },{
193 .strid = "video_bitrate_mode",
194 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
195 },{
196 .strid = "video_bitrate",
197 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
198 },{
199 .strid = "video_bitrate_peak",
200 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
201 },{
202 .strid = "video_temporal_decimation",
203 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
204 },{
205 .strid = "stream_type",
206 .id = V4L2_CID_MPEG_STREAM_TYPE,
207 },{
208 .strid = "video_spatial_filter_mode",
209 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
210 },{
211 .strid = "video_spatial_filter",
212 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
213 },{
214 .strid = "video_luma_spatial_filter_type",
215 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
216 },{
217 .strid = "video_chroma_spatial_filter_type",
218 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
219 },{
220 .strid = "video_temporal_filter_mode",
221 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
222 },{
223 .strid = "video_temporal_filter",
224 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
225 },{
226 .strid = "video_median_filter_type",
227 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
228 },{
229 .strid = "video_luma_median_filter_top",
230 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
231 },{
232 .strid = "video_luma_median_filter_bottom",
233 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
234 },{
235 .strid = "video_chroma_median_filter_top",
236 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
237 },{
238 .strid = "video_chroma_median_filter_bottom",
239 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
240 }
241};
eca8ebfc 242#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 243
434449f4 244
d855497e 245static const char *control_values_srate[] = {
434449f4
MI		 246 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
247 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
248 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 249};
250
251
d855497e 252
d855497e
MI		 253static const char *control_values_input[] = {
254 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 255 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 256 [PVR2_CVAL_INPUT_RADIO] = "radio",
257 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
258 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
259};
260
261
262static const char *control_values_audiomode[] = {
263 [V4L2_TUNER_MODE_MONO] = "Mono",
264 [V4L2_TUNER_MODE_STEREO] = "Stereo",
265 [V4L2_TUNER_MODE_LANG1] = "Lang1",
266 [V4L2_TUNER_MODE_LANG2] = "Lang2",
267 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
268};
269
270
271static const char *control_values_hsm[] = {
272 [PVR2_CVAL_HSM_FAIL] = "Fail",
273 [PVR2_CVAL_HSM_HIGH] = "High",
274 [PVR2_CVAL_HSM_FULL] = "Full",
275};
276
277
681c7399
MI		 278static const char *pvr2_state_names[] = {
279 [PVR2_STATE_NONE] = "none",
280 [PVR2_STATE_DEAD] = "dead",
281 [PVR2_STATE_COLD] = "cold",
282 [PVR2_STATE_WARM] = "warm",
283 [PVR2_STATE_ERROR] = "error",
284 [PVR2_STATE_READY] = "ready",
285 [PVR2_STATE_RUN] = "run",
d855497e
MI		 286};
287
681c7399 288
694dca2b 289struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 290 unsigned char id;
291 unsigned char *desc;
292};
293
694dca2b 294static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 295 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
296 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 297 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 298 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
299 {FX2CMD_REG_WRITE, "write encoder register"},
300 {FX2CMD_REG_READ, "read encoder register"},
301 {FX2CMD_MEMSEL, "encoder memsel"},
302 {FX2CMD_I2C_WRITE, "i2c write"},
303 {FX2CMD_I2C_READ, "i2c read"},
304 {FX2CMD_GET_USB_SPEED, "get USB speed"},
305 {FX2CMD_STREAMING_ON, "stream on"},
306 {FX2CMD_STREAMING_OFF, "stream off"},
307 {FX2CMD_FWPOST1, "fwpost1"},
308 {FX2CMD_POWER_OFF, "power off"},
309 {FX2CMD_POWER_ON, "power on"},
310 {FX2CMD_DEEP_RESET, "deep reset"},
311 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
312 {FX2CMD_GET_IR_CODE, "get IR code"},
313 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
314 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
315 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
316 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
317 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
318 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
319 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
320};
321
322
1cb03b76 323static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 324static void pvr2_hdw_state_sched(struct pvr2_hdw *);
325static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 326static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399 327static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 328static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
329static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
330static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 331static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 332static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 333static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 334static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
335static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 336static void pvr2_hdw_quiescent_timeout(unsigned long);
337static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 338static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 339static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 340static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
341 unsigned int timeout,int probe_fl,
342 void *write_data,unsigned int write_len,
343 void *read_data,unsigned int read_len);
432907f7 344static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 345
681c7399
MI		 346
347static void trace_stbit(const char *name,int val)
348{
349 pvr2_trace(PVR2_TRACE_STBITS,
350 "State bit %s <-- %s",
351 name,(val ? "true" : "false"));
352}
353
d855497e
MI		 354static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
355{
356 struct pvr2_hdw *hdw = cptr->hdw;
357 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
358 *vp = hdw->freqTable[hdw->freqProgSlot-1];
359 } else {
360 *vp = 0;
361 }
362 return 0;
363}
364
365static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
366{
367 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 368 unsigned int slotId = hdw->freqProgSlot;
369 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
370 hdw->freqTable[slotId-1] = v;
371 /* Handle side effects correctly - if we're tuned to this
372 slot, then forgot the slot id relation since the stored
373 frequency has been changed. */
374 if (hdw->freqSelector) {
375 if (hdw->freqSlotRadio == slotId) {
376 hdw->freqSlotRadio = 0;
377 }
378 } else {
379 if (hdw->freqSlotTelevision == slotId) {
380 hdw->freqSlotTelevision = 0;
381 }
382 }
d855497e
MI		 383 }
384 return 0;
385}
386
387static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
388{
389 *vp = cptr->hdw->freqProgSlot;
390 return 0;
391}
392
393static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
394{
395 struct pvr2_hdw *hdw = cptr->hdw;
396 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
397 hdw->freqProgSlot = v;
398 }
399 return 0;
400}
401
402static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
403{
1bde0289
MI		 404 struct pvr2_hdw *hdw = cptr->hdw;
405 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 406 return 0;
407}
408
1bde0289 409static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 410{
411 unsigned freq = 0;
412 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 413 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
414 if (slotId > 0) {
415 freq = hdw->freqTable[slotId-1];
416 if (!freq) return 0;
417 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 418 }
1bde0289
MI		 419 if (hdw->freqSelector) {
420 hdw->freqSlotRadio = slotId;
421 } else {
422 hdw->freqSlotTelevision = slotId;
d855497e
MI		 423 }
424 return 0;
425}
426
427static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
428{
1bde0289 429 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 430 return 0;
431}
432
433static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
434{
435 return cptr->hdw->freqDirty != 0;
436}
437
438static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
439{
440 cptr->hdw->freqDirty = 0;
441}
442
443static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
444{
1bde0289 445 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 446 return 0;
447}
448
e784bfb9 449static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
450{
432907f7
MI		 451 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
452 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
453 if (stat != 0) {
432907f7 454 return stat;
e784bfb9 455 }
432907f7 456 *left = cap->bounds.left;
e784bfb9 457 return 0;
458}
459
460static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
461{
432907f7
MI		 462 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
463 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
464 if (stat != 0) {
432907f7
MI		 465 return stat;
466 }
467 *left = cap->bounds.left;
468 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 469 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 470 }
471 return 0;
472}
473
474static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
475{
432907f7
MI		 476 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
477 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
478 if (stat != 0) {
432907f7 479 return stat;
e784bfb9 480 }
432907f7 481 *top = cap->bounds.top;
e784bfb9 482 return 0;
483}
484
432907f7 485static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 486{
432907f7
MI		 487 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
488 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
489 if (stat != 0) {
432907f7
MI		 490 return stat;
491 }
492 *top = cap->bounds.top;
493 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 494 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 495 }
496 return 0;
497}
498
432907f7
MI		 499static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
500{
501 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
502 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
503 if (stat != 0) {
432907f7
MI		 504 return stat;
505 }
506 *val = 0;
507 if (cap->bounds.width > cptr->hdw->cropl_val) {
432907f7
MI		 508 *val = cap->bounds.width - cptr->hdw->cropl_val;
509 }
510 return 0;
511}
512
513static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
514{
515 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
516 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
517 if (stat != 0) {
432907f7
MI		 518 return stat;
519 }
520 *val = 0;
521 if (cap->bounds.height > cptr->hdw->cropt_val) {
432907f7
MI		 522 *val = cap->bounds.height - cptr->hdw->cropt_val;
523 }
524 return 0;
525}
526
527static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
528{
529 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
530 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
531 if (stat != 0) {
432907f7
MI		 532 return stat;
533 }
534 *val = cap->bounds.left;
535 return 0;
536}
537
538static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
539{
540 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
541 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
542 if (stat != 0) {
432907f7
MI		 543 return stat;
544 }
545 *val = cap->bounds.top;
546 return 0;
547}
548
549static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
550{
551 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
552 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
553 if (stat != 0) {
432907f7
MI		 554 return stat;
555 }
556 *val = cap->bounds.width;
557 return 0;
558}
559
560static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
561{
562 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
563 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
564 if (stat != 0) {
432907f7
MI		 565 return stat;
566 }
567 *val = cap->bounds.height;
568 return 0;
569}
570
571static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
572{
573 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
574 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
575 if (stat != 0) {
432907f7
MI		 576 return stat;
577 }
578 *val = cap->defrect.left;
579 return 0;
580}
581
582static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
583{
584 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
585 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
586 if (stat != 0) {
432907f7
MI		 587 return stat;
588 }
589 *val = cap->defrect.top;
590 return 0;
591}
592
593static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
594{
595 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
596 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
597 if (stat != 0) {
432907f7
MI		 598 return stat;
599 }
600 *val = cap->defrect.width;
601 return 0;
602}
603
604static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
605{
606 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
607 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
608 if (stat != 0) {
432907f7
MI		 609 return stat;
610 }
611 *val = cap->defrect.height;
612 return 0;
613}
614
615static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
616{
617 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
618 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
619 if (stat != 0) {
432907f7
MI		 620 return stat;
621 }
622 *val = cap->pixelaspect.numerator;
623 return 0;
624}
625
626static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
627{
628 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
629 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
630 if (stat != 0) {
432907f7
MI		 631 return stat;
632 }
633 *val = cap->pixelaspect.denominator;
634 return 0;
635}
636
637static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 638{
432907f7
MI		 639 /* Actual maximum depends on the video standard in effect. */
640 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
641 *vp = 480;
e784bfb9 642 } else {
432907f7 643 *vp = 576;
e784bfb9 644 }
645 return 0;
646}
647
3ad9fc37
MI		 648static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
649{
989eb154
MI		 650 /* Actual minimum depends on device digitizer type. */
651 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 652 *vp = 75;
653 } else {
654 *vp = 17;
655 }
656 return 0;
657}
658
1bde0289 659static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 660{
1bde0289
MI		 661 *vp = cptr->hdw->input_val;
662 return 0;
663}
664
29bf5b1d
MI		 665static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
666{
1cb03b76 667 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 668}
669
1bde0289
MI		 670static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
671{
1cb03b76 672 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 673}
674
675static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
676{
677 return cptr->hdw->input_dirty != 0;
678}
679
680static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
681{
682 cptr->hdw->input_dirty = 0;
683}
684
5549f54f 685
25d8527a
PK		 686static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
687{
644afdb9
MI		 688 unsigned long fv;
689 struct pvr2_hdw *hdw = cptr->hdw;
690 if (hdw->tuner_signal_stale) {
a51f5000 691 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 692 }
693 fv = hdw->tuner_signal_info.rangehigh;
694 if (!fv) {
695 /* Safety fallback */
25d8527a 696 *vp = TV_MAX_FREQ;
644afdb9 697 return 0;
25d8527a 698 }
644afdb9
MI		 699 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
700 fv = (fv * 125) / 2;
701 } else {
702 fv = fv * 62500;
703 }
704 *vp = fv;
25d8527a
PK		 705 return 0;
706}
707
708static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
709{
644afdb9
MI		 710 unsigned long fv;
711 struct pvr2_hdw *hdw = cptr->hdw;
712 if (hdw->tuner_signal_stale) {
a51f5000 713 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 714 }
715 fv = hdw->tuner_signal_info.rangelow;
716 if (!fv) {
717 /* Safety fallback */
25d8527a 718 *vp = TV_MIN_FREQ;
644afdb9
MI		 719 return 0;
720 }
721 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
722 fv = (fv * 125) / 2;
723 } else {
724 fv = fv * 62500;
25d8527a 725 }
644afdb9 726 *vp = fv;
25d8527a
PK		 727 return 0;
728}
729
b30d2441
MI		 730static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
731{
732 return cptr->hdw->enc_stale != 0;
733}
734
735static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
736{
737 cptr->hdw->enc_stale = 0;
681c7399 738 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 739}
740
741static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
742{
743 int ret;
744 struct v4l2_ext_controls cs;
745 struct v4l2_ext_control c1;
746 memset(&cs,0,sizeof(cs));
747 memset(&c1,0,sizeof(c1));
748 cs.controls = &c1;
749 cs.count = 1;
750 c1.id = cptr->info->v4l_id;
01f1e44f 751 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 752 VIDIOC_G_EXT_CTRLS);
753 if (ret) return ret;
754 *vp = c1.value;
755 return 0;
756}
757
758static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
759{
760 int ret;
681c7399 761 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 762 struct v4l2_ext_controls cs;
763 struct v4l2_ext_control c1;
764 memset(&cs,0,sizeof(cs));
765 memset(&c1,0,sizeof(c1));
766 cs.controls = &c1;
767 cs.count = 1;
768 c1.id = cptr->info->v4l_id;
769 c1.value = v;
681c7399
MI		 770 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
771 hdw->state_encoder_run, &cs,
b30d2441 772 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 773 if (ret == -EBUSY) {
774 /* Oops. cx2341x is telling us it's not safe to change
775 this control while we're capturing. Make a note of this
776 fact so that the pipeline will be stopped the next time
777 controls are committed. Then go on ahead and store this
778 change anyway. */
779 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
780 0, &cs,
781 VIDIOC_S_EXT_CTRLS);
782 if (!ret) hdw->enc_unsafe_stale = !0;
783 }
b30d2441 784 if (ret) return ret;
681c7399 785 hdw->enc_stale = !0;
b30d2441
MI		 786 return 0;
787}
788
789static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
790{
791 struct v4l2_queryctrl qctrl;
792 struct pvr2_ctl_info *info;
793 qctrl.id = cptr->info->v4l_id;
794 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
795 /* Strip out the const so we can adjust a function pointer. It's
796 OK to do this here because we know this is a dynamically created
797 control, so the underlying storage for the info pointer is (a)
798 private to us, and (b) not in read-only storage. Either we do
799 this or we significantly complicate the underlying control
800 implementation. */
801 info = (struct pvr2_ctl_info *)(cptr->info);
802 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
803 if (info->set_value) {
a0fd1cb1 804 info->set_value = NULL;
b30d2441
MI		 805 }
806 } else {
807 if (!(info->set_value)) {
808 info->set_value = ctrl_cx2341x_set;
809 }
810 }
811 return qctrl.flags;
812}
813
d855497e
MI		 814static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
815{
681c7399
MI		 816 *vp = cptr->hdw->state_pipeline_req;
817 return 0;
818}
819
820static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
821{
822 *vp = cptr->hdw->master_state;
d855497e
MI		 823 return 0;
824}
825
826static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
827{
828 int result = pvr2_hdw_is_hsm(cptr->hdw);
829 *vp = PVR2_CVAL_HSM_FULL;
830 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
831 if (result) *vp = PVR2_CVAL_HSM_HIGH;
832 return 0;
833}
834
835static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
836{
837 *vp = cptr->hdw->std_mask_avail;
838 return 0;
839}
840
841static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
842{
843 struct pvr2_hdw *hdw = cptr->hdw;
844 v4l2_std_id ns;
845 ns = hdw->std_mask_avail;
846 ns = (ns & ~m) | (v & m);
847 if (ns == hdw->std_mask_avail) return 0;
848 hdw->std_mask_avail = ns;
849 pvr2_hdw_internal_set_std_avail(hdw);
850 pvr2_hdw_internal_find_stdenum(hdw);
851 return 0;
852}
853
854static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
855 char *bufPtr,unsigned int bufSize,
856 unsigned int *len)
857{
858 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
859 return 0;
860}
861
862static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
863 const char *bufPtr,unsigned int bufSize,
864 int *mskp,int *valp)
865{
866 int ret;
867 v4l2_std_id id;
868 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
869 if (ret < 0) return ret;
870 if (mskp) *mskp = id;
871 if (valp) *valp = id;
872 return 0;
873}
874
875static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
876{
877 *vp = cptr->hdw->std_mask_cur;
878 return 0;
879}
880
881static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
882{
883 struct pvr2_hdw *hdw = cptr->hdw;
884 v4l2_std_id ns;
885 ns = hdw->std_mask_cur;
886 ns = (ns & ~m) | (v & m);
887 if (ns == hdw->std_mask_cur) return 0;
888 hdw->std_mask_cur = ns;
889 hdw->std_dirty = !0;
890 pvr2_hdw_internal_find_stdenum(hdw);
891 return 0;
892}
893
894static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
895{
896 return cptr->hdw->std_dirty != 0;
897}
898
899static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
900{
901 cptr->hdw->std_dirty = 0;
902}
903
904static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
905{
18103c57 906 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 907 pvr2_hdw_status_poll(hdw);
18103c57
MI		 908 *vp = hdw->tuner_signal_info.signal;
909 return 0;
910}
911
912static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
913{
914 int val = 0;
915 unsigned int subchan;
916 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 917 pvr2_hdw_status_poll(hdw);
18103c57
MI		 918 subchan = hdw->tuner_signal_info.rxsubchans;
919 if (subchan & V4L2_TUNER_SUB_MONO) {
920 val |= (1 << V4L2_TUNER_MODE_MONO);
921 }
922 if (subchan & V4L2_TUNER_SUB_STEREO) {
923 val |= (1 << V4L2_TUNER_MODE_STEREO);
924 }
925 if (subchan & V4L2_TUNER_SUB_LANG1) {
926 val |= (1 << V4L2_TUNER_MODE_LANG1);
927 }
928 if (subchan & V4L2_TUNER_SUB_LANG2) {
929 val |= (1 << V4L2_TUNER_MODE_LANG2);
930 }
931 *vp = val;
d855497e
MI		 932 return 0;
933}
934
d855497e
MI		 935
936static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
937{
938 struct pvr2_hdw *hdw = cptr->hdw;
939 if (v < 0) return -EINVAL;
940 if (v > hdw->std_enum_cnt) return -EINVAL;
941 hdw->std_enum_cur = v;
942 if (!v) return 0;
943 v--;
944 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
945 hdw->std_mask_cur = hdw->std_defs[v].id;
946 hdw->std_dirty = !0;
947 return 0;
948}
949
950
951static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
952{
953 *vp = cptr->hdw->std_enum_cur;
954 return 0;
955}
956
957
958static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
959{
960 return cptr->hdw->std_dirty != 0;
961}
962
963
964static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
965{
966 cptr->hdw->std_dirty = 0;
967}
968
969
970#define DEFINT(vmin,vmax) \
971 .type = pvr2_ctl_int, \
972 .def.type_int.min_value = vmin, \
973 .def.type_int.max_value = vmax
974
975#define DEFENUM(tab) \
976 .type = pvr2_ctl_enum, \
27c7b710 977 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 978 .def.type_enum.value_names = tab
979
33213963
MI		 980#define DEFBOOL \
981 .type = pvr2_ctl_bool
982
d855497e
MI		 983#define DEFMASK(msk,tab) \
984 .type = pvr2_ctl_bitmask, \
985 .def.type_bitmask.valid_bits = msk, \
986 .def.type_bitmask.bit_names = tab
987
988#define DEFREF(vname) \
989 .set_value = ctrl_set_##vname, \
990 .get_value = ctrl_get_##vname, \
991 .is_dirty = ctrl_isdirty_##vname, \
992 .clear_dirty = ctrl_cleardirty_##vname
993
994
995#define VCREATE_FUNCS(vname) \
996static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
997{*vp = cptr->hdw->vname##_val; return 0;} \
998static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
999{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1000static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1001{return cptr->hdw->vname##_dirty != 0;} \
1002static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1003{cptr->hdw->vname##_dirty = 0;}
1004
1005VCREATE_FUNCS(brightness)
1006VCREATE_FUNCS(contrast)
1007VCREATE_FUNCS(saturation)
1008VCREATE_FUNCS(hue)
1009VCREATE_FUNCS(volume)
1010VCREATE_FUNCS(balance)
1011VCREATE_FUNCS(bass)
1012VCREATE_FUNCS(treble)
1013VCREATE_FUNCS(mute)
e784bfb9 1014VCREATE_FUNCS(cropl)
1015VCREATE_FUNCS(cropt)
1016VCREATE_FUNCS(cropw)
1017VCREATE_FUNCS(croph)
c05c0462
MI		 1018VCREATE_FUNCS(audiomode)
1019VCREATE_FUNCS(res_hor)
1020VCREATE_FUNCS(res_ver)
d855497e 1021VCREATE_FUNCS(srate)
d855497e 1022
d855497e
MI		 1023/* Table definition of all controls which can be manipulated */
1024static const struct pvr2_ctl_info control_defs[] = {
1025 {
1026 .v4l_id = V4L2_CID_BRIGHTNESS,
1027 .desc = "Brightness",
1028 .name = "brightness",
1029 .default_value = 128,
1030 DEFREF(brightness),
1031 DEFINT(0,255),
1032 },{
1033 .v4l_id = V4L2_CID_CONTRAST,
1034 .desc = "Contrast",
1035 .name = "contrast",
1036 .default_value = 68,
1037 DEFREF(contrast),
1038 DEFINT(0,127),
1039 },{
1040 .v4l_id = V4L2_CID_SATURATION,
1041 .desc = "Saturation",
1042 .name = "saturation",
1043 .default_value = 64,
1044 DEFREF(saturation),
1045 DEFINT(0,127),
1046 },{
1047 .v4l_id = V4L2_CID_HUE,
1048 .desc = "Hue",
1049 .name = "hue",
1050 .default_value = 0,
1051 DEFREF(hue),
1052 DEFINT(-128,127),
1053 },{
1054 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1055 .desc = "Volume",
1056 .name = "volume",
139eecf9 1057 .default_value = 62000,
d855497e
MI		 1058 DEFREF(volume),
1059 DEFINT(0,65535),
1060 },{
1061 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1062 .desc = "Balance",
1063 .name = "balance",
1064 .default_value = 0,
1065 DEFREF(balance),
1066 DEFINT(-32768,32767),
1067 },{
1068 .v4l_id = V4L2_CID_AUDIO_BASS,
1069 .desc = "Bass",
1070 .name = "bass",
1071 .default_value = 0,
1072 DEFREF(bass),
1073 DEFINT(-32768,32767),
1074 },{
1075 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1076 .desc = "Treble",
1077 .name = "treble",
1078 .default_value = 0,
1079 DEFREF(treble),
1080 DEFINT(-32768,32767),
1081 },{
1082 .v4l_id = V4L2_CID_AUDIO_MUTE,
1083 .desc = "Mute",
1084 .name = "mute",
1085 .default_value = 0,
1086 DEFREF(mute),
33213963 1087 DEFBOOL,
e784bfb9 1088 }, {
432907f7 1089 .desc = "Capture crop left margin",
e784bfb9 1090 .name = "crop_left",
1091 .internal_id = PVR2_CID_CROPL,
1092 .default_value = 0,
1093 DEFREF(cropl),
1094 DEFINT(-129, 340),
1095 .get_min_value = ctrl_cropl_min_get,
1096 .get_max_value = ctrl_cropl_max_get,
432907f7 1097 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1098 }, {
432907f7 1099 .desc = "Capture crop top margin",
e784bfb9 1100 .name = "crop_top",
1101 .internal_id = PVR2_CID_CROPT,
1102 .default_value = 0,
1103 DEFREF(cropt),
1104 DEFINT(-35, 544),
1105 .get_min_value = ctrl_cropt_min_get,
1106 .get_max_value = ctrl_cropt_max_get,
432907f7 1107 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1108 }, {
432907f7 1109 .desc = "Capture crop width",
e784bfb9 1110 .name = "crop_width",
1111 .internal_id = PVR2_CID_CROPW,
1112 .default_value = 720,
1113 DEFREF(cropw),
432907f7
MI		 1114 .get_max_value = ctrl_cropw_max_get,
1115 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1116 }, {
432907f7 1117 .desc = "Capture crop height",
e784bfb9 1118 .name = "crop_height",
1119 .internal_id = PVR2_CID_CROPH,
1120 .default_value = 480,
1121 DEFREF(croph),
432907f7
MI		 1122 .get_max_value = ctrl_croph_max_get,
1123 .get_def_value = ctrl_get_cropcapdh,
1124 }, {
1125 .desc = "Capture capability pixel aspect numerator",
1126 .name = "cropcap_pixel_numerator",
1127 .internal_id = PVR2_CID_CROPCAPPAN,
1128 .get_value = ctrl_get_cropcappan,
1129 }, {
1130 .desc = "Capture capability pixel aspect denominator",
1131 .name = "cropcap_pixel_denominator",
1132 .internal_id = PVR2_CID_CROPCAPPAD,
1133 .get_value = ctrl_get_cropcappad,
1134 }, {
1135 .desc = "Capture capability bounds top",
1136 .name = "cropcap_bounds_top",
1137 .internal_id = PVR2_CID_CROPCAPBT,
1138 .get_value = ctrl_get_cropcapbt,
1139 }, {
1140 .desc = "Capture capability bounds left",
1141 .name = "cropcap_bounds_left",
1142 .internal_id = PVR2_CID_CROPCAPBL,
1143 .get_value = ctrl_get_cropcapbl,
1144 }, {
1145 .desc = "Capture capability bounds width",
1146 .name = "cropcap_bounds_width",
1147 .internal_id = PVR2_CID_CROPCAPBW,
1148 .get_value = ctrl_get_cropcapbw,
1149 }, {
1150 .desc = "Capture capability bounds height",
1151 .name = "cropcap_bounds_height",
1152 .internal_id = PVR2_CID_CROPCAPBH,
1153 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1154 },{
1155 .desc = "Video Source",
1156 .name = "input",
1157 .internal_id = PVR2_CID_INPUT,
1158 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1159 .check_value = ctrl_check_input,
c05c0462
MI		 1160 DEFREF(input),
1161 DEFENUM(control_values_input),
1162 },{
1163 .desc = "Audio Mode",
1164 .name = "audio_mode",
1165 .internal_id = PVR2_CID_AUDIOMODE,
1166 .default_value = V4L2_TUNER_MODE_STEREO,
1167 DEFREF(audiomode),
1168 DEFENUM(control_values_audiomode),
1169 },{
1170 .desc = "Horizontal capture resolution",
1171 .name = "resolution_hor",
1172 .internal_id = PVR2_CID_HRES,
1173 .default_value = 720,
1174 DEFREF(res_hor),
3ad9fc37 1175 DEFINT(19,720),
c05c0462
MI		 1176 },{
1177 .desc = "Vertical capture resolution",
1178 .name = "resolution_ver",
1179 .internal_id = PVR2_CID_VRES,
1180 .default_value = 480,
1181 DEFREF(res_ver),
3ad9fc37
MI		 1182 DEFINT(17,576),
1183 /* Hook in check for video standard and adjust maximum
1184 depending on the standard. */
1185 .get_max_value = ctrl_vres_max_get,
1186 .get_min_value = ctrl_vres_min_get,
d855497e 1187 },{
b30d2441 1188 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1189 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1190 .desc = "Audio Sampling Frequency",
d855497e 1191 .name = "srate",
d855497e
MI		 1192 DEFREF(srate),
1193 DEFENUM(control_values_srate),
d855497e
MI		 1194 },{
1195 .desc = "Tuner Frequency (Hz)",
1196 .name = "frequency",
1197 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1198 .default_value = 0,
d855497e
MI		 1199 .set_value = ctrl_freq_set,
1200 .get_value = ctrl_freq_get,
1201 .is_dirty = ctrl_freq_is_dirty,
1202 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1203 DEFINT(0,0),
25d8527a
PK		 1204 /* Hook in check for input value (tv/radio) and adjust
1205 max/min values accordingly */
1206 .get_max_value = ctrl_freq_max_get,
1207 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1208 },{
1209 .desc = "Channel",
1210 .name = "channel",
1211 .set_value = ctrl_channel_set,
1212 .get_value = ctrl_channel_get,
1213 DEFINT(0,FREQTABLE_SIZE),
1214 },{
1215 .desc = "Channel Program Frequency",
1216 .name = "freq_table_value",
1217 .set_value = ctrl_channelfreq_set,
1218 .get_value = ctrl_channelfreq_get,
644afdb9 1219 DEFINT(0,0),
1bde0289
MI		 1220 /* Hook in check for input value (tv/radio) and adjust
1221 max/min values accordingly */
1bde0289
MI		 1222 .get_max_value = ctrl_freq_max_get,
1223 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1224 },{
1225 .desc = "Channel Program ID",
1226 .name = "freq_table_channel",
1227 .set_value = ctrl_channelprog_set,
1228 .get_value = ctrl_channelprog_get,
1229 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1230 },{
1231 .desc = "Streaming Enabled",
1232 .name = "streaming_enabled",
1233 .get_value = ctrl_streamingenabled_get,
33213963 1234 DEFBOOL,
d855497e
MI		 1235 },{
1236 .desc = "USB Speed",
1237 .name = "usb_speed",
1238 .get_value = ctrl_hsm_get,
1239 DEFENUM(control_values_hsm),
681c7399
MI		 1240 },{
1241 .desc = "Master State",
1242 .name = "master_state",
1243 .get_value = ctrl_masterstate_get,
1244 DEFENUM(pvr2_state_names),
d855497e
MI		 1245 },{
1246 .desc = "Signal Present",
1247 .name = "signal_present",
1248 .get_value = ctrl_signal_get,
18103c57
MI		 1249 DEFINT(0,65535),
1250 },{
1251 .desc = "Audio Modes Present",
1252 .name = "audio_modes_present",
1253 .get_value = ctrl_audio_modes_present_get,
1254 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1255 v4l. Nothing outside of this module cares about this,
1256 but I reuse it in order to also reuse the
1257 control_values_audiomode string table. */
1258 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1259 (1 << V4L2_TUNER_MODE_STEREO)|
1260 (1 << V4L2_TUNER_MODE_LANG1)|
1261 (1 << V4L2_TUNER_MODE_LANG2)),
1262 control_values_audiomode),
d855497e
MI		 1263 },{
1264 .desc = "Video Standards Available Mask",
1265 .name = "video_standard_mask_available",
1266 .internal_id = PVR2_CID_STDAVAIL,
1267 .skip_init = !0,
1268 .get_value = ctrl_stdavail_get,
1269 .set_value = ctrl_stdavail_set,
1270 .val_to_sym = ctrl_std_val_to_sym,
1271 .sym_to_val = ctrl_std_sym_to_val,
1272 .type = pvr2_ctl_bitmask,
1273 },{
1274 .desc = "Video Standards In Use Mask",
1275 .name = "video_standard_mask_active",
1276 .internal_id = PVR2_CID_STDCUR,
1277 .skip_init = !0,
1278 .get_value = ctrl_stdcur_get,
1279 .set_value = ctrl_stdcur_set,
1280 .is_dirty = ctrl_stdcur_is_dirty,
1281 .clear_dirty = ctrl_stdcur_clear_dirty,
1282 .val_to_sym = ctrl_std_val_to_sym,
1283 .sym_to_val = ctrl_std_sym_to_val,
1284 .type = pvr2_ctl_bitmask,
d855497e
MI		 1285 },{
1286 .desc = "Video Standard Name",
1287 .name = "video_standard",
1288 .internal_id = PVR2_CID_STDENUM,
1289 .skip_init = !0,
1290 .get_value = ctrl_stdenumcur_get,
1291 .set_value = ctrl_stdenumcur_set,
1292 .is_dirty = ctrl_stdenumcur_is_dirty,
1293 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1294 .type = pvr2_ctl_enum,
1295 }
1296};
1297
eca8ebfc 1298#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1299
1300
1301const char *pvr2_config_get_name(enum pvr2_config cfg)
1302{
1303 switch (cfg) {
1304 case pvr2_config_empty: return "empty";
1305 case pvr2_config_mpeg: return "mpeg";
1306 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1307 case pvr2_config_pcm: return "pcm";
1308 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1309 }
1310 return "<unknown>";
1311}
1312
1313
1314struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1315{
1316 return hdw->usb_dev;
1317}
1318
1319
1320unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1321{
1322 return hdw->serial_number;
1323}
1324
31a18547
MI		 1325
1326const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1327{
1328 return hdw->bus_info;
1329}
1330
1331
13a88797
MI		 1332const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1333{
1334 return hdw->identifier;
1335}
1336
1337
1bde0289
MI		 1338unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1339{
1340 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1341}
1342
1343/* Set the currently tuned frequency and account for all possible
1344 driver-core side effects of this action. */
f55a8712 1345static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1346{
7c74e57e 1347 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1348 if (hdw->freqSelector) {
1349 /* Swing over to radio frequency selection */
1350 hdw->freqSelector = 0;
1351 hdw->freqDirty = !0;
1352 }
1bde0289
MI		 1353 if (hdw->freqValRadio != val) {
1354 hdw->freqValRadio = val;
1355 hdw->freqSlotRadio = 0;
7c74e57e 1356 hdw->freqDirty = !0;
1bde0289 1357 }
7c74e57e 1358 } else {
1bde0289
MI		 1359 if (!(hdw->freqSelector)) {
1360 /* Swing over to television frequency selection */
1361 hdw->freqSelector = 1;
1362 hdw->freqDirty = !0;
1363 }
1bde0289
MI		 1364 if (hdw->freqValTelevision != val) {
1365 hdw->freqValTelevision = val;
1366 hdw->freqSlotTelevision = 0;
7c74e57e 1367 hdw->freqDirty = !0;
1bde0289 1368 }
1bde0289
MI		 1369 }
1370}
1371
d855497e
MI		 1372int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1373{
1374 return hdw->unit_number;
1375}
1376
1377
1378/* Attempt to locate one of the given set of files. Messages are logged
1379 appropriate to what has been found. The return value will be 0 or
1380 greater on success (it will be the index of the file name found) and
1381 fw_entry will be filled in. Otherwise a negative error is returned on
1382 failure. If the return value is -ENOENT then no viable firmware file
1383 could be located. */
1384static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1385 const struct firmware **fw_entry,
1386 const char *fwtypename,
1387 unsigned int fwcount,
1388 const char *fwnames[])
1389{
1390 unsigned int idx;
1391 int ret = -EINVAL;
1392 for (idx = 0; idx < fwcount; idx++) {
1393 ret = request_firmware(fw_entry,
1394 fwnames[idx],
1395 &hdw->usb_dev->dev);
1396 if (!ret) {
1397 trace_firmware("Located %s firmware: %s;"
1398 " uploading...",
1399 fwtypename,
1400 fwnames[idx]);
1401 return idx;
1402 }
1403 if (ret == -ENOENT) continue;
1404 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1405 "request_firmware fatal error with code=%d",ret);
1406 return ret;
1407 }
1408 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1409 "***WARNING***"
1410 " Device %s firmware"
1411 " seems to be missing.",
1412 fwtypename);
1413 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1414 "Did you install the pvrusb2 firmware files"
1415 " in their proper location?");
1416 if (fwcount == 1) {
1417 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1418 "request_firmware unable to locate %s file %s",
1419 fwtypename,fwnames[0]);
1420 } else {
1421 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1422 "request_firmware unable to locate"
1423 " one of the following %s files:",
1424 fwtypename);
1425 for (idx = 0; idx < fwcount; idx++) {
1426 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1427 "request_firmware: Failed to find %s",
1428 fwnames[idx]);
1429 }
1430 }
1431 return ret;
1432}
1433
1434
1435/*
1436 * pvr2_upload_firmware1().
1437 *
1438 * Send the 8051 firmware to the device. After the upload, arrange for
1439 * device to re-enumerate.
1440 *
1441 * NOTE : the pointer to the firmware data given by request_firmware()
1442 * is not suitable for an usb transaction.
1443 *
1444 */
07e337ee 1445static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1446{
a0fd1cb1 1447 const struct firmware *fw_entry = NULL;
d855497e
MI		 1448 void *fw_ptr;
1449 unsigned int pipe;
9081d901 1450 unsigned int fwsize;
d855497e
MI		 1451 int ret;
1452 u16 address;
1d643a37 1453
989eb154 1454 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1455 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1456 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1457 "Connected device type defines"
1458 " no firmware to upload; ignoring firmware");
1459 return -ENOTTY;
1d643a37
MI		 1460 }
1461
d855497e
MI		 1462 hdw->fw1_state = FW1_STATE_FAILED; // default result
1463
1464 trace_firmware("pvr2_upload_firmware1");
1465
1466 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1467 hdw->hdw_desc->fx2_firmware.cnt,
1468 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1469 if (ret < 0) {
1470 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1471 return ret;
1472 }
1473
d855497e
MI		 1474 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1475
1476 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
9081d901 1477 fwsize = fw_entry->size;
d855497e 1478
9081d901
MI		 1479 if ((fwsize != 0x2000) &&
1480 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
c21c2db4
MI		 1481 if (hdw->hdw_desc->flag_fx2_16kb) {
1482 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1483 "Wrong fx2 firmware size"
1484 " (expected 8192 or 16384, got %u)",
9081d901 1485 fwsize);
c21c2db4
MI		 1486 } else {
1487 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1488 "Wrong fx2 firmware size"
1489 " (expected 8192, got %u)",
9081d901 1490 fwsize);
c21c2db4 1491 }
d855497e
MI		 1492 release_firmware(fw_entry);
1493 return -ENOMEM;
1494 }
1495
1496 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1497 if (fw_ptr == NULL){
1498 release_firmware(fw_entry);
1499 return -ENOMEM;
1500 }
1501
1502 /* We have to hold the CPU during firmware upload. */
1503 pvr2_hdw_cpureset_assert(hdw,1);
1504
1505 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1506 chunk. */
1507
1508 ret = 0;
9081d901 1509 for (address = 0; address < fwsize; address += 0x800) {
d855497e
MI		 1510 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1511 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1512 0, fw_ptr, 0x800, HZ);
1513 }
1514
1515 trace_firmware("Upload done, releasing device's CPU");
1516
1517 /* Now release the CPU. It will disconnect and reconnect later. */
1518 pvr2_hdw_cpureset_assert(hdw,0);
1519
1520 kfree(fw_ptr);
1521 release_firmware(fw_entry);
1522
1523 trace_firmware("Upload done (%d bytes sent)",ret);
1524
75727460
GF		 1525 /* We should have written fwsize bytes */
1526 if (ret == fwsize) {
d855497e
MI		 1527 hdw->fw1_state = FW1_STATE_RELOAD;
1528 return 0;
1529 }
1530
1531 return -EIO;
1532}
1533
1534
1535/*
1536 * pvr2_upload_firmware2()
1537 *
1538 * This uploads encoder firmware on endpoint 2.
1539 *
1540 */
1541
1542int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1543{
a0fd1cb1 1544 const struct firmware *fw_entry = NULL;
d855497e 1545 void *fw_ptr;
90060d32 1546 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1547 int actual_length;
1548 int ret = 0;
1549 int fwidx;
1550 static const char *fw_files[] = {
1551 CX2341X_FIRM_ENC_FILENAME,
1552 };
1553
989eb154 1554 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1555 return 0;
1556 }
1557
d855497e
MI		 1558 trace_firmware("pvr2_upload_firmware2");
1559
1560 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1561 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1562 if (ret < 0) return ret;
1563 fwidx = ret;
1564 ret = 0;
b30d2441
MI		 1565 /* Since we're about to completely reinitialize the encoder,
1566 invalidate our cached copy of its configuration state. Next
1567 time we configure the encoder, then we'll fully configure it. */
1568 hdw->enc_cur_valid = 0;
d855497e 1569
d913d630
MI		 1570 /* Encoder is about to be reset so note that as far as we're
1571 concerned now, the encoder has never been run. */
1572 del_timer_sync(&hdw->encoder_run_timer);
1573 if (hdw->state_encoder_runok) {
1574 hdw->state_encoder_runok = 0;
1575 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1576 }
1577
d855497e
MI		 1578 /* First prepare firmware loading */
1579 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1580 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1581 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1582 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1583 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1584 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1585 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1586 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1587 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1588 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1589 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1590 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1591 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1592 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1593 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1594 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1595 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1596 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1597
1598 if (ret) {
1599 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1600 "firmware2 upload prep failed, ret=%d",ret);
1601 release_firmware(fw_entry);
21684ba9 1602 goto done;
d855497e
MI		 1603 }
1604
1605 /* Now send firmware */
1606
1607 fw_len = fw_entry->size;
1608
90060d32 1609 if (fw_len % sizeof(u32)) {
d855497e
MI		 1610 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1611 "size of %s firmware"
48dc30a1 1612 " must be a multiple of %zu bytes",
90060d32 1613 fw_files[fwidx],sizeof(u32));
d855497e 1614 release_firmware(fw_entry);
21684ba9
MI		 1615 ret = -EINVAL;
1616 goto done;
d855497e
MI		 1617 }
1618
1619 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1620 if (fw_ptr == NULL){
1621 release_firmware(fw_entry);
1622 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1623 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1624 ret = -ENOMEM;
1625 goto done;
d855497e
MI		 1626 }
1627
1628 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1629
90060d32
MI		 1630 fw_done = 0;
1631 for (fw_done = 0; fw_done < fw_len;) {
1632 bcnt = fw_len - fw_done;
1633 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1634 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1635 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1636 /* Some background info: The data being swapped here is a
1637 firmware image destined for the mpeg encoder chip that
1638 lives at the other end of a USB endpoint. The encoder
1639 chip always talks in 32 bit chunks and its storage is
1640 organized into 32 bit words. However from the file
1641 system to the encoder chip everything is purely a byte
1642 stream. The firmware file's contents are always 32 bit
1643 swapped from what the encoder expects. Thus the need
1644 always exists to swap the bytes regardless of the endian
1645 type of the host processor and therefore swab32() makes
1646 the most sense. */
90060d32 1647 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1648 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1649
1650 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1651 &actual_length, HZ);
90060d32
MI		 1652 ret |= (actual_length != bcnt);
1653 if (ret) break;
1654 fw_done += bcnt;
d855497e
MI		 1655 }
1656
1657 trace_firmware("upload of %s : %i / %i ",
1658 fw_files[fwidx],fw_done,fw_len);
1659
1660 kfree(fw_ptr);
1661 release_firmware(fw_entry);
1662
1663 if (ret) {
1664 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1665 "firmware2 upload transfer failure");
21684ba9 1666 goto done;
d855497e
MI		 1667 }
1668
1669 /* Finish upload */
1670
1671 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1672 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1673 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1674
1675 if (ret) {
1676 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1677 "firmware2 upload post-proc failure");
d855497e 1678 }
21684ba9
MI		 1679
1680 done:
1df59f0b
MI		 1681 if (hdw->hdw_desc->signal_routing_scheme ==
1682 PVR2_ROUTING_SCHEME_GOTVIEW) {
1683 /* Ensure that GPIO 11 is set to output for GOTVIEW
1684 hardware. */
1685 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1686 }
d855497e
MI		 1687 return ret;
1688}
1689
1690
681c7399
MI		 1691static const char *pvr2_get_state_name(unsigned int st)
1692{
1693 if (st < ARRAY_SIZE(pvr2_state_names)) {
1694 return pvr2_state_names[st];
d855497e 1695 }
681c7399 1696 return "???";
d855497e
MI		 1697}
1698
681c7399 1699static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1700{
af78e16b
MI		 1701 /* Even though we really only care about the video decoder chip at
1702 this point, we'll broadcast stream on/off to all sub-devices
1703 anyway, just in case somebody else wants to hear the
1704 command... */
e260508d
MI		 1705 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1706 (enablefl ? "on" : "off"));
af78e16b
MI		 1707 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1708 if (hdw->decoder_client_id) {
1709 /* We get here if the encoder has been noticed. Otherwise
1710 we'll issue a warning to the user (which should
1711 normally never happen). */
1712 return 0;
1713 }
1714 if (!hdw->flag_decoder_missed) {
1715 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1716 "WARNING: No decoder present");
1717 hdw->flag_decoder_missed = !0;
1718 trace_stbit("flag_decoder_missed",
1719 hdw->flag_decoder_missed);
1720 }
1721 return -EIO;
d855497e
MI		 1722}
1723
1724
681c7399 1725int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1726{
681c7399 1727 return hdw->master_state;
d855497e
MI		 1728}
1729
1730
681c7399 1731static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1732{
681c7399
MI		 1733 if (!hdw->flag_tripped) return 0;
1734 hdw->flag_tripped = 0;
1735 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1736 "Clearing driver error statuss");
1737 return !0;
d855497e
MI		 1738}
1739
1740
681c7399 1741int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1742{
681c7399 1743 int fl;
d855497e 1744 LOCK_TAKE(hdw->big_lock); do {
681c7399 1745 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1746 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1747 if (fl) pvr2_hdw_state_sched(hdw);
1748 return 0;
d855497e
MI		 1749}
1750
1751
d855497e
MI		 1752
1753
1754int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1755{
681c7399 1756 return hdw->state_pipeline_req != 0;
d855497e
MI		 1757}
1758
1759
1760int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1761{
681c7399 1762 int ret,st;
d855497e 1763 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1764 pvr2_hdw_untrip_unlocked(hdw);
1765 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1766 hdw->state_pipeline_req = enable_flag != 0;
1767 pvr2_trace(PVR2_TRACE_START_STOP,
1768 "/*--TRACE_STREAM--*/ %s",
1769 enable_flag ? "enable" : "disable");
1770 }
1771 pvr2_hdw_state_sched(hdw);
d855497e 1772 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1773 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1774 if (enable_flag) {
1775 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1776 if (st != PVR2_STATE_READY) return -EIO;
1777 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1778 }
1779 }
d855497e
MI		 1780 return 0;
1781}
1782
1783
1784int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1785{
681c7399 1786 int fl;
d855497e 1787 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1788 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1789 hdw->desired_stream_type = config;
1790 hdw->state_pipeline_config = 0;
1791 trace_stbit("state_pipeline_config",
1792 hdw->state_pipeline_config);
1793 pvr2_hdw_state_sched(hdw);
1794 }
d855497e 1795 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1796 if (fl) return 0;
1797 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1798}
1799
1800
1801static int get_default_tuner_type(struct pvr2_hdw *hdw)
1802{
1803 int unit_number = hdw->unit_number;
1804 int tp = -1;
1805 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1806 tp = tuner[unit_number];
1807 }
1808 if (tp < 0) return -EINVAL;
1809 hdw->tuner_type = tp;
aaf7884d 1810 hdw->tuner_updated = !0;
d855497e
MI		 1811 return 0;
1812}
1813
1814
1815static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1816{
1817 int unit_number = hdw->unit_number;
1818 int tp = 0;
1819 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1820 tp = video_std[unit_number];
6a540254 1821 if (tp) return tp;
d855497e 1822 }
6a540254 1823 return 0;
d855497e
MI		 1824}
1825
1826
1827static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1828{
1829 int unit_number = hdw->unit_number;
1830 int tp = 0;
1831 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1832 tp = tolerance[unit_number];
1833 }
1834 return tp;
1835}
1836
1837
1838static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1839{
1840 /* Try a harmless request to fetch the eeprom's address over
1841 endpoint 1. See what happens. Only the full FX2 image can
1842 respond to this. If this probe fails then likely the FX2
1843 firmware needs be loaded. */
1844 int result;
1845 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1846 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1847 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1848 hdw->cmd_buffer,1,
1849 hdw->cmd_buffer,1);
1850 if (result < 0) break;
1851 } while(0); LOCK_GIVE(hdw->ctl_lock);
1852 if (result) {
1853 pvr2_trace(PVR2_TRACE_INIT,
1854 "Probe of device endpoint 1 result status %d",
1855 result);
1856 } else {
1857 pvr2_trace(PVR2_TRACE_INIT,
1858 "Probe of device endpoint 1 succeeded");
1859 }
1860 return result == 0;
1861}
1862
9f66d4ea
MI		 1863struct pvr2_std_hack {
1864 v4l2_std_id pat; /* Pattern to match */
1865 v4l2_std_id msk; /* Which bits we care about */
1866 v4l2_std_id std; /* What additional standards or default to set */
1867};
1868
1869/* This data structure labels specific combinations of standards from
1870 tveeprom that we'll try to recognize. If we recognize one, then assume
1871 a specified default standard to use. This is here because tveeprom only
1872 tells us about available standards not the intended default standard (if
1873 any) for the device in question. We guess the default based on what has
1874 been reported as available. Note that this is only for guessing a
1875 default - which can always be overridden explicitly - and if the user
1876 has otherwise named a default then that default will always be used in
1877 place of this table. */
ebff0330 1878static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1879 { /* PAL(B/G) */
1880 .pat = V4L2_STD_B|V4L2_STD_GH,
1881 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1882 },
1883 { /* NTSC(M) */
1884 .pat = V4L2_STD_MN,
1885 .std = V4L2_STD_NTSC_M,
1886 },
1887 { /* PAL(I) */
1888 .pat = V4L2_STD_PAL_I,
1889 .std = V4L2_STD_PAL_I,
1890 },
1891 { /* SECAM(L/L') */
1892 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1893 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1894 },
1895 { /* PAL(D/D1/K) */
1896 .pat = V4L2_STD_DK,
ea2562d9 1897 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1898 },
1899};
1900
d855497e
MI		 1901static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1902{
1903 char buf[40];
1904 unsigned int bcnt;
3d290bdb 1905 v4l2_std_id std1,std2,std3;
d855497e
MI		 1906
1907 std1 = get_default_standard(hdw);
3d290bdb 1908 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1909
1910 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1911 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1912 "Supported video standard(s) reported available"
1913 " in hardware: %.*s",
d855497e
MI		 1914 bcnt,buf);
1915
1916 hdw->std_mask_avail = hdw->std_mask_eeprom;
1917
3d290bdb 1918 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1919 if (std2) {
1920 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1921 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1922 "Expanding supported video standards"
1923 " to include: %.*s",
1924 bcnt,buf);
1925 hdw->std_mask_avail |= std2;
1926 }
1927
1928 pvr2_hdw_internal_set_std_avail(hdw);
1929
1930 if (std1) {
1931 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1932 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1933 "Initial video standard forced to %.*s",
1934 bcnt,buf);
1935 hdw->std_mask_cur = std1;
1936 hdw->std_dirty = !0;
1937 pvr2_hdw_internal_find_stdenum(hdw);
1938 return;
1939 }
3d290bdb
MI		 1940 if (std3) {
1941 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1942 pvr2_trace(PVR2_TRACE_STD,
1943 "Initial video standard"
1944 " (determined by device type): %.*s",bcnt,buf);
1945 hdw->std_mask_cur = std3;
1946 hdw->std_dirty = !0;
1947 pvr2_hdw_internal_find_stdenum(hdw);
1948 return;
1949 }
d855497e 1950
9f66d4ea
MI		 1951 {
1952 unsigned int idx;
1953 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1954 if (std_eeprom_maps[idx].msk ?
1955 ((std_eeprom_maps[idx].pat ^
1956 hdw->std_mask_eeprom) &
1957 std_eeprom_maps[idx].msk) :
1958 (std_eeprom_maps[idx].pat !=
1959 hdw->std_mask_eeprom)) continue;
1960 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1961 std_eeprom_maps[idx].std);
56585386 1962 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1963 "Initial video standard guessed as %.*s",
1964 bcnt,buf);
1965 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1966 hdw->std_dirty = !0;
1967 pvr2_hdw_internal_find_stdenum(hdw);
1968 return;
1969 }
1970 }
1971
d855497e
MI		 1972 if (hdw->std_enum_cnt > 1) {
1973 // Autoselect the first listed standard
1974 hdw->std_enum_cur = 1;
1975 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1976 hdw->std_dirty = !0;
56585386 1977 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1978 "Initial video standard auto-selected to %s",
1979 hdw->std_defs[hdw->std_enum_cur-1].name);
1980 return;
1981 }
1982
0885ba1d 1983 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1984 "Unable to select a viable initial video standard");
1985}
1986
1987
e9c64a78
MI		 1988static unsigned int pvr2_copy_i2c_addr_list(
1989 unsigned short *dst, const unsigned char *src,
1990 unsigned int dst_max)
1991{
3ab8d295 1992 unsigned int cnt = 0;
e9c64a78
MI		 1993 if (!src) return 0;
1994 while (src[cnt] && (cnt + 1) < dst_max) {
1995 dst[cnt] = src[cnt];
1996 cnt++;
1997 }
1998 dst[cnt] = I2C_CLIENT_END;
1999 return cnt;
2000}
2001
2002
e17d787c
MI		 2003static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
2004{
2005 /*
2006 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
2007 for cx25840 causes that module to correctly set up its video
2008 scaling. This is really a problem in the cx25840 module itself,
2009 but we work around it here. The problem has not been seen in
2010 ivtv because there VBI is supported and set up. We don't do VBI
2011 here (at least not yet) and thus we never attempted to even set
2012 it up.
2013 */
2014 struct v4l2_format fmt;
2015 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2016 /* We're not using a cx25840 so don't enable the hack */
2017 return;
2018 }
2019
2020 pvr2_trace(PVR2_TRACE_INIT,
2021 "Module ID %u:"
2022 " Executing cx25840 VBI hack",
2023 hdw->decoder_client_id);
2024 memset(&fmt, 0, sizeof(fmt));
2025 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2026 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
2027 video, s_fmt, &fmt);
2028}
2029
2030
1ab5e74f
MI		 2031static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2032 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 2033{
2034 const char *fname;
2035 unsigned char mid;
2036 struct v4l2_subdev *sd;
2037 unsigned int i2ccnt;
2038 const unsigned char *p;
2039 /* Arbitrary count - max # i2c addresses we will probe */
2040 unsigned short i2caddr[25];
2041
2042 mid = cd->module_id;
2043 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2044 if (!fname) {
2045 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2046 "Module ID %u for device %s has no name?"
2047 " The driver might have a configuration problem.",
e9c64a78
MI		 2048 mid,
2049 hdw->hdw_desc->description);
1ab5e74f 2050 return -EINVAL;
e9c64a78 2051 }
bd14d4f8
MI		 2052 pvr2_trace(PVR2_TRACE_INIT,
2053 "Module ID %u (%s) for device %s being loaded...",
2054 mid, fname,
2055 hdw->hdw_desc->description);
e9c64a78
MI		 2056
2057 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2058 ARRAY_SIZE(i2caddr));
2059 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2060 module_i2c_addresses[mid] : NULL) != NULL)) {
2061 /* Second chance: Try default i2c address list */
2062 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2063 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2064 if (i2ccnt) {
2065 pvr2_trace(PVR2_TRACE_INIT,
2066 "Module ID %u:"
2067 " Using default i2c address list",
2068 mid);
2069 }
e9c64a78
MI		 2070 }
2071
2072 if (!i2ccnt) {
2073 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 2074 "Module ID %u (%s) for device %s:"
27108147
MI		 2075 " No i2c addresses."
2076 " The driver might have a configuration problem.",
1ab5e74f
MI		 2077 mid, fname, hdw->hdw_desc->description);
2078 return -EINVAL;
e9c64a78
MI		 2079 }
2080
53dacb15
HV		 2081 /* Note how the 2nd and 3rd arguments are the same for
2082 * v4l2_i2c_new_subdev(). Why?
e9c64a78
MI		 2083 * Well the 2nd argument is the module name to load, while the 3rd
2084 * argument is documented in the framework as being the "chipid" -
2085 * and every other place where I can find examples of this, the
2086 * "chipid" appears to just be the module name again. So here we
2087 * just do the same thing. */
2088 if (i2ccnt == 1) {
bd14d4f8
MI		 2089 pvr2_trace(PVR2_TRACE_INIT,
2090 "Module ID %u:"
2091 " Setting up with specified i2c address 0x%x",
2092 mid, i2caddr[0]);
e6574f2f 2093 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
e9c64a78 2094 fname, fname,
53dacb15 2095 i2caddr[0], NULL);
e9c64a78 2096 } else {
bd14d4f8
MI		 2097 pvr2_trace(PVR2_TRACE_INIT,
2098 "Module ID %u:"
2099 " Setting up with address probe list",
2100 mid);
53dacb15 2101 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
e9c64a78 2102 fname, fname,
53dacb15 2103 0, i2caddr);
e9c64a78
MI		 2104 }
2105
446dfdc6
MI		 2106 if (!sd) {
2107 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2108 "Module ID %u (%s) for device %s failed to load."
2109 " Possible missing sub-device kernel module or"
2110 " initialization failure within module.",
1ab5e74f
MI		 2111 mid, fname, hdw->hdw_desc->description);
2112 return -EIO;
446dfdc6
MI		 2113 }
2114
2115 /* Tag this sub-device instance with the module ID we know about.
2116 In other places we'll use that tag to determine if the instance
2117 requires special handling. */
2118 sd->grp_id = mid;
2119
bd14d4f8 2120 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2121
e9c64a78 2122
00e5f736
MI		 2123 /* client-specific setup... */
2124 switch (mid) {
2125 case PVR2_CLIENT_ID_CX25840:
00e5f736
MI		 2126 case PVR2_CLIENT_ID_SAA7115:
2127 hdw->decoder_client_id = mid;
2128 break;
2129 default: break;
2130 }
1ab5e74f
MI		 2131
2132 return 0;
e9c64a78
MI		 2133}
2134
2135
2136static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2137{
2138 unsigned int idx;
2139 const struct pvr2_string_table *cm;
2140 const struct pvr2_device_client_table *ct;
1ab5e74f 2141 int okFl = !0;
e9c64a78
MI		 2142
2143 cm = &hdw->hdw_desc->client_modules;
2144 for (idx = 0; idx < cm->cnt; idx++) {
2145 request_module(cm->lst[idx]);
2146 }
2147
2148 ct = &hdw->hdw_desc->client_table;
2149 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2150 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2151 }
27108147
MI		 2152 if (!okFl) {
2153 hdw->flag_modulefail = !0;
2154 pvr2_hdw_render_useless(hdw);
2155 }
e9c64a78
MI		 2156}
2157
2158
d855497e
MI		 2159static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2160{
2161 int ret;
2162 unsigned int idx;
2163 struct pvr2_ctrl *cptr;
2164 int reloadFl = 0;
989eb154 2165 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2166 if (!reloadFl) {
2167 reloadFl =
2168 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2169 == 0);
2170 if (reloadFl) {
2171 pvr2_trace(PVR2_TRACE_INIT,
2172 "USB endpoint config looks strange"
2173 "; possibly firmware needs to be"
2174 " loaded");
2175 }
d855497e 2176 }
1d643a37
MI		 2177 if (!reloadFl) {
2178 reloadFl = !pvr2_hdw_check_firmware(hdw);
2179 if (reloadFl) {
2180 pvr2_trace(PVR2_TRACE_INIT,
2181 "Check for FX2 firmware failed"
2182 "; possibly firmware needs to be"
2183 " loaded");
2184 }
d855497e 2185 }
1d643a37
MI		 2186 if (reloadFl) {
2187 if (pvr2_upload_firmware1(hdw) != 0) {
2188 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2189 "Failure uploading firmware1");
2190 }
2191 return;
d855497e 2192 }
d855497e
MI		 2193 }
2194 hdw->fw1_state = FW1_STATE_OK;
2195
d855497e
MI		 2196 if (!pvr2_hdw_dev_ok(hdw)) return;
2197
27764726
MI		 2198 hdw->force_dirty = !0;
2199
989eb154 2200 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2201 pvr2_hdw_cmd_powerup(hdw);
2202 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2203 }
2204
31335b13 2205 /* Take the IR chip out of reset, if appropriate */
27eab384 2206 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
31335b13
MI		 2207 pvr2_issue_simple_cmd(hdw,
2208 FX2CMD_HCW_ZILOG_RESET |
2209 (1 << 8) |
2210 ((0) << 16));
2211 }
2212
d855497e
MI		 2213 // This step MUST happen after the earlier powerup step.
2214 pvr2_i2c_core_init(hdw);
2215 if (!pvr2_hdw_dev_ok(hdw)) return;
2216
e9c64a78 2217 pvr2_hdw_load_modules(hdw);
1ab5e74f 2218 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2219
cc26b076 2220 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
5c6cb4e2 2221
c05c0462 2222 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2223 cptr = hdw->controls + idx;
2224 if (cptr->info->skip_init) continue;
2225 if (!cptr->info->set_value) continue;
2226 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2227 }
2228
e17d787c
MI		 2229 pvr2_hdw_cx25840_vbi_hack(hdw);
2230
1bde0289
MI		 2231 /* Set up special default values for the television and radio
2232 frequencies here. It's not really important what these defaults
2233 are, but I set them to something usable in the Chicago area just
2234 to make driver testing a little easier. */
2235
5a4f5da6
MK		 2236 hdw->freqValTelevision = default_tv_freq;
2237 hdw->freqValRadio = default_radio_freq;
1bde0289 2238
d855497e
MI		 2239 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2240 // thread-safe against the normal pvr2_send_request() mechanism.
2241 // (We should make it thread safe).
2242
aaf7884d
MI		 2243 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2244 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2245 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2246 if (ret < 0) {
2247 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2248 "Unable to determine location of eeprom,"
2249 " skipping");
2250 } else {
2251 hdw->eeprom_addr = ret;
2252 pvr2_eeprom_analyze(hdw);
2253 if (!pvr2_hdw_dev_ok(hdw)) return;
2254 }
2255 } else {
2256 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2257 hdw->tuner_updated = !0;
2258 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2259 }
2260
13a88797
MI		 2261 if (hdw->serial_number) {
2262 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2263 "sn-%lu", hdw->serial_number);
2264 } else if (hdw->unit_number >= 0) {
2265 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2266 "unit-%c",
2267 hdw->unit_number + 'a');
2268 } else {
2269 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2270 "unit-??");
2271 }
2272 hdw->identifier[idx] = 0;
2273
d855497e
MI		 2274 pvr2_hdw_setup_std(hdw);
2275
2276 if (!get_default_tuner_type(hdw)) {
2277 pvr2_trace(PVR2_TRACE_INIT,
2278 "pvr2_hdw_setup: Tuner type overridden to %d",
2279 hdw->tuner_type);
2280 }
2281
d855497e
MI		 2282
2283 if (!pvr2_hdw_dev_ok(hdw)) return;
2284
1df59f0b
MI		 2285 if (hdw->hdw_desc->signal_routing_scheme ==
2286 PVR2_ROUTING_SCHEME_GOTVIEW) {
2287 /* Ensure that GPIO 11 is set to output for GOTVIEW
2288 hardware. */
2289 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2290 }
2291
681c7399 2292 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2293
2294 hdw->vid_stream = pvr2_stream_create();
2295 if (!pvr2_hdw_dev_ok(hdw)) return;
2296 pvr2_trace(PVR2_TRACE_INIT,
2297 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2298 if (hdw->vid_stream) {
2299 idx = get_default_error_tolerance(hdw);
2300 if (idx) {
2301 pvr2_trace(PVR2_TRACE_INIT,
2302 "pvr2_hdw_setup: video stream %p"
2303 " setting tolerance %u",
2304 hdw->vid_stream,idx);
2305 }
2306 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2307 PVR2_VID_ENDPOINT,idx);
2308 }
2309
2310 if (!pvr2_hdw_dev_ok(hdw)) return;
2311
d855497e 2312 hdw->flag_init_ok = !0;
681c7399
MI		 2313
2314 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2315}
2316
2317
681c7399
MI		 2318/* Set up the structure and attempt to put the device into a usable state.
2319 This can be a time-consuming operation, which is why it is not done
2320 internally as part of the create() step. */
2321static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2322{
2323 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2324 do {
d855497e
MI		 2325 pvr2_hdw_setup_low(hdw);
2326 pvr2_trace(PVR2_TRACE_INIT,
2327 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2328 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2329 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2330 if (hdw->flag_init_ok) {
d855497e
MI		 2331 pvr2_trace(
2332 PVR2_TRACE_INFO,
2333 "Device initialization"
2334 " completed successfully.");
2335 break;
2336 }
2337 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2338 pvr2_trace(
2339 PVR2_TRACE_INFO,
2340 "Device microcontroller firmware"
2341 " (re)loaded; it should now reset"
2342 " and reconnect.");
2343 break;
2344 }
2345 pvr2_trace(
2346 PVR2_TRACE_ERROR_LEGS,
2347 "Device initialization was not successful.");
2348 if (hdw->fw1_state == FW1_STATE_MISSING) {
2349 pvr2_trace(
2350 PVR2_TRACE_ERROR_LEGS,
2351 "Giving up since device"
2352 " microcontroller firmware"
2353 " appears to be missing.");
2354 break;
2355 }
2356 }
27108147
MI		 2357 if (hdw->flag_modulefail) {
2358 pvr2_trace(
2359 PVR2_TRACE_ERROR_LEGS,
2360 "***WARNING*** pvrusb2 driver initialization"
2361 " failed due to the failure of one or more"
2362 " sub-device kernel modules.");
2363 pvr2_trace(
2364 PVR2_TRACE_ERROR_LEGS,
2365 "You need to resolve the failing condition"
2366 " before this driver can function. There"
2367 " should be some earlier messages giving more"
2368 " information about the problem.");
515ebf79 2369 break;
27108147 2370 }
d855497e
MI		 2371 if (procreload) {
2372 pvr2_trace(
2373 PVR2_TRACE_ERROR_LEGS,
2374 "Attempting pvrusb2 recovery by reloading"
2375 " primary firmware.");
2376 pvr2_trace(
2377 PVR2_TRACE_ERROR_LEGS,
2378 "If this works, device should disconnect"
2379 " and reconnect in a sane state.");
2380 hdw->fw1_state = FW1_STATE_UNKNOWN;
2381 pvr2_upload_firmware1(hdw);
2382 } else {
2383 pvr2_trace(
2384 PVR2_TRACE_ERROR_LEGS,
2385 "***WARNING*** pvrusb2 device hardware"
2386 " appears to be jammed"
2387 " and I can't clear it.");
2388 pvr2_trace(
2389 PVR2_TRACE_ERROR_LEGS,
2390 "You might need to power cycle"
2391 " the pvrusb2 device"
2392 " in order to recover.");
2393 }
681c7399 2394 } while (0);
d855497e 2395 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2396}
2397
2398
c4a8828d
MI		 2399/* Perform second stage initialization. Set callback pointer first so that
2400 we can avoid a possible initialization race (if the kernel thread runs
2401 before the callback has been set). */
794b1607
MI		 2402int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2403 void (*callback_func)(void *),
2404 void *callback_data)
c4a8828d
MI		 2405{
2406 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2407 if (hdw->flag_disconnected) {
2408 /* Handle a race here: If we're already
2409 disconnected by this point, then give up. If we
2410 get past this then we'll remain connected for
2411 the duration of initialization since the entire
2412 initialization sequence is now protected by the
2413 big_lock. */
2414 break;
2415 }
c4a8828d
MI		 2416 hdw->state_data = callback_data;
2417 hdw->state_func = callback_func;
97f26ff6 2418 pvr2_hdw_setup(hdw);
c4a8828d 2419 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2420 return hdw->flag_init_ok;
c4a8828d
MI		 2421}
2422
2423
2424/* Create, set up, and return a structure for interacting with the
2425 underlying hardware. */
d855497e
MI		 2426struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2427 const struct usb_device_id *devid)
2428{
7fb20fa3 2429 unsigned int idx,cnt1,cnt2,m;
fe15f136 2430 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2431 int valid_std_mask;
2432 struct pvr2_ctrl *cptr;
b72b7bf5 2433 struct usb_device *usb_dev;
989eb154 2434 const struct pvr2_device_desc *hdw_desc;
d855497e 2435 __u8 ifnum;
b30d2441
MI		 2436 struct v4l2_queryctrl qctrl;
2437 struct pvr2_ctl_info *ciptr;
d855497e 2438
b72b7bf5
MI		 2439 usb_dev = interface_to_usbdev(intf);
2440
d130fa8a 2441 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2442
fe15f136
MI		 2443 if (hdw_desc == NULL) {
2444 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2445 " No device description pointer,"
2446 " unable to continue.");
2447 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2448 " please contact Mike Isely <isely@pobox.com>"
2449 " to get it included in the driver\n");
2450 goto fail;
2451 }
2452
ca545f7c 2453 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2454 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2455 hdw,hdw_desc->description);
e67e376b 2456 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
00970beb 2457 hdw_desc->description);
d855497e 2458 if (!hdw) goto fail;
681c7399
MI		 2459
2460 init_timer(&hdw->quiescent_timer);
2461 hdw->quiescent_timer.data = (unsigned long)hdw;
2462 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2463
2464 init_timer(&hdw->encoder_wait_timer);
2465 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2466 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2467
d913d630
MI		 2468 init_timer(&hdw->encoder_run_timer);
2469 hdw->encoder_run_timer.data = (unsigned long)hdw;
2470 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2471
681c7399
MI		 2472 hdw->master_state = PVR2_STATE_DEAD;
2473
2474 init_waitqueue_head(&hdw->state_wait_data);
2475
18103c57 2476 hdw->tuner_signal_stale = !0;
b30d2441 2477 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2478
7fb20fa3
MI		 2479 /* Calculate which inputs are OK */
2480 m = 0;
2481 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2482 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2483 m |= 1 << PVR2_CVAL_INPUT_DTV;
2484 }
7fb20fa3
MI		 2485 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2486 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2487 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2488 hdw->input_avail_mask = m;
1cb03b76 2489 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2490
62433e31
MI		 2491 /* If not a hybrid device, pathway_state never changes. So
2492 initialize it here to what it should forever be. */
2493 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2494 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2495 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2496 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2497 }
2498
c05c0462 2499 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2500 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2501 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2502 GFP_KERNEL);
2503 if (!hdw->controls) goto fail;
989eb154 2504 hdw->hdw_desc = hdw_desc;
27eab384 2505 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
c05c0462
MI		 2506 for (idx = 0; idx < hdw->control_cnt; idx++) {
2507 cptr = hdw->controls + idx;
2508 cptr->hdw = hdw;
2509 }
d855497e
MI		 2510 for (idx = 0; idx < 32; idx++) {
2511 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2512 }
c05c0462 2513 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2514 cptr = hdw->controls + idx;
d855497e
MI		 2515 cptr->info = control_defs+idx;
2516 }
dbc40a0e
MI		 2517
2518 /* Ensure that default input choice is a valid one. */
2519 m = hdw->input_avail_mask;
2520 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2521 if (!((1 << idx) & m)) continue;
2522 hdw->input_val = idx;
2523 break;
2524 }
2525
b30d2441 2526 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2527 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2528 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2529 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2530 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2531 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2532 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2533 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2534 ciptr->name = mpeg_ids[idx].strid;
2535 ciptr->v4l_id = mpeg_ids[idx].id;
2536 ciptr->skip_init = !0;
2537 ciptr->get_value = ctrl_cx2341x_get;
2538 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2539 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2540 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2541 qctrl.id = ciptr->v4l_id;
2542 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2543 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2544 ciptr->set_value = ctrl_cx2341x_set;
2545 }
2546 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2547 PVR2_CTLD_INFO_DESC_SIZE);
2548 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2549 ciptr->default_value = qctrl.default_value;
2550 switch (qctrl.type) {
2551 default:
2552 case V4L2_CTRL_TYPE_INTEGER:
2553 ciptr->type = pvr2_ctl_int;
2554 ciptr->def.type_int.min_value = qctrl.minimum;
2555 ciptr->def.type_int.max_value = qctrl.maximum;
2556 break;
2557 case V4L2_CTRL_TYPE_BOOLEAN:
2558 ciptr->type = pvr2_ctl_bool;
2559 break;
2560 case V4L2_CTRL_TYPE_MENU:
2561 ciptr->type = pvr2_ctl_enum;
2562 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2563 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2564 ciptr->v4l_id);
b30d2441
MI		 2565 for (cnt1 = 0;
2566 ciptr->def.type_enum.value_names[cnt1] != NULL;
2567 cnt1++) { }
2568 ciptr->def.type_enum.count = cnt1;
2569 break;
2570 }
2571 cptr->info = ciptr;
2572 }
d855497e
MI		 2573
2574 // Initialize video standard enum dynamic control
2575 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2576 if (cptr) {
2577 memcpy(&hdw->std_info_enum,cptr->info,
2578 sizeof(hdw->std_info_enum));
2579 cptr->info = &hdw->std_info_enum;
2580
2581 }
2582 // Initialize control data regarding video standard masks
2583 valid_std_mask = pvr2_std_get_usable();
2584 for (idx = 0; idx < 32; idx++) {
2585 if (!(valid_std_mask & (1 << idx))) continue;
2586 cnt1 = pvr2_std_id_to_str(
2587 hdw->std_mask_names[idx],
2588 sizeof(hdw->std_mask_names[idx])-1,
2589 1 << idx);
2590 hdw->std_mask_names[idx][cnt1] = 0;
2591 }
2592 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2593 if (cptr) {
2594 memcpy(&hdw->std_info_avail,cptr->info,
2595 sizeof(hdw->std_info_avail));
2596 cptr->info = &hdw->std_info_avail;
2597 hdw->std_info_avail.def.type_bitmask.bit_names =
2598 hdw->std_mask_ptrs;
2599 hdw->std_info_avail.def.type_bitmask.valid_bits =
2600 valid_std_mask;
2601 }
2602 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2603 if (cptr) {
2604 memcpy(&hdw->std_info_cur,cptr->info,
2605 sizeof(hdw->std_info_cur));
2606 cptr->info = &hdw->std_info_cur;
2607 hdw->std_info_cur.def.type_bitmask.bit_names =
2608 hdw->std_mask_ptrs;
2609 hdw->std_info_avail.def.type_bitmask.valid_bits =
2610 valid_std_mask;
2611 }
2612
432907f7 2613 hdw->cropcap_stale = !0;
d855497e
MI		 2614 hdw->eeprom_addr = -1;
2615 hdw->unit_number = -1;
8079384e
MI		 2616 hdw->v4l_minor_number_video = -1;
2617 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2618 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2619 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2620 if (!hdw->ctl_write_buffer) goto fail;
2621 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2622 if (!hdw->ctl_read_buffer) goto fail;
2623 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2624 if (!hdw->ctl_write_urb) goto fail;
2625 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2626 if (!hdw->ctl_read_urb) goto fail;
2627
70ad6383 2628 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
b72b7bf5
MI		 2629 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2630 "Error registering with v4l core, giving up");
2631 goto fail;
2632 }
8df0c87c 2633 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2634 for (idx = 0; idx < PVR_NUM; idx++) {
2635 if (unit_pointers[idx]) continue;
2636 hdw->unit_number = idx;
2637 unit_pointers[idx] = hdw;
2638 break;
2639 }
8df0c87c 2640 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2641
2642 cnt1 = 0;
2643 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2644 cnt1 += cnt2;
2645 if (hdw->unit_number >= 0) {
2646 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2647 ('a' + hdw->unit_number));
2648 cnt1 += cnt2;
2649 }
2650 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2651 hdw->name[cnt1] = 0;
2652
681c7399
MI		 2653 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2654 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
681c7399 2655
d855497e
MI		 2656 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2657 hdw->unit_number,hdw->name);
2658
2659 hdw->tuner_type = -1;
2660 hdw->flag_ok = !0;
d855497e
MI		 2661
2662 hdw->usb_intf = intf;
b72b7bf5 2663 hdw->usb_dev = usb_dev;
d855497e 2664
87e3495c 2665 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2666
d855497e
MI		 2667 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2668 usb_set_interface(hdw->usb_dev,ifnum,0);
2669
2670 mutex_init(&hdw->ctl_lock_mutex);
2671 mutex_init(&hdw->big_lock_mutex);
2672
2673 return hdw;
2674 fail:
2675 if (hdw) {
681c7399 2676 del_timer_sync(&hdw->quiescent_timer);
d913d630 2677 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2678 del_timer_sync(&hdw->encoder_wait_timer);
2679 if (hdw->workqueue) {
2680 flush_workqueue(hdw->workqueue);
2681 destroy_workqueue(hdw->workqueue);
2682 hdw->workqueue = NULL;
2683 }
5e55d2ce
MK		 2684 usb_free_urb(hdw->ctl_read_urb);
2685 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2686 kfree(hdw->ctl_read_buffer);
2687 kfree(hdw->ctl_write_buffer);
2688 kfree(hdw->controls);
2689 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2690 kfree(hdw->std_defs);
2691 kfree(hdw->std_enum_names);
d855497e
MI		 2692 kfree(hdw);
2693 }
a0fd1cb1 2694 return NULL;
d855497e
MI		 2695}
2696
2697
2698/* Remove _all_ associations between this driver and the underlying USB
2699 layer. */
07e337ee 2700static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2701{
2702 if (hdw->flag_disconnected) return;
2703 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2704 if (hdw->ctl_read_urb) {
2705 usb_kill_urb(hdw->ctl_read_urb);
2706 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2707 hdw->ctl_read_urb = NULL;
d855497e
MI		 2708 }
2709 if (hdw->ctl_write_urb) {
2710 usb_kill_urb(hdw->ctl_write_urb);
2711 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2712 hdw->ctl_write_urb = NULL;
d855497e
MI		 2713 }
2714 if (hdw->ctl_read_buffer) {
2715 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2716 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2717 }
2718 if (hdw->ctl_write_buffer) {
2719 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2720 hdw->ctl_write_buffer = NULL;
d855497e 2721 }
d855497e 2722 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2723 /* If we don't do this, then there will be a dangling struct device
2724 reference to our disappearing device persisting inside the V4L
2725 core... */
dc070bcc 2726 v4l2_device_disconnect(&hdw->v4l2_dev);
a0fd1cb1
MI		 2727 hdw->usb_dev = NULL;
2728 hdw->usb_intf = NULL;
681c7399 2729 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2730}
2731
2732
2733/* Destroy hardware interaction structure */
2734void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2735{
401c27ce 2736 if (!hdw) return;
d855497e 2737 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2738 if (hdw->workqueue) {
2739 flush_workqueue(hdw->workqueue);
2740 destroy_workqueue(hdw->workqueue);
2741 hdw->workqueue = NULL;
2742 }
8f59100a 2743 del_timer_sync(&hdw->quiescent_timer);
d913d630 2744 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2745 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2746 if (hdw->fw_buffer) {
2747 kfree(hdw->fw_buffer);
a0fd1cb1 2748 hdw->fw_buffer = NULL;
d855497e
MI		 2749 }
2750 if (hdw->vid_stream) {
2751 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2752 hdw->vid_stream = NULL;
d855497e 2753 }
d855497e 2754 pvr2_i2c_core_done(hdw);
b72b7bf5 2755 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2756 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2757 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2758 if ((hdw->unit_number >= 0) &&
2759 (hdw->unit_number < PVR_NUM) &&
2760 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2761 unit_pointers[hdw->unit_number] = NULL;
d855497e 2762 }
8df0c87c 2763 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2764 kfree(hdw->controls);
2765 kfree(hdw->mpeg_ctrl_info);
2766 kfree(hdw->std_defs);
2767 kfree(hdw->std_enum_names);
d855497e
MI		 2768 kfree(hdw);
2769}
2770
2771
d855497e
MI		 2772int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2773{
2774 return (hdw && hdw->flag_ok);
2775}
2776
2777
2778/* Called when hardware has been unplugged */
2779void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2780{
2781 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2782 LOCK_TAKE(hdw->big_lock);
2783 LOCK_TAKE(hdw->ctl_lock);
2784 pvr2_hdw_remove_usb_stuff(hdw);
2785 LOCK_GIVE(hdw->ctl_lock);
2786 LOCK_GIVE(hdw->big_lock);
2787}
2788
2789
2790// Attempt to autoselect an appropriate value for std_enum_cur given
2791// whatever is currently in std_mask_cur
07e337ee 2792static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2793{
2794 unsigned int idx;
2795 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2796 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2797 hdw->std_enum_cur = idx;
2798 return;
2799 }
2800 }
2801 hdw->std_enum_cur = 0;
2802}
2803
2804
2805// Calculate correct set of enumerated standards based on currently known
2806// set of available standards bits.
07e337ee 2807static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2808{
2809 struct v4l2_standard *newstd;
2810 unsigned int std_cnt;
2811 unsigned int idx;
2812
2813 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2814
2815 if (hdw->std_defs) {
2816 kfree(hdw->std_defs);
a0fd1cb1 2817 hdw->std_defs = NULL;
d855497e
MI		 2818 }
2819 hdw->std_enum_cnt = 0;
2820 if (hdw->std_enum_names) {
2821 kfree(hdw->std_enum_names);
a0fd1cb1 2822 hdw->std_enum_names = NULL;
d855497e
MI		 2823 }
2824
2825 if (!std_cnt) {
2826 pvr2_trace(
2827 PVR2_TRACE_ERROR_LEGS,
2828 "WARNING: Failed to identify any viable standards");
2829 }
2830 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2831 hdw->std_enum_names[0] = "none";
2832 for (idx = 0; idx < std_cnt; idx++) {
2833 hdw->std_enum_names[idx+1] =
2834 newstd[idx].name;
2835 }
2836 // Set up the dynamic control for this standard
2837 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2838 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2839 hdw->std_defs = newstd;
2840 hdw->std_enum_cnt = std_cnt+1;
2841 hdw->std_enum_cur = 0;
2842 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2843}
2844
2845
2846int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2847 struct v4l2_standard *std,
2848 unsigned int idx)
2849{
2850 int ret = -EINVAL;
2851 if (!idx) return ret;
2852 LOCK_TAKE(hdw->big_lock); do {
2853 if (idx >= hdw->std_enum_cnt) break;
2854 idx--;
2855 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2856 ret = 0;
2857 } while (0); LOCK_GIVE(hdw->big_lock);
2858 return ret;
2859}
2860
2861
2862/* Get the number of defined controls */
2863unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2864{
c05c0462 2865 return hdw->control_cnt;
d855497e
MI		 2866}
2867
2868
2869/* Retrieve a control handle given its index (0..count-1) */
2870struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2871 unsigned int idx)
2872{
a0fd1cb1 2873 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2874 return hdw->controls + idx;
2875}
2876
2877
2878/* Retrieve a control handle given its index (0..count-1) */
2879struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2880 unsigned int ctl_id)
2881{
2882 struct pvr2_ctrl *cptr;
2883 unsigned int idx;
2884 int i;
2885
2886 /* This could be made a lot more efficient, but for now... */
c05c0462 2887 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2888 cptr = hdw->controls + idx;
2889 i = cptr->info->internal_id;
2890 if (i && (i == ctl_id)) return cptr;
2891 }
a0fd1cb1 2892 return NULL;
d855497e
MI		 2893}
2894
2895
a761f431 2896/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2897struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2898{
2899 struct pvr2_ctrl *cptr;
2900 unsigned int idx;
2901 int i;
2902
2903 /* This could be made a lot more efficient, but for now... */
c05c0462 2904 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2905 cptr = hdw->controls + idx;
2906 i = cptr->info->v4l_id;
2907 if (i && (i == ctl_id)) return cptr;
2908 }
a0fd1cb1 2909 return NULL;
d855497e
MI		 2910}
2911
2912
a761f431
MI		 2913/* Given a V4L ID for its immediate predecessor, retrieve the control
2914 structure associated with it. */
2915struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2916 unsigned int ctl_id)
2917{
2918 struct pvr2_ctrl *cptr,*cp2;
2919 unsigned int idx;
2920 int i;
2921
2922 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2923 cp2 = NULL;
a761f431
MI		 2924 for (idx = 0; idx < hdw->control_cnt; idx++) {
2925 cptr = hdw->controls + idx;
2926 i = cptr->info->v4l_id;
2927 if (!i) continue;
2928 if (i <= ctl_id) continue;
2929 if (cp2 && (cp2->info->v4l_id < i)) continue;
2930 cp2 = cptr;
2931 }
2932 return cp2;
a0fd1cb1 2933 return NULL;
a761f431
MI		 2934}
2935
2936
d855497e
MI		 2937static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2938{
2939 switch (tp) {
2940 case pvr2_ctl_int: return "integer";
2941 case pvr2_ctl_enum: return "enum";
33213963 2942 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2943 case pvr2_ctl_bitmask: return "bitmask";
2944 }
2945 return "";
2946}
2947
2948
2641df36
MI		 2949static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2950 const char *name, int val)
2951{
2952 struct v4l2_control ctrl;
2953 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2954 memset(&ctrl, 0, sizeof(ctrl));
2955 ctrl.id = id;
2956 ctrl.value = val;
2957 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2958}
2959
2960#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
27764726 2961 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2641df36
MI		 2962 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2963 }
2964
5ceaad14 2965/* Execute whatever commands are required to update the state of all the
2641df36 2966 sub-devices so that they match our current control values. */
5ceaad14
MI		 2967static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2968{
edb9dcb8
MI		 2969 struct v4l2_subdev *sd;
2970 unsigned int id;
2971 pvr2_subdev_update_func fp;
2972
75212a02
MI		 2973 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2974
27764726 2975 if (hdw->tuner_updated || hdw->force_dirty) {
75212a02
MI		 2976 struct tuner_setup setup;
2977 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2978 hdw->tuner_type);
2979 if (((int)(hdw->tuner_type)) >= 0) {
fcd62cf7 2980 memset(&setup, 0, sizeof(setup));
75212a02
MI		 2981 setup.addr = ADDR_UNSET;
2982 setup.type = hdw->tuner_type;
2983 setup.mode_mask = T_RADIO | T_ANALOG_TV;
2984 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2985 tuner, s_type_addr, &setup);
2986 }
2987 }
2988
27764726 2989 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
b481880b 2990 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 2991 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2992 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2993 tuner, s_radio);
2994 } else {
2995 v4l2_std_id vs;
2996 vs = hdw->std_mask_cur;
2997 v4l2_device_call_all(&hdw->v4l2_dev, 0,
f41737ec 2998 core, s_std, vs);
a6862da2 2999 pvr2_hdw_cx25840_vbi_hack(hdw);
2641df36
MI		 3000 }
3001 hdw->tuner_signal_stale = !0;
3002 hdw->cropcap_stale = !0;
3003 }
3004
3005 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
3006 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
3007 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
3008 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
3009 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
3010 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
3011 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
3012 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
3013 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
3014
27764726 3015 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2641df36
MI		 3016 struct v4l2_tuner vt;
3017 memset(&vt, 0, sizeof(vt));
3018 vt.audmode = hdw->audiomode_val;
3019 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3020 }
3021
27764726 3022 if (hdw->freqDirty || hdw->force_dirty) {
2641df36
MI		 3023 unsigned long fv;
3024 struct v4l2_frequency freq;
3025 fv = pvr2_hdw_get_cur_freq(hdw);
3026 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3027 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3028 memset(&freq, 0, sizeof(freq));
3029 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3030 /* ((fv * 1000) / 62500) */
3031 freq.frequency = (fv * 2) / 125;
3032 } else {
3033 freq.frequency = fv / 62500;
3034 }
3035 /* tuner-core currently doesn't seem to care about this, but
3036 let's set it anyway for completeness. */
3037 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3038 freq.type = V4L2_TUNER_RADIO;
3039 } else {
3040 freq.type = V4L2_TUNER_ANALOG_TV;
3041 }
3042 freq.tuner = 0;
3043 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3044 s_frequency, &freq);
3045 }
3046
27764726 3047 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2641df36
MI		 3048 struct v4l2_format fmt;
3049 memset(&fmt, 0, sizeof(fmt));
3050 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
3051 fmt.fmt.pix.width = hdw->res_hor_val;
3052 fmt.fmt.pix.height = hdw->res_ver_val;
7dfdf1ee 3053 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2641df36
MI		 3054 fmt.fmt.pix.width, fmt.fmt.pix.height);
3055 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3056 }
3057
27764726 3058 if (hdw->srate_dirty || hdw->force_dirty) {
01c59df8
MI		 3059 u32 val;
3060 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3061 hdw->srate_val);
3062 switch (hdw->srate_val) {
3063 default:
3064 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3065 val = 48000;
3066 break;
3067 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3068 val = 44100;
3069 break;
3070 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3071 val = 32000;
3072 break;
3073 }
3074 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3075 audio, s_clock_freq, val);
3076 }
3077
2641df36
MI		 3078 /* Unable to set crop parameters; there is apparently no equivalent
3079 for VIDIOC_S_CROP */
3080
edb9dcb8
MI		 3081 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3082 id = sd->grp_id;
3083 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3084 fp = pvr2_module_update_functions[id];
3085 if (!fp) continue;
3086 (*fp)(hdw, sd);
3087 }
2641df36 3088
27764726 3089 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2641df36
MI		 3090 pvr2_hdw_status_poll(hdw);
3091 }
5ceaad14
MI		 3092}
3093
3094
681c7399
MI		 3095/* Figure out if we need to commit control changes. If so, mark internal
3096 state flags to indicate this fact and return true. Otherwise do nothing
3097 else and return false. */
3098static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3099{
d855497e
MI		 3100 unsigned int idx;
3101 struct pvr2_ctrl *cptr;
3102 int value;
27764726 3103 int commit_flag = hdw->force_dirty;
d855497e
MI		 3104 char buf[100];
3105 unsigned int bcnt,ccnt;
3106
c05c0462 3107 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3108 cptr = hdw->controls + idx;
5fa1247a 3109 if (!cptr->info->is_dirty) continue;
d855497e 3110 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3111 commit_flag = !0;
d855497e 3112
fe23a280 3113 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3114 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3115 cptr->info->name);
3116 value = 0;
3117 cptr->info->get_value(cptr,&value);
3118 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3119 buf+bcnt,
3120 sizeof(buf)-bcnt,&ccnt);
3121 bcnt += ccnt;
3122 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3123 get_ctrl_typename(cptr->info->type));
3124 pvr2_trace(PVR2_TRACE_CTL,
3125 "/*--TRACE_COMMIT--*/ %.*s",
3126 bcnt,buf);
3127 }
3128
3129 if (!commit_flag) {
3130 /* Nothing has changed */
3131 return 0;
3132 }
3133
681c7399
MI		 3134 hdw->state_pipeline_config = 0;
3135 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3136 pvr2_hdw_state_sched(hdw);
3137
3138 return !0;
3139}
3140
3141
3142/* Perform all operations needed to commit all control changes. This must
3143 be performed in synchronization with the pipeline state and is thus
3144 expected to be called as part of the driver's worker thread. Return
3145 true if commit successful, otherwise return false to indicate that
3146 commit isn't possible at this time. */
3147static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3148{
3149 unsigned int idx;
3150 struct pvr2_ctrl *cptr;
3151 int disruptive_change;
3152
ab062fe3
MI		 3153 /* Handle some required side effects when the video standard is
3154 changed.... */
d855497e 3155 if (hdw->std_dirty) {
d855497e 3156 int nvres;
00528d9c 3157 int gop_size;
d855497e
MI		 3158 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3159 nvres = 480;
00528d9c 3160 gop_size = 15;
d855497e
MI		 3161 } else {
3162 nvres = 576;
00528d9c 3163 gop_size = 12;
d855497e 3164 }
00528d9c
MI		 3165 /* Rewrite the vertical resolution to be appropriate to the
3166 video standard that has been selected. */
d855497e
MI		 3167 if (nvres != hdw->res_ver_val) {
3168 hdw->res_ver_val = nvres;
3169 hdw->res_ver_dirty = !0;
3170 }
00528d9c
MI		 3171 /* Rewrite the GOP size to be appropriate to the video
3172 standard that has been selected. */
3173 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3174 struct v4l2_ext_controls cs;
3175 struct v4l2_ext_control c1;
3176 memset(&cs, 0, sizeof(cs));
3177 memset(&c1, 0, sizeof(c1));
3178 cs.controls = &c1;
3179 cs.count = 1;
3180 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3181 c1.value = gop_size;
3182 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3183 VIDIOC_S_EXT_CTRLS);
3184 }
d855497e
MI		 3185 }
3186
38d9a2cf 3187 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 3188 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3189 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3190 hdw->pathway_state)) {
3191 /* Change of mode being asked for... */
3192 hdw->state_pathway_ok = 0;
e9db1ff2 3193 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3194 }
3195 if (!hdw->state_pathway_ok) {
3196 /* Can't commit anything until pathway is ok. */
3197 return 0;
3198 }
e784bfb9 3199 /* The broadcast decoder can only scale down, so if
3200 * res_*_dirty && crop window < output format ==> enlarge crop.
3201 *
3202 * The mpeg encoder receives fields of res_hor_val dots and
3203 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3204 */
3205 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3206 hdw->cropw_val = hdw->res_hor_val;
3207 hdw->cropw_dirty = !0;
3208 } else if (hdw->cropw_dirty) {
3209 hdw->res_hor_dirty = !0; /* must rescale */
3210 hdw->res_hor_val = min(720, hdw->cropw_val);
3211 }
3212 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3213 hdw->croph_val = hdw->res_ver_val;
3214 hdw->croph_dirty = !0;
3215 } else if (hdw->croph_dirty) {
3216 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3217 hdw->res_ver_dirty = !0;
3218 hdw->res_ver_val = min(nvres, hdw->croph_val);
3219 }
3220
681c7399
MI		 3221 /* If any of the below has changed, then we can't do the update
3222 while the pipeline is running. Pipeline must be paused first
3223 and decoder -> encoder connection be made quiescent before we
3224 can proceed. */
3225 disruptive_change =
3226 (hdw->std_dirty ||
3227 hdw->enc_unsafe_stale ||
3228 hdw->srate_dirty ||
3229 hdw->res_ver_dirty ||
3230 hdw->res_hor_dirty ||
755879c6
MI		 3231 hdw->cropw_dirty ||
3232 hdw->croph_dirty ||
681c7399
MI		 3233 hdw->input_dirty ||
3234 (hdw->active_stream_type != hdw->desired_stream_type));
3235 if (disruptive_change && !hdw->state_pipeline_idle) {
3236 /* Pipeline is not idle; we can't proceed. Arrange to
3237 cause pipeline to stop so that we can try this again
3238 later.... */
3239 hdw->state_pipeline_pause = !0;
3240 return 0;
275b2e28
PK		 3241 }
3242
b30d2441
MI		 3243 if (hdw->srate_dirty) {
3244 /* Write new sample rate into control structure since
3245 * the master copy is stale. We must track srate
3246 * separate from the mpeg control structure because
3247 * other logic also uses this value. */
3248 struct v4l2_ext_controls cs;
3249 struct v4l2_ext_control c1;
3250 memset(&cs,0,sizeof(cs));
3251 memset(&c1,0,sizeof(c1));
3252 cs.controls = &c1;
3253 cs.count = 1;
3254 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3255 c1.value = hdw->srate_val;
01f1e44f 3256 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3257 }
c05c0462 3258
681c7399
MI		 3259 if (hdw->active_stream_type != hdw->desired_stream_type) {
3260 /* Handle any side effects of stream config here */
3261 hdw->active_stream_type = hdw->desired_stream_type;
3262 }
3263
1df59f0b
MI		 3264 if (hdw->hdw_desc->signal_routing_scheme ==
3265 PVR2_ROUTING_SCHEME_GOTVIEW) {
3266 u32 b;
3267 /* Handle GOTVIEW audio switching */
3268 pvr2_hdw_gpio_get_out(hdw,&b);
3269 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3270 /* Set GPIO 11 */
3271 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3272 } else {
3273 /* Clear GPIO 11 */
3274 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3275 }
3276 }
3277
e68a619a
MI		 3278 /* Check and update state for all sub-devices. */
3279 pvr2_subdev_update(hdw);
3280
75212a02 3281 hdw->tuner_updated = 0;
27764726 3282 hdw->force_dirty = 0;
5ceaad14
MI		 3283 for (idx = 0; idx < hdw->control_cnt; idx++) {
3284 cptr = hdw->controls + idx;
3285 if (!cptr->info->clear_dirty) continue;
3286 cptr->info->clear_dirty(cptr);
3287 }
3288
62433e31
MI		 3289 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3290 hdw->state_encoder_run) {
3291 /* If encoder isn't running or it can't be touched, then
3292 this will get worked out later when we start the
3293 encoder. */
681c7399
MI		 3294 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3295 }
d855497e 3296
681c7399 3297 hdw->state_pipeline_config = !0;
432907f7
MI		 3298 /* Hardware state may have changed in a way to cause the cropping
3299 capabilities to have changed. So mark it stale, which will
3300 cause a later re-fetch. */
681c7399
MI		 3301 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3302 return !0;
d855497e
MI		 3303}
3304
3305
3306int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3307{
681c7399
MI		 3308 int fl;
3309 LOCK_TAKE(hdw->big_lock);
3310 fl = pvr2_hdw_commit_setup(hdw);
3311 LOCK_GIVE(hdw->big_lock);
3312 if (!fl) return 0;
3313 return pvr2_hdw_wait(hdw,0);
3314}
3315
3316
681c7399 3317static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3318{
681c7399
MI		 3319 int fl = 0;
3320 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3321 LOCK_TAKE(hdw->big_lock); do {
681c7399 3322 fl = pvr2_hdw_state_eval(hdw);
d855497e 3323 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3324 if (fl && hdw->state_func) {
3325 hdw->state_func(hdw->state_data);
3326 }
d855497e
MI		 3327}
3328
3329
681c7399 3330static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3331{
681c7399
MI		 3332 return wait_event_interruptible(
3333 hdw->state_wait_data,
3334 (hdw->state_stale == 0) &&
3335 (!state || (hdw->master_state != state)));
3336}
3337
3338
d855497e
MI		 3339/* Return name for this driver instance */
3340const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3341{
3342 return hdw->name;
3343}
3344
3345
78a47101
MI		 3346const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3347{
3348 return hdw->hdw_desc->description;
3349}
3350
3351
3352const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3353{
3354 return hdw->hdw_desc->shortname;
3355}
3356
3357
d855497e
MI		 3358int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3359{
3360 int result;
3361 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3362 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3363 result = pvr2_send_request(hdw,
3364 hdw->cmd_buffer,1,
3365 hdw->cmd_buffer,1);
3366 if (result < 0) break;
3367 result = (hdw->cmd_buffer[0] != 0);
3368 } while(0); LOCK_GIVE(hdw->ctl_lock);
3369 return result;
3370}
3371
3372
18103c57
MI		 3373/* Execute poll of tuner status */
3374void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3375{
d855497e 3376 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3377 pvr2_hdw_status_poll(hdw);
d855497e 3378 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3379}
3380
3381
432907f7
MI		 3382static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3383{
3384 if (!hdw->cropcap_stale) {
432907f7
MI		 3385 return 0;
3386 }
a51f5000 3387 pvr2_hdw_status_poll(hdw);
432907f7 3388 if (hdw->cropcap_stale) {
432907f7
MI		 3389 return -EIO;
3390 }
3391 return 0;
3392}
3393
3394
3395/* Return information about cropping capabilities */
3396int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3397{
3398 int stat = 0;
3399 LOCK_TAKE(hdw->big_lock);
3400 stat = pvr2_hdw_check_cropcap(hdw);
3401 if (!stat) {
432907f7
MI		 3402 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3403 }
3404 LOCK_GIVE(hdw->big_lock);
3405 return stat;
3406}
3407
3408
18103c57
MI		 3409/* Return information about the tuner */
3410int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3411{
3412 LOCK_TAKE(hdw->big_lock); do {
3413 if (hdw->tuner_signal_stale) {
a51f5000 3414 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3415 }
3416 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3417 } while (0); LOCK_GIVE(hdw->big_lock);
3418 return 0;
d855497e
MI		 3419}
3420
3421
3422/* Get handle to video output stream */
3423struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3424{
3425 return hp->vid_stream;
3426}
3427
3428
3429void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3430{
4f1a3e5b 3431 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3432 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3433 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
ed3261a8 3434 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3435 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3436 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3437 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3438 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3439 } while (0); LOCK_GIVE(hdw->big_lock);
3440}
3441
4db666cc
MI		 3442
3443/* Grab EEPROM contents, needed for direct method. */
3444#define EEPROM_SIZE 8192
3445#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3446static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3447{
3448 struct i2c_msg msg[2];
3449 u8 *eeprom;
3450 u8 iadd[2];
3451 u8 addr;
3452 u16 eepromSize;
3453 unsigned int offs;
3454 int ret;
3455 int mode16 = 0;
3456 unsigned pcnt,tcnt;
3457 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3458 if (!eeprom) {
3459 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3460 "Failed to allocate memory"
3461 " required to read eeprom");
3462 return NULL;
3463 }
3464
3465 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3466 hdw->eeprom_addr);
3467 addr = hdw->eeprom_addr;
3468 /* Seems that if the high bit is set, then the *real* eeprom
3469 address is shifted right now bit position (noticed this in
3470 newer PVR USB2 hardware) */
3471 if (addr & 0x80) addr >>= 1;
3472
3473 /* FX2 documentation states that a 16bit-addressed eeprom is
3474 expected if the I2C address is an odd number (yeah, this is
3475 strange but it's what they do) */
3476 mode16 = (addr & 1);
3477 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3478 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3479 " using %d bit addressing",eepromSize,addr,
3480 mode16 ? 16 : 8);
3481
3482 msg[0].addr = addr;
3483 msg[0].flags = 0;
3484 msg[0].len = mode16 ? 2 : 1;
3485 msg[0].buf = iadd;
3486 msg[1].addr = addr;
3487 msg[1].flags = I2C_M_RD;
3488
3489 /* We have to do the actual eeprom data fetch ourselves, because
3490 (1) we're only fetching part of the eeprom, and (2) if we were
3491 getting the whole thing our I2C driver can't grab it in one
3492 pass - which is what tveeprom is otherwise going to attempt */
3493 memset(eeprom,0,EEPROM_SIZE);
3494 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3495 pcnt = 16;
3496 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3497 offs = tcnt + (eepromSize - EEPROM_SIZE);
3498 if (mode16) {
3499 iadd[0] = offs >> 8;
3500 iadd[1] = offs;
3501 } else {
3502 iadd[0] = offs;
3503 }
3504 msg[1].len = pcnt;
3505 msg[1].buf = eeprom+tcnt;
3506 if ((ret = i2c_transfer(&hdw->i2c_adap,
3507 msg,ARRAY_SIZE(msg))) != 2) {
3508 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3509 "eeprom fetch set offs err=%d",ret);
3510 kfree(eeprom);
3511 return NULL;
3512 }
3513 }
3514 return eeprom;
3515}
3516
3517
3518void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
568efaa2 3519 int mode,
4db666cc 3520 int enable_flag)
d855497e
MI		 3521{
3522 int ret;
3523 u16 address;
3524 unsigned int pipe;
3525 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3526 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3527
3528 if (!enable_flag) {
3529 pvr2_trace(PVR2_TRACE_FIRMWARE,
3530 "Cleaning up after CPU firmware fetch");
3531 kfree(hdw->fw_buffer);
a0fd1cb1 3532 hdw->fw_buffer = NULL;
d855497e 3533 hdw->fw_size = 0;
4db666cc
MI		 3534 if (hdw->fw_cpu_flag) {
3535 /* Now release the CPU. It will disconnect
3536 and reconnect later. */
3537 pvr2_hdw_cpureset_assert(hdw,0);
3538 }
d855497e
MI		 3539 break;
3540 }
3541
568efaa2 3542 hdw->fw_cpu_flag = (mode != 2);
4db666cc 3543 if (hdw->fw_cpu_flag) {
568efaa2 3544 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
4db666cc 3545 pvr2_trace(PVR2_TRACE_FIRMWARE,
568efaa2
MI		 3546 "Preparing to suck out CPU firmware"
3547 " (size=%u)", hdw->fw_size);
4db666cc
MI		 3548 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3549 if (!hdw->fw_buffer) {
3550 hdw->fw_size = 0;
3551 break;
3552 }
d855497e 3553
4db666cc
MI		 3554 /* We have to hold the CPU during firmware upload. */
3555 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3556
4db666cc
MI		 3557 /* download the firmware from address 0000-1fff in 2048
3558 (=0x800) bytes chunk. */
d855497e 3559
4db666cc
MI		 3560 pvr2_trace(PVR2_TRACE_FIRMWARE,
3561 "Grabbing CPU firmware");
3562 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3563 for(address = 0; address < hdw->fw_size;
3564 address += 0x800) {
3565 ret = usb_control_msg(hdw->usb_dev,pipe,
3566 0xa0,0xc0,
3567 address,0,
3568 hdw->fw_buffer+address,
3569 0x800,HZ);
3570 if (ret < 0) break;
3571 }
d855497e 3572
4db666cc
MI		 3573 pvr2_trace(PVR2_TRACE_FIRMWARE,
3574 "Done grabbing CPU firmware");
3575 } else {
3576 pvr2_trace(PVR2_TRACE_FIRMWARE,
3577 "Sucking down EEPROM contents");
3578 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3579 if (!hdw->fw_buffer) {
3580 pvr2_trace(PVR2_TRACE_FIRMWARE,
3581 "EEPROM content suck failed.");
3582 break;
3583 }
3584 hdw->fw_size = EEPROM_SIZE;
3585 pvr2_trace(PVR2_TRACE_FIRMWARE,
3586 "Done sucking down EEPROM contents");
3587 }
d855497e
MI		 3588
3589 } while (0); LOCK_GIVE(hdw->big_lock);
3590}
3591
3592
3593/* Return true if we're in a mode for retrieval CPU firmware */
3594int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3595{
5fa1247a 3596 return hdw->fw_buffer != NULL;
d855497e
MI		 3597}
3598
3599
3600int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3601 char *buf,unsigned int cnt)
3602{
3603 int ret = -EINVAL;
3604 LOCK_TAKE(hdw->big_lock); do {
3605 if (!buf) break;
3606 if (!cnt) break;
3607
3608 if (!hdw->fw_buffer) {
3609 ret = -EIO;
3610 break;
3611 }
3612
3613 if (offs >= hdw->fw_size) {
3614 pvr2_trace(PVR2_TRACE_FIRMWARE,
3615 "Read firmware data offs=%d EOF",
3616 offs);
3617 ret = 0;
3618 break;
3619 }
3620
3621 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3622
3623 memcpy(buf,hdw->fw_buffer+offs,cnt);
3624
3625 pvr2_trace(PVR2_TRACE_FIRMWARE,
3626 "Read firmware data offs=%d cnt=%d",
3627 offs,cnt);
3628 ret = cnt;
3629 } while (0); LOCK_GIVE(hdw->big_lock);
3630
3631 return ret;
3632}
3633
3634
fd5a75fe 3635int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3636 enum pvr2_v4l_type index)
d855497e 3637{
fd5a75fe 3638 switch (index) {
8079384e
MI		 3639 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3640 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3641 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3642 default: return -1;
3643 }
d855497e
MI		 3644}
3645
3646
2fdf3d9c 3647/* Store a v4l minor device number */
fd5a75fe 3648void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3649 enum pvr2_v4l_type index,int v)
d855497e 3650{
fd5a75fe 3651 switch (index) {
8079384e
MI		 3652 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3653 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3654 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3655 default: break;
3656 }
d855497e
MI		 3657}
3658
3659
7d12e780 3660static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3661{
3662 struct pvr2_hdw *hdw = urb->context;
3663 hdw->ctl_write_pend_flag = 0;
3664 if (hdw->ctl_read_pend_flag) return;
3665 complete(&hdw->ctl_done);
3666}
3667
3668
7d12e780 3669static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3670{
3671 struct pvr2_hdw *hdw = urb->context;
3672 hdw->ctl_read_pend_flag = 0;
3673 if (hdw->ctl_write_pend_flag) return;
3674 complete(&hdw->ctl_done);
3675}
3676
3677
3678static void pvr2_ctl_timeout(unsigned long data)
3679{
3680 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3681 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3682 hdw->ctl_timeout_flag = !0;
5e55d2ce 3683 if (hdw->ctl_write_pend_flag)
d855497e 3684 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3685 if (hdw->ctl_read_pend_flag)
d855497e 3686 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3687 }
3688}
3689
3690
e61b6fc5
MI		 3691/* Issue a command and get a response from the device. This extended
3692 version includes a probe flag (which if set means that device errors
3693 should not be logged or treated as fatal) and a timeout in jiffies.
3694 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3695static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3696 unsigned int timeout,int probe_fl,
3697 void *write_data,unsigned int write_len,
3698 void *read_data,unsigned int read_len)
d855497e
MI		 3699{
3700 unsigned int idx;
3701 int status = 0;
3702 struct timer_list timer;
3703 if (!hdw->ctl_lock_held) {
3704 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3705 "Attempted to execute control transfer"
3706 " without lock!!");
3707 return -EDEADLK;
3708 }
681c7399 3709 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3710 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3711 "Attempted to execute control transfer"
3712 " when device not ok");
3713 return -EIO;
3714 }
3715 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3716 if (!probe_fl) {
3717 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3718 "Attempted to execute control transfer"
3719 " when USB is disconnected");
3720 }
3721 return -ENOTTY;
3722 }
3723
3724 /* Ensure that we have sane parameters */
3725 if (!write_data) write_len = 0;
3726 if (!read_data) read_len = 0;
3727 if (write_len > PVR2_CTL_BUFFSIZE) {
3728 pvr2_trace(
3729 PVR2_TRACE_ERROR_LEGS,
3730 "Attempted to execute %d byte"
3731 " control-write transfer (limit=%d)",
3732 write_len,PVR2_CTL_BUFFSIZE);
3733 return -EINVAL;
3734 }
3735 if (read_len > PVR2_CTL_BUFFSIZE) {
3736 pvr2_trace(
3737 PVR2_TRACE_ERROR_LEGS,
3738 "Attempted to execute %d byte"
3739 " control-read transfer (limit=%d)",
3740 write_len,PVR2_CTL_BUFFSIZE);
3741 return -EINVAL;
3742 }
3743 if ((!write_len) && (!read_len)) {
3744 pvr2_trace(
3745 PVR2_TRACE_ERROR_LEGS,
3746 "Attempted to execute null control transfer?");
3747 return -EINVAL;
3748 }
3749
3750
3751 hdw->cmd_debug_state = 1;
3752 if (write_len) {
3753 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3754 } else {
3755 hdw->cmd_debug_code = 0;
3756 }
3757 hdw->cmd_debug_write_len = write_len;
3758 hdw->cmd_debug_read_len = read_len;
3759
3760 /* Initialize common stuff */
3761 init_completion(&hdw->ctl_done);
3762 hdw->ctl_timeout_flag = 0;
3763 hdw->ctl_write_pend_flag = 0;
3764 hdw->ctl_read_pend_flag = 0;
3765 init_timer(&timer);
3766 timer.expires = jiffies + timeout;
3767 timer.data = (unsigned long)hdw;
3768 timer.function = pvr2_ctl_timeout;
3769
3770 if (write_len) {
3771 hdw->cmd_debug_state = 2;
3772 /* Transfer write data to internal buffer */
3773 for (idx = 0; idx < write_len; idx++) {
3774 hdw->ctl_write_buffer[idx] =
3775 ((unsigned char *)write_data)[idx];
3776 }
3777 /* Initiate a write request */
3778 usb_fill_bulk_urb(hdw->ctl_write_urb,
3779 hdw->usb_dev,
3780 usb_sndbulkpipe(hdw->usb_dev,
3781 PVR2_CTL_WRITE_ENDPOINT),
3782 hdw->ctl_write_buffer,
3783 write_len,
3784 pvr2_ctl_write_complete,
3785 hdw);
3786 hdw->ctl_write_urb->actual_length = 0;
3787 hdw->ctl_write_pend_flag = !0;
3788 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3789 if (status < 0) {
3790 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3791 "Failed to submit write-control"
3792 " URB status=%d",status);
3793 hdw->ctl_write_pend_flag = 0;
3794 goto done;
3795 }
3796 }
3797
3798 if (read_len) {
3799 hdw->cmd_debug_state = 3;
3800 memset(hdw->ctl_read_buffer,0x43,read_len);
3801 /* Initiate a read request */
3802 usb_fill_bulk_urb(hdw->ctl_read_urb,
3803 hdw->usb_dev,
3804 usb_rcvbulkpipe(hdw->usb_dev,
3805 PVR2_CTL_READ_ENDPOINT),
3806 hdw->ctl_read_buffer,
3807 read_len,
3808 pvr2_ctl_read_complete,
3809 hdw);
3810 hdw->ctl_read_urb->actual_length = 0;
3811 hdw->ctl_read_pend_flag = !0;
3812 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3813 if (status < 0) {
3814 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3815 "Failed to submit read-control"
3816 " URB status=%d",status);
3817 hdw->ctl_read_pend_flag = 0;
3818 goto done;
3819 }
3820 }
3821
3822 /* Start timer */
3823 add_timer(&timer);
3824
3825 /* Now wait for all I/O to complete */
3826 hdw->cmd_debug_state = 4;
3827 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3828 wait_for_completion(&hdw->ctl_done);
3829 }
3830 hdw->cmd_debug_state = 5;
3831
3832 /* Stop timer */
3833 del_timer_sync(&timer);
3834
3835 hdw->cmd_debug_state = 6;
3836 status = 0;
3837
3838 if (hdw->ctl_timeout_flag) {
3839 status = -ETIMEDOUT;
3840 if (!probe_fl) {
3841 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3842 "Timed out control-write");
3843 }
3844 goto done;
3845 }
3846
3847 if (write_len) {
3848 /* Validate results of write request */
3849 if ((hdw->ctl_write_urb->status != 0) &&
3850 (hdw->ctl_write_urb->status != -ENOENT) &&
3851 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3852 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3853 /* USB subsystem is reporting some kind of failure
3854 on the write */
3855 status = hdw->ctl_write_urb->status;
3856 if (!probe_fl) {
3857 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3858 "control-write URB failure,"
3859 " status=%d",
3860 status);
3861 }
3862 goto done;
3863 }
3864 if (hdw->ctl_write_urb->actual_length < write_len) {
3865 /* Failed to write enough data */
3866 status = -EIO;
3867 if (!probe_fl) {
3868 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3869 "control-write URB short,"
3870 " expected=%d got=%d",
3871 write_len,
3872 hdw->ctl_write_urb->actual_length);
3873 }
3874 goto done;
3875 }
3876 }
3877 if (read_len) {
3878 /* Validate results of read request */
3879 if ((hdw->ctl_read_urb->status != 0) &&
3880 (hdw->ctl_read_urb->status != -ENOENT) &&
3881 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3882 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3883 /* USB subsystem is reporting some kind of failure
3884 on the read */
3885 status = hdw->ctl_read_urb->status;
3886 if (!probe_fl) {
3887 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3888 "control-read URB failure,"
3889 " status=%d",
3890 status);
3891 }
3892 goto done;
3893 }
3894 if (hdw->ctl_read_urb->actual_length < read_len) {
3895 /* Failed to read enough data */
3896 status = -EIO;
3897 if (!probe_fl) {
3898 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3899 "control-read URB short,"
3900 " expected=%d got=%d",
3901 read_len,
3902 hdw->ctl_read_urb->actual_length);
3903 }
3904 goto done;
3905 }
3906 /* Transfer retrieved data out from internal buffer */
3907 for (idx = 0; idx < read_len; idx++) {
3908 ((unsigned char *)read_data)[idx] =
3909 hdw->ctl_read_buffer[idx];
3910 }
3911 }
3912
3913 done:
3914
3915 hdw->cmd_debug_state = 0;
3916 if ((status < 0) && (!probe_fl)) {
681c7399 3917 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3918 }
3919 return status;
3920}
3921
3922
3923int pvr2_send_request(struct pvr2_hdw *hdw,
3924 void *write_data,unsigned int write_len,
3925 void *read_data,unsigned int read_len)
3926{
3927 return pvr2_send_request_ex(hdw,HZ*4,0,
3928 write_data,write_len,
3929 read_data,read_len);
3930}
3931
1c9d10d4
MI		 3932
3933static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3934{
3935 int ret;
3936 unsigned int cnt = 1;
3937 unsigned int args = 0;
3938 LOCK_TAKE(hdw->ctl_lock);
3939 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3940 args = (cmdcode >> 8) & 0xffu;
3941 args = (args > 2) ? 2 : args;
3942 if (args) {
3943 cnt += args;
3944 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3945 if (args > 1) {
3946 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3947 }
3948 }
3949 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3950 unsigned int idx;
3951 unsigned int ccnt,bcnt;
3952 char tbuf[50];
3953 cmdcode &= 0xffu;
3954 bcnt = 0;
3955 ccnt = scnprintf(tbuf+bcnt,
3956 sizeof(tbuf)-bcnt,
3957 "Sending FX2 command 0x%x",cmdcode);
3958 bcnt += ccnt;
3959 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3960 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3961 ccnt = scnprintf(tbuf+bcnt,
3962 sizeof(tbuf)-bcnt,
3963 " \"%s\"",
3964 pvr2_fx2cmd_desc[idx].desc);
3965 bcnt += ccnt;
3966 break;
3967 }
3968 }
3969 if (args) {
3970 ccnt = scnprintf(tbuf+bcnt,
3971 sizeof(tbuf)-bcnt,
3972 " (%u",hdw->cmd_buffer[1]);
3973 bcnt += ccnt;
3974 if (args > 1) {
3975 ccnt = scnprintf(tbuf+bcnt,
3976 sizeof(tbuf)-bcnt,
3977 ",%u",hdw->cmd_buffer[2]);
3978 bcnt += ccnt;
3979 }
3980 ccnt = scnprintf(tbuf+bcnt,
3981 sizeof(tbuf)-bcnt,
3982 ")");
3983 bcnt += ccnt;
3984 }
3985 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3986 }
3987 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3988 LOCK_GIVE(hdw->ctl_lock);
3989 return ret;
3990}
3991
3992
d855497e
MI		 3993int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3994{
3995 int ret;
3996
3997 LOCK_TAKE(hdw->ctl_lock);
3998
8d364363 3999 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 4000 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
4001 hdw->cmd_buffer[5] = 0;
4002 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4003 hdw->cmd_buffer[7] = reg & 0xff;
4004
4005
4006 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4007
4008 LOCK_GIVE(hdw->ctl_lock);
4009
4010 return ret;
4011}
4012
4013
07e337ee 4014static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 4015{
4016 int ret = 0;
4017
4018 LOCK_TAKE(hdw->ctl_lock);
4019
8d364363 4020 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 4021 hdw->cmd_buffer[1] = 0;
4022 hdw->cmd_buffer[2] = 0;
4023 hdw->cmd_buffer[3] = 0;
4024 hdw->cmd_buffer[4] = 0;
4025 hdw->cmd_buffer[5] = 0;
4026 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4027 hdw->cmd_buffer[7] = reg & 0xff;
4028
4029 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4030 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4031
4032 LOCK_GIVE(hdw->ctl_lock);
4033
4034 return ret;
4035}
4036
4037
681c7399 4038void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 4039{
4040 if (!hdw->flag_ok) return;
681c7399
MI		 4041 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4042 "Device being rendered inoperable");
d855497e 4043 if (hdw->vid_stream) {
a0fd1cb1 4044 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 4045 }
681c7399
MI		 4046 hdw->flag_ok = 0;
4047 trace_stbit("flag_ok",hdw->flag_ok);
4048 pvr2_hdw_state_sched(hdw);
d855497e
MI		 4049}
4050
4051
4052void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4053{
4054 int ret;
4055 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4056 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4057 if (ret == 0) {
d855497e
MI		 4058 ret = usb_reset_device(hdw->usb_dev);
4059 usb_unlock_device(hdw->usb_dev);
4060 } else {
4061 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4062 "Failed to lock USB device ret=%d",ret);
4063 }
4064 if (init_pause_msec) {
4065 pvr2_trace(PVR2_TRACE_INFO,
4066 "Waiting %u msec for hardware to settle",
4067 init_pause_msec);
4068 msleep(init_pause_msec);
4069 }
4070
4071}
4072
4073
4074void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4075{
4076 char da[1];
4077 unsigned int pipe;
4078 int ret;
4079
4080 if (!hdw->usb_dev) return;
4081
4082 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4083
4084 da[0] = val ? 0x01 : 0x00;
4085
4086 /* Write the CPUCS register on the 8051. The lsb of the register
4087 is the reset bit; a 1 asserts reset while a 0 clears it. */
4088 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4089 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4090 if (ret < 0) {
4091 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4092 "cpureset_assert(%d) error=%d",val,ret);
4093 pvr2_hdw_render_useless(hdw);
4094 }
4095}
4096
4097
4098int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4099{
1c9d10d4 4100 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4101}
4102
4103
e1edb19a
MK		 4104int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4105{
1c9d10d4 4106 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4107}
4108
1c9d10d4 4109
e1edb19a
MK		 4110int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4111{
1c9d10d4 4112 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4113}
4114
d855497e
MI		 4115
4116int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4117{
af78e16b
MI		 4118 pvr2_trace(PVR2_TRACE_INIT,
4119 "Requesting decoder reset");
af78e16b
MI		 4120 if (hdw->decoder_client_id) {
4121 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4122 core, reset, 0);
e17d787c 4123 pvr2_hdw_cx25840_vbi_hack(hdw);
af78e16b 4124 return 0;
d855497e 4125 }
d855497e 4126 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4127 "Unable to reset decoder: nothing attached");
4128 return -ENOTTY;
d855497e
MI		 4129}
4130
4131
62433e31 4132static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4133{
1c9d10d4
MI		 4134 hdw->flag_ok = !0;
4135 return pvr2_issue_simple_cmd(hdw,
4136 FX2CMD_HCW_DEMOD_RESETIN |
4137 (1 << 8) |
4138 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4139}
4140
84147f3d 4141
62433e31 4142static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4143{
1c9d10d4
MI		 4144 hdw->flag_ok = !0;
4145 return pvr2_issue_simple_cmd(hdw,(onoff ?
4146 FX2CMD_ONAIR_DTV_POWER_ON :
4147 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4148}
4149
62433e31
MI		 4150
4151static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4152 int onoff)
84147f3d 4153{
1c9d10d4
MI		 4154 return pvr2_issue_simple_cmd(hdw,(onoff ?
4155 FX2CMD_ONAIR_DTV_STREAMING_ON :
4156 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4157}
4158
62433e31
MI		 4159
4160static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4161{
4162 int cmode;
4163 /* Compare digital/analog desired setting with current setting. If
4164 they don't match, fix it... */
4165 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4166 if (cmode == hdw->pathway_state) {
4167 /* They match; nothing to do */
4168 return;
4169 }
4170
4171 switch (hdw->hdw_desc->digital_control_scheme) {
4172 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4173 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4174 if (cmode == PVR2_PATHWAY_ANALOG) {
4175 /* If moving to analog mode, also force the decoder
4176 to reset. If no decoder is attached, then it's
4177 ok to ignore this because if/when the decoder
4178 attaches, it will reset itself at that time. */
4179 pvr2_hdw_cmd_decoder_reset(hdw);
4180 }
4181 break;
4182 case PVR2_DIGITAL_SCHEME_ONAIR:
4183 /* Supposedly we should always have the power on whether in
4184 digital or analog mode. But for now do what appears to
4185 work... */
bb0c2fe0 4186 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4187 break;
4188 default: break;
4189 }
4190
1b9c18c5 4191 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4192 hdw->pathway_state = cmode;
4193}
4194
4195
e9b59f6e 4196static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4197{
4198 /* change some GPIO data
4199 *
4200 * note: bit d7 of dir appears to control the LED,
4201 * so we shut it off here.
4202 *
c55a97d7 4203 */
40381cb0 4204 if (onoff) {
c55a97d7 4205 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4206 } else {
c55a97d7 4207 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4208 }
c55a97d7 4209 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4210}
c55a97d7 4211
40381cb0
MI		 4212
4213typedef void (*led_method_func)(struct pvr2_hdw *,int);
4214
4215static led_method_func led_methods[] = {
4216 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4217};
4218
4219
4220/* Toggle LED */
4221static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4222{
4223 unsigned int scheme_id;
4224 led_method_func fp;
4225
4226 if ((!onoff) == (!hdw->led_on)) return;
4227
4228 hdw->led_on = onoff != 0;
4229
4230 scheme_id = hdw->hdw_desc->led_scheme;
4231 if (scheme_id < ARRAY_SIZE(led_methods)) {
4232 fp = led_methods[scheme_id];
4233 } else {
4234 fp = NULL;
4235 }
4236
4237 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4238}
4239
4240
e61b6fc5 4241/* Stop / start video stream transport */
07e337ee 4242static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4243{
bb0c2fe0
MI		 4244 int ret;
4245
4246 /* If we're in analog mode, then just issue the usual analog
4247 command. */
4248 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4249 return pvr2_issue_simple_cmd(hdw,
4250 (runFl ?
4251 FX2CMD_STREAMING_ON :
4252 FX2CMD_STREAMING_OFF));
4253 /*Note: Not reached */
4254 }
4255
4256 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4257 /* Whoops, we don't know what mode we're in... */
4258 return -EINVAL;
4259 }
4260
4261 /* To get here we have to be in digital mode. The mechanism here
4262 is unfortunately different for different vendors. So we switch
4263 on the device's digital scheme attribute in order to figure out
4264 what to do. */
4265 switch (hdw->hdw_desc->digital_control_scheme) {
4266 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4267 return pvr2_issue_simple_cmd(hdw,
4268 (runFl ?
4269 FX2CMD_HCW_DTV_STREAMING_ON :
4270 FX2CMD_HCW_DTV_STREAMING_OFF));
4271 case PVR2_DIGITAL_SCHEME_ONAIR:
4272 ret = pvr2_issue_simple_cmd(hdw,
4273 (runFl ?
4274 FX2CMD_STREAMING_ON :
4275 FX2CMD_STREAMING_OFF));
4276 if (ret) return ret;
4277 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4278 default:
4279 return -EINVAL;
62433e31 4280 }
d855497e
MI		 4281}
4282
4283
62433e31
MI		 4284/* Evaluate whether or not state_pathway_ok can change */
4285static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4286{
4287 if (hdw->state_pathway_ok) {
4288 /* Nothing to do if pathway is already ok */
4289 return 0;
4290 }
4291 if (!hdw->state_pipeline_idle) {
4292 /* Not allowed to change anything if pipeline is not idle */
4293 return 0;
4294 }
4295 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4296 hdw->state_pathway_ok = !0;
e9db1ff2 4297 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4298 return !0;
4299}
4300
4301
681c7399
MI		 4302/* Evaluate whether or not state_encoder_ok can change */
4303static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4304{
4305 if (hdw->state_encoder_ok) return 0;
4306 if (hdw->flag_tripped) return 0;
4307 if (hdw->state_encoder_run) return 0;
4308 if (hdw->state_encoder_config) return 0;
4309 if (hdw->state_decoder_run) return 0;
4310 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4311 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4312 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4313 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4314 return 0;
4315 }
4316
681c7399
MI		 4317 if (pvr2_upload_firmware2(hdw) < 0) {
4318 hdw->flag_tripped = !0;
4319 trace_stbit("flag_tripped",hdw->flag_tripped);
4320 return !0;
4321 }
4322 hdw->state_encoder_ok = !0;
4323 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4324 return !0;
4325}
4326
4327
4328/* Evaluate whether or not state_encoder_config can change */
4329static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4330{
4331 if (hdw->state_encoder_config) {
4332 if (hdw->state_encoder_ok) {
4333 if (hdw->state_pipeline_req &&
4334 !hdw->state_pipeline_pause) return 0;
4335 }
4336 hdw->state_encoder_config = 0;
4337 hdw->state_encoder_waitok = 0;
4338 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4339 /* paranoia - solve race if timer just completed */
4340 del_timer_sync(&hdw->encoder_wait_timer);
4341 } else {
62433e31
MI		 4342 if (!hdw->state_pathway_ok ||
4343 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4344 !hdw->state_encoder_ok ||
681c7399
MI		 4345 !hdw->state_pipeline_idle ||
4346 hdw->state_pipeline_pause ||
4347 !hdw->state_pipeline_req ||
4348 !hdw->state_pipeline_config) {
4349 /* We must reset the enforced wait interval if
4350 anything has happened that might have disturbed
4351 the encoder. This should be a rare case. */
4352 if (timer_pending(&hdw->encoder_wait_timer)) {
4353 del_timer_sync(&hdw->encoder_wait_timer);
4354 }
4355 if (hdw->state_encoder_waitok) {
4356 /* Must clear the state - therefore we did
4357 something to a state bit and must also
4358 return true. */
4359 hdw->state_encoder_waitok = 0;
4360 trace_stbit("state_encoder_waitok",
4361 hdw->state_encoder_waitok);
4362 return !0;
4363 }
4364 return 0;
4365 }
4366 if (!hdw->state_encoder_waitok) {
4367 if (!timer_pending(&hdw->encoder_wait_timer)) {
4368 /* waitok flag wasn't set and timer isn't
4369 running. Check flag once more to avoid
4370 a race then start the timer. This is
4371 the point when we measure out a minimal
4372 quiet interval before doing something to
4373 the encoder. */
4374 if (!hdw->state_encoder_waitok) {
4375 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4376 jiffies +
4377 (HZ * TIME_MSEC_ENCODER_WAIT
4378 / 1000);
681c7399
MI		 4379 add_timer(&hdw->encoder_wait_timer);
4380 }
4381 }
4382 /* We can't continue until we know we have been
4383 quiet for the interval measured by this
4384 timer. */
4385 return 0;
4386 }
4387 pvr2_encoder_configure(hdw);
4388 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4389 }
4390 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4391 return !0;
4392}
4393
4394
d913d630
MI		 4395/* Return true if the encoder should not be running. */
4396static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4397{
4398 if (!hdw->state_encoder_ok) {
4399 /* Encoder isn't healthy at the moment, so stop it. */
4400 return !0;
4401 }
4402 if (!hdw->state_pathway_ok) {
4403 /* Mode is not understood at the moment (i.e. it wants to
4404 change), so encoder must be stopped. */
4405 return !0;
4406 }
4407
4408 switch (hdw->pathway_state) {
4409 case PVR2_PATHWAY_ANALOG:
4410 if (!hdw->state_decoder_run) {
4411 /* We're in analog mode and the decoder is not
4412 running; thus the encoder should be stopped as
4413 well. */
4414 return !0;
4415 }
4416 break;
4417 case PVR2_PATHWAY_DIGITAL:
4418 if (hdw->state_encoder_runok) {
4419 /* This is a funny case. We're in digital mode so
4420 really the encoder should be stopped. However
4421 if it really is running, only kill it after
4422 runok has been set. This gives a chance for the
4423 onair quirk to function (encoder must run
4424 briefly first, at least once, before onair
4425 digital streaming can work). */
4426 return !0;
4427 }
4428 break;
4429 default:
4430 /* Unknown mode; so encoder should be stopped. */
4431 return !0;
4432 }
4433
4434 /* If we get here, we haven't found a reason to stop the
4435 encoder. */
4436 return 0;
4437}
4438
4439
4440/* Return true if the encoder should be running. */
4441static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4442{
4443 if (!hdw->state_encoder_ok) {
4444 /* Don't run the encoder if it isn't healthy... */
4445 return 0;
4446 }
4447 if (!hdw->state_pathway_ok) {
4448 /* Don't run the encoder if we don't (yet) know what mode
4449 we need to be in... */
4450 return 0;
4451 }
4452
4453 switch (hdw->pathway_state) {
4454 case PVR2_PATHWAY_ANALOG:
4455 if (hdw->state_decoder_run) {
4456 /* In analog mode, if the decoder is running, then
4457 run the encoder. */
4458 return !0;
4459 }
4460 break;
4461 case PVR2_PATHWAY_DIGITAL:
4462 if ((hdw->hdw_desc->digital_control_scheme ==
4463 PVR2_DIGITAL_SCHEME_ONAIR) &&
4464 !hdw->state_encoder_runok) {
4465 /* This is a quirk. OnAir hardware won't stream
4466 digital until the encoder has been run at least
4467 once, for a minimal period of time (empiricially
4468 measured to be 1/4 second). So if we're on
4469 OnAir hardware and the encoder has never been
4470 run at all, then start the encoder. Normal
4471 state machine logic in the driver will
4472 automatically handle the remaining bits. */
4473 return !0;
4474 }
4475 break;
4476 default:
4477 /* For completeness (unknown mode; encoder won't run ever) */
4478 break;
4479 }
4480 /* If we get here, then we haven't found any reason to run the
4481 encoder, so don't run it. */
4482 return 0;
4483}
4484
4485
681c7399
MI		 4486/* Evaluate whether or not state_encoder_run can change */
4487static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4488{
4489 if (hdw->state_encoder_run) {
d913d630 4490 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4491 if (hdw->state_encoder_ok) {
d913d630 4492 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4493 if (pvr2_encoder_stop(hdw) < 0) return !0;
4494 }
4495 hdw->state_encoder_run = 0;
4496 } else {
d913d630 4497 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4498 if (pvr2_encoder_start(hdw) < 0) return !0;
4499 hdw->state_encoder_run = !0;
d913d630
MI		 4500 if (!hdw->state_encoder_runok) {
4501 hdw->encoder_run_timer.expires =
83ce57aa 4502 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4503 add_timer(&hdw->encoder_run_timer);
4504 }
681c7399
MI		 4505 }
4506 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4507 return !0;
4508}
4509
4510
4511/* Timeout function for quiescent timer. */
4512static void pvr2_hdw_quiescent_timeout(unsigned long data)
4513{
4514 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4515 hdw->state_decoder_quiescent = !0;
4516 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4517 hdw->state_stale = !0;
4518 queue_work(hdw->workqueue,&hdw->workpoll);
4519}
4520
4521
4522/* Timeout function for encoder wait timer. */
4523static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4524{
4525 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4526 hdw->state_encoder_waitok = !0;
4527 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4528 hdw->state_stale = !0;
4529 queue_work(hdw->workqueue,&hdw->workpoll);
4530}
4531
4532
d913d630
MI		 4533/* Timeout function for encoder run timer. */
4534static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4535{
4536 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4537 if (!hdw->state_encoder_runok) {
4538 hdw->state_encoder_runok = !0;
4539 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4540 hdw->state_stale = !0;
4541 queue_work(hdw->workqueue,&hdw->workpoll);
4542 }
4543}
4544
4545
681c7399
MI		 4546/* Evaluate whether or not state_decoder_run can change */
4547static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4548{
4549 if (hdw->state_decoder_run) {
4550 if (hdw->state_encoder_ok) {
4551 if (hdw->state_pipeline_req &&
62433e31
MI		 4552 !hdw->state_pipeline_pause &&
4553 hdw->state_pathway_ok) return 0;
681c7399
MI		 4554 }
4555 if (!hdw->flag_decoder_missed) {
4556 pvr2_decoder_enable(hdw,0);
4557 }
4558 hdw->state_decoder_quiescent = 0;
4559 hdw->state_decoder_run = 0;
4560 /* paranoia - solve race if timer just completed */
4561 del_timer_sync(&hdw->quiescent_timer);
4562 } else {
4563 if (!hdw->state_decoder_quiescent) {
4564 if (!timer_pending(&hdw->quiescent_timer)) {
4565 /* We don't do something about the
4566 quiescent timer until right here because
4567 we also want to catch cases where the
4568 decoder was already not running (like
4569 after initialization) as opposed to
4570 knowing that we had just stopped it.
4571 The second flag check is here to cover a
4572 race - the timer could have run and set
4573 this flag just after the previous check
4574 but before we did the pending check. */
4575 if (!hdw->state_decoder_quiescent) {
4576 hdw->quiescent_timer.expires =
83ce57aa
MI		 4577 jiffies +
4578 (HZ * TIME_MSEC_DECODER_WAIT
4579 / 1000);
681c7399
MI		 4580 add_timer(&hdw->quiescent_timer);
4581 }
4582 }
4583 /* Don't allow decoder to start again until it has
4584 been quiesced first. This little detail should
4585 hopefully further stabilize the encoder. */
4586 return 0;
4587 }
62433e31
MI		 4588 if (!hdw->state_pathway_ok ||
4589 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4590 !hdw->state_pipeline_req ||
681c7399
MI		 4591 hdw->state_pipeline_pause ||
4592 !hdw->state_pipeline_config ||
4593 !hdw->state_encoder_config ||
4594 !hdw->state_encoder_ok) return 0;
4595 del_timer_sync(&hdw->quiescent_timer);
4596 if (hdw->flag_decoder_missed) return 0;
4597 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4598 hdw->state_decoder_quiescent = 0;
4599 hdw->state_decoder_run = !0;
4600 }
4601 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4602 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4603 return !0;
4604}
4605
4606
4607/* Evaluate whether or not state_usbstream_run can change */
4608static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4609{
4610 if (hdw->state_usbstream_run) {
72998b71 4611 int fl = !0;
62433e31 4612 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4613 fl = (hdw->state_encoder_ok &&
4614 hdw->state_encoder_run);
4615 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4616 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4617 fl = hdw->state_encoder_ok;
4618 }
4619 if (fl &&
4620 hdw->state_pipeline_req &&
4621 !hdw->state_pipeline_pause &&
4622 hdw->state_pathway_ok) {
4623 return 0;
681c7399
MI		 4624 }
4625 pvr2_hdw_cmd_usbstream(hdw,0);
4626 hdw->state_usbstream_run = 0;
4627 } else {
62433e31
MI		 4628 if (!hdw->state_pipeline_req ||
4629 hdw->state_pipeline_pause ||
4630 !hdw->state_pathway_ok) return 0;
4631 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4632 if (!hdw->state_encoder_ok ||
4633 !hdw->state_encoder_run) return 0;
72998b71
MI		 4634 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4635 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4636 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4637 if (hdw->state_encoder_run) return 0;
4638 if (hdw->hdw_desc->digital_control_scheme ==
4639 PVR2_DIGITAL_SCHEME_ONAIR) {
4640 /* OnAir digital receivers won't stream
4641 unless the analog encoder has run first.
4642 Why? I have no idea. But don't even
4643 try until we know the analog side is
4644 known to have run. */
4645 if (!hdw->state_encoder_runok) return 0;
4646 }
62433e31 4647 }
681c7399
MI		 4648 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4649 hdw->state_usbstream_run = !0;
4650 }
4651 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4652 return !0;
4653}
4654
4655
4656/* Attempt to configure pipeline, if needed */
4657static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4658{
4659 if (hdw->state_pipeline_config ||
4660 hdw->state_pipeline_pause) return 0;
4661 pvr2_hdw_commit_execute(hdw);
4662 return !0;
4663}
4664
4665
4666/* Update pipeline idle and pipeline pause tracking states based on other
4667 inputs. This must be called whenever the other relevant inputs have
4668 changed. */
4669static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4670{
4671 unsigned int st;
4672 int updatedFl = 0;
4673 /* Update pipeline state */
4674 st = !(hdw->state_encoder_run ||
4675 hdw->state_decoder_run ||
4676 hdw->state_usbstream_run ||
4677 (!hdw->state_decoder_quiescent));
4678 if (!st != !hdw->state_pipeline_idle) {
4679 hdw->state_pipeline_idle = st;
4680 updatedFl = !0;
4681 }
4682 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4683 hdw->state_pipeline_pause = 0;
4684 updatedFl = !0;
4685 }
4686 return updatedFl;
4687}
4688
4689
4690typedef int (*state_eval_func)(struct pvr2_hdw *);
4691
4692/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4693static const state_eval_func eval_funcs[] = {
62433e31 4694 state_eval_pathway_ok,
681c7399
MI		 4695 state_eval_pipeline_config,
4696 state_eval_encoder_ok,
4697 state_eval_encoder_config,
4698 state_eval_decoder_run,
4699 state_eval_encoder_run,
4700 state_eval_usbstream_run,
4701};
4702
4703
4704/* Process various states and return true if we did anything interesting. */
4705static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4706{
4707 unsigned int i;
4708 int state_updated = 0;
4709 int check_flag;
4710
4711 if (!hdw->state_stale) return 0;
4712 if ((hdw->fw1_state != FW1_STATE_OK) ||
4713 !hdw->flag_ok) {
4714 hdw->state_stale = 0;
4715 return !0;
4716 }
4717 /* This loop is the heart of the entire driver. It keeps trying to
4718 evaluate various bits of driver state until nothing changes for
4719 one full iteration. Each "bit of state" tracks some global
4720 aspect of the driver, e.g. whether decoder should run, if
4721 pipeline is configured, usb streaming is on, etc. We separately
4722 evaluate each of those questions based on other driver state to
4723 arrive at the correct running configuration. */
4724 do {
4725 check_flag = 0;
4726 state_update_pipeline_state(hdw);
4727 /* Iterate over each bit of state */
4728 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4729 if ((*eval_funcs[i])(hdw)) {
4730 check_flag = !0;
4731 state_updated = !0;
4732 state_update_pipeline_state(hdw);
4733 }
4734 }
4735 } while (check_flag && hdw->flag_ok);
4736 hdw->state_stale = 0;
4737 trace_stbit("state_stale",hdw->state_stale);
4738 return state_updated;
4739}
4740
4741
1cb03b76
MI		 4742static unsigned int print_input_mask(unsigned int msk,
4743 char *buf,unsigned int acnt)
4744{
4745 unsigned int idx,ccnt;
4746 unsigned int tcnt = 0;
4747 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4748 if (!((1 << idx) & msk)) continue;
4749 ccnt = scnprintf(buf+tcnt,
4750 acnt-tcnt,
4751 "%s%s",
4752 (tcnt ? ", " : ""),
4753 control_values_input[idx]);
4754 tcnt += ccnt;
4755 }
4756 return tcnt;
4757}
4758
4759
62433e31
MI		 4760static const char *pvr2_pathway_state_name(int id)
4761{
4762 switch (id) {
4763 case PVR2_PATHWAY_ANALOG: return "analog";
4764 case PVR2_PATHWAY_DIGITAL: return "digital";
4765 default: return "unknown";
4766 }
4767}
4768
4769
681c7399
MI		 4770static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4771 char *buf,unsigned int acnt)
4772{
4773 switch (which) {
4774 case 0:
4775 return scnprintf(
4776 buf,acnt,
e9db1ff2 4777 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4778 (hdw->flag_ok ? " <ok>" : " <fail>"),
4779 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4780 (hdw->flag_disconnected ? " <disconnected>" :
4781 " <connected>"),
4782 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4783 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4784 pvr2_pathway_state_name(hdw->pathway_state));
4785
681c7399
MI		 4786 case 1:
4787 return scnprintf(
4788 buf,acnt,
4789 "pipeline:%s%s%s%s",
4790 (hdw->state_pipeline_idle ? " <idle>" : ""),
4791 (hdw->state_pipeline_config ?
4792 " <configok>" : " <stale>"),
4793 (hdw->state_pipeline_req ? " <req>" : ""),
4794 (hdw->state_pipeline_pause ? " <pause>" : ""));
4795 case 2:
4796 return scnprintf(
4797 buf,acnt,
62433e31 4798 "worker:%s%s%s%s%s%s%s",
681c7399
MI		 4799 (hdw->state_decoder_run ?
4800 " <decode:run>" :
4801 (hdw->state_decoder_quiescent ?
4802 "" : " <decode:stop>")),
4803 (hdw->state_decoder_quiescent ?
4804 " <decode:quiescent>" : ""),
4805 (hdw->state_encoder_ok ?
4806 "" : " <encode:init>"),
4807 (hdw->state_encoder_run ?
d913d630
MI		 4808 (hdw->state_encoder_runok ?
4809 " <encode:run>" :
4810 " <encode:firstrun>") :
4811 (hdw->state_encoder_runok ?
4812 " <encode:stop>" :
4813 " <encode:virgin>")),
681c7399
MI		 4814 (hdw->state_encoder_config ?
4815 " <encode:configok>" :
4816 (hdw->state_encoder_waitok ?
b9a37d91 4817 "" : " <encode:waitok>")),
681c7399 4818 (hdw->state_usbstream_run ?
62433e31
MI		 4819 " <usb:run>" : " <usb:stop>"),
4820 (hdw->state_pathway_ok ?
e9db1ff2 4821 " <pathway:ok>" : ""));
681c7399
MI		 4822 case 3:
4823 return scnprintf(
4824 buf,acnt,
4825 "state: %s",
4826 pvr2_get_state_name(hdw->master_state));
ad0992e9 4827 case 4: {
1cb03b76
MI		 4828 unsigned int tcnt = 0;
4829 unsigned int ccnt;
4830
4831 ccnt = scnprintf(buf,
4832 acnt,
4833 "Hardware supported inputs: ");
4834 tcnt += ccnt;
4835 tcnt += print_input_mask(hdw->input_avail_mask,
4836 buf+tcnt,
4837 acnt-tcnt);
4838 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4839 ccnt = scnprintf(buf+tcnt,
4840 acnt-tcnt,
4841 "; allowed inputs: ");
4842 tcnt += ccnt;
4843 tcnt += print_input_mask(hdw->input_allowed_mask,
4844 buf+tcnt,
4845 acnt-tcnt);
4846 }
4847 return tcnt;
4848 }
4849 case 5: {
ad0992e9
MI		 4850 struct pvr2_stream_stats stats;
4851 if (!hdw->vid_stream) break;
4852 pvr2_stream_get_stats(hdw->vid_stream,
4853 &stats,
4854 0);
4855 return scnprintf(
4856 buf,acnt,
4857 "Bytes streamed=%u"
4858 " URBs: queued=%u idle=%u ready=%u"
4859 " processed=%u failed=%u",
4860 stats.bytes_processed,
4861 stats.buffers_in_queue,
4862 stats.buffers_in_idle,
4863 stats.buffers_in_ready,
4864 stats.buffers_processed,
4865 stats.buffers_failed);
4866 }
27eab384
MI		 4867 case 6: {
4868 unsigned int id = hdw->ir_scheme_active;
4869 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4870 (id >= ARRAY_SIZE(ir_scheme_names) ?
4871 "?" : ir_scheme_names[id]));
4872 }
2eb563b7
MI		 4873 default: break;
4874 }
4875 return 0;
4876}
4877
4878
4879/* Generate report containing info about attached sub-devices and attached
4880 i2c clients, including an indication of which attached i2c clients are
4881 actually sub-devices. */
4882static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4883 char *buf, unsigned int acnt)
4884{
4885 struct v4l2_subdev *sd;
4886 unsigned int tcnt = 0;
4887 unsigned int ccnt;
4888 struct i2c_client *client;
2eb563b7
MI		 4889 const char *p;
4890 unsigned int id;
4891
fa7ce764 4892 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
2eb563b7
MI		 4893 tcnt += ccnt;
4894 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4895 id = sd->grp_id;
4896 p = NULL;
4897 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4898 if (p) {
fa7ce764 4899 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
2eb563b7
MI		 4900 tcnt += ccnt;
4901 } else {
4902 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
fa7ce764 4903 " (unknown id=%u):", id);
2eb563b7
MI		 4904 tcnt += ccnt;
4905 }
fa7ce764
JD		 4906 client = v4l2_get_subdevdata(sd);
4907 if (client) {
4908 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4909 " %s @ %02x\n", client->name,
4910 client->addr);
4911 tcnt += ccnt;
4912 } else {
4913 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4914 " no i2c client\n");
4915 tcnt += ccnt;
858f910e 4916 }
681c7399 4917 }
2eb563b7 4918 return tcnt;
681c7399
MI		 4919}
4920
4921
4922unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4923 char *buf,unsigned int acnt)
4924{
4925 unsigned int bcnt,ccnt,idx;
4926 bcnt = 0;
4927 LOCK_TAKE(hdw->big_lock);
4928 for (idx = 0; ; idx++) {
4929 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4930 if (!ccnt) break;
4931 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4932 if (!acnt) break;
4933 buf[0] = '\n'; ccnt = 1;
4934 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4935 }
2eb563b7
MI		 4936 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4937 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
681c7399
MI		 4938 LOCK_GIVE(hdw->big_lock);
4939 return bcnt;
4940}
4941
4942
4943static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4944{
2eb563b7
MI		 4945 char buf[256];
4946 unsigned int idx, ccnt;
4947 unsigned int lcnt, ucnt;
681c7399
MI		 4948
4949 for (idx = 0; ; idx++) {
4950 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4951 if (!ccnt) break;
4952 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4953 }
2eb563b7
MI		 4954 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4955 ucnt = 0;
4956 while (ucnt < ccnt) {
4957 lcnt = 0;
4958 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4959 lcnt++;
4960 }
4961 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4962 ucnt += lcnt + 1;
4963 }
681c7399
MI		 4964}
4965
4966
4967/* Evaluate and update the driver's current state, taking various actions
4968 as appropriate for the update. */
4969static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4970{
4971 unsigned int st;
4972 int state_updated = 0;
4973 int callback_flag = 0;
1b9c18c5 4974 int analog_mode;
681c7399
MI		 4975
4976 pvr2_trace(PVR2_TRACE_STBITS,
4977 "Drive state check START");
4978 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4979 pvr2_hdw_state_log_state(hdw);
4980 }
4981
4982 /* Process all state and get back over disposition */
4983 state_updated = pvr2_hdw_state_update(hdw);
4984
1b9c18c5
MI		 4985 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4986
681c7399
MI		 4987 /* Update master state based upon all other states. */
4988 if (!hdw->flag_ok) {
4989 st = PVR2_STATE_DEAD;
4990 } else if (hdw->fw1_state != FW1_STATE_OK) {
4991 st = PVR2_STATE_COLD;
72998b71
MI		 4992 } else if ((analog_mode ||
4993 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4994 !hdw->state_encoder_ok) {
681c7399 4995 st = PVR2_STATE_WARM;
1b9c18c5
MI		 4996 } else if (hdw->flag_tripped ||
4997 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 4998 st = PVR2_STATE_ERROR;
62433e31 4999 } else if (hdw->state_usbstream_run &&
1b9c18c5 5000 (!analog_mode ||
62433e31 5001 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 5002 st = PVR2_STATE_RUN;
5003 } else {
5004 st = PVR2_STATE_READY;
5005 }
5006 if (hdw->master_state != st) {
5007 pvr2_trace(PVR2_TRACE_STATE,
5008 "Device state change from %s to %s",
5009 pvr2_get_state_name(hdw->master_state),
5010 pvr2_get_state_name(st));
40381cb0 5011 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 5012 hdw->master_state = st;
5013 state_updated = !0;
5014 callback_flag = !0;
5015 }
5016 if (state_updated) {
5017 /* Trigger anyone waiting on any state changes here. */
5018 wake_up(&hdw->state_wait_data);
5019 }
5020
5021 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5022 pvr2_hdw_state_log_state(hdw);
5023 }
5024 pvr2_trace(PVR2_TRACE_STBITS,
5025 "Drive state check DONE callback=%d",callback_flag);
5026
5027 return callback_flag;
5028}
5029
5030
5031/* Cause kernel thread to check / update driver state */
5032static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5033{
5034 if (hdw->state_stale) return;
5035 hdw->state_stale = !0;
5036 trace_stbit("state_stale",hdw->state_stale);
5037 queue_work(hdw->workqueue,&hdw->workpoll);
5038}
5039
5040
d855497e
MI		 5041int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5042{
5043 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5044}
5045
5046
5047int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5048{
5049 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5050}
5051
5052
5053int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5054{
5055 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5056}
5057
5058
5059int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5060{
5061 u32 cval,nval;
5062 int ret;
5063 if (~msk) {
5064 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5065 if (ret) return ret;
5066 nval = (cval & ~msk) | (val & msk);
5067 pvr2_trace(PVR2_TRACE_GPIO,
5068 "GPIO direction changing 0x%x:0x%x"
5069 " from 0x%x to 0x%x",
5070 msk,val,cval,nval);
5071 } else {
5072 nval = val;
5073 pvr2_trace(PVR2_TRACE_GPIO,
5074 "GPIO direction changing to 0x%x",nval);
5075 }
5076 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5077}
5078
5079
5080int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5081{
5082 u32 cval,nval;
5083 int ret;
5084 if (~msk) {
5085 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5086 if (ret) return ret;
5087 nval = (cval & ~msk) | (val & msk);
5088 pvr2_trace(PVR2_TRACE_GPIO,
5089 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5090 msk,val,cval,nval);
5091 } else {
5092 nval = val;
5093 pvr2_trace(PVR2_TRACE_GPIO,
5094 "GPIO output changing to 0x%x",nval);
5095 }
5096 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5097}
5098
5099
a51f5000
MI		 5100void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5101{
40f07111
MI		 5102 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5103 memset(vtp, 0, sizeof(*vtp));
2641df36 5104 hdw->tuner_signal_stale = 0;
40f07111
MI		 5105 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5106 using v4l2-subdev - therefore we can't support that AT ALL right
5107 now. (Of course, no sub-drivers seem to implement it either.
5108 But now it's a a chicken and egg problem...) */
5109 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5110 &hdw->tuner_signal_info);
2641df36 5111 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5112 " type=%u strength=%u audio=0x%x cap=0x%x"
5113 " low=%u hi=%u",
5114 vtp->type,
5115 vtp->signal, vtp->rxsubchans, vtp->capability,
5116 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5117
5118 /* We have to do this to avoid getting into constant polling if
5119 there's nobody to answer a poll of cropcap info. */
5120 hdw->cropcap_stale = 0;
a51f5000
MI		 5121}
5122
5123
7fb20fa3
MI		 5124unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5125{
5126 return hdw->input_avail_mask;
5127}
5128
5129
1cb03b76
MI		 5130unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5131{
5132 return hdw->input_allowed_mask;
5133}
5134
5135
5136static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5137{
5138 if (hdw->input_val != v) {
5139 hdw->input_val = v;
5140 hdw->input_dirty = !0;
5141 }
5142
5143 /* Handle side effects - if we switch to a mode that needs the RF
5144 tuner, then select the right frequency choice as well and mark
5145 it dirty. */
5146 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5147 hdw->freqSelector = 0;
5148 hdw->freqDirty = !0;
5149 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5150 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5151 hdw->freqSelector = 1;
5152 hdw->freqDirty = !0;
5153 }
5154 return 0;
5155}
5156
5157
5158int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5159 unsigned int change_mask,
5160 unsigned int change_val)
5161{
5162 int ret = 0;
5163 unsigned int nv,m,idx;
5164 LOCK_TAKE(hdw->big_lock);
5165 do {
5166 nv = hdw->input_allowed_mask & ~change_mask;
5167 nv |= (change_val & change_mask);
5168 nv &= hdw->input_avail_mask;
5169 if (!nv) {
5170 /* No legal modes left; return error instead. */
5171 ret = -EPERM;
5172 break;
5173 }
5174 hdw->input_allowed_mask = nv;
5175 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5176 /* Current mode is still in the allowed mask, so
5177 we're done. */
5178 break;
5179 }
5180 /* Select and switch to a mode that is still in the allowed
5181 mask */
5182 if (!hdw->input_allowed_mask) {
5183 /* Nothing legal; give up */
5184 break;
5185 }
5186 m = hdw->input_allowed_mask;
5187 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5188 if (!((1 << idx) & m)) continue;
5189 pvr2_hdw_set_input(hdw,idx);
5190 break;
5191 }
5192 } while (0);
5193 LOCK_GIVE(hdw->big_lock);
5194 return ret;
5195}
5196
5197
e61b6fc5 5198/* Find I2C address of eeprom */
07e337ee 5199static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5200{
5201 int result;
5202 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5203 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5204 result = pvr2_send_request(hdw,
5205 hdw->cmd_buffer,1,
5206 hdw->cmd_buffer,1);
5207 if (result < 0) break;
5208 result = hdw->cmd_buffer[0];
5209 } while(0); LOCK_GIVE(hdw->ctl_lock);
5210 return result;
5211}
5212
5213
32ffa9ae 5214int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5215 struct v4l2_dbg_match *match, u64 reg_id,
5216 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5217{
5218#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 5219 struct v4l2_dbg_register req;
6d98816f
MI		 5220 int stat = 0;
5221 int okFl = 0;
32ffa9ae 5222
201f5c9c
MI		 5223 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5224
aecde8b5 5225 req.match = *match;
32ffa9ae
MI		 5226 req.reg = reg_id;
5227 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5228 /* It would be nice to know if a sub-device answered the request */
5229 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5230 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5231 if (okFl) {
5232 return stat;
5233 }
32ffa9ae
MI		 5234 return -EINVAL;
5235#else
5236 return -ENOSYS;
5237#endif
5238}
5239
5240
d855497e
MI		 5241/*
5242 Stuff for Emacs to see, in order to encourage consistent editing style:
5243 *** Local Variables: ***
5244 *** mode: c ***
5245 *** fill-column: 75 ***
5246 *** tab-width: 8 ***
5247 *** c-basic-offset: 8 ***
5248 *** End: ***
5249 */
Linux kernel - Deliverables
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