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[media] saa7115: Fix standards detection
[deliverable/linux.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
75212a02 27#include <media/tuner.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
d855497e
MI		 33#include "pvrusb2-eeprom.h"
34#include "pvrusb2-hdw-internal.h"
35#include "pvrusb2-encoder.h"
36#include "pvrusb2-debug.h"
8d364363 37#include "pvrusb2-fx2-cmd.h"
5f6dae80 38#include "pvrusb2-wm8775.h"
6f956512 39#include "pvrusb2-video-v4l.h"
634ba268 40#include "pvrusb2-cx2584x-v4l.h"
2a6b627f 41#include "pvrusb2-cs53l32a.h"
76891d65 42#include "pvrusb2-audio.h"
d855497e 43
1bde0289
MI		 44#define TV_MIN_FREQ 55250000L
45#define TV_MAX_FREQ 850000000L
25d8527a 46
83ce57aa
MI		 47/* This defines a minimum interval that the decoder must remain quiet
48 before we are allowed to start it running. */
49#define TIME_MSEC_DECODER_WAIT 50
50
6e931375
MI		 51/* This defines a minimum interval that the decoder must be allowed to run
52 before we can safely begin using its streaming output. */
53#define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
54
83ce57aa 55/* This defines a minimum interval that the encoder must remain quiet
91b5b489
MI		 56 before we are allowed to configure it. */
57#define TIME_MSEC_ENCODER_WAIT 50
83ce57aa
MI		 58
59/* This defines the minimum interval that the encoder must successfully run
60 before we consider that the encoder has run at least once since its
61 firmware has been loaded. This measurement is in important for cases
62 where we can't do something until we know that the encoder has been run
63 at least once. */
64#define TIME_MSEC_ENCODER_OK 250
65
a0fd1cb1 66static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 67static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 68
ff699e6b 69static int ctlchg;
ff699e6b 70static int procreload;
d855497e
MI		 71static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
72static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
73static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 74static int init_pause_msec;
d855497e
MI		 75
76module_param(ctlchg, int, S_IRUGO|S_IWUSR);
77MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
78module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
79MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 80module_param(procreload, int, S_IRUGO|S_IWUSR);
81MODULE_PARM_DESC(procreload,
82 "Attempt init failure recovery with firmware reload");
83module_param_array(tuner, int, NULL, 0444);
84MODULE_PARM_DESC(tuner,"specify installed tuner type");
85module_param_array(video_std, int, NULL, 0444);
86MODULE_PARM_DESC(video_std,"specify initial video standard");
87module_param_array(tolerance, int, NULL, 0444);
88MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
89
6f441ed7
MI		 90/* US Broadcast channel 3 (61.25 MHz), to help with testing */
91static int default_tv_freq = 61250000L;
5a4f5da6
MK		 92/* 104.3 MHz, a usable FM station for my area */
93static int default_radio_freq = 104300000L;
94
95module_param_named(tv_freq, default_tv_freq, int, 0444);
96MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
97module_param_named(radio_freq, default_radio_freq, int, 0444);
98MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
99
d855497e
MI		 100#define PVR2_CTL_WRITE_ENDPOINT 0x01
101#define PVR2_CTL_READ_ENDPOINT 0x81
102
103#define PVR2_GPIO_IN 0x9008
104#define PVR2_GPIO_OUT 0x900c
105#define PVR2_GPIO_DIR 0x9020
106
107#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
108
109#define PVR2_FIRMWARE_ENDPOINT 0x02
110
111/* size of a firmware chunk */
112#define FIRMWARE_CHUNK_SIZE 0x2000
113
edb9dcb8
MI		 114typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
115 struct v4l2_subdev *);
116
117static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 118 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 119 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 120 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 121 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
2a6b627f 122 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
edb9dcb8
MI		 123};
124
e9c64a78
MI		 125static const char *module_names[] = {
126 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
127 [PVR2_CLIENT_ID_CX25840] = "cx25840",
128 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
129 [PVR2_CLIENT_ID_TUNER] = "tuner",
bb65242a 130 [PVR2_CLIENT_ID_DEMOD] = "tuner",
851981a1 131 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
5f6dae80 132 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 133};
134
135
136static const unsigned char *module_i2c_addresses[] = {
137 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
bb65242a 138 [PVR2_CLIENT_ID_DEMOD] = "\x43",
1dfe6c77
MI		 139 [PVR2_CLIENT_ID_MSP3400] = "\x40",
140 [PVR2_CLIENT_ID_SAA7115] = "\x21",
ae111f76 141 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 142 [PVR2_CLIENT_ID_CX25840] = "\x44",
23334a22 143 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
e9c64a78
MI		 144};
145
146
27eab384
MI		 147static const char *ir_scheme_names[] = {
148 [PVR2_IR_SCHEME_NONE] = "none",
149 [PVR2_IR_SCHEME_29XXX] = "29xxx",
150 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
151 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
152 [PVR2_IR_SCHEME_ZILOG] = "Zilog",
153};
154
155
b30d2441
MI		 156/* Define the list of additional controls we'll dynamically construct based
157 on query of the cx2341x module. */
158struct pvr2_mpeg_ids {
159 const char *strid;
160 int id;
161};
162static const struct pvr2_mpeg_ids mpeg_ids[] = {
163 {
164 .strid = "audio_layer",
165 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
166 },{
167 .strid = "audio_bitrate",
168 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
169 },{
170 /* Already using audio_mode elsewhere :-( */
171 .strid = "mpeg_audio_mode",
172 .id = V4L2_CID_MPEG_AUDIO_MODE,
173 },{
174 .strid = "mpeg_audio_mode_extension",
175 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
176 },{
177 .strid = "audio_emphasis",
178 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
179 },{
180 .strid = "audio_crc",
181 .id = V4L2_CID_MPEG_AUDIO_CRC,
182 },{
183 .strid = "video_aspect",
184 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
185 },{
186 .strid = "video_b_frames",
187 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
188 },{
189 .strid = "video_gop_size",
190 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
191 },{
192 .strid = "video_gop_closure",
193 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 194 },{
195 .strid = "video_bitrate_mode",
196 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
197 },{
198 .strid = "video_bitrate",
199 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
200 },{
201 .strid = "video_bitrate_peak",
202 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
203 },{
204 .strid = "video_temporal_decimation",
205 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
206 },{
207 .strid = "stream_type",
208 .id = V4L2_CID_MPEG_STREAM_TYPE,
209 },{
210 .strid = "video_spatial_filter_mode",
211 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
212 },{
213 .strid = "video_spatial_filter",
214 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
215 },{
216 .strid = "video_luma_spatial_filter_type",
217 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
218 },{
219 .strid = "video_chroma_spatial_filter_type",
220 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
221 },{
222 .strid = "video_temporal_filter_mode",
223 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
224 },{
225 .strid = "video_temporal_filter",
226 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
227 },{
228 .strid = "video_median_filter_type",
229 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
230 },{
231 .strid = "video_luma_median_filter_top",
232 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
233 },{
234 .strid = "video_luma_median_filter_bottom",
235 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
236 },{
237 .strid = "video_chroma_median_filter_top",
238 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
239 },{
240 .strid = "video_chroma_median_filter_bottom",
241 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
242 }
243};
eca8ebfc 244#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 245
434449f4 246
d855497e 247static const char *control_values_srate[] = {
434449f4
MI		 248 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
249 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
250 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 251};
252
253
d855497e 254
d855497e
MI		 255static const char *control_values_input[] = {
256 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 257 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 258 [PVR2_CVAL_INPUT_RADIO] = "radio",
259 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
260 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
261};
262
263
264static const char *control_values_audiomode[] = {
265 [V4L2_TUNER_MODE_MONO] = "Mono",
266 [V4L2_TUNER_MODE_STEREO] = "Stereo",
267 [V4L2_TUNER_MODE_LANG1] = "Lang1",
268 [V4L2_TUNER_MODE_LANG2] = "Lang2",
269 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
270};
271
272
273static const char *control_values_hsm[] = {
274 [PVR2_CVAL_HSM_FAIL] = "Fail",
275 [PVR2_CVAL_HSM_HIGH] = "High",
276 [PVR2_CVAL_HSM_FULL] = "Full",
277};
278
279
681c7399
MI		 280static const char *pvr2_state_names[] = {
281 [PVR2_STATE_NONE] = "none",
282 [PVR2_STATE_DEAD] = "dead",
283 [PVR2_STATE_COLD] = "cold",
284 [PVR2_STATE_WARM] = "warm",
285 [PVR2_STATE_ERROR] = "error",
286 [PVR2_STATE_READY] = "ready",
287 [PVR2_STATE_RUN] = "run",
d855497e
MI		 288};
289
681c7399 290
694dca2b 291struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 292 unsigned char id;
293 unsigned char *desc;
294};
295
694dca2b 296static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 297 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
298 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 299 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 300 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
301 {FX2CMD_REG_WRITE, "write encoder register"},
302 {FX2CMD_REG_READ, "read encoder register"},
303 {FX2CMD_MEMSEL, "encoder memsel"},
304 {FX2CMD_I2C_WRITE, "i2c write"},
305 {FX2CMD_I2C_READ, "i2c read"},
306 {FX2CMD_GET_USB_SPEED, "get USB speed"},
307 {FX2CMD_STREAMING_ON, "stream on"},
308 {FX2CMD_STREAMING_OFF, "stream off"},
309 {FX2CMD_FWPOST1, "fwpost1"},
310 {FX2CMD_POWER_OFF, "power off"},
311 {FX2CMD_POWER_ON, "power on"},
312 {FX2CMD_DEEP_RESET, "deep reset"},
313 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
314 {FX2CMD_GET_IR_CODE, "get IR code"},
315 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
316 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
317 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
318 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
319 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
320 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
321 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
322};
323
324
1cb03b76 325static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 326static void pvr2_hdw_state_sched(struct pvr2_hdw *);
327static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 328static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399 329static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 330static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
331static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
332static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 333static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 334static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 335static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 336static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
337static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399 338static void pvr2_hdw_quiescent_timeout(unsigned long);
6e931375 339static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
681c7399 340static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 341static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 342static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 343static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
344 unsigned int timeout,int probe_fl,
345 void *write_data,unsigned int write_len,
346 void *read_data,unsigned int read_len);
432907f7 347static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 348
681c7399
MI		 349
350static void trace_stbit(const char *name,int val)
351{
352 pvr2_trace(PVR2_TRACE_STBITS,
353 "State bit %s <-- %s",
354 name,(val ? "true" : "false"));
355}
356
d855497e
MI		 357static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
358{
359 struct pvr2_hdw *hdw = cptr->hdw;
360 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
361 *vp = hdw->freqTable[hdw->freqProgSlot-1];
362 } else {
363 *vp = 0;
364 }
365 return 0;
366}
367
368static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
369{
370 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 371 unsigned int slotId = hdw->freqProgSlot;
372 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
373 hdw->freqTable[slotId-1] = v;
374 /* Handle side effects correctly - if we're tuned to this
375 slot, then forgot the slot id relation since the stored
376 frequency has been changed. */
377 if (hdw->freqSelector) {
378 if (hdw->freqSlotRadio == slotId) {
379 hdw->freqSlotRadio = 0;
380 }
381 } else {
382 if (hdw->freqSlotTelevision == slotId) {
383 hdw->freqSlotTelevision = 0;
384 }
385 }
d855497e
MI		 386 }
387 return 0;
388}
389
390static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
391{
392 *vp = cptr->hdw->freqProgSlot;
393 return 0;
394}
395
396static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
397{
398 struct pvr2_hdw *hdw = cptr->hdw;
399 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
400 hdw->freqProgSlot = v;
401 }
402 return 0;
403}
404
405static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
406{
1bde0289
MI		 407 struct pvr2_hdw *hdw = cptr->hdw;
408 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 409 return 0;
410}
411
1bde0289 412static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 413{
414 unsigned freq = 0;
415 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 416 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
417 if (slotId > 0) {
418 freq = hdw->freqTable[slotId-1];
419 if (!freq) return 0;
420 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 421 }
1bde0289
MI		 422 if (hdw->freqSelector) {
423 hdw->freqSlotRadio = slotId;
424 } else {
425 hdw->freqSlotTelevision = slotId;
d855497e
MI		 426 }
427 return 0;
428}
429
430static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
431{
1bde0289 432 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 433 return 0;
434}
435
436static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
437{
438 return cptr->hdw->freqDirty != 0;
439}
440
441static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
442{
443 cptr->hdw->freqDirty = 0;
444}
445
446static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
447{
1bde0289 448 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 449 return 0;
450}
451
e784bfb9 452static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
453{
432907f7
MI		 454 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
455 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
456 if (stat != 0) {
432907f7 457 return stat;
e784bfb9 458 }
432907f7 459 *left = cap->bounds.left;
e784bfb9 460 return 0;
461}
462
463static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
464{
432907f7
MI		 465 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
466 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
467 if (stat != 0) {
432907f7
MI		 468 return stat;
469 }
470 *left = cap->bounds.left;
471 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 472 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 473 }
474 return 0;
475}
476
477static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
478{
432907f7
MI		 479 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
480 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
481 if (stat != 0) {
432907f7 482 return stat;
e784bfb9 483 }
432907f7 484 *top = cap->bounds.top;
e784bfb9 485 return 0;
486}
487
432907f7 488static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 489{
432907f7
MI		 490 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
491 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
492 if (stat != 0) {
432907f7
MI		 493 return stat;
494 }
495 *top = cap->bounds.top;
496 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 497 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 498 }
499 return 0;
500}
501
6188a0f1 502static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
432907f7
MI		 503{
504 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
6188a0f1
SV		 505 int stat, bleftend, cleft;
506
507 stat = pvr2_hdw_check_cropcap(cptr->hdw);
432907f7 508 if (stat != 0) {
432907f7
MI		 509 return stat;
510 }
6188a0f1
SV		 511 bleftend = cap->bounds.left+cap->bounds.width;
512 cleft = cptr->hdw->cropl_val;
513
514 *width = cleft < bleftend ? bleftend-cleft : 0;
432907f7
MI		 515 return 0;
516}
517
6188a0f1 518static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
432907f7
MI		 519{
520 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
6188a0f1
SV		 521 int stat, btopend, ctop;
522
523 stat = pvr2_hdw_check_cropcap(cptr->hdw);
432907f7 524 if (stat != 0) {
432907f7
MI		 525 return stat;
526 }
6188a0f1
SV		 527 btopend = cap->bounds.top+cap->bounds.height;
528 ctop = cptr->hdw->cropt_val;
529
530 *height = ctop < btopend ? btopend-ctop : 0;
432907f7
MI		 531 return 0;
532}
533
534static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
535{
536 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
537 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
538 if (stat != 0) {
432907f7
MI		 539 return stat;
540 }
541 *val = cap->bounds.left;
542 return 0;
543}
544
545static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
546{
547 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
548 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
549 if (stat != 0) {
432907f7
MI		 550 return stat;
551 }
552 *val = cap->bounds.top;
553 return 0;
554}
555
556static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
557{
558 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
559 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
560 if (stat != 0) {
432907f7
MI		 561 return stat;
562 }
563 *val = cap->bounds.width;
564 return 0;
565}
566
567static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
568{
569 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
570 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
571 if (stat != 0) {
432907f7
MI		 572 return stat;
573 }
574 *val = cap->bounds.height;
575 return 0;
576}
577
578static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
579{
580 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
581 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
582 if (stat != 0) {
432907f7
MI		 583 return stat;
584 }
585 *val = cap->defrect.left;
586 return 0;
587}
588
589static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
590{
591 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
592 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
593 if (stat != 0) {
432907f7
MI		 594 return stat;
595 }
596 *val = cap->defrect.top;
597 return 0;
598}
599
600static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
601{
602 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
603 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
604 if (stat != 0) {
432907f7
MI		 605 return stat;
606 }
607 *val = cap->defrect.width;
608 return 0;
609}
610
611static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
612{
613 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
614 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
615 if (stat != 0) {
432907f7
MI		 616 return stat;
617 }
618 *val = cap->defrect.height;
619 return 0;
620}
621
622static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
623{
624 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
625 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
626 if (stat != 0) {
432907f7
MI		 627 return stat;
628 }
629 *val = cap->pixelaspect.numerator;
630 return 0;
631}
632
633static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
634{
635 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
636 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
637 if (stat != 0) {
432907f7
MI		 638 return stat;
639 }
640 *val = cap->pixelaspect.denominator;
641 return 0;
642}
643
644static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 645{
432907f7
MI		 646 /* Actual maximum depends on the video standard in effect. */
647 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
648 *vp = 480;
e784bfb9 649 } else {
432907f7 650 *vp = 576;
e784bfb9 651 }
652 return 0;
653}
654
3ad9fc37
MI		 655static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
656{
989eb154
MI		 657 /* Actual minimum depends on device digitizer type. */
658 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 659 *vp = 75;
660 } else {
661 *vp = 17;
662 }
663 return 0;
664}
665
1bde0289 666static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 667{
1bde0289
MI		 668 *vp = cptr->hdw->input_val;
669 return 0;
670}
671
29bf5b1d
MI		 672static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
673{
1cb03b76 674 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 675}
676
1bde0289
MI		 677static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
678{
1cb03b76 679 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 680}
681
682static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
683{
684 return cptr->hdw->input_dirty != 0;
685}
686
687static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
688{
689 cptr->hdw->input_dirty = 0;
690}
691
5549f54f 692
25d8527a
PK		 693static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
694{
644afdb9
MI		 695 unsigned long fv;
696 struct pvr2_hdw *hdw = cptr->hdw;
697 if (hdw->tuner_signal_stale) {
a51f5000 698 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 699 }
700 fv = hdw->tuner_signal_info.rangehigh;
701 if (!fv) {
702 /* Safety fallback */
25d8527a 703 *vp = TV_MAX_FREQ;
644afdb9 704 return 0;
25d8527a 705 }
644afdb9
MI		 706 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
707 fv = (fv * 125) / 2;
708 } else {
709 fv = fv * 62500;
710 }
711 *vp = fv;
25d8527a
PK		 712 return 0;
713}
714
715static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
716{
644afdb9
MI		 717 unsigned long fv;
718 struct pvr2_hdw *hdw = cptr->hdw;
719 if (hdw->tuner_signal_stale) {
a51f5000 720 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 721 }
722 fv = hdw->tuner_signal_info.rangelow;
723 if (!fv) {
724 /* Safety fallback */
25d8527a 725 *vp = TV_MIN_FREQ;
644afdb9
MI		 726 return 0;
727 }
728 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
729 fv = (fv * 125) / 2;
730 } else {
731 fv = fv * 62500;
25d8527a 732 }
644afdb9 733 *vp = fv;
25d8527a
PK		 734 return 0;
735}
736
b30d2441
MI		 737static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
738{
739 return cptr->hdw->enc_stale != 0;
740}
741
742static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
743{
744 cptr->hdw->enc_stale = 0;
681c7399 745 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 746}
747
748static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
749{
750 int ret;
751 struct v4l2_ext_controls cs;
752 struct v4l2_ext_control c1;
753 memset(&cs,0,sizeof(cs));
754 memset(&c1,0,sizeof(c1));
755 cs.controls = &c1;
756 cs.count = 1;
757 c1.id = cptr->info->v4l_id;
01f1e44f 758 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 759 VIDIOC_G_EXT_CTRLS);
760 if (ret) return ret;
761 *vp = c1.value;
762 return 0;
763}
764
765static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
766{
767 int ret;
681c7399 768 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 769 struct v4l2_ext_controls cs;
770 struct v4l2_ext_control c1;
771 memset(&cs,0,sizeof(cs));
772 memset(&c1,0,sizeof(c1));
773 cs.controls = &c1;
774 cs.count = 1;
775 c1.id = cptr->info->v4l_id;
776 c1.value = v;
681c7399
MI		 777 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
778 hdw->state_encoder_run, &cs,
b30d2441 779 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 780 if (ret == -EBUSY) {
781 /* Oops. cx2341x is telling us it's not safe to change
782 this control while we're capturing. Make a note of this
783 fact so that the pipeline will be stopped the next time
784 controls are committed. Then go on ahead and store this
785 change anyway. */
786 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
787 0, &cs,
788 VIDIOC_S_EXT_CTRLS);
789 if (!ret) hdw->enc_unsafe_stale = !0;
790 }
b30d2441 791 if (ret) return ret;
681c7399 792 hdw->enc_stale = !0;
b30d2441
MI		 793 return 0;
794}
795
796static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
797{
798 struct v4l2_queryctrl qctrl;
799 struct pvr2_ctl_info *info;
800 qctrl.id = cptr->info->v4l_id;
801 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
802 /* Strip out the const so we can adjust a function pointer. It's
803 OK to do this here because we know this is a dynamically created
804 control, so the underlying storage for the info pointer is (a)
805 private to us, and (b) not in read-only storage. Either we do
806 this or we significantly complicate the underlying control
807 implementation. */
808 info = (struct pvr2_ctl_info *)(cptr->info);
809 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
810 if (info->set_value) {
a0fd1cb1 811 info->set_value = NULL;
b30d2441
MI		 812 }
813 } else {
814 if (!(info->set_value)) {
815 info->set_value = ctrl_cx2341x_set;
816 }
817 }
818 return qctrl.flags;
819}
820
d855497e
MI		 821static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
822{
681c7399
MI		 823 *vp = cptr->hdw->state_pipeline_req;
824 return 0;
825}
826
827static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
828{
829 *vp = cptr->hdw->master_state;
d855497e
MI		 830 return 0;
831}
832
833static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
834{
835 int result = pvr2_hdw_is_hsm(cptr->hdw);
836 *vp = PVR2_CVAL_HSM_FULL;
837 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
838 if (result) *vp = PVR2_CVAL_HSM_HIGH;
839 return 0;
840}
841
842static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
843{
844 *vp = cptr->hdw->std_mask_avail;
845 return 0;
846}
847
848static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
849{
850 struct pvr2_hdw *hdw = cptr->hdw;
851 v4l2_std_id ns;
852 ns = hdw->std_mask_avail;
853 ns = (ns & ~m) | (v & m);
854 if (ns == hdw->std_mask_avail) return 0;
855 hdw->std_mask_avail = ns;
856 pvr2_hdw_internal_set_std_avail(hdw);
857 pvr2_hdw_internal_find_stdenum(hdw);
858 return 0;
859}
860
861static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
862 char *bufPtr,unsigned int bufSize,
863 unsigned int *len)
864{
865 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
866 return 0;
867}
868
869static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
870 const char *bufPtr,unsigned int bufSize,
871 int *mskp,int *valp)
872{
873 int ret;
874 v4l2_std_id id;
875 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
876 if (ret < 0) return ret;
877 if (mskp) *mskp = id;
878 if (valp) *valp = id;
879 return 0;
880}
881
882static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
883{
884 *vp = cptr->hdw->std_mask_cur;
885 return 0;
886}
887
888static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
889{
890 struct pvr2_hdw *hdw = cptr->hdw;
891 v4l2_std_id ns;
892 ns = hdw->std_mask_cur;
893 ns = (ns & ~m) | (v & m);
894 if (ns == hdw->std_mask_cur) return 0;
895 hdw->std_mask_cur = ns;
896 hdw->std_dirty = !0;
897 pvr2_hdw_internal_find_stdenum(hdw);
898 return 0;
899}
900
901static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
902{
903 return cptr->hdw->std_dirty != 0;
904}
905
906static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
907{
908 cptr->hdw->std_dirty = 0;
909}
910
911static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
912{
18103c57 913 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 914 pvr2_hdw_status_poll(hdw);
18103c57
MI		 915 *vp = hdw->tuner_signal_info.signal;
916 return 0;
917}
918
919static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
920{
921 int val = 0;
922 unsigned int subchan;
923 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 924 pvr2_hdw_status_poll(hdw);
18103c57
MI		 925 subchan = hdw->tuner_signal_info.rxsubchans;
926 if (subchan & V4L2_TUNER_SUB_MONO) {
927 val |= (1 << V4L2_TUNER_MODE_MONO);
928 }
929 if (subchan & V4L2_TUNER_SUB_STEREO) {
930 val |= (1 << V4L2_TUNER_MODE_STEREO);
931 }
932 if (subchan & V4L2_TUNER_SUB_LANG1) {
933 val |= (1 << V4L2_TUNER_MODE_LANG1);
934 }
935 if (subchan & V4L2_TUNER_SUB_LANG2) {
936 val |= (1 << V4L2_TUNER_MODE_LANG2);
937 }
938 *vp = val;
d855497e
MI		 939 return 0;
940}
941
d855497e
MI		 942
943static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
944{
945 struct pvr2_hdw *hdw = cptr->hdw;
946 if (v < 0) return -EINVAL;
947 if (v > hdw->std_enum_cnt) return -EINVAL;
948 hdw->std_enum_cur = v;
949 if (!v) return 0;
950 v--;
951 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
952 hdw->std_mask_cur = hdw->std_defs[v].id;
953 hdw->std_dirty = !0;
954 return 0;
955}
956
957
958static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
959{
960 *vp = cptr->hdw->std_enum_cur;
961 return 0;
962}
963
964
965static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
966{
967 return cptr->hdw->std_dirty != 0;
968}
969
970
971static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
972{
973 cptr->hdw->std_dirty = 0;
974}
975
976
977#define DEFINT(vmin,vmax) \
978 .type = pvr2_ctl_int, \
979 .def.type_int.min_value = vmin, \
980 .def.type_int.max_value = vmax
981
982#define DEFENUM(tab) \
983 .type = pvr2_ctl_enum, \
27c7b710 984 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 985 .def.type_enum.value_names = tab
986
33213963
MI		 987#define DEFBOOL \
988 .type = pvr2_ctl_bool
989
d855497e
MI		 990#define DEFMASK(msk,tab) \
991 .type = pvr2_ctl_bitmask, \
992 .def.type_bitmask.valid_bits = msk, \
993 .def.type_bitmask.bit_names = tab
994
995#define DEFREF(vname) \
996 .set_value = ctrl_set_##vname, \
997 .get_value = ctrl_get_##vname, \
998 .is_dirty = ctrl_isdirty_##vname, \
999 .clear_dirty = ctrl_cleardirty_##vname
1000
1001
1002#define VCREATE_FUNCS(vname) \
1003static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
1004{*vp = cptr->hdw->vname##_val; return 0;} \
1005static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
1006{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1007static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1008{return cptr->hdw->vname##_dirty != 0;} \
1009static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1010{cptr->hdw->vname##_dirty = 0;}
1011
1012VCREATE_FUNCS(brightness)
1013VCREATE_FUNCS(contrast)
1014VCREATE_FUNCS(saturation)
1015VCREATE_FUNCS(hue)
1016VCREATE_FUNCS(volume)
1017VCREATE_FUNCS(balance)
1018VCREATE_FUNCS(bass)
1019VCREATE_FUNCS(treble)
1020VCREATE_FUNCS(mute)
e784bfb9 1021VCREATE_FUNCS(cropl)
1022VCREATE_FUNCS(cropt)
1023VCREATE_FUNCS(cropw)
1024VCREATE_FUNCS(croph)
c05c0462
MI		 1025VCREATE_FUNCS(audiomode)
1026VCREATE_FUNCS(res_hor)
1027VCREATE_FUNCS(res_ver)
d855497e 1028VCREATE_FUNCS(srate)
d855497e 1029
d855497e
MI		 1030/* Table definition of all controls which can be manipulated */
1031static const struct pvr2_ctl_info control_defs[] = {
1032 {
1033 .v4l_id = V4L2_CID_BRIGHTNESS,
1034 .desc = "Brightness",
1035 .name = "brightness",
1036 .default_value = 128,
1037 DEFREF(brightness),
1038 DEFINT(0,255),
1039 },{
1040 .v4l_id = V4L2_CID_CONTRAST,
1041 .desc = "Contrast",
1042 .name = "contrast",
1043 .default_value = 68,
1044 DEFREF(contrast),
1045 DEFINT(0,127),
1046 },{
1047 .v4l_id = V4L2_CID_SATURATION,
1048 .desc = "Saturation",
1049 .name = "saturation",
1050 .default_value = 64,
1051 DEFREF(saturation),
1052 DEFINT(0,127),
1053 },{
1054 .v4l_id = V4L2_CID_HUE,
1055 .desc = "Hue",
1056 .name = "hue",
1057 .default_value = 0,
1058 DEFREF(hue),
1059 DEFINT(-128,127),
1060 },{
1061 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1062 .desc = "Volume",
1063 .name = "volume",
139eecf9 1064 .default_value = 62000,
d855497e
MI		 1065 DEFREF(volume),
1066 DEFINT(0,65535),
1067 },{
1068 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1069 .desc = "Balance",
1070 .name = "balance",
1071 .default_value = 0,
1072 DEFREF(balance),
1073 DEFINT(-32768,32767),
1074 },{
1075 .v4l_id = V4L2_CID_AUDIO_BASS,
1076 .desc = "Bass",
1077 .name = "bass",
1078 .default_value = 0,
1079 DEFREF(bass),
1080 DEFINT(-32768,32767),
1081 },{
1082 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1083 .desc = "Treble",
1084 .name = "treble",
1085 .default_value = 0,
1086 DEFREF(treble),
1087 DEFINT(-32768,32767),
1088 },{
1089 .v4l_id = V4L2_CID_AUDIO_MUTE,
1090 .desc = "Mute",
1091 .name = "mute",
1092 .default_value = 0,
1093 DEFREF(mute),
33213963 1094 DEFBOOL,
e784bfb9 1095 }, {
432907f7 1096 .desc = "Capture crop left margin",
e784bfb9 1097 .name = "crop_left",
1098 .internal_id = PVR2_CID_CROPL,
1099 .default_value = 0,
1100 DEFREF(cropl),
1101 DEFINT(-129, 340),
1102 .get_min_value = ctrl_cropl_min_get,
1103 .get_max_value = ctrl_cropl_max_get,
432907f7 1104 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1105 }, {
432907f7 1106 .desc = "Capture crop top margin",
e784bfb9 1107 .name = "crop_top",
1108 .internal_id = PVR2_CID_CROPT,
1109 .default_value = 0,
1110 DEFREF(cropt),
1111 DEFINT(-35, 544),
1112 .get_min_value = ctrl_cropt_min_get,
1113 .get_max_value = ctrl_cropt_max_get,
432907f7 1114 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1115 }, {
432907f7 1116 .desc = "Capture crop width",
e784bfb9 1117 .name = "crop_width",
1118 .internal_id = PVR2_CID_CROPW,
1119 .default_value = 720,
1120 DEFREF(cropw),
35fa5d4c 1121 DEFINT(0, 864),
432907f7
MI		 1122 .get_max_value = ctrl_cropw_max_get,
1123 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1124 }, {
432907f7 1125 .desc = "Capture crop height",
e784bfb9 1126 .name = "crop_height",
1127 .internal_id = PVR2_CID_CROPH,
1128 .default_value = 480,
1129 DEFREF(croph),
35fa5d4c 1130 DEFINT(0, 576),
432907f7
MI		 1131 .get_max_value = ctrl_croph_max_get,
1132 .get_def_value = ctrl_get_cropcapdh,
1133 }, {
1134 .desc = "Capture capability pixel aspect numerator",
1135 .name = "cropcap_pixel_numerator",
1136 .internal_id = PVR2_CID_CROPCAPPAN,
1137 .get_value = ctrl_get_cropcappan,
1138 }, {
1139 .desc = "Capture capability pixel aspect denominator",
1140 .name = "cropcap_pixel_denominator",
1141 .internal_id = PVR2_CID_CROPCAPPAD,
1142 .get_value = ctrl_get_cropcappad,
1143 }, {
1144 .desc = "Capture capability bounds top",
1145 .name = "cropcap_bounds_top",
1146 .internal_id = PVR2_CID_CROPCAPBT,
1147 .get_value = ctrl_get_cropcapbt,
1148 }, {
1149 .desc = "Capture capability bounds left",
1150 .name = "cropcap_bounds_left",
1151 .internal_id = PVR2_CID_CROPCAPBL,
1152 .get_value = ctrl_get_cropcapbl,
1153 }, {
1154 .desc = "Capture capability bounds width",
1155 .name = "cropcap_bounds_width",
1156 .internal_id = PVR2_CID_CROPCAPBW,
1157 .get_value = ctrl_get_cropcapbw,
1158 }, {
1159 .desc = "Capture capability bounds height",
1160 .name = "cropcap_bounds_height",
1161 .internal_id = PVR2_CID_CROPCAPBH,
1162 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1163 },{
1164 .desc = "Video Source",
1165 .name = "input",
1166 .internal_id = PVR2_CID_INPUT,
1167 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1168 .check_value = ctrl_check_input,
c05c0462
MI		 1169 DEFREF(input),
1170 DEFENUM(control_values_input),
1171 },{
1172 .desc = "Audio Mode",
1173 .name = "audio_mode",
1174 .internal_id = PVR2_CID_AUDIOMODE,
1175 .default_value = V4L2_TUNER_MODE_STEREO,
1176 DEFREF(audiomode),
1177 DEFENUM(control_values_audiomode),
1178 },{
1179 .desc = "Horizontal capture resolution",
1180 .name = "resolution_hor",
1181 .internal_id = PVR2_CID_HRES,
1182 .default_value = 720,
1183 DEFREF(res_hor),
3ad9fc37 1184 DEFINT(19,720),
c05c0462
MI		 1185 },{
1186 .desc = "Vertical capture resolution",
1187 .name = "resolution_ver",
1188 .internal_id = PVR2_CID_VRES,
1189 .default_value = 480,
1190 DEFREF(res_ver),
3ad9fc37
MI		 1191 DEFINT(17,576),
1192 /* Hook in check for video standard and adjust maximum
1193 depending on the standard. */
1194 .get_max_value = ctrl_vres_max_get,
1195 .get_min_value = ctrl_vres_min_get,
d855497e 1196 },{
b30d2441 1197 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1198 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1199 .desc = "Audio Sampling Frequency",
d855497e 1200 .name = "srate",
d855497e
MI		 1201 DEFREF(srate),
1202 DEFENUM(control_values_srate),
d855497e
MI		 1203 },{
1204 .desc = "Tuner Frequency (Hz)",
1205 .name = "frequency",
1206 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1207 .default_value = 0,
d855497e
MI		 1208 .set_value = ctrl_freq_set,
1209 .get_value = ctrl_freq_get,
1210 .is_dirty = ctrl_freq_is_dirty,
1211 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1212 DEFINT(0,0),
25d8527a
PK		 1213 /* Hook in check for input value (tv/radio) and adjust
1214 max/min values accordingly */
1215 .get_max_value = ctrl_freq_max_get,
1216 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1217 },{
1218 .desc = "Channel",
1219 .name = "channel",
1220 .set_value = ctrl_channel_set,
1221 .get_value = ctrl_channel_get,
1222 DEFINT(0,FREQTABLE_SIZE),
1223 },{
1224 .desc = "Channel Program Frequency",
1225 .name = "freq_table_value",
1226 .set_value = ctrl_channelfreq_set,
1227 .get_value = ctrl_channelfreq_get,
644afdb9 1228 DEFINT(0,0),
1bde0289
MI		 1229 /* Hook in check for input value (tv/radio) and adjust
1230 max/min values accordingly */
1bde0289
MI		 1231 .get_max_value = ctrl_freq_max_get,
1232 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1233 },{
1234 .desc = "Channel Program ID",
1235 .name = "freq_table_channel",
1236 .set_value = ctrl_channelprog_set,
1237 .get_value = ctrl_channelprog_get,
1238 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1239 },{
1240 .desc = "Streaming Enabled",
1241 .name = "streaming_enabled",
1242 .get_value = ctrl_streamingenabled_get,
33213963 1243 DEFBOOL,
d855497e
MI		 1244 },{
1245 .desc = "USB Speed",
1246 .name = "usb_speed",
1247 .get_value = ctrl_hsm_get,
1248 DEFENUM(control_values_hsm),
681c7399
MI		 1249 },{
1250 .desc = "Master State",
1251 .name = "master_state",
1252 .get_value = ctrl_masterstate_get,
1253 DEFENUM(pvr2_state_names),
d855497e
MI		 1254 },{
1255 .desc = "Signal Present",
1256 .name = "signal_present",
1257 .get_value = ctrl_signal_get,
18103c57
MI		 1258 DEFINT(0,65535),
1259 },{
1260 .desc = "Audio Modes Present",
1261 .name = "audio_modes_present",
1262 .get_value = ctrl_audio_modes_present_get,
1263 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1264 v4l. Nothing outside of this module cares about this,
1265 but I reuse it in order to also reuse the
1266 control_values_audiomode string table. */
1267 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1268 (1 << V4L2_TUNER_MODE_STEREO)|
1269 (1 << V4L2_TUNER_MODE_LANG1)|
1270 (1 << V4L2_TUNER_MODE_LANG2)),
1271 control_values_audiomode),
d855497e
MI		 1272 },{
1273 .desc = "Video Standards Available Mask",
1274 .name = "video_standard_mask_available",
1275 .internal_id = PVR2_CID_STDAVAIL,
1276 .skip_init = !0,
1277 .get_value = ctrl_stdavail_get,
1278 .set_value = ctrl_stdavail_set,
1279 .val_to_sym = ctrl_std_val_to_sym,
1280 .sym_to_val = ctrl_std_sym_to_val,
1281 .type = pvr2_ctl_bitmask,
1282 },{
1283 .desc = "Video Standards In Use Mask",
1284 .name = "video_standard_mask_active",
1285 .internal_id = PVR2_CID_STDCUR,
1286 .skip_init = !0,
1287 .get_value = ctrl_stdcur_get,
1288 .set_value = ctrl_stdcur_set,
1289 .is_dirty = ctrl_stdcur_is_dirty,
1290 .clear_dirty = ctrl_stdcur_clear_dirty,
1291 .val_to_sym = ctrl_std_val_to_sym,
1292 .sym_to_val = ctrl_std_sym_to_val,
1293 .type = pvr2_ctl_bitmask,
d855497e
MI		 1294 },{
1295 .desc = "Video Standard Name",
1296 .name = "video_standard",
1297 .internal_id = PVR2_CID_STDENUM,
1298 .skip_init = !0,
1299 .get_value = ctrl_stdenumcur_get,
1300 .set_value = ctrl_stdenumcur_set,
1301 .is_dirty = ctrl_stdenumcur_is_dirty,
1302 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1303 .type = pvr2_ctl_enum,
1304 }
1305};
1306
eca8ebfc 1307#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1308
1309
1310const char *pvr2_config_get_name(enum pvr2_config cfg)
1311{
1312 switch (cfg) {
1313 case pvr2_config_empty: return "empty";
1314 case pvr2_config_mpeg: return "mpeg";
1315 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1316 case pvr2_config_pcm: return "pcm";
1317 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1318 }
1319 return "<unknown>";
1320}
1321
1322
1323struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1324{
1325 return hdw->usb_dev;
1326}
1327
1328
1329unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1330{
1331 return hdw->serial_number;
1332}
1333
31a18547
MI		 1334
1335const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1336{
1337 return hdw->bus_info;
1338}
1339
1340
13a88797
MI		 1341const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1342{
1343 return hdw->identifier;
1344}
1345
1346
1bde0289
MI		 1347unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1348{
1349 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1350}
1351
1352/* Set the currently tuned frequency and account for all possible
1353 driver-core side effects of this action. */
f55a8712 1354static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1355{
7c74e57e 1356 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1357 if (hdw->freqSelector) {
1358 /* Swing over to radio frequency selection */
1359 hdw->freqSelector = 0;
1360 hdw->freqDirty = !0;
1361 }
1bde0289
MI		 1362 if (hdw->freqValRadio != val) {
1363 hdw->freqValRadio = val;
1364 hdw->freqSlotRadio = 0;
7c74e57e 1365 hdw->freqDirty = !0;
1bde0289 1366 }
7c74e57e 1367 } else {
1bde0289
MI		 1368 if (!(hdw->freqSelector)) {
1369 /* Swing over to television frequency selection */
1370 hdw->freqSelector = 1;
1371 hdw->freqDirty = !0;
1372 }
1bde0289
MI		 1373 if (hdw->freqValTelevision != val) {
1374 hdw->freqValTelevision = val;
1375 hdw->freqSlotTelevision = 0;
7c74e57e 1376 hdw->freqDirty = !0;
1bde0289 1377 }
1bde0289
MI		 1378 }
1379}
1380
d855497e
MI		 1381int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1382{
1383 return hdw->unit_number;
1384}
1385
1386
1387/* Attempt to locate one of the given set of files. Messages are logged
1388 appropriate to what has been found. The return value will be 0 or
1389 greater on success (it will be the index of the file name found) and
1390 fw_entry will be filled in. Otherwise a negative error is returned on
1391 failure. If the return value is -ENOENT then no viable firmware file
1392 could be located. */
1393static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1394 const struct firmware **fw_entry,
1395 const char *fwtypename,
1396 unsigned int fwcount,
1397 const char *fwnames[])
1398{
1399 unsigned int idx;
1400 int ret = -EINVAL;
1401 for (idx = 0; idx < fwcount; idx++) {
1402 ret = request_firmware(fw_entry,
1403 fwnames[idx],
1404 &hdw->usb_dev->dev);
1405 if (!ret) {
1406 trace_firmware("Located %s firmware: %s;"
1407 " uploading...",
1408 fwtypename,
1409 fwnames[idx]);
1410 return idx;
1411 }
1412 if (ret == -ENOENT) continue;
1413 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1414 "request_firmware fatal error with code=%d",ret);
1415 return ret;
1416 }
1417 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1418 "***WARNING***"
1419 " Device %s firmware"
1420 " seems to be missing.",
1421 fwtypename);
1422 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1423 "Did you install the pvrusb2 firmware files"
1424 " in their proper location?");
1425 if (fwcount == 1) {
1426 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1427 "request_firmware unable to locate %s file %s",
1428 fwtypename,fwnames[0]);
1429 } else {
1430 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1431 "request_firmware unable to locate"
1432 " one of the following %s files:",
1433 fwtypename);
1434 for (idx = 0; idx < fwcount; idx++) {
1435 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1436 "request_firmware: Failed to find %s",
1437 fwnames[idx]);
1438 }
1439 }
1440 return ret;
1441}
1442
1443
1444/*
1445 * pvr2_upload_firmware1().
1446 *
1447 * Send the 8051 firmware to the device. After the upload, arrange for
1448 * device to re-enumerate.
1449 *
1450 * NOTE : the pointer to the firmware data given by request_firmware()
1451 * is not suitable for an usb transaction.
1452 *
1453 */
07e337ee 1454static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1455{
a0fd1cb1 1456 const struct firmware *fw_entry = NULL;
d855497e
MI		 1457 void *fw_ptr;
1458 unsigned int pipe;
9081d901 1459 unsigned int fwsize;
d855497e
MI		 1460 int ret;
1461 u16 address;
1d643a37 1462
989eb154 1463 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1464 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1465 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1466 "Connected device type defines"
1467 " no firmware to upload; ignoring firmware");
1468 return -ENOTTY;
1d643a37
MI		 1469 }
1470
d855497e
MI		 1471 hdw->fw1_state = FW1_STATE_FAILED; // default result
1472
1473 trace_firmware("pvr2_upload_firmware1");
1474
1475 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1476 hdw->hdw_desc->fx2_firmware.cnt,
1477 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1478 if (ret < 0) {
1479 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1480 return ret;
1481 }
1482
d855497e
MI		 1483 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1484
1485 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
9081d901 1486 fwsize = fw_entry->size;
d855497e 1487
9081d901
MI		 1488 if ((fwsize != 0x2000) &&
1489 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
c21c2db4
MI		 1490 if (hdw->hdw_desc->flag_fx2_16kb) {
1491 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1492 "Wrong fx2 firmware size"
1493 " (expected 8192 or 16384, got %u)",
9081d901 1494 fwsize);
c21c2db4
MI		 1495 } else {
1496 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1497 "Wrong fx2 firmware size"
1498 " (expected 8192, got %u)",
9081d901 1499 fwsize);
c21c2db4 1500 }
d855497e
MI		 1501 release_firmware(fw_entry);
1502 return -ENOMEM;
1503 }
1504
1505 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1506 if (fw_ptr == NULL){
1507 release_firmware(fw_entry);
1508 return -ENOMEM;
1509 }
1510
1511 /* We have to hold the CPU during firmware upload. */
1512 pvr2_hdw_cpureset_assert(hdw,1);
1513
1514 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1515 chunk. */
1516
1517 ret = 0;
9081d901 1518 for (address = 0; address < fwsize; address += 0x800) {
d855497e
MI		 1519 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1520 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1521 0, fw_ptr, 0x800, HZ);
1522 }
1523
1524 trace_firmware("Upload done, releasing device's CPU");
1525
1526 /* Now release the CPU. It will disconnect and reconnect later. */
1527 pvr2_hdw_cpureset_assert(hdw,0);
1528
1529 kfree(fw_ptr);
1530 release_firmware(fw_entry);
1531
1532 trace_firmware("Upload done (%d bytes sent)",ret);
1533
75727460
GF		 1534 /* We should have written fwsize bytes */
1535 if (ret == fwsize) {
d855497e
MI		 1536 hdw->fw1_state = FW1_STATE_RELOAD;
1537 return 0;
1538 }
1539
1540 return -EIO;
1541}
1542
1543
1544/*
1545 * pvr2_upload_firmware2()
1546 *
1547 * This uploads encoder firmware on endpoint 2.
1548 *
1549 */
1550
1551int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1552{
a0fd1cb1 1553 const struct firmware *fw_entry = NULL;
d855497e 1554 void *fw_ptr;
90060d32 1555 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1556 int actual_length;
1557 int ret = 0;
1558 int fwidx;
1559 static const char *fw_files[] = {
1560 CX2341X_FIRM_ENC_FILENAME,
1561 };
1562
989eb154 1563 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1564 return 0;
1565 }
1566
d855497e
MI		 1567 trace_firmware("pvr2_upload_firmware2");
1568
1569 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1570 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1571 if (ret < 0) return ret;
1572 fwidx = ret;
1573 ret = 0;
b30d2441
MI		 1574 /* Since we're about to completely reinitialize the encoder,
1575 invalidate our cached copy of its configuration state. Next
1576 time we configure the encoder, then we'll fully configure it. */
1577 hdw->enc_cur_valid = 0;
d855497e 1578
d913d630
MI		 1579 /* Encoder is about to be reset so note that as far as we're
1580 concerned now, the encoder has never been run. */
1581 del_timer_sync(&hdw->encoder_run_timer);
1582 if (hdw->state_encoder_runok) {
1583 hdw->state_encoder_runok = 0;
1584 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1585 }
1586
d855497e
MI		 1587 /* First prepare firmware loading */
1588 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1589 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1590 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1591 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1592 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1593 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1594 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1595 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1596 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1597 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1598 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1599 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1600 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1601 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1602 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1603 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1604 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1605 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1606
1607 if (ret) {
1608 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1609 "firmware2 upload prep failed, ret=%d",ret);
1610 release_firmware(fw_entry);
21684ba9 1611 goto done;
d855497e
MI		 1612 }
1613
1614 /* Now send firmware */
1615
1616 fw_len = fw_entry->size;
1617
90060d32 1618 if (fw_len % sizeof(u32)) {
d855497e
MI		 1619 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1620 "size of %s firmware"
48dc30a1 1621 " must be a multiple of %zu bytes",
90060d32 1622 fw_files[fwidx],sizeof(u32));
d855497e 1623 release_firmware(fw_entry);
21684ba9
MI		 1624 ret = -EINVAL;
1625 goto done;
d855497e
MI		 1626 }
1627
1628 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1629 if (fw_ptr == NULL){
1630 release_firmware(fw_entry);
1631 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1632 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1633 ret = -ENOMEM;
1634 goto done;
d855497e
MI		 1635 }
1636
1637 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1638
90060d32
MI		 1639 fw_done = 0;
1640 for (fw_done = 0; fw_done < fw_len;) {
1641 bcnt = fw_len - fw_done;
1642 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1643 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1644 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1645 /* Some background info: The data being swapped here is a
1646 firmware image destined for the mpeg encoder chip that
1647 lives at the other end of a USB endpoint. The encoder
1648 chip always talks in 32 bit chunks and its storage is
1649 organized into 32 bit words. However from the file
1650 system to the encoder chip everything is purely a byte
1651 stream. The firmware file's contents are always 32 bit
1652 swapped from what the encoder expects. Thus the need
1653 always exists to swap the bytes regardless of the endian
1654 type of the host processor and therefore swab32() makes
1655 the most sense. */
90060d32 1656 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1657 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1658
1659 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1660 &actual_length, HZ);
90060d32
MI		 1661 ret |= (actual_length != bcnt);
1662 if (ret) break;
1663 fw_done += bcnt;
d855497e
MI		 1664 }
1665
1666 trace_firmware("upload of %s : %i / %i ",
1667 fw_files[fwidx],fw_done,fw_len);
1668
1669 kfree(fw_ptr);
1670 release_firmware(fw_entry);
1671
1672 if (ret) {
1673 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1674 "firmware2 upload transfer failure");
21684ba9 1675 goto done;
d855497e
MI		 1676 }
1677
1678 /* Finish upload */
1679
1680 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1681 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1682 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1683
1684 if (ret) {
1685 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1686 "firmware2 upload post-proc failure");
d855497e 1687 }
21684ba9
MI		 1688
1689 done:
1df59f0b
MI		 1690 if (hdw->hdw_desc->signal_routing_scheme ==
1691 PVR2_ROUTING_SCHEME_GOTVIEW) {
1692 /* Ensure that GPIO 11 is set to output for GOTVIEW
1693 hardware. */
1694 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1695 }
d855497e
MI		 1696 return ret;
1697}
1698
1699
681c7399
MI		 1700static const char *pvr2_get_state_name(unsigned int st)
1701{
1702 if (st < ARRAY_SIZE(pvr2_state_names)) {
1703 return pvr2_state_names[st];
d855497e 1704 }
681c7399 1705 return "???";
d855497e
MI		 1706}
1707
681c7399 1708static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1709{
af78e16b
MI		 1710 /* Even though we really only care about the video decoder chip at
1711 this point, we'll broadcast stream on/off to all sub-devices
1712 anyway, just in case somebody else wants to hear the
1713 command... */
e260508d
MI		 1714 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1715 (enablefl ? "on" : "off"));
af78e16b 1716 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
3ccc646b 1717 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
af78e16b
MI		 1718 if (hdw->decoder_client_id) {
1719 /* We get here if the encoder has been noticed. Otherwise
1720 we'll issue a warning to the user (which should
1721 normally never happen). */
1722 return 0;
1723 }
1724 if (!hdw->flag_decoder_missed) {
1725 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1726 "WARNING: No decoder present");
1727 hdw->flag_decoder_missed = !0;
1728 trace_stbit("flag_decoder_missed",
1729 hdw->flag_decoder_missed);
1730 }
1731 return -EIO;
d855497e
MI		 1732}
1733
1734
681c7399 1735int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1736{
681c7399 1737 return hdw->master_state;
d855497e
MI		 1738}
1739
1740
681c7399 1741static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1742{
681c7399
MI		 1743 if (!hdw->flag_tripped) return 0;
1744 hdw->flag_tripped = 0;
1745 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1746 "Clearing driver error statuss");
1747 return !0;
d855497e
MI		 1748}
1749
1750
681c7399 1751int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1752{
681c7399 1753 int fl;
d855497e 1754 LOCK_TAKE(hdw->big_lock); do {
681c7399 1755 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1756 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1757 if (fl) pvr2_hdw_state_sched(hdw);
1758 return 0;
d855497e
MI		 1759}
1760
1761
d855497e
MI		 1762
1763
1764int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1765{
681c7399 1766 return hdw->state_pipeline_req != 0;
d855497e
MI		 1767}
1768
1769
1770int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1771{
681c7399 1772 int ret,st;
d855497e 1773 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1774 pvr2_hdw_untrip_unlocked(hdw);
1775 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1776 hdw->state_pipeline_req = enable_flag != 0;
1777 pvr2_trace(PVR2_TRACE_START_STOP,
1778 "/*--TRACE_STREAM--*/ %s",
1779 enable_flag ? "enable" : "disable");
1780 }
1781 pvr2_hdw_state_sched(hdw);
d855497e 1782 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1783 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1784 if (enable_flag) {
1785 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1786 if (st != PVR2_STATE_READY) return -EIO;
1787 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1788 }
1789 }
d855497e
MI		 1790 return 0;
1791}
1792
1793
1794int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1795{
681c7399 1796 int fl;
d855497e 1797 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1798 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1799 hdw->desired_stream_type = config;
1800 hdw->state_pipeline_config = 0;
1801 trace_stbit("state_pipeline_config",
1802 hdw->state_pipeline_config);
1803 pvr2_hdw_state_sched(hdw);
1804 }
d855497e 1805 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1806 if (fl) return 0;
1807 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1808}
1809
1810
1811static int get_default_tuner_type(struct pvr2_hdw *hdw)
1812{
1813 int unit_number = hdw->unit_number;
1814 int tp = -1;
1815 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1816 tp = tuner[unit_number];
1817 }
1818 if (tp < 0) return -EINVAL;
1819 hdw->tuner_type = tp;
aaf7884d 1820 hdw->tuner_updated = !0;
d855497e
MI		 1821 return 0;
1822}
1823
1824
1825static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1826{
1827 int unit_number = hdw->unit_number;
1828 int tp = 0;
1829 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1830 tp = video_std[unit_number];
6a540254 1831 if (tp) return tp;
d855497e 1832 }
6a540254 1833 return 0;
d855497e
MI		 1834}
1835
1836
1837static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1838{
1839 int unit_number = hdw->unit_number;
1840 int tp = 0;
1841 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1842 tp = tolerance[unit_number];
1843 }
1844 return tp;
1845}
1846
1847
1848static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1849{
1850 /* Try a harmless request to fetch the eeprom's address over
1851 endpoint 1. See what happens. Only the full FX2 image can
1852 respond to this. If this probe fails then likely the FX2
1853 firmware needs be loaded. */
1854 int result;
1855 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1856 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1857 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1858 hdw->cmd_buffer,1,
1859 hdw->cmd_buffer,1);
1860 if (result < 0) break;
1861 } while(0); LOCK_GIVE(hdw->ctl_lock);
1862 if (result) {
1863 pvr2_trace(PVR2_TRACE_INIT,
1864 "Probe of device endpoint 1 result status %d",
1865 result);
1866 } else {
1867 pvr2_trace(PVR2_TRACE_INIT,
1868 "Probe of device endpoint 1 succeeded");
1869 }
1870 return result == 0;
1871}
1872
9f66d4ea
MI		 1873struct pvr2_std_hack {
1874 v4l2_std_id pat; /* Pattern to match */
1875 v4l2_std_id msk; /* Which bits we care about */
1876 v4l2_std_id std; /* What additional standards or default to set */
1877};
1878
1879/* This data structure labels specific combinations of standards from
1880 tveeprom that we'll try to recognize. If we recognize one, then assume
1881 a specified default standard to use. This is here because tveeprom only
1882 tells us about available standards not the intended default standard (if
1883 any) for the device in question. We guess the default based on what has
1884 been reported as available. Note that this is only for guessing a
1885 default - which can always be overridden explicitly - and if the user
1886 has otherwise named a default then that default will always be used in
1887 place of this table. */
ebff0330 1888static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1889 { /* PAL(B/G) */
1890 .pat = V4L2_STD_B|V4L2_STD_GH,
1891 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1892 },
1893 { /* NTSC(M) */
1894 .pat = V4L2_STD_MN,
1895 .std = V4L2_STD_NTSC_M,
1896 },
1897 { /* PAL(I) */
1898 .pat = V4L2_STD_PAL_I,
1899 .std = V4L2_STD_PAL_I,
1900 },
1901 { /* SECAM(L/L') */
1902 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1903 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1904 },
1905 { /* PAL(D/D1/K) */
1906 .pat = V4L2_STD_DK,
ea2562d9 1907 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1908 },
1909};
1910
d855497e
MI		 1911static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1912{
1913 char buf[40];
1914 unsigned int bcnt;
3d290bdb 1915 v4l2_std_id std1,std2,std3;
d855497e
MI		 1916
1917 std1 = get_default_standard(hdw);
3d290bdb 1918 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1919
1920 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1921 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1922 "Supported video standard(s) reported available"
1923 " in hardware: %.*s",
d855497e
MI		 1924 bcnt,buf);
1925
1926 hdw->std_mask_avail = hdw->std_mask_eeprom;
1927
3d290bdb 1928 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1929 if (std2) {
1930 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1931 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1932 "Expanding supported video standards"
1933 " to include: %.*s",
1934 bcnt,buf);
1935 hdw->std_mask_avail |= std2;
1936 }
1937
1938 pvr2_hdw_internal_set_std_avail(hdw);
1939
1940 if (std1) {
1941 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1942 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1943 "Initial video standard forced to %.*s",
1944 bcnt,buf);
1945 hdw->std_mask_cur = std1;
1946 hdw->std_dirty = !0;
1947 pvr2_hdw_internal_find_stdenum(hdw);
1948 return;
1949 }
3d290bdb
MI		 1950 if (std3) {
1951 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1952 pvr2_trace(PVR2_TRACE_STD,
1953 "Initial video standard"
1954 " (determined by device type): %.*s",bcnt,buf);
1955 hdw->std_mask_cur = std3;
1956 hdw->std_dirty = !0;
1957 pvr2_hdw_internal_find_stdenum(hdw);
1958 return;
1959 }
d855497e 1960
9f66d4ea
MI		 1961 {
1962 unsigned int idx;
1963 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1964 if (std_eeprom_maps[idx].msk ?
1965 ((std_eeprom_maps[idx].pat ^
1966 hdw->std_mask_eeprom) &
1967 std_eeprom_maps[idx].msk) :
1968 (std_eeprom_maps[idx].pat !=
1969 hdw->std_mask_eeprom)) continue;
1970 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1971 std_eeprom_maps[idx].std);
56585386 1972 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1973 "Initial video standard guessed as %.*s",
1974 bcnt,buf);
1975 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1976 hdw->std_dirty = !0;
1977 pvr2_hdw_internal_find_stdenum(hdw);
1978 return;
1979 }
1980 }
1981
d855497e
MI		 1982 if (hdw->std_enum_cnt > 1) {
1983 // Autoselect the first listed standard
1984 hdw->std_enum_cur = 1;
1985 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1986 hdw->std_dirty = !0;
56585386 1987 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1988 "Initial video standard auto-selected to %s",
1989 hdw->std_defs[hdw->std_enum_cur-1].name);
1990 return;
1991 }
1992
0885ba1d 1993 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1994 "Unable to select a viable initial video standard");
1995}
1996
1997
e9c64a78
MI		 1998static unsigned int pvr2_copy_i2c_addr_list(
1999 unsigned short *dst, const unsigned char *src,
2000 unsigned int dst_max)
2001{
3ab8d295 2002 unsigned int cnt = 0;
e9c64a78
MI		 2003 if (!src) return 0;
2004 while (src[cnt] && (cnt + 1) < dst_max) {
2005 dst[cnt] = src[cnt];
2006 cnt++;
2007 }
2008 dst[cnt] = I2C_CLIENT_END;
2009 return cnt;
2010}
2011
2012
e17d787c
MI		 2013static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
2014{
2015 /*
2016 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
2017 for cx25840 causes that module to correctly set up its video
2018 scaling. This is really a problem in the cx25840 module itself,
2019 but we work around it here. The problem has not been seen in
2020 ivtv because there VBI is supported and set up. We don't do VBI
2021 here (at least not yet) and thus we never attempted to even set
2022 it up.
2023 */
2024 struct v4l2_format fmt;
2025 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2026 /* We're not using a cx25840 so don't enable the hack */
2027 return;
2028 }
2029
2030 pvr2_trace(PVR2_TRACE_INIT,
2031 "Module ID %u:"
2032 " Executing cx25840 VBI hack",
2033 hdw->decoder_client_id);
2034 memset(&fmt, 0, sizeof(fmt));
2035 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
058caa87
MI		 2036 fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
2037 fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
e17d787c 2038 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
09419af3 2039 vbi, s_sliced_fmt, &fmt.fmt.sliced);
e17d787c
MI		 2040}
2041
2042
1ab5e74f
MI		 2043static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2044 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 2045{
2046 const char *fname;
2047 unsigned char mid;
2048 struct v4l2_subdev *sd;
2049 unsigned int i2ccnt;
2050 const unsigned char *p;
2051 /* Arbitrary count - max # i2c addresses we will probe */
2052 unsigned short i2caddr[25];
2053
2054 mid = cd->module_id;
2055 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2056 if (!fname) {
2057 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2058 "Module ID %u for device %s has no name?"
2059 " The driver might have a configuration problem.",
e9c64a78
MI		 2060 mid,
2061 hdw->hdw_desc->description);
1ab5e74f 2062 return -EINVAL;
e9c64a78 2063 }
bd14d4f8
MI		 2064 pvr2_trace(PVR2_TRACE_INIT,
2065 "Module ID %u (%s) for device %s being loaded...",
2066 mid, fname,
2067 hdw->hdw_desc->description);
e9c64a78
MI		 2068
2069 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2070 ARRAY_SIZE(i2caddr));
2071 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2072 module_i2c_addresses[mid] : NULL) != NULL)) {
2073 /* Second chance: Try default i2c address list */
2074 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2075 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2076 if (i2ccnt) {
2077 pvr2_trace(PVR2_TRACE_INIT,
2078 "Module ID %u:"
2079 " Using default i2c address list",
2080 mid);
2081 }
e9c64a78
MI		 2082 }
2083
2084 if (!i2ccnt) {
2085 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 2086 "Module ID %u (%s) for device %s:"
27108147
MI		 2087 " No i2c addresses."
2088 " The driver might have a configuration problem.",
1ab5e74f
MI		 2089 mid, fname, hdw->hdw_desc->description);
2090 return -EINVAL;
e9c64a78
MI		 2091 }
2092
e9c64a78 2093 if (i2ccnt == 1) {
bd14d4f8
MI		 2094 pvr2_trace(PVR2_TRACE_INIT,
2095 "Module ID %u:"
2096 " Setting up with specified i2c address 0x%x",
2097 mid, i2caddr[0]);
e6574f2f 2098 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
9a1f8b34 2099 fname, i2caddr[0], NULL);
e9c64a78 2100 } else {
bd14d4f8
MI		 2101 pvr2_trace(PVR2_TRACE_INIT,
2102 "Module ID %u:"
2103 " Setting up with address probe list",
2104 mid);
53dacb15 2105 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
9a1f8b34 2106 fname, 0, i2caddr);
e9c64a78
MI		 2107 }
2108
446dfdc6
MI		 2109 if (!sd) {
2110 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2111 "Module ID %u (%s) for device %s failed to load."
2112 " Possible missing sub-device kernel module or"
2113 " initialization failure within module.",
1ab5e74f
MI		 2114 mid, fname, hdw->hdw_desc->description);
2115 return -EIO;
446dfdc6
MI		 2116 }
2117
2118 /* Tag this sub-device instance with the module ID we know about.
2119 In other places we'll use that tag to determine if the instance
2120 requires special handling. */
2121 sd->grp_id = mid;
2122
bd14d4f8 2123 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2124
e9c64a78 2125
00e5f736
MI		 2126 /* client-specific setup... */
2127 switch (mid) {
2128 case PVR2_CLIENT_ID_CX25840:
00e5f736
MI		 2129 case PVR2_CLIENT_ID_SAA7115:
2130 hdw->decoder_client_id = mid;
2131 break;
2132 default: break;
2133 }
1ab5e74f
MI		 2134
2135 return 0;
e9c64a78
MI		 2136}
2137
2138
2139static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2140{
2141 unsigned int idx;
2142 const struct pvr2_string_table *cm;
2143 const struct pvr2_device_client_table *ct;
1ab5e74f 2144 int okFl = !0;
e9c64a78
MI		 2145
2146 cm = &hdw->hdw_desc->client_modules;
2147 for (idx = 0; idx < cm->cnt; idx++) {
2148 request_module(cm->lst[idx]);
2149 }
2150
2151 ct = &hdw->hdw_desc->client_table;
2152 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2153 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2154 }
27108147
MI		 2155 if (!okFl) {
2156 hdw->flag_modulefail = !0;
2157 pvr2_hdw_render_useless(hdw);
2158 }
e9c64a78
MI		 2159}
2160
2161
d855497e
MI		 2162static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2163{
2164 int ret;
2165 unsigned int idx;
2166 struct pvr2_ctrl *cptr;
2167 int reloadFl = 0;
989eb154 2168 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2169 if (!reloadFl) {
2170 reloadFl =
2171 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2172 == 0);
2173 if (reloadFl) {
2174 pvr2_trace(PVR2_TRACE_INIT,
2175 "USB endpoint config looks strange"
2176 "; possibly firmware needs to be"
2177 " loaded");
2178 }
d855497e 2179 }
1d643a37
MI		 2180 if (!reloadFl) {
2181 reloadFl = !pvr2_hdw_check_firmware(hdw);
2182 if (reloadFl) {
2183 pvr2_trace(PVR2_TRACE_INIT,
2184 "Check for FX2 firmware failed"
2185 "; possibly firmware needs to be"
2186 " loaded");
2187 }
d855497e 2188 }
1d643a37
MI		 2189 if (reloadFl) {
2190 if (pvr2_upload_firmware1(hdw) != 0) {
2191 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2192 "Failure uploading firmware1");
2193 }
2194 return;
d855497e 2195 }
d855497e
MI		 2196 }
2197 hdw->fw1_state = FW1_STATE_OK;
2198
d855497e
MI		 2199 if (!pvr2_hdw_dev_ok(hdw)) return;
2200
27764726
MI		 2201 hdw->force_dirty = !0;
2202
989eb154 2203 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2204 pvr2_hdw_cmd_powerup(hdw);
2205 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2206 }
2207
31335b13 2208 /* Take the IR chip out of reset, if appropriate */
27eab384 2209 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
31335b13
MI		 2210 pvr2_issue_simple_cmd(hdw,
2211 FX2CMD_HCW_ZILOG_RESET |
2212 (1 << 8) |
2213 ((0) << 16));
2214 }
2215
d855497e
MI		 2216 // This step MUST happen after the earlier powerup step.
2217 pvr2_i2c_core_init(hdw);
2218 if (!pvr2_hdw_dev_ok(hdw)) return;
2219
e9c64a78 2220 pvr2_hdw_load_modules(hdw);
1ab5e74f 2221 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2222
cc26b076 2223 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
5c6cb4e2 2224
c05c0462 2225 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2226 cptr = hdw->controls + idx;
2227 if (cptr->info->skip_init) continue;
2228 if (!cptr->info->set_value) continue;
2229 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2230 }
2231
e17d787c
MI		 2232 pvr2_hdw_cx25840_vbi_hack(hdw);
2233
1bde0289
MI		 2234 /* Set up special default values for the television and radio
2235 frequencies here. It's not really important what these defaults
2236 are, but I set them to something usable in the Chicago area just
2237 to make driver testing a little easier. */
2238
5a4f5da6
MK		 2239 hdw->freqValTelevision = default_tv_freq;
2240 hdw->freqValRadio = default_radio_freq;
1bde0289 2241
d855497e
MI		 2242 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2243 // thread-safe against the normal pvr2_send_request() mechanism.
2244 // (We should make it thread safe).
2245
aaf7884d
MI		 2246 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2247 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2248 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2249 if (ret < 0) {
2250 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2251 "Unable to determine location of eeprom,"
2252 " skipping");
2253 } else {
2254 hdw->eeprom_addr = ret;
2255 pvr2_eeprom_analyze(hdw);
2256 if (!pvr2_hdw_dev_ok(hdw)) return;
2257 }
2258 } else {
2259 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2260 hdw->tuner_updated = !0;
2261 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2262 }
2263
13a88797
MI		 2264 if (hdw->serial_number) {
2265 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2266 "sn-%lu", hdw->serial_number);
2267 } else if (hdw->unit_number >= 0) {
2268 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2269 "unit-%c",
2270 hdw->unit_number + 'a');
2271 } else {
2272 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2273 "unit-??");
2274 }
2275 hdw->identifier[idx] = 0;
2276
d855497e
MI		 2277 pvr2_hdw_setup_std(hdw);
2278
2279 if (!get_default_tuner_type(hdw)) {
2280 pvr2_trace(PVR2_TRACE_INIT,
2281 "pvr2_hdw_setup: Tuner type overridden to %d",
2282 hdw->tuner_type);
2283 }
2284
d855497e
MI		 2285
2286 if (!pvr2_hdw_dev_ok(hdw)) return;
2287
1df59f0b
MI		 2288 if (hdw->hdw_desc->signal_routing_scheme ==
2289 PVR2_ROUTING_SCHEME_GOTVIEW) {
2290 /* Ensure that GPIO 11 is set to output for GOTVIEW
2291 hardware. */
2292 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2293 }
2294
681c7399 2295 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2296
2297 hdw->vid_stream = pvr2_stream_create();
2298 if (!pvr2_hdw_dev_ok(hdw)) return;
2299 pvr2_trace(PVR2_TRACE_INIT,
2300 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2301 if (hdw->vid_stream) {
2302 idx = get_default_error_tolerance(hdw);
2303 if (idx) {
2304 pvr2_trace(PVR2_TRACE_INIT,
2305 "pvr2_hdw_setup: video stream %p"
2306 " setting tolerance %u",
2307 hdw->vid_stream,idx);
2308 }
2309 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2310 PVR2_VID_ENDPOINT,idx);
2311 }
2312
2313 if (!pvr2_hdw_dev_ok(hdw)) return;
2314
d855497e 2315 hdw->flag_init_ok = !0;
681c7399
MI		 2316
2317 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2318}
2319
2320
681c7399
MI		 2321/* Set up the structure and attempt to put the device into a usable state.
2322 This can be a time-consuming operation, which is why it is not done
2323 internally as part of the create() step. */
2324static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2325{
2326 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2327 do {
d855497e
MI		 2328 pvr2_hdw_setup_low(hdw);
2329 pvr2_trace(PVR2_TRACE_INIT,
2330 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2331 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2332 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2333 if (hdw->flag_init_ok) {
d855497e
MI		 2334 pvr2_trace(
2335 PVR2_TRACE_INFO,
2336 "Device initialization"
2337 " completed successfully.");
2338 break;
2339 }
2340 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2341 pvr2_trace(
2342 PVR2_TRACE_INFO,
2343 "Device microcontroller firmware"
2344 " (re)loaded; it should now reset"
2345 " and reconnect.");
2346 break;
2347 }
2348 pvr2_trace(
2349 PVR2_TRACE_ERROR_LEGS,
2350 "Device initialization was not successful.");
2351 if (hdw->fw1_state == FW1_STATE_MISSING) {
2352 pvr2_trace(
2353 PVR2_TRACE_ERROR_LEGS,
2354 "Giving up since device"
2355 " microcontroller firmware"
2356 " appears to be missing.");
2357 break;
2358 }
2359 }
27108147
MI		 2360 if (hdw->flag_modulefail) {
2361 pvr2_trace(
2362 PVR2_TRACE_ERROR_LEGS,
2363 "***WARNING*** pvrusb2 driver initialization"
2364 " failed due to the failure of one or more"
2365 " sub-device kernel modules.");
2366 pvr2_trace(
2367 PVR2_TRACE_ERROR_LEGS,
2368 "You need to resolve the failing condition"
2369 " before this driver can function. There"
2370 " should be some earlier messages giving more"
2371 " information about the problem.");
515ebf79 2372 break;
27108147 2373 }
d855497e
MI		 2374 if (procreload) {
2375 pvr2_trace(
2376 PVR2_TRACE_ERROR_LEGS,
2377 "Attempting pvrusb2 recovery by reloading"
2378 " primary firmware.");
2379 pvr2_trace(
2380 PVR2_TRACE_ERROR_LEGS,
2381 "If this works, device should disconnect"
2382 " and reconnect in a sane state.");
2383 hdw->fw1_state = FW1_STATE_UNKNOWN;
2384 pvr2_upload_firmware1(hdw);
2385 } else {
2386 pvr2_trace(
2387 PVR2_TRACE_ERROR_LEGS,
2388 "***WARNING*** pvrusb2 device hardware"
2389 " appears to be jammed"
2390 " and I can't clear it.");
2391 pvr2_trace(
2392 PVR2_TRACE_ERROR_LEGS,
2393 "You might need to power cycle"
2394 " the pvrusb2 device"
2395 " in order to recover.");
2396 }
681c7399 2397 } while (0);
d855497e 2398 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2399}
2400
2401
c4a8828d
MI		 2402/* Perform second stage initialization. Set callback pointer first so that
2403 we can avoid a possible initialization race (if the kernel thread runs
2404 before the callback has been set). */
794b1607
MI		 2405int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2406 void (*callback_func)(void *),
2407 void *callback_data)
c4a8828d
MI		 2408{
2409 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2410 if (hdw->flag_disconnected) {
2411 /* Handle a race here: If we're already
2412 disconnected by this point, then give up. If we
2413 get past this then we'll remain connected for
2414 the duration of initialization since the entire
2415 initialization sequence is now protected by the
2416 big_lock. */
2417 break;
2418 }
c4a8828d
MI		 2419 hdw->state_data = callback_data;
2420 hdw->state_func = callback_func;
97f26ff6 2421 pvr2_hdw_setup(hdw);
c4a8828d 2422 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2423 return hdw->flag_init_ok;
c4a8828d
MI		 2424}
2425
2426
2427/* Create, set up, and return a structure for interacting with the
2428 underlying hardware. */
d855497e
MI		 2429struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2430 const struct usb_device_id *devid)
2431{
7fb20fa3 2432 unsigned int idx,cnt1,cnt2,m;
fe15f136 2433 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2434 int valid_std_mask;
2435 struct pvr2_ctrl *cptr;
b72b7bf5 2436 struct usb_device *usb_dev;
989eb154 2437 const struct pvr2_device_desc *hdw_desc;
d855497e 2438 __u8 ifnum;
b30d2441
MI		 2439 struct v4l2_queryctrl qctrl;
2440 struct pvr2_ctl_info *ciptr;
d855497e 2441
b72b7bf5
MI		 2442 usb_dev = interface_to_usbdev(intf);
2443
d130fa8a 2444 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2445
fe15f136
MI		 2446 if (hdw_desc == NULL) {
2447 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2448 " No device description pointer,"
2449 " unable to continue.");
2450 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2451 " please contact Mike Isely <isely@pobox.com>"
2452 " to get it included in the driver\n");
2453 goto fail;
2454 }
2455
ca545f7c 2456 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2457 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2458 hdw,hdw_desc->description);
e67e376b 2459 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
00970beb 2460 hdw_desc->description);
8fd04448
MI		 2461 if (hdw_desc->flag_is_experimental) {
2462 pvr2_trace(PVR2_TRACE_INFO, "**********");
2463 pvr2_trace(PVR2_TRACE_INFO,
2464 "WARNING: Support for this device (%s) is"
2465 " experimental.", hdw_desc->description);
2466 pvr2_trace(PVR2_TRACE_INFO,
2467 "Important functionality might not be"
2468 " entirely working.");
2469 pvr2_trace(PVR2_TRACE_INFO,
2470 "Please consider contacting the driver author to"
2471 " help with further stabilization of the driver.");
2472 pvr2_trace(PVR2_TRACE_INFO, "**********");
2473 }
d855497e 2474 if (!hdw) goto fail;
681c7399
MI		 2475
2476 init_timer(&hdw->quiescent_timer);
2477 hdw->quiescent_timer.data = (unsigned long)hdw;
2478 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2479
6e931375
MI		 2480 init_timer(&hdw->decoder_stabilization_timer);
2481 hdw->decoder_stabilization_timer.data = (unsigned long)hdw;
2482 hdw->decoder_stabilization_timer.function =
2483 pvr2_hdw_decoder_stabilization_timeout;
2484
681c7399
MI		 2485 init_timer(&hdw->encoder_wait_timer);
2486 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2487 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2488
d913d630
MI		 2489 init_timer(&hdw->encoder_run_timer);
2490 hdw->encoder_run_timer.data = (unsigned long)hdw;
2491 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2492
681c7399
MI		 2493 hdw->master_state = PVR2_STATE_DEAD;
2494
2495 init_waitqueue_head(&hdw->state_wait_data);
2496
18103c57 2497 hdw->tuner_signal_stale = !0;
b30d2441 2498 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2499
7fb20fa3
MI		 2500 /* Calculate which inputs are OK */
2501 m = 0;
2502 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2503 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2504 m |= 1 << PVR2_CVAL_INPUT_DTV;
2505 }
7fb20fa3
MI		 2506 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2507 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2508 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2509 hdw->input_avail_mask = m;
1cb03b76 2510 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2511
62433e31
MI		 2512 /* If not a hybrid device, pathway_state never changes. So
2513 initialize it here to what it should forever be. */
2514 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2515 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2516 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2517 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2518 }
2519
c05c0462 2520 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2521 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2522 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2523 GFP_KERNEL);
2524 if (!hdw->controls) goto fail;
989eb154 2525 hdw->hdw_desc = hdw_desc;
27eab384 2526 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
c05c0462
MI		 2527 for (idx = 0; idx < hdw->control_cnt; idx++) {
2528 cptr = hdw->controls + idx;
2529 cptr->hdw = hdw;
2530 }
d855497e
MI		 2531 for (idx = 0; idx < 32; idx++) {
2532 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2533 }
c05c0462 2534 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2535 cptr = hdw->controls + idx;
d855497e
MI		 2536 cptr->info = control_defs+idx;
2537 }
dbc40a0e
MI		 2538
2539 /* Ensure that default input choice is a valid one. */
2540 m = hdw->input_avail_mask;
2541 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2542 if (!((1 << idx) & m)) continue;
2543 hdw->input_val = idx;
2544 break;
2545 }
2546
b30d2441 2547 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2548 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2549 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2550 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2551 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2552 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2553 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2554 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2555 ciptr->name = mpeg_ids[idx].strid;
2556 ciptr->v4l_id = mpeg_ids[idx].id;
2557 ciptr->skip_init = !0;
2558 ciptr->get_value = ctrl_cx2341x_get;
2559 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2560 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2561 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2562 qctrl.id = ciptr->v4l_id;
2563 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2564 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2565 ciptr->set_value = ctrl_cx2341x_set;
2566 }
2567 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2568 PVR2_CTLD_INFO_DESC_SIZE);
2569 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2570 ciptr->default_value = qctrl.default_value;
2571 switch (qctrl.type) {
2572 default:
2573 case V4L2_CTRL_TYPE_INTEGER:
2574 ciptr->type = pvr2_ctl_int;
2575 ciptr->def.type_int.min_value = qctrl.minimum;
2576 ciptr->def.type_int.max_value = qctrl.maximum;
2577 break;
2578 case V4L2_CTRL_TYPE_BOOLEAN:
2579 ciptr->type = pvr2_ctl_bool;
2580 break;
2581 case V4L2_CTRL_TYPE_MENU:
2582 ciptr->type = pvr2_ctl_enum;
2583 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2584 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2585 ciptr->v4l_id);
b30d2441
MI		 2586 for (cnt1 = 0;
2587 ciptr->def.type_enum.value_names[cnt1] != NULL;
2588 cnt1++) { }
2589 ciptr->def.type_enum.count = cnt1;
2590 break;
2591 }
2592 cptr->info = ciptr;
2593 }
d855497e
MI		 2594
2595 // Initialize video standard enum dynamic control
2596 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2597 if (cptr) {
2598 memcpy(&hdw->std_info_enum,cptr->info,
2599 sizeof(hdw->std_info_enum));
2600 cptr->info = &hdw->std_info_enum;
2601
2602 }
2603 // Initialize control data regarding video standard masks
2604 valid_std_mask = pvr2_std_get_usable();
2605 for (idx = 0; idx < 32; idx++) {
2606 if (!(valid_std_mask & (1 << idx))) continue;
2607 cnt1 = pvr2_std_id_to_str(
2608 hdw->std_mask_names[idx],
2609 sizeof(hdw->std_mask_names[idx])-1,
2610 1 << idx);
2611 hdw->std_mask_names[idx][cnt1] = 0;
2612 }
2613 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2614 if (cptr) {
2615 memcpy(&hdw->std_info_avail,cptr->info,
2616 sizeof(hdw->std_info_avail));
2617 cptr->info = &hdw->std_info_avail;
2618 hdw->std_info_avail.def.type_bitmask.bit_names =
2619 hdw->std_mask_ptrs;
2620 hdw->std_info_avail.def.type_bitmask.valid_bits =
2621 valid_std_mask;
2622 }
2623 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2624 if (cptr) {
2625 memcpy(&hdw->std_info_cur,cptr->info,
2626 sizeof(hdw->std_info_cur));
2627 cptr->info = &hdw->std_info_cur;
2628 hdw->std_info_cur.def.type_bitmask.bit_names =
2629 hdw->std_mask_ptrs;
2630 hdw->std_info_avail.def.type_bitmask.valid_bits =
2631 valid_std_mask;
2632 }
2633
432907f7 2634 hdw->cropcap_stale = !0;
d855497e
MI		 2635 hdw->eeprom_addr = -1;
2636 hdw->unit_number = -1;
8079384e
MI		 2637 hdw->v4l_minor_number_video = -1;
2638 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2639 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2640 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2641 if (!hdw->ctl_write_buffer) goto fail;
2642 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2643 if (!hdw->ctl_read_buffer) goto fail;
2644 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2645 if (!hdw->ctl_write_urb) goto fail;
2646 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2647 if (!hdw->ctl_read_urb) goto fail;
2648
70ad6383 2649 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
b72b7bf5
MI		 2650 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2651 "Error registering with v4l core, giving up");
2652 goto fail;
2653 }
8df0c87c 2654 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2655 for (idx = 0; idx < PVR_NUM; idx++) {
2656 if (unit_pointers[idx]) continue;
2657 hdw->unit_number = idx;
2658 unit_pointers[idx] = hdw;
2659 break;
2660 }
8df0c87c 2661 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2662
2663 cnt1 = 0;
2664 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2665 cnt1 += cnt2;
2666 if (hdw->unit_number >= 0) {
2667 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2668 ('a' + hdw->unit_number));
2669 cnt1 += cnt2;
2670 }
2671 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2672 hdw->name[cnt1] = 0;
2673
681c7399
MI		 2674 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2675 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
681c7399 2676
d855497e
MI		 2677 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2678 hdw->unit_number,hdw->name);
2679
2680 hdw->tuner_type = -1;
2681 hdw->flag_ok = !0;
d855497e
MI		 2682
2683 hdw->usb_intf = intf;
b72b7bf5 2684 hdw->usb_dev = usb_dev;
d855497e 2685
87e3495c 2686 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2687
d855497e
MI		 2688 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2689 usb_set_interface(hdw->usb_dev,ifnum,0);
2690
2691 mutex_init(&hdw->ctl_lock_mutex);
2692 mutex_init(&hdw->big_lock_mutex);
2693
2694 return hdw;
2695 fail:
2696 if (hdw) {
681c7399 2697 del_timer_sync(&hdw->quiescent_timer);
6e931375 2698 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2699 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2700 del_timer_sync(&hdw->encoder_wait_timer);
2701 if (hdw->workqueue) {
2702 flush_workqueue(hdw->workqueue);
2703 destroy_workqueue(hdw->workqueue);
2704 hdw->workqueue = NULL;
2705 }
5e55d2ce
MK		 2706 usb_free_urb(hdw->ctl_read_urb);
2707 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2708 kfree(hdw->ctl_read_buffer);
2709 kfree(hdw->ctl_write_buffer);
2710 kfree(hdw->controls);
2711 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2712 kfree(hdw->std_defs);
2713 kfree(hdw->std_enum_names);
d855497e
MI		 2714 kfree(hdw);
2715 }
a0fd1cb1 2716 return NULL;
d855497e
MI		 2717}
2718
2719
2720/* Remove _all_ associations between this driver and the underlying USB
2721 layer. */
07e337ee 2722static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2723{
2724 if (hdw->flag_disconnected) return;
2725 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2726 if (hdw->ctl_read_urb) {
2727 usb_kill_urb(hdw->ctl_read_urb);
2728 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2729 hdw->ctl_read_urb = NULL;
d855497e
MI		 2730 }
2731 if (hdw->ctl_write_urb) {
2732 usb_kill_urb(hdw->ctl_write_urb);
2733 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2734 hdw->ctl_write_urb = NULL;
d855497e
MI		 2735 }
2736 if (hdw->ctl_read_buffer) {
2737 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2738 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2739 }
2740 if (hdw->ctl_write_buffer) {
2741 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2742 hdw->ctl_write_buffer = NULL;
d855497e 2743 }
d855497e 2744 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2745 /* If we don't do this, then there will be a dangling struct device
2746 reference to our disappearing device persisting inside the V4L
2747 core... */
dc070bcc 2748 v4l2_device_disconnect(&hdw->v4l2_dev);
a0fd1cb1
MI		 2749 hdw->usb_dev = NULL;
2750 hdw->usb_intf = NULL;
681c7399 2751 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2752}
2753
2754
2755/* Destroy hardware interaction structure */
2756void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2757{
401c27ce 2758 if (!hdw) return;
d855497e 2759 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2760 if (hdw->workqueue) {
2761 flush_workqueue(hdw->workqueue);
2762 destroy_workqueue(hdw->workqueue);
2763 hdw->workqueue = NULL;
2764 }
8f59100a 2765 del_timer_sync(&hdw->quiescent_timer);
6e931375 2766 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2767 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2768 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2769 if (hdw->fw_buffer) {
2770 kfree(hdw->fw_buffer);
a0fd1cb1 2771 hdw->fw_buffer = NULL;
d855497e
MI		 2772 }
2773 if (hdw->vid_stream) {
2774 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2775 hdw->vid_stream = NULL;
d855497e 2776 }
d855497e 2777 pvr2_i2c_core_done(hdw);
b72b7bf5 2778 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2779 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2780 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2781 if ((hdw->unit_number >= 0) &&
2782 (hdw->unit_number < PVR_NUM) &&
2783 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2784 unit_pointers[hdw->unit_number] = NULL;
d855497e 2785 }
8df0c87c 2786 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2787 kfree(hdw->controls);
2788 kfree(hdw->mpeg_ctrl_info);
2789 kfree(hdw->std_defs);
2790 kfree(hdw->std_enum_names);
d855497e
MI		 2791 kfree(hdw);
2792}
2793
2794
d855497e
MI		 2795int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2796{
2797 return (hdw && hdw->flag_ok);
2798}
2799
2800
2801/* Called when hardware has been unplugged */
2802void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2803{
2804 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2805 LOCK_TAKE(hdw->big_lock);
2806 LOCK_TAKE(hdw->ctl_lock);
2807 pvr2_hdw_remove_usb_stuff(hdw);
2808 LOCK_GIVE(hdw->ctl_lock);
2809 LOCK_GIVE(hdw->big_lock);
2810}
2811
2812
2813// Attempt to autoselect an appropriate value for std_enum_cur given
2814// whatever is currently in std_mask_cur
07e337ee 2815static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2816{
2817 unsigned int idx;
2818 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2819 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2820 hdw->std_enum_cur = idx;
2821 return;
2822 }
2823 }
2824 hdw->std_enum_cur = 0;
2825}
2826
2827
2828// Calculate correct set of enumerated standards based on currently known
2829// set of available standards bits.
07e337ee 2830static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2831{
2832 struct v4l2_standard *newstd;
2833 unsigned int std_cnt;
2834 unsigned int idx;
2835
2836 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2837
2838 if (hdw->std_defs) {
2839 kfree(hdw->std_defs);
a0fd1cb1 2840 hdw->std_defs = NULL;
d855497e
MI		 2841 }
2842 hdw->std_enum_cnt = 0;
2843 if (hdw->std_enum_names) {
2844 kfree(hdw->std_enum_names);
a0fd1cb1 2845 hdw->std_enum_names = NULL;
d855497e
MI		 2846 }
2847
2848 if (!std_cnt) {
2849 pvr2_trace(
2850 PVR2_TRACE_ERROR_LEGS,
2851 "WARNING: Failed to identify any viable standards");
2852 }
c05df8b3
XW		 2853
2854 /* Set up the dynamic control for this standard */
d855497e 2855 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
c05df8b3
XW		 2856 if (hdw->std_enum_names) {
2857 hdw->std_enum_names[0] = "none";
2858 for (idx = 0; idx < std_cnt; idx++)
2859 hdw->std_enum_names[idx+1] = newstd[idx].name;
2860 hdw->std_info_enum.def.type_enum.value_names =
2861 hdw->std_enum_names;
2862 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2863 } else {
2864 pvr2_trace(
2865 PVR2_TRACE_ERROR_LEGS,
2866 "WARNING: Failed to alloc memory for names");
2867 hdw->std_info_enum.def.type_enum.value_names = NULL;
2868 hdw->std_info_enum.def.type_enum.count = 0;
2869 }
d855497e
MI		 2870 hdw->std_defs = newstd;
2871 hdw->std_enum_cnt = std_cnt+1;
2872 hdw->std_enum_cur = 0;
2873 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2874}
2875
2876
2877int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2878 struct v4l2_standard *std,
2879 unsigned int idx)
2880{
2881 int ret = -EINVAL;
2882 if (!idx) return ret;
2883 LOCK_TAKE(hdw->big_lock); do {
2884 if (idx >= hdw->std_enum_cnt) break;
2885 idx--;
2886 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2887 ret = 0;
2888 } while (0); LOCK_GIVE(hdw->big_lock);
2889 return ret;
2890}
2891
2892
2893/* Get the number of defined controls */
2894unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2895{
c05c0462 2896 return hdw->control_cnt;
d855497e
MI		 2897}
2898
2899
2900/* Retrieve a control handle given its index (0..count-1) */
2901struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2902 unsigned int idx)
2903{
a0fd1cb1 2904 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2905 return hdw->controls + idx;
2906}
2907
2908
2909/* Retrieve a control handle given its index (0..count-1) */
2910struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2911 unsigned int ctl_id)
2912{
2913 struct pvr2_ctrl *cptr;
2914 unsigned int idx;
2915 int i;
2916
2917 /* This could be made a lot more efficient, but for now... */
c05c0462 2918 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2919 cptr = hdw->controls + idx;
2920 i = cptr->info->internal_id;
2921 if (i && (i == ctl_id)) return cptr;
2922 }
a0fd1cb1 2923 return NULL;
d855497e
MI		 2924}
2925
2926
a761f431 2927/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2928struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2929{
2930 struct pvr2_ctrl *cptr;
2931 unsigned int idx;
2932 int i;
2933
2934 /* This could be made a lot more efficient, but for now... */
c05c0462 2935 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2936 cptr = hdw->controls + idx;
2937 i = cptr->info->v4l_id;
2938 if (i && (i == ctl_id)) return cptr;
2939 }
a0fd1cb1 2940 return NULL;
d855497e
MI		 2941}
2942
2943
a761f431
MI		 2944/* Given a V4L ID for its immediate predecessor, retrieve the control
2945 structure associated with it. */
2946struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2947 unsigned int ctl_id)
2948{
2949 struct pvr2_ctrl *cptr,*cp2;
2950 unsigned int idx;
2951 int i;
2952
2953 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2954 cp2 = NULL;
a761f431
MI		 2955 for (idx = 0; idx < hdw->control_cnt; idx++) {
2956 cptr = hdw->controls + idx;
2957 i = cptr->info->v4l_id;
2958 if (!i) continue;
2959 if (i <= ctl_id) continue;
2960 if (cp2 && (cp2->info->v4l_id < i)) continue;
2961 cp2 = cptr;
2962 }
2963 return cp2;
a0fd1cb1 2964 return NULL;
a761f431
MI		 2965}
2966
2967
d855497e
MI		 2968static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2969{
2970 switch (tp) {
2971 case pvr2_ctl_int: return "integer";
2972 case pvr2_ctl_enum: return "enum";
33213963 2973 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2974 case pvr2_ctl_bitmask: return "bitmask";
2975 }
2976 return "";
2977}
2978
2979
2641df36
MI		 2980static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2981 const char *name, int val)
2982{
2983 struct v4l2_control ctrl;
2984 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2985 memset(&ctrl, 0, sizeof(ctrl));
2986 ctrl.id = id;
2987 ctrl.value = val;
2988 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2989}
2990
2991#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
27764726 2992 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2641df36
MI		 2993 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2994 }
2995
5ceaad14 2996/* Execute whatever commands are required to update the state of all the
2641df36 2997 sub-devices so that they match our current control values. */
5ceaad14
MI		 2998static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2999{
edb9dcb8
MI		 3000 struct v4l2_subdev *sd;
3001 unsigned int id;
3002 pvr2_subdev_update_func fp;
3003
75212a02
MI		 3004 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
3005
27764726 3006 if (hdw->tuner_updated || hdw->force_dirty) {
75212a02
MI		 3007 struct tuner_setup setup;
3008 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
3009 hdw->tuner_type);
3010 if (((int)(hdw->tuner_type)) >= 0) {
fcd62cf7 3011 memset(&setup, 0, sizeof(setup));
75212a02
MI		 3012 setup.addr = ADDR_UNSET;
3013 setup.type = hdw->tuner_type;
3014 setup.mode_mask = T_RADIO | T_ANALOG_TV;
3015 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3016 tuner, s_type_addr, &setup);
3017 }
3018 }
3019
27764726 3020 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
b481880b 3021 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 3022 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3023 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3024 tuner, s_radio);
3025 } else {
3026 v4l2_std_id vs;
3027 vs = hdw->std_mask_cur;
3028 v4l2_device_call_all(&hdw->v4l2_dev, 0,
f41737ec 3029 core, s_std, vs);
a6862da2 3030 pvr2_hdw_cx25840_vbi_hack(hdw);
2641df36
MI		 3031 }
3032 hdw->tuner_signal_stale = !0;
3033 hdw->cropcap_stale = !0;
3034 }
3035
3036 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
3037 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
3038 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
3039 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
3040 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
3041 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
3042 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
3043 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
3044 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
3045
27764726 3046 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2641df36
MI		 3047 struct v4l2_tuner vt;
3048 memset(&vt, 0, sizeof(vt));
50e9efd6
HV		 3049 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
3050 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2641df36
MI		 3051 vt.audmode = hdw->audiomode_val;
3052 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3053 }
3054
27764726 3055 if (hdw->freqDirty || hdw->force_dirty) {
2641df36
MI		 3056 unsigned long fv;
3057 struct v4l2_frequency freq;
3058 fv = pvr2_hdw_get_cur_freq(hdw);
3059 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3060 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3061 memset(&freq, 0, sizeof(freq));
3062 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3063 /* ((fv * 1000) / 62500) */
3064 freq.frequency = (fv * 2) / 125;
3065 } else {
3066 freq.frequency = fv / 62500;
3067 }
3068 /* tuner-core currently doesn't seem to care about this, but
3069 let's set it anyway for completeness. */
3070 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3071 freq.type = V4L2_TUNER_RADIO;
3072 } else {
3073 freq.type = V4L2_TUNER_ANALOG_TV;
3074 }
3075 freq.tuner = 0;
3076 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3077 s_frequency, &freq);
3078 }
3079
27764726 3080 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
fa190ee9 3081 struct v4l2_mbus_framefmt fmt;
2641df36 3082 memset(&fmt, 0, sizeof(fmt));
fa190ee9
HV		 3083 fmt.width = hdw->res_hor_val;
3084 fmt.height = hdw->res_ver_val;
3085 fmt.code = V4L2_MBUS_FMT_FIXED;
7dfdf1ee 3086 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
fa190ee9
HV		 3087 fmt.width, fmt.height);
3088 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_mbus_fmt, &fmt);
2641df36
MI		 3089 }
3090
27764726 3091 if (hdw->srate_dirty || hdw->force_dirty) {
01c59df8
MI		 3092 u32 val;
3093 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3094 hdw->srate_val);
3095 switch (hdw->srate_val) {
3096 default:
3097 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3098 val = 48000;
3099 break;
3100 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3101 val = 44100;
3102 break;
3103 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3104 val = 32000;
3105 break;
3106 }
3107 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3108 audio, s_clock_freq, val);
3109 }
3110
2641df36
MI		 3111 /* Unable to set crop parameters; there is apparently no equivalent
3112 for VIDIOC_S_CROP */
3113
edb9dcb8
MI		 3114 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3115 id = sd->grp_id;
3116 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3117 fp = pvr2_module_update_functions[id];
3118 if (!fp) continue;
3119 (*fp)(hdw, sd);
3120 }
2641df36 3121
27764726 3122 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2641df36
MI		 3123 pvr2_hdw_status_poll(hdw);
3124 }
5ceaad14
MI		 3125}
3126
3127
681c7399
MI		 3128/* Figure out if we need to commit control changes. If so, mark internal
3129 state flags to indicate this fact and return true. Otherwise do nothing
3130 else and return false. */
3131static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3132{
d855497e
MI		 3133 unsigned int idx;
3134 struct pvr2_ctrl *cptr;
3135 int value;
27764726 3136 int commit_flag = hdw->force_dirty;
d855497e
MI		 3137 char buf[100];
3138 unsigned int bcnt,ccnt;
3139
c05c0462 3140 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3141 cptr = hdw->controls + idx;
5fa1247a 3142 if (!cptr->info->is_dirty) continue;
d855497e 3143 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3144 commit_flag = !0;
d855497e 3145
fe23a280 3146 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3147 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3148 cptr->info->name);
3149 value = 0;
3150 cptr->info->get_value(cptr,&value);
3151 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3152 buf+bcnt,
3153 sizeof(buf)-bcnt,&ccnt);
3154 bcnt += ccnt;
3155 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3156 get_ctrl_typename(cptr->info->type));
3157 pvr2_trace(PVR2_TRACE_CTL,
3158 "/*--TRACE_COMMIT--*/ %.*s",
3159 bcnt,buf);
3160 }
3161
3162 if (!commit_flag) {
3163 /* Nothing has changed */
3164 return 0;
3165 }
3166
681c7399
MI		 3167 hdw->state_pipeline_config = 0;
3168 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3169 pvr2_hdw_state_sched(hdw);
3170
3171 return !0;
3172}
3173
3174
3175/* Perform all operations needed to commit all control changes. This must
3176 be performed in synchronization with the pipeline state and is thus
3177 expected to be called as part of the driver's worker thread. Return
3178 true if commit successful, otherwise return false to indicate that
3179 commit isn't possible at this time. */
3180static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3181{
3182 unsigned int idx;
3183 struct pvr2_ctrl *cptr;
3184 int disruptive_change;
3185
9bf98321
MI		 3186 if (hdw->input_dirty && hdw->state_pathway_ok &&
3187 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3188 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3189 hdw->pathway_state)) {
3190 /* Change of mode being asked for... */
3191 hdw->state_pathway_ok = 0;
3192 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3193 }
3194 if (!hdw->state_pathway_ok) {
3195 /* Can't commit anything until pathway is ok. */
3196 return 0;
3197 }
3198
ab062fe3
MI		 3199 /* Handle some required side effects when the video standard is
3200 changed.... */
d855497e 3201 if (hdw->std_dirty) {
d855497e 3202 int nvres;
00528d9c 3203 int gop_size;
d855497e
MI		 3204 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3205 nvres = 480;
00528d9c 3206 gop_size = 15;
d855497e
MI		 3207 } else {
3208 nvres = 576;
00528d9c 3209 gop_size = 12;
d855497e 3210 }
00528d9c
MI		 3211 /* Rewrite the vertical resolution to be appropriate to the
3212 video standard that has been selected. */
d855497e
MI		 3213 if (nvres != hdw->res_ver_val) {
3214 hdw->res_ver_val = nvres;
3215 hdw->res_ver_dirty = !0;
3216 }
00528d9c
MI		 3217 /* Rewrite the GOP size to be appropriate to the video
3218 standard that has been selected. */
3219 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3220 struct v4l2_ext_controls cs;
3221 struct v4l2_ext_control c1;
3222 memset(&cs, 0, sizeof(cs));
3223 memset(&c1, 0, sizeof(c1));
3224 cs.controls = &c1;
3225 cs.count = 1;
3226 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3227 c1.value = gop_size;
3228 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3229 VIDIOC_S_EXT_CTRLS);
3230 }
d855497e
MI		 3231 }
3232
e784bfb9 3233 /* The broadcast decoder can only scale down, so if
3234 * res_*_dirty && crop window < output format ==> enlarge crop.
3235 *
3236 * The mpeg encoder receives fields of res_hor_val dots and
3237 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3238 */
3239 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3240 hdw->cropw_val = hdw->res_hor_val;
3241 hdw->cropw_dirty = !0;
3242 } else if (hdw->cropw_dirty) {
3243 hdw->res_hor_dirty = !0; /* must rescale */
3244 hdw->res_hor_val = min(720, hdw->cropw_val);
3245 }
3246 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3247 hdw->croph_val = hdw->res_ver_val;
3248 hdw->croph_dirty = !0;
3249 } else if (hdw->croph_dirty) {
3250 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3251 hdw->res_ver_dirty = !0;
3252 hdw->res_ver_val = min(nvres, hdw->croph_val);
3253 }
3254
681c7399
MI		 3255 /* If any of the below has changed, then we can't do the update
3256 while the pipeline is running. Pipeline must be paused first
3257 and decoder -> encoder connection be made quiescent before we
3258 can proceed. */
3259 disruptive_change =
3260 (hdw->std_dirty ||
3261 hdw->enc_unsafe_stale ||
3262 hdw->srate_dirty ||
3263 hdw->res_ver_dirty ||
3264 hdw->res_hor_dirty ||
755879c6
MI		 3265 hdw->cropw_dirty ||
3266 hdw->croph_dirty ||
681c7399
MI		 3267 hdw->input_dirty ||
3268 (hdw->active_stream_type != hdw->desired_stream_type));
3269 if (disruptive_change && !hdw->state_pipeline_idle) {
3270 /* Pipeline is not idle; we can't proceed. Arrange to
3271 cause pipeline to stop so that we can try this again
3272 later.... */
3273 hdw->state_pipeline_pause = !0;
3274 return 0;
275b2e28
PK		 3275 }
3276
b30d2441
MI		 3277 if (hdw->srate_dirty) {
3278 /* Write new sample rate into control structure since
3279 * the master copy is stale. We must track srate
3280 * separate from the mpeg control structure because
3281 * other logic also uses this value. */
3282 struct v4l2_ext_controls cs;
3283 struct v4l2_ext_control c1;
3284 memset(&cs,0,sizeof(cs));
3285 memset(&c1,0,sizeof(c1));
3286 cs.controls = &c1;
3287 cs.count = 1;
3288 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3289 c1.value = hdw->srate_val;
01f1e44f 3290 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3291 }
c05c0462 3292
681c7399
MI		 3293 if (hdw->active_stream_type != hdw->desired_stream_type) {
3294 /* Handle any side effects of stream config here */
3295 hdw->active_stream_type = hdw->desired_stream_type;
3296 }
3297
1df59f0b
MI		 3298 if (hdw->hdw_desc->signal_routing_scheme ==
3299 PVR2_ROUTING_SCHEME_GOTVIEW) {
3300 u32 b;
3301 /* Handle GOTVIEW audio switching */
3302 pvr2_hdw_gpio_get_out(hdw,&b);
3303 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3304 /* Set GPIO 11 */
3305 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3306 } else {
3307 /* Clear GPIO 11 */
3308 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3309 }
3310 }
3311
e68a619a
MI		 3312 /* Check and update state for all sub-devices. */
3313 pvr2_subdev_update(hdw);
3314
75212a02 3315 hdw->tuner_updated = 0;
27764726 3316 hdw->force_dirty = 0;
5ceaad14
MI		 3317 for (idx = 0; idx < hdw->control_cnt; idx++) {
3318 cptr = hdw->controls + idx;
3319 if (!cptr->info->clear_dirty) continue;
3320 cptr->info->clear_dirty(cptr);
3321 }
3322
62433e31
MI		 3323 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3324 hdw->state_encoder_run) {
3325 /* If encoder isn't running or it can't be touched, then
3326 this will get worked out later when we start the
3327 encoder. */
681c7399
MI		 3328 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3329 }
d855497e 3330
681c7399 3331 hdw->state_pipeline_config = !0;
432907f7
MI		 3332 /* Hardware state may have changed in a way to cause the cropping
3333 capabilities to have changed. So mark it stale, which will
3334 cause a later re-fetch. */
681c7399
MI		 3335 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3336 return !0;
d855497e
MI		 3337}
3338
3339
3340int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3341{
681c7399
MI		 3342 int fl;
3343 LOCK_TAKE(hdw->big_lock);
3344 fl = pvr2_hdw_commit_setup(hdw);
3345 LOCK_GIVE(hdw->big_lock);
3346 if (!fl) return 0;
3347 return pvr2_hdw_wait(hdw,0);
3348}
3349
3350
681c7399 3351static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3352{
681c7399
MI		 3353 int fl = 0;
3354 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3355 LOCK_TAKE(hdw->big_lock); do {
681c7399 3356 fl = pvr2_hdw_state_eval(hdw);
d855497e 3357 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3358 if (fl && hdw->state_func) {
3359 hdw->state_func(hdw->state_data);
3360 }
d855497e
MI		 3361}
3362
3363
681c7399 3364static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3365{
681c7399
MI		 3366 return wait_event_interruptible(
3367 hdw->state_wait_data,
3368 (hdw->state_stale == 0) &&
3369 (!state || (hdw->master_state != state)));
3370}
3371
3372
d855497e
MI		 3373/* Return name for this driver instance */
3374const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3375{
3376 return hdw->name;
3377}
3378
3379
78a47101
MI		 3380const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3381{
3382 return hdw->hdw_desc->description;
3383}
3384
3385
3386const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3387{
3388 return hdw->hdw_desc->shortname;
3389}
3390
3391
d855497e
MI		 3392int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3393{
3394 int result;
3395 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3396 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3397 result = pvr2_send_request(hdw,
3398 hdw->cmd_buffer,1,
3399 hdw->cmd_buffer,1);
3400 if (result < 0) break;
3401 result = (hdw->cmd_buffer[0] != 0);
3402 } while(0); LOCK_GIVE(hdw->ctl_lock);
3403 return result;
3404}
3405
3406
18103c57
MI		 3407/* Execute poll of tuner status */
3408void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3409{
d855497e 3410 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3411 pvr2_hdw_status_poll(hdw);
d855497e 3412 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3413}
3414
3415
432907f7
MI		 3416static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3417{
3418 if (!hdw->cropcap_stale) {
432907f7
MI		 3419 return 0;
3420 }
a51f5000 3421 pvr2_hdw_status_poll(hdw);
432907f7 3422 if (hdw->cropcap_stale) {
432907f7
MI		 3423 return -EIO;
3424 }
3425 return 0;
3426}
3427
3428
3429/* Return information about cropping capabilities */
3430int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3431{
3432 int stat = 0;
3433 LOCK_TAKE(hdw->big_lock);
3434 stat = pvr2_hdw_check_cropcap(hdw);
3435 if (!stat) {
432907f7
MI		 3436 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3437 }
3438 LOCK_GIVE(hdw->big_lock);
3439 return stat;
3440}
3441
3442
18103c57
MI		 3443/* Return information about the tuner */
3444int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3445{
3446 LOCK_TAKE(hdw->big_lock); do {
3447 if (hdw->tuner_signal_stale) {
a51f5000 3448 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3449 }
3450 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3451 } while (0); LOCK_GIVE(hdw->big_lock);
3452 return 0;
d855497e
MI		 3453}
3454
3455
3456/* Get handle to video output stream */
3457struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3458{
3459 return hp->vid_stream;
3460}
3461
3462
3463void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3464{
4f1a3e5b 3465 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3466 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3467 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
ed3261a8 3468 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3469 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3470 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3471 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3472 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3473 } while (0); LOCK_GIVE(hdw->big_lock);
3474}
3475
4db666cc
MI		 3476
3477/* Grab EEPROM contents, needed for direct method. */
3478#define EEPROM_SIZE 8192
3479#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3480static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3481{
3482 struct i2c_msg msg[2];
3483 u8 *eeprom;
3484 u8 iadd[2];
3485 u8 addr;
3486 u16 eepromSize;
3487 unsigned int offs;
3488 int ret;
3489 int mode16 = 0;
3490 unsigned pcnt,tcnt;
3491 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3492 if (!eeprom) {
3493 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3494 "Failed to allocate memory"
3495 " required to read eeprom");
3496 return NULL;
3497 }
3498
3499 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3500 hdw->eeprom_addr);
3501 addr = hdw->eeprom_addr;
3502 /* Seems that if the high bit is set, then the *real* eeprom
3503 address is shifted right now bit position (noticed this in
3504 newer PVR USB2 hardware) */
3505 if (addr & 0x80) addr >>= 1;
3506
3507 /* FX2 documentation states that a 16bit-addressed eeprom is
3508 expected if the I2C address is an odd number (yeah, this is
3509 strange but it's what they do) */
3510 mode16 = (addr & 1);
3511 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3512 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3513 " using %d bit addressing",eepromSize,addr,
3514 mode16 ? 16 : 8);
3515
3516 msg[0].addr = addr;
3517 msg[0].flags = 0;
3518 msg[0].len = mode16 ? 2 : 1;
3519 msg[0].buf = iadd;
3520 msg[1].addr = addr;
3521 msg[1].flags = I2C_M_RD;
3522
3523 /* We have to do the actual eeprom data fetch ourselves, because
3524 (1) we're only fetching part of the eeprom, and (2) if we were
3525 getting the whole thing our I2C driver can't grab it in one
3526 pass - which is what tveeprom is otherwise going to attempt */
3527 memset(eeprom,0,EEPROM_SIZE);
3528 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3529 pcnt = 16;
3530 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3531 offs = tcnt + (eepromSize - EEPROM_SIZE);
3532 if (mode16) {
3533 iadd[0] = offs >> 8;
3534 iadd[1] = offs;
3535 } else {
3536 iadd[0] = offs;
3537 }
3538 msg[1].len = pcnt;
3539 msg[1].buf = eeprom+tcnt;
3540 if ((ret = i2c_transfer(&hdw->i2c_adap,
3541 msg,ARRAY_SIZE(msg))) != 2) {
3542 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3543 "eeprom fetch set offs err=%d",ret);
3544 kfree(eeprom);
3545 return NULL;
3546 }
3547 }
3548 return eeprom;
3549}
3550
3551
3552void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
568efaa2 3553 int mode,
4db666cc 3554 int enable_flag)
d855497e
MI		 3555{
3556 int ret;
3557 u16 address;
3558 unsigned int pipe;
3559 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3560 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3561
3562 if (!enable_flag) {
3563 pvr2_trace(PVR2_TRACE_FIRMWARE,
3564 "Cleaning up after CPU firmware fetch");
3565 kfree(hdw->fw_buffer);
a0fd1cb1 3566 hdw->fw_buffer = NULL;
d855497e 3567 hdw->fw_size = 0;
4db666cc
MI		 3568 if (hdw->fw_cpu_flag) {
3569 /* Now release the CPU. It will disconnect
3570 and reconnect later. */
3571 pvr2_hdw_cpureset_assert(hdw,0);
3572 }
d855497e
MI		 3573 break;
3574 }
3575
568efaa2 3576 hdw->fw_cpu_flag = (mode != 2);
4db666cc 3577 if (hdw->fw_cpu_flag) {
568efaa2 3578 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
4db666cc 3579 pvr2_trace(PVR2_TRACE_FIRMWARE,
568efaa2
MI		 3580 "Preparing to suck out CPU firmware"
3581 " (size=%u)", hdw->fw_size);
4db666cc
MI		 3582 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3583 if (!hdw->fw_buffer) {
3584 hdw->fw_size = 0;
3585 break;
3586 }
d855497e 3587
4db666cc
MI		 3588 /* We have to hold the CPU during firmware upload. */
3589 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3590
4db666cc
MI		 3591 /* download the firmware from address 0000-1fff in 2048
3592 (=0x800) bytes chunk. */
d855497e 3593
4db666cc
MI		 3594 pvr2_trace(PVR2_TRACE_FIRMWARE,
3595 "Grabbing CPU firmware");
3596 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3597 for(address = 0; address < hdw->fw_size;
3598 address += 0x800) {
3599 ret = usb_control_msg(hdw->usb_dev,pipe,
3600 0xa0,0xc0,
3601 address,0,
3602 hdw->fw_buffer+address,
3603 0x800,HZ);
3604 if (ret < 0) break;
3605 }
d855497e 3606
4db666cc
MI		 3607 pvr2_trace(PVR2_TRACE_FIRMWARE,
3608 "Done grabbing CPU firmware");
3609 } else {
3610 pvr2_trace(PVR2_TRACE_FIRMWARE,
3611 "Sucking down EEPROM contents");
3612 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3613 if (!hdw->fw_buffer) {
3614 pvr2_trace(PVR2_TRACE_FIRMWARE,
3615 "EEPROM content suck failed.");
3616 break;
3617 }
3618 hdw->fw_size = EEPROM_SIZE;
3619 pvr2_trace(PVR2_TRACE_FIRMWARE,
3620 "Done sucking down EEPROM contents");
3621 }
d855497e
MI		 3622
3623 } while (0); LOCK_GIVE(hdw->big_lock);
3624}
3625
3626
3627/* Return true if we're in a mode for retrieval CPU firmware */
3628int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3629{
5fa1247a 3630 return hdw->fw_buffer != NULL;
d855497e
MI		 3631}
3632
3633
3634int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3635 char *buf,unsigned int cnt)
3636{
3637 int ret = -EINVAL;
3638 LOCK_TAKE(hdw->big_lock); do {
3639 if (!buf) break;
3640 if (!cnt) break;
3641
3642 if (!hdw->fw_buffer) {
3643 ret = -EIO;
3644 break;
3645 }
3646
3647 if (offs >= hdw->fw_size) {
3648 pvr2_trace(PVR2_TRACE_FIRMWARE,
3649 "Read firmware data offs=%d EOF",
3650 offs);
3651 ret = 0;
3652 break;
3653 }
3654
3655 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3656
3657 memcpy(buf,hdw->fw_buffer+offs,cnt);
3658
3659 pvr2_trace(PVR2_TRACE_FIRMWARE,
3660 "Read firmware data offs=%d cnt=%d",
3661 offs,cnt);
3662 ret = cnt;
3663 } while (0); LOCK_GIVE(hdw->big_lock);
3664
3665 return ret;
3666}
3667
3668
fd5a75fe 3669int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3670 enum pvr2_v4l_type index)
d855497e 3671{
fd5a75fe 3672 switch (index) {
8079384e
MI		 3673 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3674 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3675 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3676 default: return -1;
3677 }
d855497e
MI		 3678}
3679
3680
2fdf3d9c 3681/* Store a v4l minor device number */
fd5a75fe 3682void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3683 enum pvr2_v4l_type index,int v)
d855497e 3684{
fd5a75fe 3685 switch (index) {
8079384e
MI		 3686 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3687 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3688 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3689 default: break;
3690 }
d855497e
MI		 3691}
3692
3693
7d12e780 3694static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3695{
3696 struct pvr2_hdw *hdw = urb->context;
3697 hdw->ctl_write_pend_flag = 0;
3698 if (hdw->ctl_read_pend_flag) return;
3699 complete(&hdw->ctl_done);
3700}
3701
3702
7d12e780 3703static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3704{
3705 struct pvr2_hdw *hdw = urb->context;
3706 hdw->ctl_read_pend_flag = 0;
3707 if (hdw->ctl_write_pend_flag) return;
3708 complete(&hdw->ctl_done);
3709}
3710
3711
3712static void pvr2_ctl_timeout(unsigned long data)
3713{
3714 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3715 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3716 hdw->ctl_timeout_flag = !0;
5e55d2ce 3717 if (hdw->ctl_write_pend_flag)
d855497e 3718 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3719 if (hdw->ctl_read_pend_flag)
d855497e 3720 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3721 }
3722}
3723
3724
e61b6fc5
MI		 3725/* Issue a command and get a response from the device. This extended
3726 version includes a probe flag (which if set means that device errors
3727 should not be logged or treated as fatal) and a timeout in jiffies.
3728 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3729static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3730 unsigned int timeout,int probe_fl,
3731 void *write_data,unsigned int write_len,
3732 void *read_data,unsigned int read_len)
d855497e
MI		 3733{
3734 unsigned int idx;
3735 int status = 0;
3736 struct timer_list timer;
3737 if (!hdw->ctl_lock_held) {
3738 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3739 "Attempted to execute control transfer"
3740 " without lock!!");
3741 return -EDEADLK;
3742 }
681c7399 3743 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3744 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3745 "Attempted to execute control transfer"
3746 " when device not ok");
3747 return -EIO;
3748 }
3749 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3750 if (!probe_fl) {
3751 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3752 "Attempted to execute control transfer"
3753 " when USB is disconnected");
3754 }
3755 return -ENOTTY;
3756 }
3757
3758 /* Ensure that we have sane parameters */
3759 if (!write_data) write_len = 0;
3760 if (!read_data) read_len = 0;
3761 if (write_len > PVR2_CTL_BUFFSIZE) {
3762 pvr2_trace(
3763 PVR2_TRACE_ERROR_LEGS,
3764 "Attempted to execute %d byte"
3765 " control-write transfer (limit=%d)",
3766 write_len,PVR2_CTL_BUFFSIZE);
3767 return -EINVAL;
3768 }
3769 if (read_len > PVR2_CTL_BUFFSIZE) {
3770 pvr2_trace(
3771 PVR2_TRACE_ERROR_LEGS,
3772 "Attempted to execute %d byte"
3773 " control-read transfer (limit=%d)",
3774 write_len,PVR2_CTL_BUFFSIZE);
3775 return -EINVAL;
3776 }
3777 if ((!write_len) && (!read_len)) {
3778 pvr2_trace(
3779 PVR2_TRACE_ERROR_LEGS,
3780 "Attempted to execute null control transfer?");
3781 return -EINVAL;
3782 }
3783
3784
3785 hdw->cmd_debug_state = 1;
3786 if (write_len) {
3787 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3788 } else {
3789 hdw->cmd_debug_code = 0;
3790 }
3791 hdw->cmd_debug_write_len = write_len;
3792 hdw->cmd_debug_read_len = read_len;
3793
3794 /* Initialize common stuff */
3795 init_completion(&hdw->ctl_done);
3796 hdw->ctl_timeout_flag = 0;
3797 hdw->ctl_write_pend_flag = 0;
3798 hdw->ctl_read_pend_flag = 0;
3799 init_timer(&timer);
3800 timer.expires = jiffies + timeout;
3801 timer.data = (unsigned long)hdw;
3802 timer.function = pvr2_ctl_timeout;
3803
3804 if (write_len) {
3805 hdw->cmd_debug_state = 2;
3806 /* Transfer write data to internal buffer */
3807 for (idx = 0; idx < write_len; idx++) {
3808 hdw->ctl_write_buffer[idx] =
3809 ((unsigned char *)write_data)[idx];
3810 }
3811 /* Initiate a write request */
3812 usb_fill_bulk_urb(hdw->ctl_write_urb,
3813 hdw->usb_dev,
3814 usb_sndbulkpipe(hdw->usb_dev,
3815 PVR2_CTL_WRITE_ENDPOINT),
3816 hdw->ctl_write_buffer,
3817 write_len,
3818 pvr2_ctl_write_complete,
3819 hdw);
3820 hdw->ctl_write_urb->actual_length = 0;
3821 hdw->ctl_write_pend_flag = !0;
3822 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3823 if (status < 0) {
3824 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3825 "Failed to submit write-control"
3826 " URB status=%d",status);
3827 hdw->ctl_write_pend_flag = 0;
3828 goto done;
3829 }
3830 }
3831
3832 if (read_len) {
3833 hdw->cmd_debug_state = 3;
3834 memset(hdw->ctl_read_buffer,0x43,read_len);
3835 /* Initiate a read request */
3836 usb_fill_bulk_urb(hdw->ctl_read_urb,
3837 hdw->usb_dev,
3838 usb_rcvbulkpipe(hdw->usb_dev,
3839 PVR2_CTL_READ_ENDPOINT),
3840 hdw->ctl_read_buffer,
3841 read_len,
3842 pvr2_ctl_read_complete,
3843 hdw);
3844 hdw->ctl_read_urb->actual_length = 0;
3845 hdw->ctl_read_pend_flag = !0;
3846 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3847 if (status < 0) {
3848 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3849 "Failed to submit read-control"
3850 " URB status=%d",status);
3851 hdw->ctl_read_pend_flag = 0;
3852 goto done;
3853 }
3854 }
3855
3856 /* Start timer */
3857 add_timer(&timer);
3858
3859 /* Now wait for all I/O to complete */
3860 hdw->cmd_debug_state = 4;
3861 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3862 wait_for_completion(&hdw->ctl_done);
3863 }
3864 hdw->cmd_debug_state = 5;
3865
3866 /* Stop timer */
3867 del_timer_sync(&timer);
3868
3869 hdw->cmd_debug_state = 6;
3870 status = 0;
3871
3872 if (hdw->ctl_timeout_flag) {
3873 status = -ETIMEDOUT;
3874 if (!probe_fl) {
3875 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3876 "Timed out control-write");
3877 }
3878 goto done;
3879 }
3880
3881 if (write_len) {
3882 /* Validate results of write request */
3883 if ((hdw->ctl_write_urb->status != 0) &&
3884 (hdw->ctl_write_urb->status != -ENOENT) &&
3885 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3886 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3887 /* USB subsystem is reporting some kind of failure
3888 on the write */
3889 status = hdw->ctl_write_urb->status;
3890 if (!probe_fl) {
3891 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3892 "control-write URB failure,"
3893 " status=%d",
3894 status);
3895 }
3896 goto done;
3897 }
3898 if (hdw->ctl_write_urb->actual_length < write_len) {
3899 /* Failed to write enough data */
3900 status = -EIO;
3901 if (!probe_fl) {
3902 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3903 "control-write URB short,"
3904 " expected=%d got=%d",
3905 write_len,
3906 hdw->ctl_write_urb->actual_length);
3907 }
3908 goto done;
3909 }
3910 }
3911 if (read_len) {
3912 /* Validate results of read request */
3913 if ((hdw->ctl_read_urb->status != 0) &&
3914 (hdw->ctl_read_urb->status != -ENOENT) &&
3915 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3916 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3917 /* USB subsystem is reporting some kind of failure
3918 on the read */
3919 status = hdw->ctl_read_urb->status;
3920 if (!probe_fl) {
3921 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3922 "control-read URB failure,"
3923 " status=%d",
3924 status);
3925 }
3926 goto done;
3927 }
3928 if (hdw->ctl_read_urb->actual_length < read_len) {
3929 /* Failed to read enough data */
3930 status = -EIO;
3931 if (!probe_fl) {
3932 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3933 "control-read URB short,"
3934 " expected=%d got=%d",
3935 read_len,
3936 hdw->ctl_read_urb->actual_length);
3937 }
3938 goto done;
3939 }
3940 /* Transfer retrieved data out from internal buffer */
3941 for (idx = 0; idx < read_len; idx++) {
3942 ((unsigned char *)read_data)[idx] =
3943 hdw->ctl_read_buffer[idx];
3944 }
3945 }
3946
3947 done:
3948
3949 hdw->cmd_debug_state = 0;
3950 if ((status < 0) && (!probe_fl)) {
681c7399 3951 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3952 }
3953 return status;
3954}
3955
3956
3957int pvr2_send_request(struct pvr2_hdw *hdw,
3958 void *write_data,unsigned int write_len,
3959 void *read_data,unsigned int read_len)
3960{
3961 return pvr2_send_request_ex(hdw,HZ*4,0,
3962 write_data,write_len,
3963 read_data,read_len);
3964}
3965
1c9d10d4
MI		 3966
3967static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3968{
3969 int ret;
3970 unsigned int cnt = 1;
3971 unsigned int args = 0;
3972 LOCK_TAKE(hdw->ctl_lock);
3973 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3974 args = (cmdcode >> 8) & 0xffu;
3975 args = (args > 2) ? 2 : args;
3976 if (args) {
3977 cnt += args;
3978 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3979 if (args > 1) {
3980 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3981 }
3982 }
3983 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3984 unsigned int idx;
3985 unsigned int ccnt,bcnt;
3986 char tbuf[50];
3987 cmdcode &= 0xffu;
3988 bcnt = 0;
3989 ccnt = scnprintf(tbuf+bcnt,
3990 sizeof(tbuf)-bcnt,
3991 "Sending FX2 command 0x%x",cmdcode);
3992 bcnt += ccnt;
3993 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3994 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3995 ccnt = scnprintf(tbuf+bcnt,
3996 sizeof(tbuf)-bcnt,
3997 " \"%s\"",
3998 pvr2_fx2cmd_desc[idx].desc);
3999 bcnt += ccnt;
4000 break;
4001 }
4002 }
4003 if (args) {
4004 ccnt = scnprintf(tbuf+bcnt,
4005 sizeof(tbuf)-bcnt,
4006 " (%u",hdw->cmd_buffer[1]);
4007 bcnt += ccnt;
4008 if (args > 1) {
4009 ccnt = scnprintf(tbuf+bcnt,
4010 sizeof(tbuf)-bcnt,
4011 ",%u",hdw->cmd_buffer[2]);
4012 bcnt += ccnt;
4013 }
4014 ccnt = scnprintf(tbuf+bcnt,
4015 sizeof(tbuf)-bcnt,
4016 ")");
4017 bcnt += ccnt;
4018 }
4019 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
4020 }
4021 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
4022 LOCK_GIVE(hdw->ctl_lock);
4023 return ret;
4024}
4025
4026
d855497e
MI		 4027int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
4028{
4029 int ret;
4030
4031 LOCK_TAKE(hdw->ctl_lock);
4032
8d364363 4033 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 4034 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
4035 hdw->cmd_buffer[5] = 0;
4036 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4037 hdw->cmd_buffer[7] = reg & 0xff;
4038
4039
4040 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4041
4042 LOCK_GIVE(hdw->ctl_lock);
4043
4044 return ret;
4045}
4046
4047
07e337ee 4048static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 4049{
4050 int ret = 0;
4051
4052 LOCK_TAKE(hdw->ctl_lock);
4053
8d364363 4054 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 4055 hdw->cmd_buffer[1] = 0;
4056 hdw->cmd_buffer[2] = 0;
4057 hdw->cmd_buffer[3] = 0;
4058 hdw->cmd_buffer[4] = 0;
4059 hdw->cmd_buffer[5] = 0;
4060 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4061 hdw->cmd_buffer[7] = reg & 0xff;
4062
4063 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4064 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4065
4066 LOCK_GIVE(hdw->ctl_lock);
4067
4068 return ret;
4069}
4070
4071
681c7399 4072void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 4073{
4074 if (!hdw->flag_ok) return;
681c7399
MI		 4075 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4076 "Device being rendered inoperable");
d855497e 4077 if (hdw->vid_stream) {
a0fd1cb1 4078 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 4079 }
681c7399
MI		 4080 hdw->flag_ok = 0;
4081 trace_stbit("flag_ok",hdw->flag_ok);
4082 pvr2_hdw_state_sched(hdw);
d855497e
MI		 4083}
4084
4085
4086void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4087{
4088 int ret;
4089 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4090 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4091 if (ret == 0) {
d855497e
MI		 4092 ret = usb_reset_device(hdw->usb_dev);
4093 usb_unlock_device(hdw->usb_dev);
4094 } else {
4095 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4096 "Failed to lock USB device ret=%d",ret);
4097 }
4098 if (init_pause_msec) {
4099 pvr2_trace(PVR2_TRACE_INFO,
4100 "Waiting %u msec for hardware to settle",
4101 init_pause_msec);
4102 msleep(init_pause_msec);
4103 }
4104
4105}
4106
4107
4108void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4109{
6861800c 4110 char *da;
d855497e
MI		 4111 unsigned int pipe;
4112 int ret;
4113
4114 if (!hdw->usb_dev) return;
4115
6861800c
MI		 4116 da = kmalloc(16, GFP_KERNEL);
4117
4118 if (da == NULL) {
4119 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4120 "Unable to allocate memory to control CPU reset");
4121 return;
4122 }
4123
d855497e
MI		 4124 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4125
4126 da[0] = val ? 0x01 : 0x00;
4127
4128 /* Write the CPUCS register on the 8051. The lsb of the register
4129 is the reset bit; a 1 asserts reset while a 0 clears it. */
4130 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4131 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4132 if (ret < 0) {
4133 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4134 "cpureset_assert(%d) error=%d",val,ret);
4135 pvr2_hdw_render_useless(hdw);
4136 }
6861800c
MI		 4137
4138 kfree(da);
d855497e
MI		 4139}
4140
4141
4142int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4143{
1c9d10d4 4144 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4145}
4146
4147
e1edb19a
MK		 4148int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4149{
1c9d10d4 4150 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4151}
4152
1c9d10d4 4153
e1edb19a
MK		 4154int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4155{
1c9d10d4 4156 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4157}
4158
d855497e
MI		 4159
4160int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4161{
af78e16b
MI		 4162 pvr2_trace(PVR2_TRACE_INIT,
4163 "Requesting decoder reset");
af78e16b
MI		 4164 if (hdw->decoder_client_id) {
4165 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4166 core, reset, 0);
e17d787c 4167 pvr2_hdw_cx25840_vbi_hack(hdw);
af78e16b 4168 return 0;
d855497e 4169 }
d855497e 4170 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4171 "Unable to reset decoder: nothing attached");
4172 return -ENOTTY;
d855497e
MI		 4173}
4174
4175
62433e31 4176static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4177{
1c9d10d4
MI		 4178 hdw->flag_ok = !0;
4179 return pvr2_issue_simple_cmd(hdw,
4180 FX2CMD_HCW_DEMOD_RESETIN |
4181 (1 << 8) |
4182 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4183}
4184
84147f3d 4185
62433e31 4186static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4187{
1c9d10d4
MI		 4188 hdw->flag_ok = !0;
4189 return pvr2_issue_simple_cmd(hdw,(onoff ?
4190 FX2CMD_ONAIR_DTV_POWER_ON :
4191 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4192}
4193
62433e31
MI		 4194
4195static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4196 int onoff)
84147f3d 4197{
1c9d10d4
MI		 4198 return pvr2_issue_simple_cmd(hdw,(onoff ?
4199 FX2CMD_ONAIR_DTV_STREAMING_ON :
4200 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4201}
4202
62433e31
MI		 4203
4204static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4205{
4206 int cmode;
4207 /* Compare digital/analog desired setting with current setting. If
4208 they don't match, fix it... */
4209 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4210 if (cmode == hdw->pathway_state) {
4211 /* They match; nothing to do */
4212 return;
4213 }
4214
4215 switch (hdw->hdw_desc->digital_control_scheme) {
4216 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4217 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4218 if (cmode == PVR2_PATHWAY_ANALOG) {
4219 /* If moving to analog mode, also force the decoder
4220 to reset. If no decoder is attached, then it's
4221 ok to ignore this because if/when the decoder
4222 attaches, it will reset itself at that time. */
4223 pvr2_hdw_cmd_decoder_reset(hdw);
4224 }
4225 break;
4226 case PVR2_DIGITAL_SCHEME_ONAIR:
4227 /* Supposedly we should always have the power on whether in
4228 digital or analog mode. But for now do what appears to
4229 work... */
bb0c2fe0 4230 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4231 break;
4232 default: break;
4233 }
4234
1b9c18c5 4235 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4236 hdw->pathway_state = cmode;
4237}
4238
4239
e9b59f6e 4240static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4241{
4242 /* change some GPIO data
4243 *
4244 * note: bit d7 of dir appears to control the LED,
4245 * so we shut it off here.
4246 *
c55a97d7 4247 */
40381cb0 4248 if (onoff) {
c55a97d7 4249 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4250 } else {
c55a97d7 4251 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4252 }
c55a97d7 4253 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4254}
c55a97d7 4255
40381cb0
MI		 4256
4257typedef void (*led_method_func)(struct pvr2_hdw *,int);
4258
4259static led_method_func led_methods[] = {
4260 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4261};
4262
4263
4264/* Toggle LED */
4265static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4266{
4267 unsigned int scheme_id;
4268 led_method_func fp;
4269
4270 if ((!onoff) == (!hdw->led_on)) return;
4271
4272 hdw->led_on = onoff != 0;
4273
4274 scheme_id = hdw->hdw_desc->led_scheme;
4275 if (scheme_id < ARRAY_SIZE(led_methods)) {
4276 fp = led_methods[scheme_id];
4277 } else {
4278 fp = NULL;
4279 }
4280
4281 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4282}
4283
4284
e61b6fc5 4285/* Stop / start video stream transport */
07e337ee 4286static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4287{
bb0c2fe0
MI		 4288 int ret;
4289
4290 /* If we're in analog mode, then just issue the usual analog
4291 command. */
4292 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4293 return pvr2_issue_simple_cmd(hdw,
4294 (runFl ?
4295 FX2CMD_STREAMING_ON :
4296 FX2CMD_STREAMING_OFF));
4297 /*Note: Not reached */
4298 }
4299
4300 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4301 /* Whoops, we don't know what mode we're in... */
4302 return -EINVAL;
4303 }
4304
4305 /* To get here we have to be in digital mode. The mechanism here
4306 is unfortunately different for different vendors. So we switch
4307 on the device's digital scheme attribute in order to figure out
4308 what to do. */
4309 switch (hdw->hdw_desc->digital_control_scheme) {
4310 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4311 return pvr2_issue_simple_cmd(hdw,
4312 (runFl ?
4313 FX2CMD_HCW_DTV_STREAMING_ON :
4314 FX2CMD_HCW_DTV_STREAMING_OFF));
4315 case PVR2_DIGITAL_SCHEME_ONAIR:
4316 ret = pvr2_issue_simple_cmd(hdw,
4317 (runFl ?
4318 FX2CMD_STREAMING_ON :
4319 FX2CMD_STREAMING_OFF));
4320 if (ret) return ret;
4321 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4322 default:
4323 return -EINVAL;
62433e31 4324 }
d855497e
MI		 4325}
4326
4327
62433e31
MI		 4328/* Evaluate whether or not state_pathway_ok can change */
4329static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4330{
4331 if (hdw->state_pathway_ok) {
4332 /* Nothing to do if pathway is already ok */
4333 return 0;
4334 }
4335 if (!hdw->state_pipeline_idle) {
4336 /* Not allowed to change anything if pipeline is not idle */
4337 return 0;
4338 }
4339 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4340 hdw->state_pathway_ok = !0;
e9db1ff2 4341 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4342 return !0;
4343}
4344
4345
681c7399
MI		 4346/* Evaluate whether or not state_encoder_ok can change */
4347static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4348{
4349 if (hdw->state_encoder_ok) return 0;
4350 if (hdw->flag_tripped) return 0;
4351 if (hdw->state_encoder_run) return 0;
4352 if (hdw->state_encoder_config) return 0;
4353 if (hdw->state_decoder_run) return 0;
4354 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4355 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4356 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4357 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4358 return 0;
4359 }
4360
681c7399
MI		 4361 if (pvr2_upload_firmware2(hdw) < 0) {
4362 hdw->flag_tripped = !0;
4363 trace_stbit("flag_tripped",hdw->flag_tripped);
4364 return !0;
4365 }
4366 hdw->state_encoder_ok = !0;
4367 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4368 return !0;
4369}
4370
4371
4372/* Evaluate whether or not state_encoder_config can change */
4373static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4374{
4375 if (hdw->state_encoder_config) {
4376 if (hdw->state_encoder_ok) {
4377 if (hdw->state_pipeline_req &&
4378 !hdw->state_pipeline_pause) return 0;
4379 }
4380 hdw->state_encoder_config = 0;
4381 hdw->state_encoder_waitok = 0;
4382 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4383 /* paranoia - solve race if timer just completed */
4384 del_timer_sync(&hdw->encoder_wait_timer);
4385 } else {
62433e31
MI		 4386 if (!hdw->state_pathway_ok ||
4387 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4388 !hdw->state_encoder_ok ||
681c7399
MI		 4389 !hdw->state_pipeline_idle ||
4390 hdw->state_pipeline_pause ||
4391 !hdw->state_pipeline_req ||
4392 !hdw->state_pipeline_config) {
4393 /* We must reset the enforced wait interval if
4394 anything has happened that might have disturbed
4395 the encoder. This should be a rare case. */
4396 if (timer_pending(&hdw->encoder_wait_timer)) {
4397 del_timer_sync(&hdw->encoder_wait_timer);
4398 }
4399 if (hdw->state_encoder_waitok) {
4400 /* Must clear the state - therefore we did
4401 something to a state bit and must also
4402 return true. */
4403 hdw->state_encoder_waitok = 0;
4404 trace_stbit("state_encoder_waitok",
4405 hdw->state_encoder_waitok);
4406 return !0;
4407 }
4408 return 0;
4409 }
4410 if (!hdw->state_encoder_waitok) {
4411 if (!timer_pending(&hdw->encoder_wait_timer)) {
4412 /* waitok flag wasn't set and timer isn't
4413 running. Check flag once more to avoid
4414 a race then start the timer. This is
4415 the point when we measure out a minimal
4416 quiet interval before doing something to
4417 the encoder. */
4418 if (!hdw->state_encoder_waitok) {
4419 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4420 jiffies +
4421 (HZ * TIME_MSEC_ENCODER_WAIT
4422 / 1000);
681c7399
MI		 4423 add_timer(&hdw->encoder_wait_timer);
4424 }
4425 }
4426 /* We can't continue until we know we have been
4427 quiet for the interval measured by this
4428 timer. */
4429 return 0;
4430 }
4431 pvr2_encoder_configure(hdw);
4432 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4433 }
4434 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4435 return !0;
4436}
4437
4438
d913d630
MI		 4439/* Return true if the encoder should not be running. */
4440static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4441{
4442 if (!hdw->state_encoder_ok) {
4443 /* Encoder isn't healthy at the moment, so stop it. */
4444 return !0;
4445 }
4446 if (!hdw->state_pathway_ok) {
4447 /* Mode is not understood at the moment (i.e. it wants to
4448 change), so encoder must be stopped. */
4449 return !0;
4450 }
4451
4452 switch (hdw->pathway_state) {
4453 case PVR2_PATHWAY_ANALOG:
4454 if (!hdw->state_decoder_run) {
4455 /* We're in analog mode and the decoder is not
4456 running; thus the encoder should be stopped as
4457 well. */
4458 return !0;
4459 }
4460 break;
4461 case PVR2_PATHWAY_DIGITAL:
4462 if (hdw->state_encoder_runok) {
4463 /* This is a funny case. We're in digital mode so
4464 really the encoder should be stopped. However
4465 if it really is running, only kill it after
4466 runok has been set. This gives a chance for the
4467 onair quirk to function (encoder must run
4468 briefly first, at least once, before onair
4469 digital streaming can work). */
4470 return !0;
4471 }
4472 break;
4473 default:
4474 /* Unknown mode; so encoder should be stopped. */
4475 return !0;
4476 }
4477
4478 /* If we get here, we haven't found a reason to stop the
4479 encoder. */
4480 return 0;
4481}
4482
4483
4484/* Return true if the encoder should be running. */
4485static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4486{
4487 if (!hdw->state_encoder_ok) {
4488 /* Don't run the encoder if it isn't healthy... */
4489 return 0;
4490 }
4491 if (!hdw->state_pathway_ok) {
4492 /* Don't run the encoder if we don't (yet) know what mode
4493 we need to be in... */
4494 return 0;
4495 }
4496
4497 switch (hdw->pathway_state) {
4498 case PVR2_PATHWAY_ANALOG:
6e931375 4499 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
d913d630
MI		 4500 /* In analog mode, if the decoder is running, then
4501 run the encoder. */
4502 return !0;
4503 }
4504 break;
4505 case PVR2_PATHWAY_DIGITAL:
4506 if ((hdw->hdw_desc->digital_control_scheme ==
4507 PVR2_DIGITAL_SCHEME_ONAIR) &&
4508 !hdw->state_encoder_runok) {
4509 /* This is a quirk. OnAir hardware won't stream
4510 digital until the encoder has been run at least
4511 once, for a minimal period of time (empiricially
4512 measured to be 1/4 second). So if we're on
4513 OnAir hardware and the encoder has never been
4514 run at all, then start the encoder. Normal
4515 state machine logic in the driver will
4516 automatically handle the remaining bits. */
4517 return !0;
4518 }
4519 break;
4520 default:
4521 /* For completeness (unknown mode; encoder won't run ever) */
4522 break;
4523 }
4524 /* If we get here, then we haven't found any reason to run the
4525 encoder, so don't run it. */
4526 return 0;
4527}
4528
4529
681c7399
MI		 4530/* Evaluate whether or not state_encoder_run can change */
4531static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4532{
4533 if (hdw->state_encoder_run) {
d913d630 4534 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4535 if (hdw->state_encoder_ok) {
d913d630 4536 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4537 if (pvr2_encoder_stop(hdw) < 0) return !0;
4538 }
4539 hdw->state_encoder_run = 0;
4540 } else {
d913d630 4541 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4542 if (pvr2_encoder_start(hdw) < 0) return !0;
4543 hdw->state_encoder_run = !0;
d913d630
MI		 4544 if (!hdw->state_encoder_runok) {
4545 hdw->encoder_run_timer.expires =
83ce57aa 4546 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4547 add_timer(&hdw->encoder_run_timer);
4548 }
681c7399
MI		 4549 }
4550 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4551 return !0;
4552}
4553
4554
4555/* Timeout function for quiescent timer. */
4556static void pvr2_hdw_quiescent_timeout(unsigned long data)
4557{
4558 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4559 hdw->state_decoder_quiescent = !0;
4560 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4561 hdw->state_stale = !0;
4562 queue_work(hdw->workqueue,&hdw->workpoll);
4563}
4564
4565
6e931375
MI		 4566/* Timeout function for decoder stabilization timer. */
4567static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4568{
4569 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4570 hdw->state_decoder_ready = !0;
4571 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4572 hdw->state_stale = !0;
4573 queue_work(hdw->workqueue, &hdw->workpoll);
4574}
4575
4576
681c7399
MI		 4577/* Timeout function for encoder wait timer. */
4578static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4579{
4580 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4581 hdw->state_encoder_waitok = !0;
4582 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4583 hdw->state_stale = !0;
4584 queue_work(hdw->workqueue,&hdw->workpoll);
4585}
4586
4587
d913d630
MI		 4588/* Timeout function for encoder run timer. */
4589static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4590{
4591 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4592 if (!hdw->state_encoder_runok) {
4593 hdw->state_encoder_runok = !0;
4594 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4595 hdw->state_stale = !0;
4596 queue_work(hdw->workqueue,&hdw->workpoll);
4597 }
4598}
4599
4600
681c7399
MI		 4601/* Evaluate whether or not state_decoder_run can change */
4602static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4603{
4604 if (hdw->state_decoder_run) {
4605 if (hdw->state_encoder_ok) {
4606 if (hdw->state_pipeline_req &&
62433e31
MI		 4607 !hdw->state_pipeline_pause &&
4608 hdw->state_pathway_ok) return 0;
681c7399
MI		 4609 }
4610 if (!hdw->flag_decoder_missed) {
4611 pvr2_decoder_enable(hdw,0);
4612 }
4613 hdw->state_decoder_quiescent = 0;
4614 hdw->state_decoder_run = 0;
6e931375 4615 /* paranoia - solve race if timer(s) just completed */
681c7399 4616 del_timer_sync(&hdw->quiescent_timer);
6e931375
MI		 4617 /* Kill the stabilization timer, in case we're killing the
4618 encoder before the previous stabilization interval has
4619 been properly timed. */
4620 del_timer_sync(&hdw->decoder_stabilization_timer);
4621 hdw->state_decoder_ready = 0;
681c7399
MI		 4622 } else {
4623 if (!hdw->state_decoder_quiescent) {
4624 if (!timer_pending(&hdw->quiescent_timer)) {
4625 /* We don't do something about the
4626 quiescent timer until right here because
4627 we also want to catch cases where the
4628 decoder was already not running (like
4629 after initialization) as opposed to
4630 knowing that we had just stopped it.
4631 The second flag check is here to cover a
4632 race - the timer could have run and set
4633 this flag just after the previous check
4634 but before we did the pending check. */
4635 if (!hdw->state_decoder_quiescent) {
4636 hdw->quiescent_timer.expires =
83ce57aa
MI		 4637 jiffies +
4638 (HZ * TIME_MSEC_DECODER_WAIT
4639 / 1000);
681c7399
MI		 4640 add_timer(&hdw->quiescent_timer);
4641 }
4642 }
4643 /* Don't allow decoder to start again until it has
4644 been quiesced first. This little detail should
4645 hopefully further stabilize the encoder. */
4646 return 0;
4647 }
62433e31
MI		 4648 if (!hdw->state_pathway_ok ||
4649 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4650 !hdw->state_pipeline_req ||
681c7399
MI		 4651 hdw->state_pipeline_pause ||
4652 !hdw->state_pipeline_config ||
4653 !hdw->state_encoder_config ||
4654 !hdw->state_encoder_ok) return 0;
4655 del_timer_sync(&hdw->quiescent_timer);
4656 if (hdw->flag_decoder_missed) return 0;
4657 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4658 hdw->state_decoder_quiescent = 0;
6e931375 4659 hdw->state_decoder_ready = 0;
681c7399 4660 hdw->state_decoder_run = !0;
fb640224
MI		 4661 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4662 hdw->decoder_stabilization_timer.expires =
4663 jiffies +
4664 (HZ * TIME_MSEC_DECODER_STABILIZATION_WAIT /
4665 1000);
4666 add_timer(&hdw->decoder_stabilization_timer);
4667 } else {
4668 hdw->state_decoder_ready = !0;
4669 }
681c7399
MI		 4670 }
4671 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4672 trace_stbit("state_decoder_run",hdw->state_decoder_run);
6e931375 4673 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
681c7399
MI		 4674 return !0;
4675}
4676
4677
4678/* Evaluate whether or not state_usbstream_run can change */
4679static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4680{
4681 if (hdw->state_usbstream_run) {
72998b71 4682 int fl = !0;
62433e31 4683 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4684 fl = (hdw->state_encoder_ok &&
4685 hdw->state_encoder_run);
4686 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4687 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4688 fl = hdw->state_encoder_ok;
4689 }
4690 if (fl &&
4691 hdw->state_pipeline_req &&
4692 !hdw->state_pipeline_pause &&
4693 hdw->state_pathway_ok) {
4694 return 0;
681c7399
MI		 4695 }
4696 pvr2_hdw_cmd_usbstream(hdw,0);
4697 hdw->state_usbstream_run = 0;
4698 } else {
62433e31
MI		 4699 if (!hdw->state_pipeline_req ||
4700 hdw->state_pipeline_pause ||
4701 !hdw->state_pathway_ok) return 0;
4702 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4703 if (!hdw->state_encoder_ok ||
4704 !hdw->state_encoder_run) return 0;
72998b71
MI		 4705 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4706 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4707 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4708 if (hdw->state_encoder_run) return 0;
4709 if (hdw->hdw_desc->digital_control_scheme ==
4710 PVR2_DIGITAL_SCHEME_ONAIR) {
4711 /* OnAir digital receivers won't stream
4712 unless the analog encoder has run first.
4713 Why? I have no idea. But don't even
4714 try until we know the analog side is
4715 known to have run. */
4716 if (!hdw->state_encoder_runok) return 0;
4717 }
62433e31 4718 }
681c7399
MI		 4719 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4720 hdw->state_usbstream_run = !0;
4721 }
4722 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4723 return !0;
4724}
4725
4726
4727/* Attempt to configure pipeline, if needed */
4728static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4729{
4730 if (hdw->state_pipeline_config ||
4731 hdw->state_pipeline_pause) return 0;
4732 pvr2_hdw_commit_execute(hdw);
4733 return !0;
4734}
4735
4736
4737/* Update pipeline idle and pipeline pause tracking states based on other
4738 inputs. This must be called whenever the other relevant inputs have
4739 changed. */
4740static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4741{
4742 unsigned int st;
4743 int updatedFl = 0;
4744 /* Update pipeline state */
4745 st = !(hdw->state_encoder_run ||
4746 hdw->state_decoder_run ||
4747 hdw->state_usbstream_run ||
4748 (!hdw->state_decoder_quiescent));
4749 if (!st != !hdw->state_pipeline_idle) {
4750 hdw->state_pipeline_idle = st;
4751 updatedFl = !0;
4752 }
4753 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4754 hdw->state_pipeline_pause = 0;
4755 updatedFl = !0;
4756 }
4757 return updatedFl;
4758}
4759
4760
4761typedef int (*state_eval_func)(struct pvr2_hdw *);
4762
4763/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4764static const state_eval_func eval_funcs[] = {
62433e31 4765 state_eval_pathway_ok,
681c7399
MI		 4766 state_eval_pipeline_config,
4767 state_eval_encoder_ok,
4768 state_eval_encoder_config,
4769 state_eval_decoder_run,
4770 state_eval_encoder_run,
4771 state_eval_usbstream_run,
4772};
4773
4774
4775/* Process various states and return true if we did anything interesting. */
4776static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4777{
4778 unsigned int i;
4779 int state_updated = 0;
4780 int check_flag;
4781
4782 if (!hdw->state_stale) return 0;
4783 if ((hdw->fw1_state != FW1_STATE_OK) ||
4784 !hdw->flag_ok) {
4785 hdw->state_stale = 0;
4786 return !0;
4787 }
4788 /* This loop is the heart of the entire driver. It keeps trying to
4789 evaluate various bits of driver state until nothing changes for
4790 one full iteration. Each "bit of state" tracks some global
4791 aspect of the driver, e.g. whether decoder should run, if
4792 pipeline is configured, usb streaming is on, etc. We separately
4793 evaluate each of those questions based on other driver state to
4794 arrive at the correct running configuration. */
4795 do {
4796 check_flag = 0;
4797 state_update_pipeline_state(hdw);
4798 /* Iterate over each bit of state */
4799 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4800 if ((*eval_funcs[i])(hdw)) {
4801 check_flag = !0;
4802 state_updated = !0;
4803 state_update_pipeline_state(hdw);
4804 }
4805 }
4806 } while (check_flag && hdw->flag_ok);
4807 hdw->state_stale = 0;
4808 trace_stbit("state_stale",hdw->state_stale);
4809 return state_updated;
4810}
4811
4812
1cb03b76
MI		 4813static unsigned int print_input_mask(unsigned int msk,
4814 char *buf,unsigned int acnt)
4815{
4816 unsigned int idx,ccnt;
4817 unsigned int tcnt = 0;
4818 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4819 if (!((1 << idx) & msk)) continue;
4820 ccnt = scnprintf(buf+tcnt,
4821 acnt-tcnt,
4822 "%s%s",
4823 (tcnt ? ", " : ""),
4824 control_values_input[idx]);
4825 tcnt += ccnt;
4826 }
4827 return tcnt;
4828}
4829
4830
62433e31
MI		 4831static const char *pvr2_pathway_state_name(int id)
4832{
4833 switch (id) {
4834 case PVR2_PATHWAY_ANALOG: return "analog";
4835 case PVR2_PATHWAY_DIGITAL: return "digital";
4836 default: return "unknown";
4837 }
4838}
4839
4840
681c7399
MI		 4841static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4842 char *buf,unsigned int acnt)
4843{
4844 switch (which) {
4845 case 0:
4846 return scnprintf(
4847 buf,acnt,
e9db1ff2 4848 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4849 (hdw->flag_ok ? " <ok>" : " <fail>"),
4850 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4851 (hdw->flag_disconnected ? " <disconnected>" :
4852 " <connected>"),
4853 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4854 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4855 pvr2_pathway_state_name(hdw->pathway_state));
4856
681c7399
MI		 4857 case 1:
4858 return scnprintf(
4859 buf,acnt,
4860 "pipeline:%s%s%s%s",
4861 (hdw->state_pipeline_idle ? " <idle>" : ""),
4862 (hdw->state_pipeline_config ?
4863 " <configok>" : " <stale>"),
4864 (hdw->state_pipeline_req ? " <req>" : ""),
4865 (hdw->state_pipeline_pause ? " <pause>" : ""));
4866 case 2:
4867 return scnprintf(
4868 buf,acnt,
62433e31 4869 "worker:%s%s%s%s%s%s%s",
681c7399 4870 (hdw->state_decoder_run ?
6e931375
MI		 4871 (hdw->state_decoder_ready ?
4872 "<decode:run>" : " <decode:start>") :
681c7399
MI		 4873 (hdw->state_decoder_quiescent ?
4874 "" : " <decode:stop>")),
4875 (hdw->state_decoder_quiescent ?
4876 " <decode:quiescent>" : ""),
4877 (hdw->state_encoder_ok ?
4878 "" : " <encode:init>"),
4879 (hdw->state_encoder_run ?
d913d630
MI		 4880 (hdw->state_encoder_runok ?
4881 " <encode:run>" :
4882 " <encode:firstrun>") :
4883 (hdw->state_encoder_runok ?
4884 " <encode:stop>" :
4885 " <encode:virgin>")),
681c7399
MI		 4886 (hdw->state_encoder_config ?
4887 " <encode:configok>" :
4888 (hdw->state_encoder_waitok ?
b9a37d91 4889 "" : " <encode:waitok>")),
681c7399 4890 (hdw->state_usbstream_run ?
62433e31
MI		 4891 " <usb:run>" : " <usb:stop>"),
4892 (hdw->state_pathway_ok ?
e9db1ff2 4893 " <pathway:ok>" : ""));
681c7399
MI		 4894 case 3:
4895 return scnprintf(
4896 buf,acnt,
4897 "state: %s",
4898 pvr2_get_state_name(hdw->master_state));
ad0992e9 4899 case 4: {
1cb03b76
MI		 4900 unsigned int tcnt = 0;
4901 unsigned int ccnt;
4902
4903 ccnt = scnprintf(buf,
4904 acnt,
4905 "Hardware supported inputs: ");
4906 tcnt += ccnt;
4907 tcnt += print_input_mask(hdw->input_avail_mask,
4908 buf+tcnt,
4909 acnt-tcnt);
4910 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4911 ccnt = scnprintf(buf+tcnt,
4912 acnt-tcnt,
4913 "; allowed inputs: ");
4914 tcnt += ccnt;
4915 tcnt += print_input_mask(hdw->input_allowed_mask,
4916 buf+tcnt,
4917 acnt-tcnt);
4918 }
4919 return tcnt;
4920 }
4921 case 5: {
ad0992e9
MI		 4922 struct pvr2_stream_stats stats;
4923 if (!hdw->vid_stream) break;
4924 pvr2_stream_get_stats(hdw->vid_stream,
4925 &stats,
4926 0);
4927 return scnprintf(
4928 buf,acnt,
4929 "Bytes streamed=%u"
4930 " URBs: queued=%u idle=%u ready=%u"
4931 " processed=%u failed=%u",
4932 stats.bytes_processed,
4933 stats.buffers_in_queue,
4934 stats.buffers_in_idle,
4935 stats.buffers_in_ready,
4936 stats.buffers_processed,
4937 stats.buffers_failed);
4938 }
27eab384
MI		 4939 case 6: {
4940 unsigned int id = hdw->ir_scheme_active;
4941 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4942 (id >= ARRAY_SIZE(ir_scheme_names) ?
4943 "?" : ir_scheme_names[id]));
4944 }
2eb563b7
MI		 4945 default: break;
4946 }
4947 return 0;
4948}
4949
4950
4951/* Generate report containing info about attached sub-devices and attached
4952 i2c clients, including an indication of which attached i2c clients are
4953 actually sub-devices. */
4954static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4955 char *buf, unsigned int acnt)
4956{
4957 struct v4l2_subdev *sd;
4958 unsigned int tcnt = 0;
4959 unsigned int ccnt;
4960 struct i2c_client *client;
2eb563b7
MI		 4961 const char *p;
4962 unsigned int id;
4963
fa7ce764 4964 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
2eb563b7
MI		 4965 tcnt += ccnt;
4966 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4967 id = sd->grp_id;
4968 p = NULL;
4969 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4970 if (p) {
fa7ce764 4971 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
2eb563b7
MI		 4972 tcnt += ccnt;
4973 } else {
4974 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
fa7ce764 4975 " (unknown id=%u):", id);
2eb563b7
MI		 4976 tcnt += ccnt;
4977 }
fa7ce764
JD		 4978 client = v4l2_get_subdevdata(sd);
4979 if (client) {
4980 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4981 " %s @ %02x\n", client->name,
4982 client->addr);
4983 tcnt += ccnt;
4984 } else {
4985 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4986 " no i2c client\n");
4987 tcnt += ccnt;
858f910e 4988 }
681c7399 4989 }
2eb563b7 4990 return tcnt;
681c7399
MI		 4991}
4992
4993
4994unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4995 char *buf,unsigned int acnt)
4996{
4997 unsigned int bcnt,ccnt,idx;
4998 bcnt = 0;
4999 LOCK_TAKE(hdw->big_lock);
5000 for (idx = 0; ; idx++) {
5001 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
5002 if (!ccnt) break;
5003 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
5004 if (!acnt) break;
5005 buf[0] = '\n'; ccnt = 1;
5006 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
5007 }
2eb563b7
MI		 5008 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
5009 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
681c7399
MI		 5010 LOCK_GIVE(hdw->big_lock);
5011 return bcnt;
5012}
5013
5014
5015static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
5016{
2eb563b7
MI		 5017 char buf[256];
5018 unsigned int idx, ccnt;
5019 unsigned int lcnt, ucnt;
681c7399
MI		 5020
5021 for (idx = 0; ; idx++) {
5022 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
5023 if (!ccnt) break;
5024 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
5025 }
2eb563b7
MI		 5026 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
5027 ucnt = 0;
5028 while (ucnt < ccnt) {
5029 lcnt = 0;
5030 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
5031 lcnt++;
5032 }
5033 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
5034 ucnt += lcnt + 1;
5035 }
681c7399
MI		 5036}
5037
5038
5039/* Evaluate and update the driver's current state, taking various actions
5040 as appropriate for the update. */
5041static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
5042{
5043 unsigned int st;
5044 int state_updated = 0;
5045 int callback_flag = 0;
1b9c18c5 5046 int analog_mode;
681c7399
MI		 5047
5048 pvr2_trace(PVR2_TRACE_STBITS,
5049 "Drive state check START");
5050 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5051 pvr2_hdw_state_log_state(hdw);
5052 }
5053
5054 /* Process all state and get back over disposition */
5055 state_updated = pvr2_hdw_state_update(hdw);
5056
1b9c18c5
MI		 5057 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
5058
681c7399
MI		 5059 /* Update master state based upon all other states. */
5060 if (!hdw->flag_ok) {
5061 st = PVR2_STATE_DEAD;
5062 } else if (hdw->fw1_state != FW1_STATE_OK) {
5063 st = PVR2_STATE_COLD;
72998b71
MI		 5064 } else if ((analog_mode ||
5065 hdw->hdw_desc->flag_digital_requires_cx23416) &&
5066 !hdw->state_encoder_ok) {
681c7399 5067 st = PVR2_STATE_WARM;
1b9c18c5
MI		 5068 } else if (hdw->flag_tripped ||
5069 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 5070 st = PVR2_STATE_ERROR;
62433e31 5071 } else if (hdw->state_usbstream_run &&
1b9c18c5 5072 (!analog_mode ||
62433e31 5073 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 5074 st = PVR2_STATE_RUN;
5075 } else {
5076 st = PVR2_STATE_READY;
5077 }
5078 if (hdw->master_state != st) {
5079 pvr2_trace(PVR2_TRACE_STATE,
5080 "Device state change from %s to %s",
5081 pvr2_get_state_name(hdw->master_state),
5082 pvr2_get_state_name(st));
40381cb0 5083 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 5084 hdw->master_state = st;
5085 state_updated = !0;
5086 callback_flag = !0;
5087 }
5088 if (state_updated) {
5089 /* Trigger anyone waiting on any state changes here. */
5090 wake_up(&hdw->state_wait_data);
5091 }
5092
5093 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5094 pvr2_hdw_state_log_state(hdw);
5095 }
5096 pvr2_trace(PVR2_TRACE_STBITS,
5097 "Drive state check DONE callback=%d",callback_flag);
5098
5099 return callback_flag;
5100}
5101
5102
5103/* Cause kernel thread to check / update driver state */
5104static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5105{
5106 if (hdw->state_stale) return;
5107 hdw->state_stale = !0;
5108 trace_stbit("state_stale",hdw->state_stale);
5109 queue_work(hdw->workqueue,&hdw->workpoll);
5110}
5111
5112
d855497e
MI		 5113int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5114{
5115 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5116}
5117
5118
5119int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5120{
5121 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5122}
5123
5124
5125int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5126{
5127 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5128}
5129
5130
5131int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5132{
5133 u32 cval,nval;
5134 int ret;
5135 if (~msk) {
5136 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5137 if (ret) return ret;
5138 nval = (cval & ~msk) | (val & msk);
5139 pvr2_trace(PVR2_TRACE_GPIO,
5140 "GPIO direction changing 0x%x:0x%x"
5141 " from 0x%x to 0x%x",
5142 msk,val,cval,nval);
5143 } else {
5144 nval = val;
5145 pvr2_trace(PVR2_TRACE_GPIO,
5146 "GPIO direction changing to 0x%x",nval);
5147 }
5148 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5149}
5150
5151
5152int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5153{
5154 u32 cval,nval;
5155 int ret;
5156 if (~msk) {
5157 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5158 if (ret) return ret;
5159 nval = (cval & ~msk) | (val & msk);
5160 pvr2_trace(PVR2_TRACE_GPIO,
5161 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5162 msk,val,cval,nval);
5163 } else {
5164 nval = val;
5165 pvr2_trace(PVR2_TRACE_GPIO,
5166 "GPIO output changing to 0x%x",nval);
5167 }
5168 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5169}
5170
5171
a51f5000
MI		 5172void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5173{
40f07111
MI		 5174 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5175 memset(vtp, 0, sizeof(*vtp));
50e9efd6
HV		 5176 vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5177 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2641df36 5178 hdw->tuner_signal_stale = 0;
40f07111
MI		 5179 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5180 using v4l2-subdev - therefore we can't support that AT ALL right
5181 now. (Of course, no sub-drivers seem to implement it either.
5182 But now it's a a chicken and egg problem...) */
4cfe3319 5183 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
2641df36 5184 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5185 " type=%u strength=%u audio=0x%x cap=0x%x"
5186 " low=%u hi=%u",
5187 vtp->type,
5188 vtp->signal, vtp->rxsubchans, vtp->capability,
5189 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5190
5191 /* We have to do this to avoid getting into constant polling if
5192 there's nobody to answer a poll of cropcap info. */
5193 hdw->cropcap_stale = 0;
a51f5000
MI		 5194}
5195
5196
7fb20fa3
MI		 5197unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5198{
5199 return hdw->input_avail_mask;
5200}
5201
5202
1cb03b76
MI		 5203unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5204{
5205 return hdw->input_allowed_mask;
5206}
5207
5208
5209static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5210{
5211 if (hdw->input_val != v) {
5212 hdw->input_val = v;
5213 hdw->input_dirty = !0;
5214 }
5215
5216 /* Handle side effects - if we switch to a mode that needs the RF
5217 tuner, then select the right frequency choice as well and mark
5218 it dirty. */
5219 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5220 hdw->freqSelector = 0;
5221 hdw->freqDirty = !0;
5222 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5223 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5224 hdw->freqSelector = 1;
5225 hdw->freqDirty = !0;
5226 }
5227 return 0;
5228}
5229
5230
5231int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5232 unsigned int change_mask,
5233 unsigned int change_val)
5234{
5235 int ret = 0;
5236 unsigned int nv,m,idx;
5237 LOCK_TAKE(hdw->big_lock);
5238 do {
5239 nv = hdw->input_allowed_mask & ~change_mask;
5240 nv |= (change_val & change_mask);
5241 nv &= hdw->input_avail_mask;
5242 if (!nv) {
5243 /* No legal modes left; return error instead. */
5244 ret = -EPERM;
5245 break;
5246 }
5247 hdw->input_allowed_mask = nv;
5248 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5249 /* Current mode is still in the allowed mask, so
5250 we're done. */
5251 break;
5252 }
5253 /* Select and switch to a mode that is still in the allowed
5254 mask */
5255 if (!hdw->input_allowed_mask) {
5256 /* Nothing legal; give up */
5257 break;
5258 }
5259 m = hdw->input_allowed_mask;
5260 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5261 if (!((1 << idx) & m)) continue;
5262 pvr2_hdw_set_input(hdw,idx);
5263 break;
5264 }
5265 } while (0);
5266 LOCK_GIVE(hdw->big_lock);
5267 return ret;
5268}
5269
5270
e61b6fc5 5271/* Find I2C address of eeprom */
07e337ee 5272static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5273{
5274 int result;
5275 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5276 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5277 result = pvr2_send_request(hdw,
5278 hdw->cmd_buffer,1,
5279 hdw->cmd_buffer,1);
5280 if (result < 0) break;
5281 result = hdw->cmd_buffer[0];
5282 } while(0); LOCK_GIVE(hdw->ctl_lock);
5283 return result;
5284}
5285
5286
32ffa9ae 5287int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5288 struct v4l2_dbg_match *match, u64 reg_id,
5289 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5290{
5291#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 5292 struct v4l2_dbg_register req;
6d98816f
MI		 5293 int stat = 0;
5294 int okFl = 0;
32ffa9ae 5295
201f5c9c
MI		 5296 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5297
aecde8b5 5298 req.match = *match;
32ffa9ae
MI		 5299 req.reg = reg_id;
5300 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5301 /* It would be nice to know if a sub-device answered the request */
5302 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5303 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5304 if (okFl) {
5305 return stat;
5306 }
32ffa9ae
MI		 5307 return -EINVAL;
5308#else
5309 return -ENOSYS;
5310#endif
5311}
5312
5313
d855497e
MI		 5314/*
5315 Stuff for Emacs to see, in order to encourage consistent editing style:
5316 *** Local Variables: ***
5317 *** mode: c ***
5318 *** fill-column: 75 ***
5319 *** tab-width: 8 ***
5320 *** c-basic-offset: 8 ***
5321 *** End: ***
5322 */
Linux kernel - Deliverables
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