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V4L/DVB (7670): pxa-camera: handle FIFO overruns
[deliverable/linux.git] / drivers / media / video / pxa_camera.c
CommitLineData
3bc43840
GL		 1/*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
3bc43840
GL		 13#include <linux/init.h>
14#include <linux/module.h>
7102b773 15#include <linux/io.h>
3bc43840
GL		 16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/errno.h>
19#include <linux/fs.h>
20#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/mm.h>
23#include <linux/moduleparam.h>
24#include <linux/time.h>
25#include <linux/version.h>
26#include <linux/device.h>
27#include <linux/platform_device.h>
28#include <linux/mutex.h>
29#include <linux/clk.h>
30
31#include <media/v4l2-common.h>
32#include <media/v4l2-dev.h>
33#include <media/soc_camera.h>
34
35#include <linux/videodev2.h>
36
37#include <asm/dma.h>
38#include <asm/arch/pxa-regs.h>
39#include <asm/arch/camera.h>
40
41#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
42#define PXA_CAM_DRV_NAME "pxa27x-camera"
43
7102b773
GL		 44#define CICR0_SIM_MP (0 << 24)
45#define CICR0_SIM_SP (1 << 24)
46#define CICR0_SIM_MS (2 << 24)
47#define CICR0_SIM_EP (3 << 24)
48#define CICR0_SIM_ES (4 << 24)
49
50#define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
51#define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
a5462e5b
MR		 52#define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
53#define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
54#define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
7102b773
GL		 55
56#define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
57#define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
58#define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
59#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
60#define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
61
62#define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
63#define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
64#define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
65#define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
66
3bc43840
GL		 67#define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
68 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
69 CICR0_EOFM | CICR0_FOM)
70
71static DEFINE_MUTEX(camera_lock);
72
73/*
74 * Structures
75 */
a5462e5b
MR		 76enum pxa_camera_active_dma {
77 DMA_Y = 0x1,
78 DMA_U = 0x2,
79 DMA_V = 0x4,
80};
81
82/* descriptor needed for the PXA DMA engine */
83struct pxa_cam_dma {
84 dma_addr_t sg_dma;
85 struct pxa_dma_desc *sg_cpu;
86 size_t sg_size;
87 int sglen;
88};
3bc43840
GL		 89
90/* buffer for one video frame */
91struct pxa_buffer {
92 /* common v4l buffer stuff -- must be first */
93 struct videobuf_buffer vb;
94
95 const struct soc_camera_data_format *fmt;
96
a5462e5b
MR		 97 /* our descriptor lists for Y, U and V channels */
98 struct pxa_cam_dma dmas[3];
99
3bc43840 100 int inwork;
a5462e5b
MR		 101
102 enum pxa_camera_active_dma active_dma;
3bc43840
GL		 103};
104
105struct pxa_framebuffer_queue {
106 dma_addr_t sg_last_dma;
107 struct pxa_dma_desc *sg_last_cpu;
108};
109
110struct pxa_camera_dev {
111 struct device *dev;
112 /* PXA27x is only supposed to handle one camera on its Quick Capture
113 * interface. If anyone ever builds hardware to enable more than
114 * one camera, they will have to modify this driver too */
115 struct soc_camera_device *icd;
116 struct clk *clk;
117
118 unsigned int irq;
119 void __iomem *base;
a5462e5b 120
e7c50688 121 int channels;
a5462e5b 122 unsigned int dma_chans[3];
3bc43840 123
3bc43840
GL		 124 struct pxacamera_platform_data *pdata;
125 struct resource *res;
126 unsigned long platform_flags;
127 unsigned long platform_mclk_10khz;
128
129 struct list_head capture;
130
131 spinlock_t lock;
132
3bc43840
GL		 133 struct pxa_buffer *active;
134};
135
136static const char *pxa_cam_driver_description = "PXA_Camera";
137
138static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
139
140/*
141 * Videobuf operations
142 */
7102b773
GL		 143static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
144 unsigned int *size)
3bc43840
GL		 145{
146 struct soc_camera_device *icd = vq->priv_data;
147
148 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
149
a5462e5b
MR		 150 /* planar capture requires Y, U and V buffers to be page aligned */
151 if (icd->current_fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
152 *size = PAGE_ALIGN(icd->width * icd->height); /* Y pages */
153 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* U pages */
154 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* V pages */
155 } else {
156 *size = icd->width * icd->height *
157 ((icd->current_fmt->depth + 7) >> 3);
158 }
3bc43840
GL		 159
160 if (0 == *count)
161 *count = 32;
162 while (*size * *count > vid_limit * 1024 * 1024)
163 (*count)--;
164
165 return 0;
166}
167
168static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
169{
170 struct soc_camera_device *icd = vq->priv_data;
171 struct soc_camera_host *ici =
172 to_soc_camera_host(icd->dev.parent);
173 struct pxa_camera_dev *pcdev = ici->priv;
174 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
a5462e5b 175 int i;
3bc43840
GL		 176
177 BUG_ON(in_interrupt());
178
7e28adb2 179 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 180 &buf->vb, buf->vb.baddr, buf->vb.bsize);
181
182 /* This waits until this buffer is out of danger, i.e., until it is no
183 * longer in STATE_QUEUED or STATE_ACTIVE */
184 videobuf_waiton(&buf->vb, 0, 0);
185 videobuf_dma_unmap(vq, dma);
186 videobuf_dma_free(dma);
187
a5462e5b
MR		 188 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
189 if (buf->dmas[i].sg_cpu)
190 dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
191 buf->dmas[i].sg_cpu,
192 buf->dmas[i].sg_dma);
193 buf->dmas[i].sg_cpu = NULL;
194 }
3bc43840
GL		 195
196 buf->vb.state = VIDEOBUF_NEEDS_INIT;
197}
198
a5462e5b
MR		 199static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
200 struct pxa_buffer *buf,
201 struct videobuf_dmabuf *dma, int channel,
202 int sglen, int sg_start, int cibr,
203 unsigned int size)
204{
205 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
206 int i;
207
208 if (pxa_dma->sg_cpu)
209 dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
210 pxa_dma->sg_cpu, pxa_dma->sg_dma);
211
212 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
213 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
214 &pxa_dma->sg_dma, GFP_KERNEL);
215 if (!pxa_dma->sg_cpu)
216 return -ENOMEM;
217
218 pxa_dma->sglen = sglen;
219
220 for (i = 0; i < sglen; i++) {
221 int sg_i = sg_start + i;
222 struct scatterlist *sg = dma->sglist;
223 unsigned int dma_len = sg_dma_len(&sg[sg_i]), xfer_len;
224
225 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
226 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(&sg[sg_i]);
227
228 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
229 xfer_len = (min(dma_len, size) + 7) & ~7;
230
231 pxa_dma->sg_cpu[i].dcmd =
232 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
233 size -= dma_len;
234 pxa_dma->sg_cpu[i].ddadr =
235 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
236 }
237
238 pxa_dma->sg_cpu[sglen - 1].ddadr = DDADR_STOP;
239 pxa_dma->sg_cpu[sglen - 1].dcmd |= DCMD_ENDIRQEN;
240
241 return 0;
242}
243
7102b773
GL		 244static int pxa_videobuf_prepare(struct videobuf_queue *vq,
245 struct videobuf_buffer *vb, enum v4l2_field field)
3bc43840
GL		 246{
247 struct soc_camera_device *icd = vq->priv_data;
248 struct soc_camera_host *ici =
249 to_soc_camera_host(icd->dev.parent);
250 struct pxa_camera_dev *pcdev = ici->priv;
251 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
a5462e5b
MR		 252 int ret;
253 int sglen_y, sglen_yu = 0, sglen_u = 0, sglen_v = 0;
254 int size_y, size_u = 0, size_v = 0;
3bc43840 255
7e28adb2 256 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 257 vb, vb->baddr, vb->bsize);
258
259 /* Added list head initialization on alloc */
260 WARN_ON(!list_empty(&vb->queue));
261
262#ifdef DEBUG
263 /* This can be useful if you want to see if we actually fill
264 * the buffer with something */
265 memset((void *)vb->baddr, 0xaa, vb->bsize);
266#endif
267
268 BUG_ON(NULL == icd->current_fmt);
269
270 /* I think, in buf_prepare you only have to protect global data,
271 * the actual buffer is yours */
272 buf->inwork = 1;
273
274 if (buf->fmt != icd->current_fmt ||
275 vb->width != icd->width ||
276 vb->height != icd->height ||
277 vb->field != field) {
278 buf->fmt = icd->current_fmt;
279 vb->width = icd->width;
280 vb->height = icd->height;
281 vb->field = field;
282 vb->state = VIDEOBUF_NEEDS_INIT;
283 }
284
285 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
286 if (0 != vb->baddr && vb->bsize < vb->size) {
287 ret = -EINVAL;
288 goto out;
289 }
290
291 if (vb->state == VIDEOBUF_NEEDS_INIT) {
292 unsigned int size = vb->size;
293 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
294
295 ret = videobuf_iolock(vq, vb, NULL);
296 if (ret)
297 goto fail;
298
a5462e5b
MR		 299 if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
300 /* FIXME the calculations should be more precise */
301 sglen_y = dma->sglen / 2;
302 sglen_u = sglen_v = dma->sglen / 4 + 1;
303 sglen_yu = sglen_y + sglen_u;
304 size_y = size / 2;
305 size_u = size_v = size / 4;
306 } else {
307 sglen_y = dma->sglen;
308 size_y = size;
309 }
310
311 /* init DMA for Y channel */
312 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, sglen_y,
313 0, 0x28, size_y);
3bc43840 314
a5462e5b
MR		 315 if (ret) {
316 dev_err(pcdev->dev,
317 "DMA initialization for Y/RGB failed\n");
3bc43840
GL		 318 goto fail;
319 }
320
a5462e5b
MR		 321 if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
322 /* init DMA for U channel */
323 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, sglen_u,
324 sglen_y, 0x30, size_u);
325 if (ret) {
326 dev_err(pcdev->dev,
327 "DMA initialization for U failed\n");
328 goto fail_u;
329 }
330
331 /* init DMA for V channel */
332 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, sglen_v,
333 sglen_yu, 0x38, size_v);
334 if (ret) {
335 dev_err(pcdev->dev,
336 "DMA initialization for V failed\n");
337 goto fail_v;
338 }
3bc43840 339 }
3bc43840
GL		 340
341 vb->state = VIDEOBUF_PREPARED;
342 }
343
344 buf->inwork = 0;
a5462e5b
MR		 345 buf->active_dma = DMA_Y;
346 if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P)
347 buf->active_dma |= DMA_U | DMA_V;
3bc43840
GL		 348
349 return 0;
350
a5462e5b
MR		 351fail_v:
352 dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
353 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
354fail_u:
355 dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
356 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
3bc43840
GL		 357fail:
358 free_buffer(vq, buf);
359out:
360 buf->inwork = 0;
361 return ret;
362}
363
7102b773
GL		 364static void pxa_videobuf_queue(struct videobuf_queue *vq,
365 struct videobuf_buffer *vb)
3bc43840
GL		 366{
367 struct soc_camera_device *icd = vq->priv_data;
368 struct soc_camera_host *ici =
369 to_soc_camera_host(icd->dev.parent);
370 struct pxa_camera_dev *pcdev = ici->priv;
371 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
7102b773 372 struct pxa_buffer *active;
3bc43840
GL		 373 unsigned long flags;
374
7e28adb2 375 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 376 vb, vb->baddr, vb->bsize);
377 spin_lock_irqsave(&pcdev->lock, flags);
378
379 list_add_tail(&vb->queue, &pcdev->capture);
380
381 vb->state = VIDEOBUF_ACTIVE;
7102b773 382 active = pcdev->active;
3bc43840 383
7102b773 384 if (!active) {
3bc43840 385 CIFR |= CIFR_RESET_F;
a5462e5b
MR		 386 DDADR(pcdev->dma_chans[0]) = buf->dmas[0].sg_dma;
387 DCSR(pcdev->dma_chans[0]) = DCSR_RUN;
388
389 if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
390 DDADR(pcdev->dma_chans[1]) = buf->dmas[1].sg_dma;
391 DCSR(pcdev->dma_chans[1]) = DCSR_RUN;
392
393 DDADR(pcdev->dma_chans[2]) = buf->dmas[2].sg_dma;
394 DCSR(pcdev->dma_chans[2]) = DCSR_RUN;
395 }
396
3bc43840
GL		 397 pcdev->active = buf;
398 CICR0 |= CICR0_ENB;
399 } else {
a5462e5b
MR		 400 struct pxa_cam_dma *buf_dma;
401 struct pxa_cam_dma *act_dma;
a5462e5b
MR		 402 int nents;
403 int i;
404
e7c50688 405 for (i = 0; i < pcdev->channels; i++) {
a5462e5b
MR		 406 buf_dma = &buf->dmas[i];
407 act_dma = &active->dmas[i];
408 nents = buf_dma->sglen;
409
410 /* Stop DMA engine */
411 DCSR(pcdev->dma_chans[i]) = 0;
412
413 /* Add the descriptors we just initialized to
414 the currently running chain */
415 act_dma->sg_cpu[act_dma->sglen - 1].ddadr =
416 buf_dma->sg_dma;
417
418 /* Setup a dummy descriptor with the DMA engines current
419 * state
3bc43840 420 */
a5462e5b
MR		 421 buf_dma->sg_cpu[nents].dsadr =
422 pcdev->res->start + 0x28 + i*8; /* CIBRx */
423 buf_dma->sg_cpu[nents].dtadr =
424 DTADR(pcdev->dma_chans[i]);
425 buf_dma->sg_cpu[nents].dcmd =
426 DCMD(pcdev->dma_chans[i]);
427
428 if (DDADR(pcdev->dma_chans[i]) == DDADR_STOP) {
429 /* The DMA engine is on the last
430 descriptor, set the next descriptors
431 address to the descriptors we just
432 initialized */
433 buf_dma->sg_cpu[nents].ddadr = buf_dma->sg_dma;
434 } else {
435 buf_dma->sg_cpu[nents].ddadr =
436 DDADR(pcdev->dma_chans[i]);
437 }
438
439 /* The next descriptor is the dummy descriptor */
440 DDADR(pcdev->dma_chans[i]) = buf_dma->sg_dma + nents *
441 sizeof(struct pxa_dma_desc);
442
443 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
3bc43840 444 }
3bc43840
GL		 445 }
446
447 spin_unlock_irqrestore(&pcdev->lock, flags);
3bc43840
GL		 448}
449
450static void pxa_videobuf_release(struct videobuf_queue *vq,
451 struct videobuf_buffer *vb)
452{
453 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
454#ifdef DEBUG
455 struct soc_camera_device *icd = vq->priv_data;
456
7e28adb2 457 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 458 vb, vb->baddr, vb->bsize);
459
460 switch (vb->state) {
461 case VIDEOBUF_ACTIVE:
7e28adb2 462 dev_dbg(&icd->dev, "%s (active)\n", __func__);
3bc43840
GL		 463 break;
464 case VIDEOBUF_QUEUED:
7e28adb2 465 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
3bc43840
GL		 466 break;
467 case VIDEOBUF_PREPARED:
7e28adb2 468 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
3bc43840
GL		 469 break;
470 default:
7e28adb2 471 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
3bc43840
GL		 472 break;
473 }
474#endif
475
476 free_buffer(vq, buf);
477}
478
a5462e5b
MR		 479static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
480 struct videobuf_buffer *vb,
481 struct pxa_buffer *buf)
482{
483 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
484 list_del_init(&vb->queue);
485 vb->state = VIDEOBUF_DONE;
486 do_gettimeofday(&vb->ts);
487 vb->field_count++;
488 wake_up(&vb->done);
489
490 if (list_empty(&pcdev->capture)) {
491 pcdev->active = NULL;
492 DCSR(pcdev->dma_chans[0]) = 0;
493 DCSR(pcdev->dma_chans[1]) = 0;
494 DCSR(pcdev->dma_chans[2]) = 0;
495 CICR0 &= ~CICR0_ENB;
496 return;
497 }
498
499 pcdev->active = list_entry(pcdev->capture.next,
500 struct pxa_buffer, vb.queue);
501}
502
503static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
504 enum pxa_camera_active_dma act_dma)
3bc43840 505{
3bc43840
GL		 506 struct pxa_buffer *buf;
507 unsigned long flags;
e7c50688 508 u32 status, camera_status, overrun;
3bc43840
GL		 509 struct videobuf_buffer *vb;
510
511 spin_lock_irqsave(&pcdev->lock, flags);
512
a5462e5b
MR		 513 status = DCSR(channel);
514 DCSR(channel) = status | DCSR_ENDINTR;
7102b773 515
3bc43840 516 if (status & DCSR_BUSERR) {
7102b773 517 dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
3bc43840
GL		 518 goto out;
519 }
520
521 if (!(status & DCSR_ENDINTR)) {
7102b773
GL		 522 dev_err(pcdev->dev, "Unknown DMA IRQ source, "
523 "status: 0x%08x\n", status);
3bc43840
GL		 524 goto out;
525 }
526
3bc43840 527 if (!pcdev->active) {
7102b773 528 dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n");
3bc43840
GL		 529 goto out;
530 }
531
e7c50688
GL		 532 camera_status = CISR;
533 overrun = CISR_IFO_0;
534 if (pcdev->channels == 3)
535 overrun |= CISR_IFO_1 | CISR_IFO_2;
536 if (camera_status & overrun) {
537 dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", camera_status);
538 /* Stop the Capture Interface */
539 CICR0 &= ~CICR0_ENB;
540 /* Stop DMA */
541 DCSR(channel) = 0;
542 /* Reset the FIFOs */
543 CIFR |= CIFR_RESET_F;
544 /* Enable End-Of-Frame Interrupt */
545 CICR0 &= ~CICR0_EOFM;
546 /* Restart the Capture Interface */
547 CICR0 |= CICR0_ENB;
548 goto out;
549 }
550
3bc43840
GL		 551 vb = &pcdev->active->vb;
552 buf = container_of(vb, struct pxa_buffer, vb);
553 WARN_ON(buf->inwork || list_empty(&vb->queue));
7e28adb2 554 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 555 vb, vb->baddr, vb->bsize);
556
a5462e5b
MR		 557 buf->active_dma &= ~act_dma;
558 if (!buf->active_dma)
559 pxa_camera_wakeup(pcdev, vb, buf);
3bc43840
GL		 560
561out:
562 spin_unlock_irqrestore(&pcdev->lock, flags);
563}
564
a5462e5b
MR		 565static void pxa_camera_dma_irq_y(int channel, void *data)
566{
567 struct pxa_camera_dev *pcdev = data;
568 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
569}
570
571static void pxa_camera_dma_irq_u(int channel, void *data)
572{
573 struct pxa_camera_dev *pcdev = data;
574 pxa_camera_dma_irq(channel, pcdev, DMA_U);
575}
576
577static void pxa_camera_dma_irq_v(int channel, void *data)
578{
579 struct pxa_camera_dev *pcdev = data;
580 pxa_camera_dma_irq(channel, pcdev, DMA_V);
581}
582
7102b773 583static struct videobuf_queue_ops pxa_videobuf_ops = {
3bc43840
GL		 584 .buf_setup = pxa_videobuf_setup,
585 .buf_prepare = pxa_videobuf_prepare,
586 .buf_queue = pxa_videobuf_queue,
587 .buf_release = pxa_videobuf_release,
588};
589
590static int mclk_get_divisor(struct pxa_camera_dev *pcdev)
591{
592 unsigned int mclk_10khz = pcdev->platform_mclk_10khz;
593 unsigned long div;
594 unsigned long lcdclk;
595
596 lcdclk = clk_get_rate(pcdev->clk) / 10000;
597
598 /* We verify platform_mclk_10khz != 0, so if anyone breaks it, here
599 * they get a nice Oops */
600 div = (lcdclk + 2 * mclk_10khz - 1) / (2 * mclk_10khz) - 1;
601
602 dev_dbg(pcdev->dev, "LCD clock %lukHz, target freq %dkHz, "
603 "divisor %lu\n", lcdclk * 10, mclk_10khz * 10, div);
604
605 return div;
606}
607
7102b773 608static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
3bc43840
GL		 609{
610 struct pxacamera_platform_data *pdata = pcdev->pdata;
611 u32 cicr4 = 0;
612
613 dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n",
614 pcdev, pdata);
615
616 if (pdata && pdata->init) {
7e28adb2 617 dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__);
3bc43840
GL		 618 pdata->init(pcdev->dev);
619 }
620
621 if (pdata && pdata->power) {
7e28adb2 622 dev_dbg(pcdev->dev, "%s: Power on camera\n", __func__);
3bc43840
GL		 623 pdata->power(pcdev->dev, 1);
624 }
625
626 if (pdata && pdata->reset) {
627 dev_dbg(pcdev->dev, "%s: Releasing camera reset\n",
7e28adb2 628 __func__);
3bc43840
GL		 629 pdata->reset(pcdev->dev, 1);
630 }
631
632 CICR0 = 0x3FF; /* disable all interrupts */
633
634 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
635 cicr4 |= CICR4_PCLK_EN;
636 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
637 cicr4 |= CICR4_MCLK_EN;
638 if (pcdev->platform_flags & PXA_CAMERA_PCP)
639 cicr4 |= CICR4_PCP;
640 if (pcdev->platform_flags & PXA_CAMERA_HSP)
641 cicr4 |= CICR4_HSP;
642 if (pcdev->platform_flags & PXA_CAMERA_VSP)
643 cicr4 |= CICR4_VSP;
644
645 CICR4 = mclk_get_divisor(pcdev) | cicr4;
646
647 clk_enable(pcdev->clk);
648}
649
7102b773 650static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
3bc43840
GL		 651{
652 struct pxacamera_platform_data *board = pcdev->pdata;
653
654 clk_disable(pcdev->clk);
655
656 if (board && board->reset) {
657 dev_dbg(pcdev->dev, "%s: Asserting camera reset\n",
7e28adb2 658 __func__);
3bc43840
GL		 659 board->reset(pcdev->dev, 0);
660 }
661
662 if (board && board->power) {
7e28adb2 663 dev_dbg(pcdev->dev, "%s: Power off camera\n", __func__);
3bc43840
GL		 664 board->power(pcdev->dev, 0);
665 }
666}
667
668static irqreturn_t pxa_camera_irq(int irq, void *data)
669{
670 struct pxa_camera_dev *pcdev = data;
671 unsigned int status = CISR;
672
673 dev_dbg(pcdev->dev, "Camera interrupt status 0x%x\n", status);
674
e7c50688
GL		 675 if (!status)
676 return IRQ_NONE;
677
3bc43840 678 CISR = status;
e7c50688
GL		 679
680 if (status & CISR_EOF) {
681 int i;
682 for (i = 0; i < pcdev->channels; i++) {
683 DDADR(pcdev->dma_chans[i]) =
684 pcdev->active->dmas[i].sg_dma;
685 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
686 }
687 CICR0 |= CICR0_EOFM;
688 }
689
3bc43840
GL		 690 return IRQ_HANDLED;
691}
692
693/* The following two functions absolutely depend on the fact, that
694 * there can be only one camera on PXA quick capture interface */
7102b773 695static int pxa_camera_add_device(struct soc_camera_device *icd)
3bc43840
GL		 696{
697 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
698 struct pxa_camera_dev *pcdev = ici->priv;
699 int ret;
700
701 mutex_lock(&camera_lock);
702
703 if (pcdev->icd) {
704 ret = -EBUSY;
705 goto ebusy;
706 }
707
708 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
709 icd->devnum);
710
7102b773 711 pxa_camera_activate(pcdev);
3bc43840
GL		 712 ret = icd->ops->init(icd);
713
714 if (!ret)
715 pcdev->icd = icd;
716
717ebusy:
718 mutex_unlock(&camera_lock);
719
720 return ret;
721}
722
7102b773 723static void pxa_camera_remove_device(struct soc_camera_device *icd)
3bc43840
GL		 724{
725 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
726 struct pxa_camera_dev *pcdev = ici->priv;
727
728 BUG_ON(icd != pcdev->icd);
729
730 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
731 icd->devnum);
732
733 /* disable capture, disable interrupts */
734 CICR0 = 0x3ff;
a5462e5b 735
3bc43840 736 /* Stop DMA engine */
a5462e5b
MR		 737 DCSR(pcdev->dma_chans[0]) = 0;
738 DCSR(pcdev->dma_chans[1]) = 0;
739 DCSR(pcdev->dma_chans[2]) = 0;
3bc43840
GL		 740
741 icd->ops->release(icd);
742
7102b773 743 pxa_camera_deactivate(pcdev);
3bc43840
GL		 744
745 pcdev->icd = NULL;
746}
747
ad5f2e85
GL		 748static int test_platform_param(struct pxa_camera_dev *pcdev,
749 unsigned char buswidth, unsigned long *flags)
3bc43840 750{
ad5f2e85
GL		 751 /*
752 * Platform specified synchronization and pixel clock polarities are
753 * only a recommendation and are only used during probing. The PXA270
754 * quick capture interface supports both.
755 */
756 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
757 SOCAM_MASTER : SOCAM_SLAVE) |
758 SOCAM_HSYNC_ACTIVE_HIGH |
759 SOCAM_HSYNC_ACTIVE_LOW |
760 SOCAM_VSYNC_ACTIVE_HIGH |
761 SOCAM_VSYNC_ACTIVE_LOW |
762 SOCAM_PCLK_SAMPLE_RISING |
763 SOCAM_PCLK_SAMPLE_FALLING;
3bc43840
GL		 764
765 /* If requested data width is supported by the platform, use it */
ad5f2e85 766 switch (buswidth) {
3bc43840 767 case 10:
ad5f2e85
GL		 768 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
769 return -EINVAL;
770 *flags |= SOCAM_DATAWIDTH_10;
3bc43840
GL		 771 break;
772 case 9:
ad5f2e85
GL		 773 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
774 return -EINVAL;
775 *flags |= SOCAM_DATAWIDTH_9;
3bc43840
GL		 776 break;
777 case 8:
ad5f2e85
GL		 778 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
779 return -EINVAL;
780 *flags |= SOCAM_DATAWIDTH_8;
3bc43840 781 }
ad5f2e85
GL		 782
783 return 0;
784}
785
786static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
787{
788 struct soc_camera_host *ici =
789 to_soc_camera_host(icd->dev.parent);
790 struct pxa_camera_dev *pcdev = ici->priv;
791 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
a5462e5b 792 u32 cicr0, cicr1, cicr4 = 0;
ad5f2e85
GL		 793 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
794
795 if (ret < 0)
796 return ret;
797
798 camera_flags = icd->ops->query_bus_param(icd);
799
800 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
801 if (!common_flags)
3bc43840
GL		 802 return -EINVAL;
803
e7c50688
GL		 804 pcdev->channels = 1;
805
ad5f2e85
GL		 806 /* Make choises, based on platform preferences */
807 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
808 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
809 if (pcdev->platform_flags & PXA_CAMERA_HSP)
810 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
811 else
812 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
813 }
814
815 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
816 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
817 if (pcdev->platform_flags & PXA_CAMERA_VSP)
818 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
819 else
820 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
821 }
822
823 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
824 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
825 if (pcdev->platform_flags & PXA_CAMERA_PCP)
826 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
827 else
828 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
829 }
830
831 ret = icd->ops->set_bus_param(icd, common_flags);
3bc43840
GL		 832 if (ret < 0)
833 return ret;
834
835 /* Datawidth is now guaranteed to be equal to one of the three values.
836 * We fix bit-per-pixel equal to data-width... */
ad5f2e85
GL		 837 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
838 case SOCAM_DATAWIDTH_10:
839 icd->buswidth = 10;
3bc43840
GL		 840 dw = 4;
841 bpp = 0x40;
842 break;
ad5f2e85
GL		 843 case SOCAM_DATAWIDTH_9:
844 icd->buswidth = 9;
3bc43840
GL		 845 dw = 3;
846 bpp = 0x20;
847 break;
848 default:
849 /* Actually it can only be 8 now,
850 * default is just to silence compiler warnings */
ad5f2e85
GL		 851 case SOCAM_DATAWIDTH_8:
852 icd->buswidth = 8;
3bc43840
GL		 853 dw = 2;
854 bpp = 0;
855 }
856
857 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
858 cicr4 |= CICR4_PCLK_EN;
859 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
860 cicr4 |= CICR4_MCLK_EN;
ad5f2e85 861 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
3bc43840 862 cicr4 |= CICR4_PCP;
ad5f2e85 863 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
3bc43840 864 cicr4 |= CICR4_HSP;
ad5f2e85 865 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
3bc43840
GL		 866 cicr4 |= CICR4_VSP;
867
868 cicr0 = CICR0;
869 if (cicr0 & CICR0_ENB)
870 CICR0 = cicr0 & ~CICR0_ENB;
a5462e5b
MR		 871
872 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
873
874 switch (pixfmt) {
875 case V4L2_PIX_FMT_YUV422P:
e7c50688 876 pcdev->channels = 3;
a5462e5b
MR		 877 cicr1 |= CICR1_YCBCR_F;
878 case V4L2_PIX_FMT_YUYV:
879 cicr1 |= CICR1_COLOR_SP_VAL(2);
880 break;
881 case V4L2_PIX_FMT_RGB555:
882 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
883 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
884 break;
885 case V4L2_PIX_FMT_RGB565:
886 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
887 break;
888 }
889
890 CICR1 = cicr1;
3bc43840 891 CICR2 = 0;
ad5f2e85 892 CICR3 = CICR3_LPF_VAL(icd->height - 1) |
3bc43840
GL		 893 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
894 CICR4 = mclk_get_divisor(pcdev) | cicr4;
895
896 /* CIF interrupts are not used, only DMA */
897 CICR0 = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
7102b773 898 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)) |
3bc43840
GL		 899 CICR0_DMAEN | CICR0_IRQ_MASK | (cicr0 & CICR0_ENB);
900
901 return 0;
902}
903
ad5f2e85
GL		 904static int pxa_camera_try_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
905{
906 struct soc_camera_host *ici =
907 to_soc_camera_host(icd->dev.parent);
908 struct pxa_camera_dev *pcdev = ici->priv;
909 unsigned long bus_flags, camera_flags;
910 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
911
912 if (ret < 0)
913 return ret;
914
915 camera_flags = icd->ops->query_bus_param(icd);
916
917 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
918}
919
920static int pxa_camera_set_fmt_cap(struct soc_camera_device *icd,
921 __u32 pixfmt, struct v4l2_rect *rect)
922{
923 return icd->ops->set_fmt_cap(icd, pixfmt, rect);
924}
925
926static int pxa_camera_try_fmt_cap(struct soc_camera_device *icd,
7102b773 927 struct v4l2_format *f)
3bc43840
GL		 928{
929 /* limit to pxa hardware capabilities */
930 if (f->fmt.pix.height < 32)
931 f->fmt.pix.height = 32;
932 if (f->fmt.pix.height > 2048)
933 f->fmt.pix.height = 2048;
934 if (f->fmt.pix.width < 48)
935 f->fmt.pix.width = 48;
936 if (f->fmt.pix.width > 2048)
937 f->fmt.pix.width = 2048;
938 f->fmt.pix.width &= ~0x01;
939
ad5f2e85
GL		 940 /* limit to sensor capabilities */
941 return icd->ops->try_fmt_cap(icd, f);
3bc43840
GL		 942}
943
7102b773
GL		 944static int pxa_camera_reqbufs(struct soc_camera_file *icf,
945 struct v4l2_requestbuffers *p)
3bc43840
GL		 946{
947 int i;
948
949 /* This is for locking debugging only. I removed spinlocks and now I
950 * check whether .prepare is ever called on a linked buffer, or whether
951 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
952 * it hadn't triggered */
953 for (i = 0; i < p->count; i++) {
954 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
955 struct pxa_buffer, vb);
956 buf->inwork = 0;
957 INIT_LIST_HEAD(&buf->vb.queue);
958 }
959
960 return 0;
961}
962
7102b773 963static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
3bc43840
GL		 964{
965 struct soc_camera_file *icf = file->private_data;
966 struct pxa_buffer *buf;
967
968 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
969 vb.stream);
970
971 poll_wait(file, &buf->vb.done, pt);
972
973 if (buf->vb.state == VIDEOBUF_DONE ||
974 buf->vb.state == VIDEOBUF_ERROR)
975 return POLLIN|POLLRDNORM;
976
977 return 0;
978}
979
7102b773
GL		 980static int pxa_camera_querycap(struct soc_camera_host *ici,
981 struct v4l2_capability *cap)
3bc43840
GL		 982{
983 /* cap->name is set by the firendly caller:-> */
984 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
985 cap->version = PXA_CAM_VERSION_CODE;
986 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
987
988 return 0;
989}
990
1a0063a9
GL		 991static spinlock_t *pxa_camera_spinlock_alloc(struct soc_camera_file *icf)
992{
993 struct soc_camera_host *ici =
994 to_soc_camera_host(icf->icd->dev.parent);
995 struct pxa_camera_dev *pcdev = ici->priv;
996
997 return &pcdev->lock;
998}
999
b8d9904c
GL		 1000static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1001 .owner = THIS_MODULE,
1002 .add = pxa_camera_add_device,
1003 .remove = pxa_camera_remove_device,
1004 .set_fmt_cap = pxa_camera_set_fmt_cap,
1005 .try_fmt_cap = pxa_camera_try_fmt_cap,
1006 .reqbufs = pxa_camera_reqbufs,
1007 .poll = pxa_camera_poll,
1008 .querycap = pxa_camera_querycap,
1009 .try_bus_param = pxa_camera_try_bus_param,
1010 .set_bus_param = pxa_camera_set_bus_param,
1a0063a9 1011 .spinlock_alloc = pxa_camera_spinlock_alloc,
b8d9904c
GL		 1012};
1013
1014/* Should be allocated dynamically too, but we have only one. */
3bc43840
GL		 1015static struct soc_camera_host pxa_soc_camera_host = {
1016 .drv_name = PXA_CAM_DRV_NAME,
7102b773 1017 .vbq_ops = &pxa_videobuf_ops,
3bc43840 1018 .msize = sizeof(struct pxa_buffer),
b8d9904c 1019 .ops = &pxa_soc_camera_host_ops,
3bc43840
GL		 1020};
1021
1022static int pxa_camera_probe(struct platform_device *pdev)
1023{
1024 struct pxa_camera_dev *pcdev;
1025 struct resource *res;
1026 void __iomem *base;
1027 unsigned int irq;
1028 int err = 0;
1029
1030 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1031 irq = platform_get_irq(pdev, 0);
1032 if (!res || !irq) {
1033 err = -ENODEV;
1034 goto exit;
1035 }
1036
1037 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1038 if (!pcdev) {
7102b773 1039 dev_err(&pdev->dev, "Could not allocate pcdev\n");
3bc43840
GL		 1040 err = -ENOMEM;
1041 goto exit;
1042 }
1043
1044 pcdev->clk = clk_get(&pdev->dev, "CAMCLK");
1045 if (IS_ERR(pcdev->clk)) {
1046 err = PTR_ERR(pcdev->clk);
1047 goto exit_kfree;
1048 }
1049
1050 dev_set_drvdata(&pdev->dev, pcdev);
1051 pcdev->res = res;
1052
1053 pcdev->pdata = pdev->dev.platform_data;
1054 pcdev->platform_flags = pcdev->pdata->flags;
ad5f2e85
GL		 1055 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1056 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
3bc43840
GL		 1057 /* Platform hasn't set available data widths. This is bad.
1058 * Warn and use a default. */
1059 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1060 "data widths, using default 10 bit\n");
1061 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1062 }
1063 pcdev->platform_mclk_10khz = pcdev->pdata->mclk_10khz;
1064 if (!pcdev->platform_mclk_10khz) {
1065 dev_warn(&pdev->dev,
1066 "mclk_10khz == 0! Please, fix your platform data. "
1067 "Using default 20MHz\n");
1068 pcdev->platform_mclk_10khz = 2000;
1069 }
1070
1071 INIT_LIST_HEAD(&pcdev->capture);
1072 spin_lock_init(&pcdev->lock);
1073
1074 /*
1075 * Request the regions.
1076 */
1077 if (!request_mem_region(res->start, res->end - res->start + 1,
1078 PXA_CAM_DRV_NAME)) {
1079 err = -EBUSY;
1080 goto exit_clk;
1081 }
1082
1083 base = ioremap(res->start, res->end - res->start + 1);
1084 if (!base) {
1085 err = -ENOMEM;
1086 goto exit_release;
1087 }
1088 pcdev->irq = irq;
1089 pcdev->base = base;
1090 pcdev->dev = &pdev->dev;
1091
1092 /* request dma */
a5462e5b
MR		 1093 pcdev->dma_chans[0] = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1094 pxa_camera_dma_irq_y, pcdev);
1095 if (pcdev->dma_chans[0] < 0) {
3bc43840
GL		 1096 dev_err(pcdev->dev, "Can't request DMA for Y\n");
1097 err = -ENOMEM;
1098 goto exit_iounmap;
1099 }
a5462e5b
MR		 1100 dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1101
1102 pcdev->dma_chans[1] = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1103 pxa_camera_dma_irq_u, pcdev);
1104 if (pcdev->dma_chans[1] < 0) {
1105 dev_err(pcdev->dev, "Can't request DMA for U\n");
1106 err = -ENOMEM;
1107 goto exit_free_dma_y;
1108 }
1109 dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1110
1111 pcdev->dma_chans[2] = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1112 pxa_camera_dma_irq_v, pcdev);
1113 if (pcdev->dma_chans[0] < 0) {
1114 dev_err(pcdev->dev, "Can't request DMA for V\n");
1115 err = -ENOMEM;
1116 goto exit_free_dma_u;
1117 }
1118 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
3bc43840 1119
a5462e5b
MR		 1120 DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1121 DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1122 DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD;
3bc43840
GL		 1123
1124 /* request irq */
1125 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1126 pcdev);
1127 if (err) {
1128 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1129 goto exit_free_dma;
1130 }
1131
1132 pxa_soc_camera_host.priv = pcdev;
1133 pxa_soc_camera_host.dev.parent = &pdev->dev;
1134 pxa_soc_camera_host.nr = pdev->id;
b8d9904c 1135 err = soc_camera_host_register(&pxa_soc_camera_host);
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GL		 1136 if (err)
1137 goto exit_free_irq;
1138
1139 return 0;
1140
1141exit_free_irq:
1142 free_irq(pcdev->irq, pcdev);
1143exit_free_dma:
a5462e5b
MR		 1144 pxa_free_dma(pcdev->dma_chans[2]);
1145exit_free_dma_u:
1146 pxa_free_dma(pcdev->dma_chans[1]);
1147exit_free_dma_y:
1148 pxa_free_dma(pcdev->dma_chans[0]);
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GL		 1149exit_iounmap:
1150 iounmap(base);
1151exit_release:
1152 release_mem_region(res->start, res->end - res->start + 1);
1153exit_clk:
1154 clk_put(pcdev->clk);
1155exit_kfree:
1156 kfree(pcdev);
1157exit:
1158 return err;
1159}
1160
1161static int __devexit pxa_camera_remove(struct platform_device *pdev)
1162{
1163 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
1164 struct resource *res;
1165
1166 clk_put(pcdev->clk);
1167
a5462e5b
MR		 1168 pxa_free_dma(pcdev->dma_chans[0]);
1169 pxa_free_dma(pcdev->dma_chans[1]);
1170 pxa_free_dma(pcdev->dma_chans[2]);
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GL		 1171 free_irq(pcdev->irq, pcdev);
1172
1173 soc_camera_host_unregister(&pxa_soc_camera_host);
1174
1175 iounmap(pcdev->base);
1176
1177 res = pcdev->res;
1178 release_mem_region(res->start, res->end - res->start + 1);
1179
1180 kfree(pcdev);
1181
7102b773 1182 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
3bc43840 1183
3bc43840
GL		 1184 return 0;
1185}
1186
3bc43840
GL		 1187static struct platform_driver pxa_camera_driver = {
1188 .driver = {
1189 .name = PXA_CAM_DRV_NAME,
1190 },
1191 .probe = pxa_camera_probe,
1192 .remove = __exit_p(pxa_camera_remove),
3bc43840
GL		 1193};
1194
1195
1196static int __devinit pxa_camera_init(void)
1197{
1198 return platform_driver_register(&pxa_camera_driver);
1199}
1200
1201static void __exit pxa_camera_exit(void)
1202{
1203 return platform_driver_unregister(&pxa_camera_driver);
1204}
1205
1206module_init(pxa_camera_init);
1207module_exit(pxa_camera_exit);
1208
1209MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1210MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1211MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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