Commit | Line | Data |
---|---|---|
3bc43840 GL |
1 | /* |
2 | * V4L2 Driver for PXA camera host | |
3 | * | |
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
3bc43840 GL |
13 | #include <linux/init.h> |
14 | #include <linux/module.h> | |
7102b773 | 15 | #include <linux/io.h> |
3bc43840 GL |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/time.h> | |
25 | #include <linux/version.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/mutex.h> | |
29 | #include <linux/clk.h> | |
30 | ||
31 | #include <media/v4l2-common.h> | |
32 | #include <media/v4l2-dev.h> | |
33 | #include <media/soc_camera.h> | |
34 | ||
35 | #include <linux/videodev2.h> | |
36 | ||
37 | #include <asm/dma.h> | |
38 | #include <asm/arch/pxa-regs.h> | |
39 | #include <asm/arch/camera.h> | |
40 | ||
41 | #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) | |
42 | #define PXA_CAM_DRV_NAME "pxa27x-camera" | |
43 | ||
7102b773 GL |
44 | #define CICR0_SIM_MP (0 << 24) |
45 | #define CICR0_SIM_SP (1 << 24) | |
46 | #define CICR0_SIM_MS (2 << 24) | |
47 | #define CICR0_SIM_EP (3 << 24) | |
48 | #define CICR0_SIM_ES (4 << 24) | |
49 | ||
50 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | |
51 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | |
52 | ||
53 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | |
54 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | |
55 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | |
56 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | |
57 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | |
58 | ||
59 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | |
60 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | |
61 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | |
62 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | |
63 | ||
3bc43840 GL |
64 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ |
65 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | |
66 | CICR0_EOFM | CICR0_FOM) | |
67 | ||
68 | static DEFINE_MUTEX(camera_lock); | |
69 | ||
70 | /* | |
71 | * Structures | |
72 | */ | |
73 | ||
74 | /* buffer for one video frame */ | |
75 | struct pxa_buffer { | |
76 | /* common v4l buffer stuff -- must be first */ | |
77 | struct videobuf_buffer vb; | |
78 | ||
79 | const struct soc_camera_data_format *fmt; | |
80 | ||
81 | /* our descriptor list needed for the PXA DMA engine */ | |
82 | dma_addr_t sg_dma; | |
83 | struct pxa_dma_desc *sg_cpu; | |
84 | size_t sg_size; | |
85 | int inwork; | |
86 | }; | |
87 | ||
88 | struct pxa_framebuffer_queue { | |
89 | dma_addr_t sg_last_dma; | |
90 | struct pxa_dma_desc *sg_last_cpu; | |
91 | }; | |
92 | ||
93 | struct pxa_camera_dev { | |
94 | struct device *dev; | |
95 | /* PXA27x is only supposed to handle one camera on its Quick Capture | |
96 | * interface. If anyone ever builds hardware to enable more than | |
97 | * one camera, they will have to modify this driver too */ | |
98 | struct soc_camera_device *icd; | |
99 | struct clk *clk; | |
100 | ||
101 | unsigned int irq; | |
102 | void __iomem *base; | |
103 | unsigned int dma_chan_y; | |
104 | ||
3bc43840 GL |
105 | struct pxacamera_platform_data *pdata; |
106 | struct resource *res; | |
107 | unsigned long platform_flags; | |
108 | unsigned long platform_mclk_10khz; | |
109 | ||
110 | struct list_head capture; | |
111 | ||
112 | spinlock_t lock; | |
113 | ||
3bc43840 GL |
114 | struct pxa_buffer *active; |
115 | }; | |
116 | ||
117 | static const char *pxa_cam_driver_description = "PXA_Camera"; | |
118 | ||
119 | static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ | |
120 | ||
121 | /* | |
122 | * Videobuf operations | |
123 | */ | |
7102b773 GL |
124 | static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, |
125 | unsigned int *size) | |
3bc43840 GL |
126 | { |
127 | struct soc_camera_device *icd = vq->priv_data; | |
128 | ||
129 | dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); | |
130 | ||
131 | *size = icd->width * icd->height * ((icd->current_fmt->depth + 7) >> 3); | |
132 | ||
133 | if (0 == *count) | |
134 | *count = 32; | |
135 | while (*size * *count > vid_limit * 1024 * 1024) | |
136 | (*count)--; | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
141 | static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) | |
142 | { | |
143 | struct soc_camera_device *icd = vq->priv_data; | |
144 | struct soc_camera_host *ici = | |
145 | to_soc_camera_host(icd->dev.parent); | |
146 | struct pxa_camera_dev *pcdev = ici->priv; | |
147 | struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); | |
148 | ||
149 | BUG_ON(in_interrupt()); | |
150 | ||
7e28adb2 | 151 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
152 | &buf->vb, buf->vb.baddr, buf->vb.bsize); |
153 | ||
154 | /* This waits until this buffer is out of danger, i.e., until it is no | |
155 | * longer in STATE_QUEUED or STATE_ACTIVE */ | |
156 | videobuf_waiton(&buf->vb, 0, 0); | |
157 | videobuf_dma_unmap(vq, dma); | |
158 | videobuf_dma_free(dma); | |
159 | ||
160 | if (buf->sg_cpu) | |
161 | dma_free_coherent(pcdev->dev, buf->sg_size, buf->sg_cpu, | |
162 | buf->sg_dma); | |
163 | buf->sg_cpu = NULL; | |
164 | ||
165 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
166 | } | |
167 | ||
7102b773 GL |
168 | static int pxa_videobuf_prepare(struct videobuf_queue *vq, |
169 | struct videobuf_buffer *vb, enum v4l2_field field) | |
3bc43840 GL |
170 | { |
171 | struct soc_camera_device *icd = vq->priv_data; | |
172 | struct soc_camera_host *ici = | |
173 | to_soc_camera_host(icd->dev.parent); | |
174 | struct pxa_camera_dev *pcdev = ici->priv; | |
175 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
176 | int i, ret; | |
177 | ||
7e28adb2 | 178 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
179 | vb, vb->baddr, vb->bsize); |
180 | ||
181 | /* Added list head initialization on alloc */ | |
182 | WARN_ON(!list_empty(&vb->queue)); | |
183 | ||
184 | #ifdef DEBUG | |
185 | /* This can be useful if you want to see if we actually fill | |
186 | * the buffer with something */ | |
187 | memset((void *)vb->baddr, 0xaa, vb->bsize); | |
188 | #endif | |
189 | ||
190 | BUG_ON(NULL == icd->current_fmt); | |
191 | ||
192 | /* I think, in buf_prepare you only have to protect global data, | |
193 | * the actual buffer is yours */ | |
194 | buf->inwork = 1; | |
195 | ||
196 | if (buf->fmt != icd->current_fmt || | |
197 | vb->width != icd->width || | |
198 | vb->height != icd->height || | |
199 | vb->field != field) { | |
200 | buf->fmt = icd->current_fmt; | |
201 | vb->width = icd->width; | |
202 | vb->height = icd->height; | |
203 | vb->field = field; | |
204 | vb->state = VIDEOBUF_NEEDS_INIT; | |
205 | } | |
206 | ||
207 | vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3); | |
208 | if (0 != vb->baddr && vb->bsize < vb->size) { | |
209 | ret = -EINVAL; | |
210 | goto out; | |
211 | } | |
212 | ||
213 | if (vb->state == VIDEOBUF_NEEDS_INIT) { | |
214 | unsigned int size = vb->size; | |
215 | struct videobuf_dmabuf *dma = videobuf_to_dma(vb); | |
216 | ||
217 | ret = videobuf_iolock(vq, vb, NULL); | |
218 | if (ret) | |
219 | goto fail; | |
220 | ||
221 | if (buf->sg_cpu) | |
222 | dma_free_coherent(pcdev->dev, buf->sg_size, buf->sg_cpu, | |
223 | buf->sg_dma); | |
224 | ||
225 | buf->sg_size = (dma->sglen + 1) * sizeof(struct pxa_dma_desc); | |
226 | buf->sg_cpu = dma_alloc_coherent(pcdev->dev, buf->sg_size, | |
227 | &buf->sg_dma, GFP_KERNEL); | |
228 | if (!buf->sg_cpu) { | |
229 | ret = -ENOMEM; | |
230 | goto fail; | |
231 | } | |
232 | ||
233 | dev_dbg(&icd->dev, "nents=%d size: %d sg=0x%p\n", | |
234 | dma->sglen, size, dma->sglist); | |
235 | for (i = 0; i < dma->sglen; i++) { | |
236 | struct scatterlist *sg = dma->sglist; | |
237 | unsigned int dma_len = sg_dma_len(&sg[i]), xfer_len; | |
238 | ||
239 | /* CIBR0 */ | |
240 | buf->sg_cpu[i].dsadr = pcdev->res->start + 0x28; | |
241 | buf->sg_cpu[i].dtadr = sg_dma_address(&sg[i]); | |
242 | /* PXA270 Developer's Manual 27.4.4.1: | |
243 | * round up to 8 bytes */ | |
244 | xfer_len = (min(dma_len, size) + 7) & ~7; | |
245 | if (xfer_len & 7) | |
246 | dev_err(&icd->dev, "Unaligned buffer: " | |
247 | "dma_len %u, size %u\n", dma_len, size); | |
248 | buf->sg_cpu[i].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | | |
249 | DCMD_INCTRGADDR | xfer_len; | |
250 | size -= dma_len; | |
251 | buf->sg_cpu[i].ddadr = buf->sg_dma + (i + 1) * | |
252 | sizeof(struct pxa_dma_desc); | |
253 | } | |
254 | buf->sg_cpu[dma->sglen - 1].ddadr = DDADR_STOP; | |
255 | buf->sg_cpu[dma->sglen - 1].dcmd |= DCMD_ENDIRQEN; | |
256 | ||
257 | vb->state = VIDEOBUF_PREPARED; | |
258 | } | |
259 | ||
260 | buf->inwork = 0; | |
261 | ||
262 | return 0; | |
263 | ||
264 | fail: | |
265 | free_buffer(vq, buf); | |
266 | out: | |
267 | buf->inwork = 0; | |
268 | return ret; | |
269 | } | |
270 | ||
7102b773 GL |
271 | static void pxa_videobuf_queue(struct videobuf_queue *vq, |
272 | struct videobuf_buffer *vb) | |
3bc43840 GL |
273 | { |
274 | struct soc_camera_device *icd = vq->priv_data; | |
275 | struct soc_camera_host *ici = | |
276 | to_soc_camera_host(icd->dev.parent); | |
277 | struct pxa_camera_dev *pcdev = ici->priv; | |
278 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
7102b773 | 279 | struct pxa_buffer *active; |
3bc43840 GL |
280 | struct videobuf_dmabuf *dma = videobuf_to_dma(vb); |
281 | int nents = dma->sglen; | |
282 | unsigned long flags; | |
283 | ||
7e28adb2 | 284 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
285 | vb, vb->baddr, vb->bsize); |
286 | spin_lock_irqsave(&pcdev->lock, flags); | |
287 | ||
288 | list_add_tail(&vb->queue, &pcdev->capture); | |
289 | ||
290 | vb->state = VIDEOBUF_ACTIVE; | |
7102b773 | 291 | active = pcdev->active; |
3bc43840 | 292 | |
7102b773 | 293 | if (!active) { |
3bc43840 GL |
294 | CIFR |= CIFR_RESET_F; |
295 | DDADR(pcdev->dma_chan_y) = buf->sg_dma; | |
296 | DCSR(pcdev->dma_chan_y) = DCSR_RUN; | |
297 | pcdev->active = buf; | |
298 | CICR0 |= CICR0_ENB; | |
299 | } else { | |
300 | struct videobuf_dmabuf *active_dma = | |
301 | videobuf_to_dma(&active->vb); | |
302 | /* Stop DMA engine */ | |
303 | DCSR(pcdev->dma_chan_y) = 0; | |
304 | ||
305 | /* Add the descriptors we just initialized to the currently | |
306 | * running chain | |
307 | */ | |
308 | active->sg_cpu[active_dma->sglen - 1].ddadr = buf->sg_dma; | |
309 | ||
310 | /* Setup a dummy descriptor with the DMA engines current | |
311 | * state | |
312 | */ | |
313 | /* CIBR0 */ | |
314 | buf->sg_cpu[nents].dsadr = pcdev->res->start + 0x28; | |
315 | buf->sg_cpu[nents].dtadr = DTADR(pcdev->dma_chan_y); | |
316 | buf->sg_cpu[nents].dcmd = DCMD(pcdev->dma_chan_y); | |
317 | ||
318 | if (DDADR(pcdev->dma_chan_y) == DDADR_STOP) { | |
319 | /* The DMA engine is on the last descriptor, set the | |
320 | * next descriptors address to the descriptors | |
321 | * we just initialized | |
322 | */ | |
323 | buf->sg_cpu[nents].ddadr = buf->sg_dma; | |
324 | } else { | |
325 | buf->sg_cpu[nents].ddadr = DDADR(pcdev->dma_chan_y); | |
326 | } | |
327 | ||
328 | /* The next descriptor is the dummy descriptor */ | |
329 | DDADR(pcdev->dma_chan_y) = buf->sg_dma + nents * | |
330 | sizeof(struct pxa_dma_desc); | |
331 | ||
332 | #ifdef DEBUG | |
333 | if (CISR & CISR_IFO_0) { | |
334 | dev_warn(pcdev->dev, "FIFO overrun\n"); | |
335 | DDADR(pcdev->dma_chan_y) = pcdev->active->sg_dma; | |
336 | ||
337 | CICR0 &= ~CICR0_ENB; | |
338 | CIFR |= CIFR_RESET_F; | |
339 | DCSR(pcdev->dma_chan_y) = DCSR_RUN; | |
340 | CICR0 |= CICR0_ENB; | |
341 | } else | |
342 | #endif | |
343 | DCSR(pcdev->dma_chan_y) = DCSR_RUN; | |
344 | } | |
345 | ||
346 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
347 | ||
348 | } | |
349 | ||
350 | static void pxa_videobuf_release(struct videobuf_queue *vq, | |
351 | struct videobuf_buffer *vb) | |
352 | { | |
353 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
354 | #ifdef DEBUG | |
355 | struct soc_camera_device *icd = vq->priv_data; | |
356 | ||
7e28adb2 | 357 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
358 | vb, vb->baddr, vb->bsize); |
359 | ||
360 | switch (vb->state) { | |
361 | case VIDEOBUF_ACTIVE: | |
7e28adb2 | 362 | dev_dbg(&icd->dev, "%s (active)\n", __func__); |
3bc43840 GL |
363 | break; |
364 | case VIDEOBUF_QUEUED: | |
7e28adb2 | 365 | dev_dbg(&icd->dev, "%s (queued)\n", __func__); |
3bc43840 GL |
366 | break; |
367 | case VIDEOBUF_PREPARED: | |
7e28adb2 | 368 | dev_dbg(&icd->dev, "%s (prepared)\n", __func__); |
3bc43840 GL |
369 | break; |
370 | default: | |
7e28adb2 | 371 | dev_dbg(&icd->dev, "%s (unknown)\n", __func__); |
3bc43840 GL |
372 | break; |
373 | } | |
374 | #endif | |
375 | ||
376 | free_buffer(vq, buf); | |
377 | } | |
378 | ||
379 | static void pxa_camera_dma_irq_y(int channel, void *data) | |
380 | { | |
381 | struct pxa_camera_dev *pcdev = data; | |
382 | struct pxa_buffer *buf; | |
383 | unsigned long flags; | |
384 | unsigned int status; | |
385 | struct videobuf_buffer *vb; | |
386 | ||
387 | spin_lock_irqsave(&pcdev->lock, flags); | |
388 | ||
389 | status = DCSR(pcdev->dma_chan_y); | |
7102b773 GL |
390 | DCSR(pcdev->dma_chan_y) = status; |
391 | ||
3bc43840 | 392 | if (status & DCSR_BUSERR) { |
7102b773 | 393 | dev_err(pcdev->dev, "DMA Bus Error IRQ!\n"); |
3bc43840 GL |
394 | goto out; |
395 | } | |
396 | ||
397 | if (!(status & DCSR_ENDINTR)) { | |
7102b773 GL |
398 | dev_err(pcdev->dev, "Unknown DMA IRQ source, " |
399 | "status: 0x%08x\n", status); | |
3bc43840 GL |
400 | goto out; |
401 | } | |
402 | ||
3bc43840 | 403 | if (!pcdev->active) { |
7102b773 | 404 | dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n"); |
3bc43840 GL |
405 | goto out; |
406 | } | |
407 | ||
408 | vb = &pcdev->active->vb; | |
409 | buf = container_of(vb, struct pxa_buffer, vb); | |
410 | WARN_ON(buf->inwork || list_empty(&vb->queue)); | |
7e28adb2 | 411 | dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
412 | vb, vb->baddr, vb->bsize); |
413 | ||
7102b773 | 414 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ |
3bc43840 GL |
415 | list_del_init(&vb->queue); |
416 | vb->state = VIDEOBUF_DONE; | |
417 | do_gettimeofday(&vb->ts); | |
418 | vb->field_count++; | |
419 | wake_up(&vb->done); | |
420 | ||
421 | if (list_empty(&pcdev->capture)) { | |
422 | pcdev->active = NULL; | |
423 | DCSR(pcdev->dma_chan_y) = 0; | |
424 | CICR0 &= ~CICR0_ENB; | |
425 | goto out; | |
426 | } | |
427 | ||
428 | pcdev->active = list_entry(pcdev->capture.next, struct pxa_buffer, | |
429 | vb.queue); | |
430 | ||
431 | out: | |
432 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
433 | } | |
434 | ||
7102b773 | 435 | static struct videobuf_queue_ops pxa_videobuf_ops = { |
3bc43840 GL |
436 | .buf_setup = pxa_videobuf_setup, |
437 | .buf_prepare = pxa_videobuf_prepare, | |
438 | .buf_queue = pxa_videobuf_queue, | |
439 | .buf_release = pxa_videobuf_release, | |
440 | }; | |
441 | ||
442 | static int mclk_get_divisor(struct pxa_camera_dev *pcdev) | |
443 | { | |
444 | unsigned int mclk_10khz = pcdev->platform_mclk_10khz; | |
445 | unsigned long div; | |
446 | unsigned long lcdclk; | |
447 | ||
448 | lcdclk = clk_get_rate(pcdev->clk) / 10000; | |
449 | ||
450 | /* We verify platform_mclk_10khz != 0, so if anyone breaks it, here | |
451 | * they get a nice Oops */ | |
452 | div = (lcdclk + 2 * mclk_10khz - 1) / (2 * mclk_10khz) - 1; | |
453 | ||
454 | dev_dbg(pcdev->dev, "LCD clock %lukHz, target freq %dkHz, " | |
455 | "divisor %lu\n", lcdclk * 10, mclk_10khz * 10, div); | |
456 | ||
457 | return div; | |
458 | } | |
459 | ||
7102b773 | 460 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) |
3bc43840 GL |
461 | { |
462 | struct pxacamera_platform_data *pdata = pcdev->pdata; | |
463 | u32 cicr4 = 0; | |
464 | ||
465 | dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n", | |
466 | pcdev, pdata); | |
467 | ||
468 | if (pdata && pdata->init) { | |
7e28adb2 | 469 | dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__); |
3bc43840 GL |
470 | pdata->init(pcdev->dev); |
471 | } | |
472 | ||
473 | if (pdata && pdata->power) { | |
7e28adb2 | 474 | dev_dbg(pcdev->dev, "%s: Power on camera\n", __func__); |
3bc43840 GL |
475 | pdata->power(pcdev->dev, 1); |
476 | } | |
477 | ||
478 | if (pdata && pdata->reset) { | |
479 | dev_dbg(pcdev->dev, "%s: Releasing camera reset\n", | |
7e28adb2 | 480 | __func__); |
3bc43840 GL |
481 | pdata->reset(pcdev->dev, 1); |
482 | } | |
483 | ||
484 | CICR0 = 0x3FF; /* disable all interrupts */ | |
485 | ||
486 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
487 | cicr4 |= CICR4_PCLK_EN; | |
488 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
489 | cicr4 |= CICR4_MCLK_EN; | |
490 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
491 | cicr4 |= CICR4_PCP; | |
492 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
493 | cicr4 |= CICR4_HSP; | |
494 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
495 | cicr4 |= CICR4_VSP; | |
496 | ||
497 | CICR4 = mclk_get_divisor(pcdev) | cicr4; | |
498 | ||
499 | clk_enable(pcdev->clk); | |
500 | } | |
501 | ||
7102b773 | 502 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) |
3bc43840 GL |
503 | { |
504 | struct pxacamera_platform_data *board = pcdev->pdata; | |
505 | ||
506 | clk_disable(pcdev->clk); | |
507 | ||
508 | if (board && board->reset) { | |
509 | dev_dbg(pcdev->dev, "%s: Asserting camera reset\n", | |
7e28adb2 | 510 | __func__); |
3bc43840 GL |
511 | board->reset(pcdev->dev, 0); |
512 | } | |
513 | ||
514 | if (board && board->power) { | |
7e28adb2 | 515 | dev_dbg(pcdev->dev, "%s: Power off camera\n", __func__); |
3bc43840 GL |
516 | board->power(pcdev->dev, 0); |
517 | } | |
518 | } | |
519 | ||
520 | static irqreturn_t pxa_camera_irq(int irq, void *data) | |
521 | { | |
522 | struct pxa_camera_dev *pcdev = data; | |
523 | unsigned int status = CISR; | |
524 | ||
525 | dev_dbg(pcdev->dev, "Camera interrupt status 0x%x\n", status); | |
526 | ||
527 | CISR = status; | |
528 | ||
529 | return IRQ_HANDLED; | |
530 | } | |
531 | ||
532 | /* The following two functions absolutely depend on the fact, that | |
533 | * there can be only one camera on PXA quick capture interface */ | |
7102b773 | 534 | static int pxa_camera_add_device(struct soc_camera_device *icd) |
3bc43840 GL |
535 | { |
536 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
537 | struct pxa_camera_dev *pcdev = ici->priv; | |
538 | int ret; | |
539 | ||
540 | mutex_lock(&camera_lock); | |
541 | ||
542 | if (pcdev->icd) { | |
543 | ret = -EBUSY; | |
544 | goto ebusy; | |
545 | } | |
546 | ||
547 | dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n", | |
548 | icd->devnum); | |
549 | ||
7102b773 | 550 | pxa_camera_activate(pcdev); |
3bc43840 GL |
551 | ret = icd->ops->init(icd); |
552 | ||
553 | if (!ret) | |
554 | pcdev->icd = icd; | |
555 | ||
556 | ebusy: | |
557 | mutex_unlock(&camera_lock); | |
558 | ||
559 | return ret; | |
560 | } | |
561 | ||
7102b773 | 562 | static void pxa_camera_remove_device(struct soc_camera_device *icd) |
3bc43840 GL |
563 | { |
564 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
565 | struct pxa_camera_dev *pcdev = ici->priv; | |
566 | ||
567 | BUG_ON(icd != pcdev->icd); | |
568 | ||
569 | dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n", | |
570 | icd->devnum); | |
571 | ||
572 | /* disable capture, disable interrupts */ | |
573 | CICR0 = 0x3ff; | |
574 | /* Stop DMA engine */ | |
575 | DCSR(pcdev->dma_chan_y) = 0; | |
576 | ||
577 | icd->ops->release(icd); | |
578 | ||
7102b773 | 579 | pxa_camera_deactivate(pcdev); |
3bc43840 GL |
580 | |
581 | pcdev->icd = NULL; | |
582 | } | |
583 | ||
ad5f2e85 GL |
584 | static int test_platform_param(struct pxa_camera_dev *pcdev, |
585 | unsigned char buswidth, unsigned long *flags) | |
3bc43840 | 586 | { |
ad5f2e85 GL |
587 | /* |
588 | * Platform specified synchronization and pixel clock polarities are | |
589 | * only a recommendation and are only used during probing. The PXA270 | |
590 | * quick capture interface supports both. | |
591 | */ | |
592 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
593 | SOCAM_MASTER : SOCAM_SLAVE) | | |
594 | SOCAM_HSYNC_ACTIVE_HIGH | | |
595 | SOCAM_HSYNC_ACTIVE_LOW | | |
596 | SOCAM_VSYNC_ACTIVE_HIGH | | |
597 | SOCAM_VSYNC_ACTIVE_LOW | | |
598 | SOCAM_PCLK_SAMPLE_RISING | | |
599 | SOCAM_PCLK_SAMPLE_FALLING; | |
3bc43840 GL |
600 | |
601 | /* If requested data width is supported by the platform, use it */ | |
ad5f2e85 | 602 | switch (buswidth) { |
3bc43840 | 603 | case 10: |
ad5f2e85 GL |
604 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)) |
605 | return -EINVAL; | |
606 | *flags |= SOCAM_DATAWIDTH_10; | |
3bc43840 GL |
607 | break; |
608 | case 9: | |
ad5f2e85 GL |
609 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)) |
610 | return -EINVAL; | |
611 | *flags |= SOCAM_DATAWIDTH_9; | |
3bc43840 GL |
612 | break; |
613 | case 8: | |
ad5f2e85 GL |
614 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)) |
615 | return -EINVAL; | |
616 | *flags |= SOCAM_DATAWIDTH_8; | |
3bc43840 | 617 | } |
ad5f2e85 GL |
618 | |
619 | return 0; | |
620 | } | |
621 | ||
622 | static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) | |
623 | { | |
624 | struct soc_camera_host *ici = | |
625 | to_soc_camera_host(icd->dev.parent); | |
626 | struct pxa_camera_dev *pcdev = ici->priv; | |
627 | unsigned long dw, bpp, bus_flags, camera_flags, common_flags; | |
628 | u32 cicr0, cicr4 = 0; | |
629 | int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags); | |
630 | ||
631 | if (ret < 0) | |
632 | return ret; | |
633 | ||
634 | camera_flags = icd->ops->query_bus_param(icd); | |
635 | ||
636 | common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags); | |
637 | if (!common_flags) | |
3bc43840 GL |
638 | return -EINVAL; |
639 | ||
ad5f2e85 GL |
640 | /* Make choises, based on platform preferences */ |
641 | if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && | |
642 | (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { | |
643 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
644 | common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; | |
645 | else | |
646 | common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; | |
647 | } | |
648 | ||
649 | if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) && | |
650 | (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) { | |
651 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
652 | common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH; | |
653 | else | |
654 | common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW; | |
655 | } | |
656 | ||
657 | if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && | |
658 | (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { | |
659 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
660 | common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; | |
661 | else | |
662 | common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; | |
663 | } | |
664 | ||
665 | ret = icd->ops->set_bus_param(icd, common_flags); | |
3bc43840 GL |
666 | if (ret < 0) |
667 | return ret; | |
668 | ||
669 | /* Datawidth is now guaranteed to be equal to one of the three values. | |
670 | * We fix bit-per-pixel equal to data-width... */ | |
ad5f2e85 GL |
671 | switch (common_flags & SOCAM_DATAWIDTH_MASK) { |
672 | case SOCAM_DATAWIDTH_10: | |
673 | icd->buswidth = 10; | |
3bc43840 GL |
674 | dw = 4; |
675 | bpp = 0x40; | |
676 | break; | |
ad5f2e85 GL |
677 | case SOCAM_DATAWIDTH_9: |
678 | icd->buswidth = 9; | |
3bc43840 GL |
679 | dw = 3; |
680 | bpp = 0x20; | |
681 | break; | |
682 | default: | |
683 | /* Actually it can only be 8 now, | |
684 | * default is just to silence compiler warnings */ | |
ad5f2e85 GL |
685 | case SOCAM_DATAWIDTH_8: |
686 | icd->buswidth = 8; | |
3bc43840 GL |
687 | dw = 2; |
688 | bpp = 0; | |
689 | } | |
690 | ||
691 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
692 | cicr4 |= CICR4_PCLK_EN; | |
693 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
694 | cicr4 |= CICR4_MCLK_EN; | |
ad5f2e85 | 695 | if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) |
3bc43840 | 696 | cicr4 |= CICR4_PCP; |
ad5f2e85 | 697 | if (common_flags & SOCAM_HSYNC_ACTIVE_LOW) |
3bc43840 | 698 | cicr4 |= CICR4_HSP; |
ad5f2e85 | 699 | if (common_flags & SOCAM_VSYNC_ACTIVE_LOW) |
3bc43840 GL |
700 | cicr4 |= CICR4_VSP; |
701 | ||
702 | cicr0 = CICR0; | |
703 | if (cicr0 & CICR0_ENB) | |
704 | CICR0 = cicr0 & ~CICR0_ENB; | |
ad5f2e85 | 705 | CICR1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw; |
3bc43840 | 706 | CICR2 = 0; |
ad5f2e85 | 707 | CICR3 = CICR3_LPF_VAL(icd->height - 1) | |
3bc43840 GL |
708 | CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top)); |
709 | CICR4 = mclk_get_divisor(pcdev) | cicr4; | |
710 | ||
711 | /* CIF interrupts are not used, only DMA */ | |
712 | CICR0 = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
7102b773 | 713 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)) | |
3bc43840 GL |
714 | CICR0_DMAEN | CICR0_IRQ_MASK | (cicr0 & CICR0_ENB); |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
ad5f2e85 GL |
719 | static int pxa_camera_try_bus_param(struct soc_camera_device *icd, __u32 pixfmt) |
720 | { | |
721 | struct soc_camera_host *ici = | |
722 | to_soc_camera_host(icd->dev.parent); | |
723 | struct pxa_camera_dev *pcdev = ici->priv; | |
724 | unsigned long bus_flags, camera_flags; | |
725 | int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags); | |
726 | ||
727 | if (ret < 0) | |
728 | return ret; | |
729 | ||
730 | camera_flags = icd->ops->query_bus_param(icd); | |
731 | ||
732 | return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL; | |
733 | } | |
734 | ||
735 | static int pxa_camera_set_fmt_cap(struct soc_camera_device *icd, | |
736 | __u32 pixfmt, struct v4l2_rect *rect) | |
737 | { | |
738 | return icd->ops->set_fmt_cap(icd, pixfmt, rect); | |
739 | } | |
740 | ||
741 | static int pxa_camera_try_fmt_cap(struct soc_camera_device *icd, | |
7102b773 | 742 | struct v4l2_format *f) |
3bc43840 GL |
743 | { |
744 | /* limit to pxa hardware capabilities */ | |
745 | if (f->fmt.pix.height < 32) | |
746 | f->fmt.pix.height = 32; | |
747 | if (f->fmt.pix.height > 2048) | |
748 | f->fmt.pix.height = 2048; | |
749 | if (f->fmt.pix.width < 48) | |
750 | f->fmt.pix.width = 48; | |
751 | if (f->fmt.pix.width > 2048) | |
752 | f->fmt.pix.width = 2048; | |
753 | f->fmt.pix.width &= ~0x01; | |
754 | ||
ad5f2e85 GL |
755 | /* limit to sensor capabilities */ |
756 | return icd->ops->try_fmt_cap(icd, f); | |
3bc43840 GL |
757 | } |
758 | ||
7102b773 GL |
759 | static int pxa_camera_reqbufs(struct soc_camera_file *icf, |
760 | struct v4l2_requestbuffers *p) | |
3bc43840 GL |
761 | { |
762 | int i; | |
763 | ||
764 | /* This is for locking debugging only. I removed spinlocks and now I | |
765 | * check whether .prepare is ever called on a linked buffer, or whether | |
766 | * a dma IRQ can occur for an in-work or unlinked buffer. Until now | |
767 | * it hadn't triggered */ | |
768 | for (i = 0; i < p->count; i++) { | |
769 | struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i], | |
770 | struct pxa_buffer, vb); | |
771 | buf->inwork = 0; | |
772 | INIT_LIST_HEAD(&buf->vb.queue); | |
773 | } | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
7102b773 | 778 | static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) |
3bc43840 GL |
779 | { |
780 | struct soc_camera_file *icf = file->private_data; | |
781 | struct pxa_buffer *buf; | |
782 | ||
783 | buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer, | |
784 | vb.stream); | |
785 | ||
786 | poll_wait(file, &buf->vb.done, pt); | |
787 | ||
788 | if (buf->vb.state == VIDEOBUF_DONE || | |
789 | buf->vb.state == VIDEOBUF_ERROR) | |
790 | return POLLIN|POLLRDNORM; | |
791 | ||
792 | return 0; | |
793 | } | |
794 | ||
7102b773 GL |
795 | static int pxa_camera_querycap(struct soc_camera_host *ici, |
796 | struct v4l2_capability *cap) | |
3bc43840 GL |
797 | { |
798 | /* cap->name is set by the firendly caller:-> */ | |
799 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); | |
800 | cap->version = PXA_CAM_VERSION_CODE; | |
801 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; | |
802 | ||
803 | return 0; | |
804 | } | |
805 | ||
1a0063a9 GL |
806 | static spinlock_t *pxa_camera_spinlock_alloc(struct soc_camera_file *icf) |
807 | { | |
808 | struct soc_camera_host *ici = | |
809 | to_soc_camera_host(icf->icd->dev.parent); | |
810 | struct pxa_camera_dev *pcdev = ici->priv; | |
811 | ||
812 | return &pcdev->lock; | |
813 | } | |
814 | ||
b8d9904c GL |
815 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { |
816 | .owner = THIS_MODULE, | |
817 | .add = pxa_camera_add_device, | |
818 | .remove = pxa_camera_remove_device, | |
819 | .set_fmt_cap = pxa_camera_set_fmt_cap, | |
820 | .try_fmt_cap = pxa_camera_try_fmt_cap, | |
821 | .reqbufs = pxa_camera_reqbufs, | |
822 | .poll = pxa_camera_poll, | |
823 | .querycap = pxa_camera_querycap, | |
824 | .try_bus_param = pxa_camera_try_bus_param, | |
825 | .set_bus_param = pxa_camera_set_bus_param, | |
1a0063a9 | 826 | .spinlock_alloc = pxa_camera_spinlock_alloc, |
b8d9904c GL |
827 | }; |
828 | ||
829 | /* Should be allocated dynamically too, but we have only one. */ | |
3bc43840 GL |
830 | static struct soc_camera_host pxa_soc_camera_host = { |
831 | .drv_name = PXA_CAM_DRV_NAME, | |
7102b773 | 832 | .vbq_ops = &pxa_videobuf_ops, |
3bc43840 | 833 | .msize = sizeof(struct pxa_buffer), |
b8d9904c | 834 | .ops = &pxa_soc_camera_host_ops, |
3bc43840 GL |
835 | }; |
836 | ||
837 | static int pxa_camera_probe(struct platform_device *pdev) | |
838 | { | |
839 | struct pxa_camera_dev *pcdev; | |
840 | struct resource *res; | |
841 | void __iomem *base; | |
842 | unsigned int irq; | |
843 | int err = 0; | |
844 | ||
845 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
846 | irq = platform_get_irq(pdev, 0); | |
847 | if (!res || !irq) { | |
848 | err = -ENODEV; | |
849 | goto exit; | |
850 | } | |
851 | ||
852 | pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); | |
853 | if (!pcdev) { | |
7102b773 | 854 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); |
3bc43840 GL |
855 | err = -ENOMEM; |
856 | goto exit; | |
857 | } | |
858 | ||
859 | pcdev->clk = clk_get(&pdev->dev, "CAMCLK"); | |
860 | if (IS_ERR(pcdev->clk)) { | |
861 | err = PTR_ERR(pcdev->clk); | |
862 | goto exit_kfree; | |
863 | } | |
864 | ||
865 | dev_set_drvdata(&pdev->dev, pcdev); | |
866 | pcdev->res = res; | |
867 | ||
868 | pcdev->pdata = pdev->dev.platform_data; | |
869 | pcdev->platform_flags = pcdev->pdata->flags; | |
ad5f2e85 GL |
870 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | |
871 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | |
3bc43840 GL |
872 | /* Platform hasn't set available data widths. This is bad. |
873 | * Warn and use a default. */ | |
874 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " | |
875 | "data widths, using default 10 bit\n"); | |
876 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
877 | } | |
878 | pcdev->platform_mclk_10khz = pcdev->pdata->mclk_10khz; | |
879 | if (!pcdev->platform_mclk_10khz) { | |
880 | dev_warn(&pdev->dev, | |
881 | "mclk_10khz == 0! Please, fix your platform data. " | |
882 | "Using default 20MHz\n"); | |
883 | pcdev->platform_mclk_10khz = 2000; | |
884 | } | |
885 | ||
886 | INIT_LIST_HEAD(&pcdev->capture); | |
887 | spin_lock_init(&pcdev->lock); | |
888 | ||
889 | /* | |
890 | * Request the regions. | |
891 | */ | |
892 | if (!request_mem_region(res->start, res->end - res->start + 1, | |
893 | PXA_CAM_DRV_NAME)) { | |
894 | err = -EBUSY; | |
895 | goto exit_clk; | |
896 | } | |
897 | ||
898 | base = ioremap(res->start, res->end - res->start + 1); | |
899 | if (!base) { | |
900 | err = -ENOMEM; | |
901 | goto exit_release; | |
902 | } | |
903 | pcdev->irq = irq; | |
904 | pcdev->base = base; | |
905 | pcdev->dev = &pdev->dev; | |
906 | ||
907 | /* request dma */ | |
908 | pcdev->dma_chan_y = pxa_request_dma("CI_Y", DMA_PRIO_HIGH, | |
909 | pxa_camera_dma_irq_y, pcdev); | |
910 | if (pcdev->dma_chan_y < 0) { | |
911 | dev_err(pcdev->dev, "Can't request DMA for Y\n"); | |
912 | err = -ENOMEM; | |
913 | goto exit_iounmap; | |
914 | } | |
915 | dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chan_y); | |
916 | ||
917 | DRCMR68 = pcdev->dma_chan_y | DRCMR_MAPVLD; | |
918 | ||
919 | /* request irq */ | |
920 | err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME, | |
921 | pcdev); | |
922 | if (err) { | |
923 | dev_err(pcdev->dev, "Camera interrupt register failed \n"); | |
924 | goto exit_free_dma; | |
925 | } | |
926 | ||
927 | pxa_soc_camera_host.priv = pcdev; | |
928 | pxa_soc_camera_host.dev.parent = &pdev->dev; | |
929 | pxa_soc_camera_host.nr = pdev->id; | |
b8d9904c | 930 | err = soc_camera_host_register(&pxa_soc_camera_host); |
3bc43840 GL |
931 | if (err) |
932 | goto exit_free_irq; | |
933 | ||
934 | return 0; | |
935 | ||
936 | exit_free_irq: | |
937 | free_irq(pcdev->irq, pcdev); | |
938 | exit_free_dma: | |
939 | pxa_free_dma(pcdev->dma_chan_y); | |
940 | exit_iounmap: | |
941 | iounmap(base); | |
942 | exit_release: | |
943 | release_mem_region(res->start, res->end - res->start + 1); | |
944 | exit_clk: | |
945 | clk_put(pcdev->clk); | |
946 | exit_kfree: | |
947 | kfree(pcdev); | |
948 | exit: | |
949 | return err; | |
950 | } | |
951 | ||
952 | static int __devexit pxa_camera_remove(struct platform_device *pdev) | |
953 | { | |
954 | struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev); | |
955 | struct resource *res; | |
956 | ||
957 | clk_put(pcdev->clk); | |
958 | ||
959 | pxa_free_dma(pcdev->dma_chan_y); | |
960 | free_irq(pcdev->irq, pcdev); | |
961 | ||
962 | soc_camera_host_unregister(&pxa_soc_camera_host); | |
963 | ||
964 | iounmap(pcdev->base); | |
965 | ||
966 | res = pcdev->res; | |
967 | release_mem_region(res->start, res->end - res->start + 1); | |
968 | ||
969 | kfree(pcdev); | |
970 | ||
7102b773 | 971 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); |
3bc43840 | 972 | |
3bc43840 GL |
973 | return 0; |
974 | } | |
975 | ||
3bc43840 GL |
976 | static struct platform_driver pxa_camera_driver = { |
977 | .driver = { | |
978 | .name = PXA_CAM_DRV_NAME, | |
979 | }, | |
980 | .probe = pxa_camera_probe, | |
981 | .remove = __exit_p(pxa_camera_remove), | |
3bc43840 GL |
982 | }; |
983 | ||
984 | ||
985 | static int __devinit pxa_camera_init(void) | |
986 | { | |
987 | return platform_driver_register(&pxa_camera_driver); | |
988 | } | |
989 | ||
990 | static void __exit pxa_camera_exit(void) | |
991 | { | |
992 | return platform_driver_unregister(&pxa_camera_driver); | |
993 | } | |
994 | ||
995 | module_init(pxa_camera_init); | |
996 | module_exit(pxa_camera_exit); | |
997 | ||
998 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | |
999 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
1000 | MODULE_LICENSE("GPL"); |