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V4L/DVB (4030): Minor code cleanup on the genpix-module
[deliverable/linux.git] / drivers / media / video / saa7134 / saa7134-dvb.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 *
3 * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
4 *
86ddd96f
MCC		 5 * Extended 3 / 2005 by Hartmut Hackmann to support various
6 * cards with the tda10046 DVB-T channel decoder
7 *
1da177e4
LT		 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/init.h>
24#include <linux/list.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/delay.h>
29#include <linux/kthread.h>
30#include <linux/suspend.h>
31
32#include "saa7134-reg.h"
33#include "saa7134.h"
5e453dc7 34#include <media/v4l2-common.h>
a78d0bfa 35#include "dvb-pll.h"
1da177e4 36
29780bb7 37#ifdef HAVE_MT352
86ddd96f
MCC		 38# include "mt352.h"
39# include "mt352_priv.h" /* FIXME */
40#endif
29780bb7 41#ifdef HAVE_TDA1004X
86ddd96f
MCC		 42# include "tda1004x.h"
43#endif
3b64e8e2
MK		 44#ifdef HAVE_NXT200X
45# include "nxt200x.h"
3b64e8e2 46#endif
1da177e4
LT		 47
48MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
49MODULE_LICENSE("GPL");
50
51static unsigned int antenna_pwr = 0;
86ddd96f 52
1da177e4
LT		 53module_param(antenna_pwr, int, 0444);
54MODULE_PARM_DESC(antenna_pwr,"enable antenna power (Pinnacle 300i)");
55
56/* ------------------------------------------------------------------ */
57
29780bb7 58#ifdef HAVE_MT352
1da177e4
LT		 59static int pinnacle_antenna_pwr(struct saa7134_dev *dev, int on)
60{
61 u32 ok;
62
63 if (!on) {
64 saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26));
65 saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26));
66 return 0;
67 }
68
69 saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26));
70 saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26));
71 udelay(10);
72
73 saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 28));
74 saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28));
75 udelay(10);
76 saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28));
77 udelay(10);
78 ok = saa_readl(SAA7134_GPIO_GPSTATUS0) & (1 << 27);
79 printk("%s: %s %s\n", dev->name, __FUNCTION__,
80 ok ? "on" : "off");
81
82 if (!ok)
83 saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26));
84 return ok;
85}
86
87static int mt352_pinnacle_init(struct dvb_frontend* fe)
88{
89 static u8 clock_config [] = { CLOCK_CTL, 0x3d, 0x28 };
90 static u8 reset [] = { RESET, 0x80 };
91 static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
92 static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 };
93 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x31 };
94 static u8 fsm_ctl_cfg[] = { 0x7b, 0x04 };
95 static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x0f };
96 static u8 scan_ctl_cfg [] = { SCAN_CTL, 0x0d };
97 static u8 irq_cfg [] = { INTERRUPT_EN_0, 0x00, 0x00, 0x00, 0x00 };
98 struct saa7134_dev *dev= fe->dvb->priv;
99
100 printk("%s: %s called\n",dev->name,__FUNCTION__);
101
102 mt352_write(fe, clock_config, sizeof(clock_config));
103 udelay(200);
104 mt352_write(fe, reset, sizeof(reset));
105 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
106 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
107 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
108 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
109
110 mt352_write(fe, fsm_ctl_cfg, sizeof(fsm_ctl_cfg));
111 mt352_write(fe, scan_ctl_cfg, sizeof(scan_ctl_cfg));
112 mt352_write(fe, irq_cfg, sizeof(irq_cfg));
df8cf706 113
1da177e4
LT		 114 return 0;
115}
116
a78d0bfa
JAR		 117static int mt352_aver777_init(struct dvb_frontend* fe)
118{
119 static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x2d };
120 static u8 reset [] = { RESET, 0x80 };
121 static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
122 static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 };
123 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x33 };
124
125 mt352_write(fe, clock_config, sizeof(clock_config));
126 udelay(200);
127 mt352_write(fe, reset, sizeof(reset));
128 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
129 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
130 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
131
132 return 0;
133}
134
bd4956b8 135static int mt352_pinnacle_tuner_calc_regs(struct dvb_frontend* fe,
a79ddae9
AQ		 136 struct dvb_frontend_parameters* params,
137 u8* pllbuf, int buf_len)
1da177e4 138{
df8cf706
HH		 139 u8 off[] = { 0x00, 0xf1};
140 u8 on[] = { 0x00, 0x71};
141 struct i2c_msg msg = {.addr=0x43, .flags=0, .buf=off, .len = sizeof(off)};
142
1da177e4
LT		 143 struct saa7134_dev *dev = fe->dvb->priv;
144 struct v4l2_frequency f;
145
a79ddae9
AQ		 146 if (buf_len < 5)
147 return -EINVAL;
148
1da177e4
LT		 149 /* set frequency (mt2050) */
150 f.tuner = 0;
151 f.type = V4L2_TUNER_DIGITAL_TV;
152 f.frequency = params->frequency / 1000 * 16 / 1000;
a9686e0d
AQ		 153 if (fe->ops->i2c_gate_ctrl)
154 fe->ops->i2c_gate_ctrl(fe, 1);
df8cf706 155 i2c_transfer(&dev->i2c_adap, &msg, 1);
1da177e4 156 saa7134_i2c_call_clients(dev,VIDIOC_S_FREQUENCY,&f);
df8cf706 157 msg.buf = on;
a9686e0d
AQ		 158 if (fe->ops->i2c_gate_ctrl)
159 fe->ops->i2c_gate_ctrl(fe, 1);
df8cf706 160 i2c_transfer(&dev->i2c_adap, &msg, 1);
1da177e4
LT		 161
162 pinnacle_antenna_pwr(dev, antenna_pwr);
163
164 /* mt352 setup */
165 mt352_pinnacle_init(fe);
a79ddae9 166 pllbuf[0] = 0x61;
1da177e4
LT		 167 pllbuf[1] = 0x00;
168 pllbuf[2] = 0x00;
169 pllbuf[3] = 0x80;
170 pllbuf[4] = 0x00;
a79ddae9 171 return 5;
1da177e4
LT		 172}
173
bd4956b8 174static int mt352_aver777_tuner_calc_regs(struct dvb_frontend *fe, struct dvb_frontend_parameters *params, u8* pllbuf, int buf_len)
a78d0bfa 175{
a79ddae9
AQ		 176 if (buf_len < 5)
177 return -EINVAL;
178
179 pllbuf[0] = 0x61;
a78d0bfa
JAR		 180 dvb_pll_configure(&dvb_pll_philips_td1316, pllbuf+1,
181 params->frequency,
182 params->u.ofdm.bandwidth);
a79ddae9 183 return 5;
a78d0bfa
JAR		 184}
185
1da177e4
LT		 186static struct mt352_config pinnacle_300i = {
187 .demod_address = 0x3c >> 1,
188 .adc_clock = 20333,
189 .if2 = 36150,
190 .no_tuner = 1,
191 .demod_init = mt352_pinnacle_init,
1da177e4 192};
a78d0bfa
JAR		 193
194static struct mt352_config avermedia_777 = {
195 .demod_address = 0xf,
196 .demod_init = mt352_aver777_init,
a78d0bfa 197};
86ddd96f 198#endif
1da177e4
LT		 199
200/* ------------------------------------------------------------------ */
201
29780bb7 202#ifdef HAVE_TDA1004X
1da177e4 203
2cf36ac4 204static int philips_tda6651_pll_set(u8 addr, struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
1da177e4
LT		 205{
206 struct saa7134_dev *dev = fe->dvb->priv;
86ddd96f 207 u8 tuner_buf[4];
2cf36ac4 208 struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tuner_buf,.len =
86ddd96f
MCC		 209 sizeof(tuner_buf) };
210 int tuner_frequency = 0;
211 u8 band, cp, filter;
212
213 /* determine charge pump */
214 tuner_frequency = params->frequency + 36166000;
215 if (tuner_frequency < 87000000)
216 return -EINVAL;
217 else if (tuner_frequency < 130000000)
218 cp = 3;
219 else if (tuner_frequency < 160000000)
220 cp = 5;
221 else if (tuner_frequency < 200000000)
222 cp = 6;
223 else if (tuner_frequency < 290000000)
224 cp = 3;
225 else if (tuner_frequency < 420000000)
226 cp = 5;
227 else if (tuner_frequency < 480000000)
228 cp = 6;
229 else if (tuner_frequency < 620000000)
230 cp = 3;
231 else if (tuner_frequency < 830000000)
232 cp = 5;
233 else if (tuner_frequency < 895000000)
234 cp = 7;
235 else
236 return -EINVAL;
237
238 /* determine band */
239 if (params->frequency < 49000000)
240 return -EINVAL;
241 else if (params->frequency < 161000000)
242 band = 1;
243 else if (params->frequency < 444000000)
244 band = 2;
245 else if (params->frequency < 861000000)
246 band = 4;
247 else
248 return -EINVAL;
249
250 /* setup PLL filter */
251 switch (params->u.ofdm.bandwidth) {
252 case BANDWIDTH_6_MHZ:
253 filter = 0;
254 break;
255
256 case BANDWIDTH_7_MHZ:
257 filter = 0;
258 break;
259
260 case BANDWIDTH_8_MHZ:
261 filter = 1;
262 break;
1da177e4 263
86ddd96f
MCC		 264 default:
265 return -EINVAL;
266 }
267
268 /* calculate divisor
269 * ((36166000+((1000000/6)/2)) + Finput)/(1000000/6)
1da177e4 270 */
86ddd96f
MCC		 271 tuner_frequency = (((params->frequency / 1000) * 6) + 217496) / 1000;
272
273 /* setup tuner buffer */
274 tuner_buf[0] = (tuner_frequency >> 8) & 0x7f;
275 tuner_buf[1] = tuner_frequency & 0xff;
276 tuner_buf[2] = 0xca;
277 tuner_buf[3] = (cp << 5) | (filter << 3) | band;
278
a79ddae9
AQ		 279 if (fe->ops->i2c_gate_ctrl)
280 fe->ops->i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 281 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
282 return -EIO;
2cf36ac4
HH		 283 msleep(1);
284 return 0;
285}
286
287static int philips_tda6651_pll_init(u8 addr, struct dvb_frontend *fe)
288{
289 struct saa7134_dev *dev = fe->dvb->priv;
290 static u8 tu1216_init[] = { 0x0b, 0xf5, 0x85, 0xab };
291 struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tu1216_init,.len = sizeof(tu1216_init) };
86ddd96f 292
2cf36ac4 293 /* setup PLL configuration */
a79ddae9
AQ		 294 if (fe->ops->i2c_gate_ctrl)
295 fe->ops->i2c_gate_ctrl(fe, 1);
2cf36ac4
HH		 296 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
297 return -EIO;
86ddd96f 298 msleep(1);
2cf36ac4 299
1da177e4
LT		 300 return 0;
301}
302
2cf36ac4
HH		 303/* ------------------------------------------------------------------ */
304
a79ddae9 305static int philips_tu1216_tuner_60_init(struct dvb_frontend *fe)
2cf36ac4
HH		 306{
307 return philips_tda6651_pll_init(0x60, fe);
308}
309
a79ddae9 310static int philips_tu1216_tuner_60_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
2cf36ac4
HH		 311{
312 return philips_tda6651_pll_set(0x60, fe, params);
313}
314
86ddd96f
MCC		 315static int philips_tu1216_request_firmware(struct dvb_frontend *fe,
316 const struct firmware **fw, char *name)
1da177e4
LT		 317{
318 struct saa7134_dev *dev = fe->dvb->priv;
319 return request_firmware(fw, name, &dev->pci->dev);
320}
321
2cf36ac4 322static struct tda1004x_config philips_tu1216_60_config = {
86ddd96f
MCC		 323
324 .demod_address = 0x8,
325 .invert = 1,
2cf36ac4 326 .invert_oclk = 0,
86ddd96f
MCC		 327 .xtal_freq = TDA10046_XTAL_4M,
328 .agc_config = TDA10046_AGC_DEFAULT,
329 .if_freq = TDA10046_FREQ_3617,
86ddd96f
MCC		 330 .request_firmware = philips_tu1216_request_firmware,
331};
332
333/* ------------------------------------------------------------------ */
334
a79ddae9 335static int philips_tu1216_tuner_61_init(struct dvb_frontend *fe)
2cf36ac4
HH		 336{
337 return philips_tda6651_pll_init(0x61, fe);
338}
339
a79ddae9 340static int philips_tu1216_tuner_61_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
2cf36ac4
HH		 341{
342 return philips_tda6651_pll_set(0x61, fe, params);
343}
344
345static struct tda1004x_config philips_tu1216_61_config = {
346
347 .demod_address = 0x8,
348 .invert = 1,
349 .invert_oclk = 0,
350 .xtal_freq = TDA10046_XTAL_4M,
351 .agc_config = TDA10046_AGC_DEFAULT,
352 .if_freq = TDA10046_FREQ_3617,
2cf36ac4
HH		 353 .request_firmware = philips_tu1216_request_firmware,
354};
355
356/* ------------------------------------------------------------------ */
357
a79ddae9 358static int philips_europa_tuner_init(struct dvb_frontend *fe)
2cf36ac4
HH		 359{
360 struct saa7134_dev *dev = fe->dvb->priv;
361 static u8 msg[] = { 0x0b, 0xf5, 0x86, 0xab };
362 struct i2c_msg init_msg = {.addr = 0x61,.flags = 0,.buf = msg,.len = sizeof(msg) };
363
364 /* setup PLL configuration */
a79ddae9
AQ		 365 if (fe->ops->i2c_gate_ctrl)
366 fe->ops->i2c_gate_ctrl(fe, 1);
2cf36ac4
HH		 367 if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1)
368 return -EIO;
369 msleep(1);
370
371 /* switch the board to dvb mode */
372 init_msg.addr = 0x43;
373 init_msg.len = 0x02;
374 msg[0] = 0x00;
375 msg[1] = 0x40;
a79ddae9
AQ		 376 if (fe->ops->i2c_gate_ctrl)
377 fe->ops->i2c_gate_ctrl(fe, 1);
2cf36ac4
HH		 378 if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1)
379 return -EIO;
380
381 return 0;
382}
383
a79ddae9 384static int philips_td1316_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
2cf36ac4
HH		 385{
386 return philips_tda6651_pll_set(0x61, fe, params);
387}
388
a79ddae9 389static int philips_europa_tuner_sleep(struct dvb_frontend *fe)
2cf36ac4
HH		 390{
391 struct saa7134_dev *dev = fe->dvb->priv;
392 /* this message actually turns the tuner back to analog mode */
393 static u8 msg[] = { 0x0b, 0xdc, 0x86, 0xa4 };
394 struct i2c_msg analog_msg = {.addr = 0x61,.flags = 0,.buf = msg,.len = sizeof(msg) };
395
396 i2c_transfer(&dev->i2c_adap, &analog_msg, 1);
397 msleep(1);
398
399 /* switch the board to analog mode */
400 analog_msg.addr = 0x43;
401 analog_msg.len = 0x02;
402 msg[0] = 0x00;
403 msg[1] = 0x14;
a79ddae9
AQ		 404 if (fe->ops->i2c_gate_ctrl)
405 fe->ops->i2c_gate_ctrl(fe, 1);
2cf36ac4 406 i2c_transfer(&dev->i2c_adap, &analog_msg, 1);
a79ddae9
AQ		 407 return 0;
408}
409
410static int philips_europa_demod_sleep(struct dvb_frontend *fe)
411{
412 struct saa7134_dev *dev = fe->dvb->priv;
413
414 if (dev->original_demod_sleep)
415 dev->original_demod_sleep(fe);
416 fe->ops->i2c_gate_ctrl(fe, 1);
417 return 0;
2cf36ac4
HH		 418}
419
420static struct tda1004x_config philips_europa_config = {
421
422 .demod_address = 0x8,
423 .invert = 0,
424 .invert_oclk = 0,
425 .xtal_freq = TDA10046_XTAL_4M,
426 .agc_config = TDA10046_AGC_IFO_AUTO_POS,
427 .if_freq = TDA10046_FREQ_052,
2cf36ac4
HH		 428 .request_firmware = NULL,
429};
430
431/* ------------------------------------------------------------------ */
86ddd96f 432
a79ddae9 433static int philips_fmd1216_tuner_init(struct dvb_frontend *fe)
86ddd96f
MCC		 434{
435 struct saa7134_dev *dev = fe->dvb->priv;
436 /* this message is to set up ATC and ALC */
437 static u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0xa0 };
438 struct i2c_msg tuner_msg = {.addr = 0x61,.flags = 0,.buf = fmd1216_init,.len = sizeof(fmd1216_init) };
439
a79ddae9
AQ		 440 if (fe->ops->i2c_gate_ctrl)
441 fe->ops->i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 442 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
443 return -EIO;
444 msleep(1);
445
446 return 0;
447}
448
a79ddae9 449static int philips_fmd1216_tuner_sleep(struct dvb_frontend *fe)
86ddd96f
MCC		 450{
451 struct saa7134_dev *dev = fe->dvb->priv;
452 /* this message actually turns the tuner back to analog mode */
453 static u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0x60 };
454 struct i2c_msg tuner_msg = {.addr = 0x61,.flags = 0,.buf = fmd1216_init,.len = sizeof(fmd1216_init) };
455
a79ddae9
AQ		 456 if (fe->ops->i2c_gate_ctrl)
457 fe->ops->i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 458 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
459 msleep(1);
460 fmd1216_init[2] = 0x86;
461 fmd1216_init[3] = 0x54;
a79ddae9
AQ		 462 if (fe->ops->i2c_gate_ctrl)
463 fe->ops->i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 464 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
465 msleep(1);
a79ddae9 466 return 0;
86ddd96f
MCC		 467}
468
a79ddae9 469static int philips_fmd1216_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
86ddd96f
MCC		 470{
471 struct saa7134_dev *dev = fe->dvb->priv;
472 u8 tuner_buf[4];
473 struct i2c_msg tuner_msg = {.addr = 0x61,.flags = 0,.buf = tuner_buf,.len =
474 sizeof(tuner_buf) };
475 int tuner_frequency = 0;
476 int divider = 0;
477 u8 band, mode, cp;
478
479 /* determine charge pump */
480 tuner_frequency = params->frequency + 36130000;
481 if (tuner_frequency < 87000000)
482 return -EINVAL;
483 /* low band */
484 else if (tuner_frequency < 180000000) {
485 band = 1;
486 mode = 7;
487 cp = 0;
488 } else if (tuner_frequency < 195000000) {
489 band = 1;
490 mode = 6;
491 cp = 1;
492 /* mid band */
493 } else if (tuner_frequency < 366000000) {
494 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
495 band = 10;
496 } else {
497 band = 2;
498 }
499 mode = 7;
500 cp = 0;
501 } else if (tuner_frequency < 478000000) {
502 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
503 band = 10;
504 } else {
505 band = 2;
506 }
507 mode = 6;
508 cp = 1;
509 /* high band */
510 } else if (tuner_frequency < 662000000) {
511 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
512 band = 12;
513 } else {
514 band = 4;
515 }
516 mode = 7;
517 cp = 0;
518 } else if (tuner_frequency < 840000000) {
519 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
520 band = 12;
521 } else {
522 band = 4;
523 }
524 mode = 6;
525 cp = 1;
526 } else {
527 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
528 band = 12;
529 } else {
530 band = 4;
531 }
532 mode = 7;
533 cp = 1;
534
535 }
536 /* calculate divisor */
537 /* ((36166000 + Finput) / 166666) rounded! */
538 divider = (tuner_frequency + 83333) / 166667;
539
540 /* setup tuner buffer */
541 tuner_buf[0] = (divider >> 8) & 0x7f;
542 tuner_buf[1] = divider & 0xff;
543 tuner_buf[2] = 0x80 | (cp << 6) | (mode << 3) | 4;
544 tuner_buf[3] = 0x40 | band;
545
a79ddae9
AQ		 546 if (fe->ops->i2c_gate_ctrl)
547 fe->ops->i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 548 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
549 return -EIO;
550 return 0;
551}
552
408b664a 553static struct tda1004x_config medion_cardbus = {
86ddd96f
MCC		 554 .demod_address = 0x08,
555 .invert = 1,
556 .invert_oclk = 0,
557 .xtal_freq = TDA10046_XTAL_16M,
558 .agc_config = TDA10046_AGC_IFO_AUTO_NEG,
559 .if_freq = TDA10046_FREQ_3613,
86ddd96f
MCC		 560 .request_firmware = NULL,
561};
562
563/* ------------------------------------------------------------------ */
564
565struct tda827x_data {
566 u32 lomax;
567 u8 spd;
568 u8 bs;
569 u8 bp;
570 u8 cp;
571 u8 gc3;
572 u8 div1p5;
573};
574
575static struct tda827x_data tda827x_dvbt[] = {
576 { .lomax = 62000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1},
577 { .lomax = 66000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1},
578 { .lomax = 76000000, .spd = 3, .bs = 1, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0},
579 { .lomax = 84000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0},
580 { .lomax = 93000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0},
581 { .lomax = 98000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0},
582 { .lomax = 109000000, .spd = 3, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
583 { .lomax = 123000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1},
584 { .lomax = 133000000, .spd = 2, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1},
585 { .lomax = 151000000, .spd = 2, .bs = 1, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
586 { .lomax = 154000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
587 { .lomax = 181000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 0, .div1p5 = 0},
588 { .lomax = 185000000, .spd = 2, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
589 { .lomax = 217000000, .spd = 2, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
590 { .lomax = 244000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1},
591 { .lomax = 265000000, .spd = 1, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1},
592 { .lomax = 302000000, .spd = 1, .bs = 1, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
593 { .lomax = 324000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
594 { .lomax = 370000000, .spd = 1, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
595 { .lomax = 454000000, .spd = 1, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
596 { .lomax = 493000000, .spd = 0, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1},
597 { .lomax = 530000000, .spd = 0, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1},
598 { .lomax = 554000000, .spd = 0, .bs = 1, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
599 { .lomax = 604000000, .spd = 0, .bs = 1, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
600 { .lomax = 696000000, .spd = 0, .bs = 2, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
601 { .lomax = 740000000, .spd = 0, .bs = 2, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0},
602 { .lomax = 820000000, .spd = 0, .bs = 3, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
603 { .lomax = 865000000, .spd = 0, .bs = 3, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0},
604 { .lomax = 0, .spd = 0, .bs = 0, .bp = 0, .cp = 0, .gc3 = 0, .div1p5 = 0}
605};
606
a79ddae9 607static int philips_tda827x_tuner_init(struct dvb_frontend *fe)
86ddd96f
MCC		 608{
609 return 0;
610}
611
a79ddae9 612static int philips_tda827x_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
86ddd96f
MCC		 613{
614 struct saa7134_dev *dev = fe->dvb->priv;
615 u8 tuner_buf[14];
616
617 struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tuner_buf,
f2421ca3 618 .len = sizeof(tuner_buf) };
86ddd96f
MCC		 619 int i, tuner_freq, if_freq;
620 u32 N;
621 switch (params->u.ofdm.bandwidth) {
622 case BANDWIDTH_6_MHZ:
623 if_freq = 4000000;
624 break;
625 case BANDWIDTH_7_MHZ:
626 if_freq = 4500000;
627 break;
628 default: /* 8 MHz or Auto */
629 if_freq = 5000000;
630 break;
631 }
632 tuner_freq = params->frequency + if_freq;
633
634 i = 0;
635 while (tda827x_dvbt[i].lomax < tuner_freq) {
636 if(tda827x_dvbt[i + 1].lomax == 0)
637 break;
638 i++;
639 }
640
641 N = ((tuner_freq + 125000) / 250000) << (tda827x_dvbt[i].spd + 2);
642 tuner_buf[0] = 0;
643 tuner_buf[1] = (N>>8) | 0x40;
644 tuner_buf[2] = N & 0xff;
645 tuner_buf[3] = 0;
646 tuner_buf[4] = 0x52;
647 tuner_buf[5] = (tda827x_dvbt[i].spd << 6) + (tda827x_dvbt[i].div1p5 << 5) +
648 (tda827x_dvbt[i].bs << 3) + tda827x_dvbt[i].bp;
649 tuner_buf[6] = (tda827x_dvbt[i].gc3 << 4) + 0x8f;
650 tuner_buf[7] = 0xbf;
651 tuner_buf[8] = 0x2a;
652 tuner_buf[9] = 0x05;
653 tuner_buf[10] = 0xff;
654 tuner_buf[11] = 0x00;
655 tuner_buf[12] = 0x00;
656 tuner_buf[13] = 0x40;
657
658 tuner_msg.len = 14;
a79ddae9
AQ		 659 if (fe->ops->i2c_gate_ctrl)
660 fe->ops->i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 661 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
662 return -EIO;
663
664 msleep(500);
665 /* correct CP value */
666 tuner_buf[0] = 0x30;
667 tuner_buf[1] = 0x50 + tda827x_dvbt[i].cp;
668 tuner_msg.len = 2;
a79ddae9
AQ		 669 if (fe->ops->i2c_gate_ctrl)
670 fe->ops->i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 671 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
672
673 return 0;
674}
675
a79ddae9 676static int philips_tda827x_tuner_sleep(struct dvb_frontend *fe)
86ddd96f
MCC		 677{
678 struct saa7134_dev *dev = fe->dvb->priv;
679 static u8 tda827x_sleep[] = { 0x30, 0xd0};
680 struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tda827x_sleep,
f2421ca3 681 .len = sizeof(tda827x_sleep) };
a79ddae9
AQ		 682 if (fe->ops->i2c_gate_ctrl)
683 fe->ops->i2c_gate_ctrl(fe, 1);
86ddd96f 684 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
a79ddae9 685 return 0;
86ddd96f
MCC		 686}
687
688static struct tda1004x_config tda827x_lifeview_config = {
689 .demod_address = 0x08,
690 .invert = 1,
691 .invert_oclk = 0,
692 .xtal_freq = TDA10046_XTAL_16M,
693 .agc_config = TDA10046_AGC_TDA827X,
694 .if_freq = TDA10046_FREQ_045,
86ddd96f 695 .request_firmware = NULL,
1da177e4 696};
90e9df7f
HH		 697
698/* ------------------------------------------------------------------ */
699
700struct tda827xa_data {
701 u32 lomax;
702 u8 svco;
703 u8 spd;
704 u8 scr;
705 u8 sbs;
706 u8 gc3;
707};
708
709static struct tda827xa_data tda827xa_dvbt[] = {
710 { .lomax = 56875000, .svco = 3, .spd = 4, .scr = 0, .sbs = 0, .gc3 = 1},
711 { .lomax = 67250000, .svco = 0, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
712 { .lomax = 81250000, .svco = 1, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
713 { .lomax = 97500000, .svco = 2, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
714 { .lomax = 113750000, .svco = 3, .spd = 3, .scr = 0, .sbs = 1, .gc3 = 1},
715 { .lomax = 134500000, .svco = 0, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
716 { .lomax = 154000000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
717 { .lomax = 162500000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
718 { .lomax = 183000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
719 { .lomax = 195000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1},
720 { .lomax = 227500000, .svco = 3, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1},
721 { .lomax = 269000000, .svco = 0, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1},
722 { .lomax = 290000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1},
723 { .lomax = 325000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
724 { .lomax = 390000000, .svco = 2, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
725 { .lomax = 455000000, .svco = 3, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
726 { .lomax = 520000000, .svco = 0, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
727 { .lomax = 538000000, .svco = 0, .spd = 0, .scr = 1, .sbs = 3, .gc3 = 1},
728 { .lomax = 550000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
729 { .lomax = 620000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
730 { .lomax = 650000000, .svco = 1, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
731 { .lomax = 700000000, .svco = 2, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
732 { .lomax = 780000000, .svco = 2, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
733 { .lomax = 820000000, .svco = 3, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
734 { .lomax = 870000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
735 { .lomax = 911000000, .svco = 3, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 0},
736 { .lomax = 0, .svco = 0, .spd = 0, .scr = 0, .sbs = 0, .gc3 = 0}};
737
738
739static int philips_tda827xa_pll_set(u8 addr, struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
740{
741 struct saa7134_dev *dev = fe->dvb->priv;
742 u8 tuner_buf[14];
743 unsigned char reg2[2];
744
745 struct i2c_msg msg = {.addr = addr,.flags = 0,.buf = tuner_buf};
746 int i, tuner_freq, if_freq;
747 u32 N;
748
749 switch (params->u.ofdm.bandwidth) {
750 case BANDWIDTH_6_MHZ:
751 if_freq = 4000000;
752 break;
753 case BANDWIDTH_7_MHZ:
754 if_freq = 4500000;
755 break;
756 default: /* 8 MHz or Auto */
757 if_freq = 5000000;
758 break;
759 }
760 tuner_freq = params->frequency + if_freq;
761
762 i = 0;
763 while (tda827xa_dvbt[i].lomax < tuner_freq) {
764 if(tda827xa_dvbt[i + 1].lomax == 0)
765 break;
766 i++;
767 }
768
769 N = ((tuner_freq + 31250) / 62500) << tda827xa_dvbt[i].spd;
770 tuner_buf[0] = 0; // subaddress
771 tuner_buf[1] = N >> 8;
772 tuner_buf[2] = N & 0xff;
773 tuner_buf[3] = 0;
774 tuner_buf[4] = 0x16;
775 tuner_buf[5] = (tda827xa_dvbt[i].spd << 5) + (tda827xa_dvbt[i].svco << 3) +
776 tda827xa_dvbt[i].sbs;
777 tuner_buf[6] = 0x4b + (tda827xa_dvbt[i].gc3 << 4);
778 tuner_buf[7] = 0x0c;
779 tuner_buf[8] = 0x06;
780 tuner_buf[9] = 0x24;
781 tuner_buf[10] = 0xff;
782 tuner_buf[11] = 0x60;
783 tuner_buf[12] = 0x00;
784 tuner_buf[13] = 0x39; // lpsel
785 msg.len = 14;
a79ddae9
AQ		 786 if (fe->ops->i2c_gate_ctrl)
787 fe->ops->i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 788 if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1)
789 return -EIO;
790
791 msg.buf= reg2;
792 msg.len = 2;
793 reg2[0] = 0x60;
794 reg2[1] = 0x3c;
a79ddae9
AQ		 795 if (fe->ops->i2c_gate_ctrl)
796 fe->ops->i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 797 i2c_transfer(&dev->i2c_adap, &msg, 1);
798
799 reg2[0] = 0xa0;
800 reg2[1] = 0x40;
a79ddae9
AQ		 801 if (fe->ops->i2c_gate_ctrl)
802 fe->ops->i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 803 i2c_transfer(&dev->i2c_adap, &msg, 1);
804
805 msleep(2);
806 /* correct CP value */
807 reg2[0] = 0x30;
808 reg2[1] = 0x10 + tda827xa_dvbt[i].scr;
809 msg.len = 2;
a79ddae9
AQ		 810 if (fe->ops->i2c_gate_ctrl)
811 fe->ops->i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 812 i2c_transfer(&dev->i2c_adap, &msg, 1);
813
814 msleep(550);
815 reg2[0] = 0x50;
816 reg2[1] = 0x4f + (tda827xa_dvbt[i].gc3 << 4);
a79ddae9
AQ		 817 if (fe->ops->i2c_gate_ctrl)
818 fe->ops->i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 819 i2c_transfer(&dev->i2c_adap, &msg, 1);
820
821 return 0;
822
823}
824
a79ddae9 825static int philips_tda827xa_tuner_sleep(u8 addr, struct dvb_frontend *fe)
90e9df7f
HH		 826{
827 struct saa7134_dev *dev = fe->dvb->priv;
828 static u8 tda827xa_sleep[] = { 0x30, 0x90};
829 struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tda827xa_sleep,
f1bcef88 830 .len = sizeof(tda827xa_sleep) };
a79ddae9
AQ		 831 if (fe->ops->i2c_gate_ctrl)
832 fe->ops->i2c_gate_ctrl(fe, 1);
90e9df7f 833 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
a79ddae9 834 return 0;
90e9df7f
HH		 835}
836
837/* ------------------------------------------------------------------ */
838
a79ddae9 839static int philips_tiger_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
90e9df7f
HH		 840{
841 int ret;
842 struct saa7134_dev *dev = fe->dvb->priv;
843 static u8 tda8290_close[] = { 0x21, 0xc0};
844 static u8 tda8290_open[] = { 0x21, 0x80};
845 struct i2c_msg tda8290_msg = {.addr = 0x4b,.flags = 0, .len = 2};
a79ddae9 846
90e9df7f
HH		 847 /* close tda8290 i2c bridge */
848 tda8290_msg.buf = tda8290_close;
849 ret = i2c_transfer(&dev->i2c_adap, &tda8290_msg, 1);
850 if (ret != 1)
851 return -EIO;
852 msleep(20);
853 ret = philips_tda827xa_pll_set(0x61, fe, params);
854 if (ret != 0)
855 return ret;
856 /* open tda8290 i2c bridge */
857 tda8290_msg.buf = tda8290_open;
858 i2c_transfer(&dev->i2c_adap, &tda8290_msg, 1);
859 return ret;
2d6b5f62 860}
90e9df7f 861
a79ddae9 862static int philips_tiger_tuner_init(struct dvb_frontend *fe)
90e9df7f
HH		 863{
864 struct saa7134_dev *dev = fe->dvb->priv;
865 static u8 data[] = { 0x3c, 0x33, 0x6a};
866 struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
867
868 if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1)
869 return -EIO;
870 return 0;
871}
872
a79ddae9 873static int philips_tiger_tuner_sleep(struct dvb_frontend *fe)
90e9df7f
HH		 874{
875 struct saa7134_dev *dev = fe->dvb->priv;
876 static u8 data[] = { 0x3c, 0x33, 0x68};
877 struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
878
879 i2c_transfer(&dev->i2c_adap, &msg, 1);
a79ddae9
AQ		 880 philips_tda827xa_tuner_sleep( 0x61, fe);
881 return 0;
90e9df7f
HH		 882}
883
884static struct tda1004x_config philips_tiger_config = {
885 .demod_address = 0x08,
886 .invert = 1,
887 .invert_oclk = 0,
888 .xtal_freq = TDA10046_XTAL_16M,
889 .agc_config = TDA10046_AGC_TDA827X,
890 .if_freq = TDA10046_FREQ_045,
90e9df7f
HH		 891 .request_firmware = NULL,
892};
893
df42eaf2
HH		 894/* ------------------------------------------------------------------ */
895
a79ddae9 896static int lifeview_trio_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
420f32fe
NS		 897{
898 int ret;
899
900 ret = philips_tda827xa_pll_set(0x60, fe, params);
901 return ret;
902}
903
a79ddae9 904static int lifeview_trio_tuner_sleep(struct dvb_frontend *fe)
420f32fe 905{
a79ddae9 906 philips_tda827xa_tuner_sleep(0x60, fe);
420f32fe
NS		 907 return 0;
908}
909
420f32fe
NS		 910static struct tda1004x_config lifeview_trio_config = {
911 .demod_address = 0x09,
912 .invert = 1,
913 .invert_oclk = 0,
914 .xtal_freq = TDA10046_XTAL_16M,
915 .agc_config = TDA10046_AGC_TDA827X_GPL,
916 .if_freq = TDA10046_FREQ_045,
420f32fe
NS		 917 .request_firmware = NULL,
918};
919
920/* ------------------------------------------------------------------ */
921
a79ddae9 922static int ads_duo_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
df42eaf2
HH		 923{
924 int ret;
925
926 ret = philips_tda827xa_pll_set(0x61, fe, params);
927 return ret;
2d6b5f62 928}
df42eaf2 929
a79ddae9 930static int ads_duo_tuner_init(struct dvb_frontend *fe)
df42eaf2
HH		 931{
932 struct saa7134_dev *dev = fe->dvb->priv;
933 /* route TDA8275a AGC input to the channel decoder */
934 saa_writeb(SAA7134_GPIO_GPSTATUS2, 0x60);
935 return 0;
936}
937
a79ddae9 938static int ads_duo_tuner_sleep(struct dvb_frontend *fe)
df42eaf2
HH		 939{
940 struct saa7134_dev *dev = fe->dvb->priv;
941 /* route TDA8275a AGC input to the analog IF chip*/
942 saa_writeb(SAA7134_GPIO_GPSTATUS2, 0x20);
a79ddae9
AQ		 943 philips_tda827xa_tuner_sleep( 0x61, fe);
944 return 0;
df42eaf2
HH		 945}
946
947static struct tda1004x_config ads_tech_duo_config = {
948 .demod_address = 0x08,
949 .invert = 1,
950 .invert_oclk = 0,
951 .xtal_freq = TDA10046_XTAL_16M,
952 .agc_config = TDA10046_AGC_TDA827X_GPL,
953 .if_freq = TDA10046_FREQ_045,
df42eaf2
HH		 954 .request_firmware = NULL,
955};
956
3dfb729f
PH		 957/* ------------------------------------------------------------------ */
958
a79ddae9 959static int tevion_dvb220rf_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
3dfb729f
PH		 960{
961 int ret;
962 ret = philips_tda827xa_pll_set(0x60, fe, params);
963 return ret;
964}
965
a79ddae9 966static int tevion_dvb220rf_tuner_sleep(struct dvb_frontend *fe)
3dfb729f 967{
a79ddae9 968 philips_tda827xa_tuner_sleep( 0x61, fe);
3dfb729f
PH		 969 return 0;
970}
971
3dfb729f
PH		 972static struct tda1004x_config tevion_dvbt220rf_config = {
973 .demod_address = 0x08,
974 .invert = 1,
975 .invert_oclk = 0,
976 .xtal_freq = TDA10046_XTAL_16M,
977 .agc_config = TDA10046_AGC_TDA827X,
978 .if_freq = TDA10046_FREQ_045,
3dfb729f
PH		 979 .request_firmware = NULL,
980};
981
86ddd96f 982#endif
1da177e4 983
90e9df7f
HH		 984/* ------------------------------------------------------------------ */
985
3b64e8e2
MK		 986#ifdef HAVE_NXT200X
987static struct nxt200x_config avertvhda180 = {
988 .demod_address = 0x0a,
3b64e8e2 989};
3e1410ad 990
fbc81c07
CM		 991static int nxt200x_set_pll_input(u8 *buf, int input)
992{
993 if (input)
994 buf[3] |= 0x08;
995 else
996 buf[3] &= ~0x08;
997 return 0;
998}
999
3e1410ad
AB		 1000static struct nxt200x_config kworldatsc110 = {
1001 .demod_address = 0x0a,
fbc81c07 1002 .set_pll_input = nxt200x_set_pll_input,
3e1410ad 1003};
3b64e8e2
MK		 1004#endif
1005
1da177e4
LT		 1006/* ------------------------------------------------------------------ */
1007
1008static int dvb_init(struct saa7134_dev *dev)
1009{
1010 /* init struct videobuf_dvb */
1011 dev->ts.nr_bufs = 32;
1012 dev->ts.nr_packets = 32*4;
1013 dev->dvb.name = dev->name;
1014 videobuf_queue_init(&dev->dvb.dvbq, &saa7134_ts_qops,
1015 dev->pci, &dev->slock,
1016 V4L2_BUF_TYPE_VIDEO_CAPTURE,
1017 V4L2_FIELD_ALTERNATE,
1018 sizeof(struct saa7134_buf),
1019 dev);
1020
1021 switch (dev->board) {
29780bb7 1022#ifdef HAVE_MT352
1da177e4
LT		 1023 case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL:
1024 printk("%s: pinnacle 300i dvb setup\n",dev->name);
1025 dev->dvb.frontend = mt352_attach(&pinnacle_300i,
1026 &dev->i2c_adap);
6b3ccab7
AQ		 1027 if (dev->dvb.frontend) {
1028 dev->dvb.frontend->ops->tuner_ops.calc_regs = mt352_pinnacle_tuner_calc_regs;
1029 }
1da177e4 1030 break;
a78d0bfa
JAR		 1031
1032 case SAA7134_BOARD_AVERMEDIA_777:
1033 printk("%s: avertv 777 dvb setup\n",dev->name);
1034 dev->dvb.frontend = mt352_attach(&avermedia_777,
1035 &dev->i2c_adap);
6b3ccab7
AQ		 1036 if (dev->dvb.frontend) {
1037 dev->dvb.frontend->ops->tuner_ops.calc_regs = mt352_aver777_tuner_calc_regs;
1038 }
a78d0bfa 1039 break;
86ddd96f 1040#endif
29780bb7 1041#ifdef HAVE_TDA1004X
1da177e4
LT		 1042 case SAA7134_BOARD_MD7134:
1043 dev->dvb.frontend = tda10046_attach(&medion_cardbus,
1044 &dev->i2c_adap);
6b3ccab7
AQ		 1045 if (dev->dvb.frontend) {
1046 dev->dvb.frontend->ops->tuner_ops.init = philips_fmd1216_tuner_init;
1047 dev->dvb.frontend->ops->tuner_ops.sleep = philips_fmd1216_tuner_sleep;
1048 dev->dvb.frontend->ops->tuner_ops.set_params = philips_fmd1216_tuner_set_params;
1049 }
1da177e4 1050 break;
86ddd96f 1051 case SAA7134_BOARD_PHILIPS_TOUGH:
2cf36ac4 1052 dev->dvb.frontend = tda10046_attach(&philips_tu1216_60_config,
86ddd96f 1053 &dev->i2c_adap);
6b3ccab7
AQ		 1054 if (dev->dvb.frontend) {
1055 dev->dvb.frontend->ops->tuner_ops.init = philips_tu1216_tuner_60_init;
1056 dev->dvb.frontend->ops->tuner_ops.set_params = philips_tu1216_tuner_60_set_params;
1057 }
86ddd96f
MCC		 1058 break;
1059 case SAA7134_BOARD_FLYDVBTDUO:
1060 dev->dvb.frontend = tda10046_attach(&tda827x_lifeview_config,
1061 &dev->i2c_adap);
6b3ccab7
AQ		 1062 if (dev->dvb.frontend) {
1063 dev->dvb.frontend->ops->tuner_ops.init = philips_tda827x_tuner_init;
1064 dev->dvb.frontend->ops->tuner_ops.sleep = philips_tda827x_tuner_sleep;
1065 dev->dvb.frontend->ops->tuner_ops.set_params = philips_tda827x_tuner_set_params;
1066 }
86ddd96f 1067 break;
10b7a903 1068 case SAA7134_BOARD_FLYDVBT_DUO_CARDBUS:
86ddd96f
MCC		 1069 dev->dvb.frontend = tda10046_attach(&tda827x_lifeview_config,
1070 &dev->i2c_adap);
6b3ccab7
AQ		 1071 if (dev->dvb.frontend) {
1072 dev->dvb.frontend->ops->tuner_ops.init = philips_tda827x_tuner_init;
1073 dev->dvb.frontend->ops->tuner_ops.sleep = philips_tda827x_tuner_sleep;
1074 dev->dvb.frontend->ops->tuner_ops.set_params = philips_tda827x_tuner_set_params;
1075 }
86ddd96f 1076 break;
2cf36ac4
HH		 1077 case SAA7134_BOARD_PHILIPS_EUROPA:
1078 dev->dvb.frontend = tda10046_attach(&philips_europa_config,
1079 &dev->i2c_adap);
6b3ccab7
AQ		 1080 if (dev->dvb.frontend) {
1081 dev->original_demod_sleep = dev->dvb.frontend->ops->sleep;
1082 dev->dvb.frontend->ops->sleep = philips_europa_demod_sleep;
1083 dev->dvb.frontend->ops->tuner_ops.init = philips_europa_tuner_init;
1084 dev->dvb.frontend->ops->tuner_ops.sleep = philips_europa_tuner_sleep;
1085 dev->dvb.frontend->ops->tuner_ops.set_params = philips_td1316_tuner_set_params;
1086 }
2cf36ac4
HH		 1087 break;
1088 case SAA7134_BOARD_VIDEOMATE_DVBT_300:
1089 dev->dvb.frontend = tda10046_attach(&philips_europa_config,
1090 &dev->i2c_adap);
6b3ccab7
AQ		 1091 if (dev->dvb.frontend) {
1092 dev->dvb.frontend->ops->tuner_ops.init = philips_europa_tuner_init;
1093 dev->dvb.frontend->ops->tuner_ops.sleep = philips_europa_tuner_sleep;
1094 dev->dvb.frontend->ops->tuner_ops.set_params = philips_td1316_tuner_set_params;
1095 }
2cf36ac4
HH		 1096 break;
1097 case SAA7134_BOARD_VIDEOMATE_DVBT_200:
1098 dev->dvb.frontend = tda10046_attach(&philips_tu1216_61_config,
1099 &dev->i2c_adap);
6b3ccab7
AQ		 1100 if (dev->dvb.frontend) {
1101 dev->dvb.frontend->ops->tuner_ops.init = philips_tu1216_tuner_61_init;
1102 dev->dvb.frontend->ops->tuner_ops.set_params = philips_tu1216_tuner_61_set_params;
1103 }
2cf36ac4 1104 break;
90e9df7f
HH		 1105 case SAA7134_BOARD_PHILIPS_TIGER:
1106 dev->dvb.frontend = tda10046_attach(&philips_tiger_config,
1107 &dev->i2c_adap);
6b3ccab7
AQ		 1108 if (dev->dvb.frontend) {
1109 dev->dvb.frontend->ops->tuner_ops.init = philips_tiger_tuner_init;
1110 dev->dvb.frontend->ops->tuner_ops.sleep = philips_tiger_tuner_sleep;
1111 dev->dvb.frontend->ops->tuner_ops.set_params = philips_tiger_tuner_set_params;
1112 }
90e9df7f 1113 break;
d4b0aba4
HH		 1114 case SAA7134_BOARD_ASUSTeK_P7131_DUAL:
1115 dev->dvb.frontend = tda10046_attach(&philips_tiger_config,
1116 &dev->i2c_adap);
6b3ccab7
AQ		 1117 if (dev->dvb.frontend) {
1118 dev->dvb.frontend->ops->tuner_ops.init = philips_tiger_tuner_init;
1119 dev->dvb.frontend->ops->tuner_ops.sleep = philips_tiger_tuner_sleep;
1120 dev->dvb.frontend->ops->tuner_ops.set_params = philips_tiger_tuner_set_params;
1121 }
d4b0aba4 1122 break;
3d8466ec
GG		 1123 case SAA7134_BOARD_FLYDVBT_LR301:
1124 dev->dvb.frontend = tda10046_attach(&tda827x_lifeview_config,
1125 &dev->i2c_adap);
6b3ccab7
AQ		 1126 if (dev->dvb.frontend) {
1127 dev->dvb.frontend->ops->tuner_ops.init = philips_tda827x_tuner_init;
1128 dev->dvb.frontend->ops->tuner_ops.sleep = philips_tda827x_tuner_sleep;
1129 dev->dvb.frontend->ops->tuner_ops.set_params = philips_tda827x_tuner_set_params;
1130 }
3d8466ec 1131 break;
420f32fe
NS		 1132 case SAA7134_BOARD_FLYDVB_TRIO:
1133 dev->dvb.frontend = tda10046_attach(&lifeview_trio_config,
1134 &dev->i2c_adap);
6b3ccab7
AQ		 1135 if (dev->dvb.frontend) {
1136 dev->dvb.frontend->ops->tuner_ops.sleep = lifeview_trio_tuner_sleep;
1137 dev->dvb.frontend->ops->tuner_ops.set_params = lifeview_trio_tuner_set_params;
1138 }
420f32fe 1139 break;
df42eaf2
HH		 1140 case SAA7134_BOARD_ADS_DUO_CARDBUS_PTV331:
1141 dev->dvb.frontend = tda10046_attach(&ads_tech_duo_config,
1142 &dev->i2c_adap);
6b3ccab7
AQ		 1143 if (dev->dvb.frontend) {
1144 dev->dvb.frontend->ops->tuner_ops.init = ads_duo_tuner_init;
1145 dev->dvb.frontend->ops->tuner_ops.sleep = ads_duo_tuner_sleep;
1146 dev->dvb.frontend->ops->tuner_ops.set_params = ads_duo_tuner_set_params;
1147 }
df42eaf2 1148 break;
3dfb729f
PH		 1149 case SAA7134_BOARD_TEVION_DVBT_220RF:
1150 dev->dvb.frontend = tda10046_attach(&tevion_dvbt220rf_config,
1151 &dev->i2c_adap);
6b3ccab7
AQ		 1152 if (dev->dvb.frontend) {
1153 dev->dvb.frontend->ops->tuner_ops.sleep = tevion_dvb220rf_tuner_sleep;
1154 dev->dvb.frontend->ops->tuner_ops.set_params = tevion_dvb220rf_tuner_set_params;
1155 }
3dfb729f 1156 break;
d95b8942
HH		 1157 case SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS:
1158 dev->dvb.frontend = tda10046_attach(&ads_tech_duo_config,
1159 &dev->i2c_adap);
6b3ccab7
AQ		 1160 if (dev->dvb.frontend) {
1161 dev->dvb.frontend->ops->tuner_ops.init = ads_duo_tuner_init;
1162 dev->dvb.frontend->ops->tuner_ops.sleep = ads_duo_tuner_sleep;
1163 dev->dvb.frontend->ops->tuner_ops.set_params = ads_duo_tuner_set_params;
1164 }
d95b8942 1165 break;
3b64e8e2
MK		 1166#endif
1167#ifdef HAVE_NXT200X
1168 case SAA7134_BOARD_AVERMEDIA_AVERTVHD_A180:
1169 dev->dvb.frontend = nxt200x_attach(&avertvhda180, &dev->i2c_adap);
a79ddae9
AQ		 1170 if (dev->dvb.frontend) {
1171 dvb_pll_attach(dev->dvb.frontend, 0x61, &dev->i2c_adap, &dvb_pll_tdhu2);
1172 }
3b64e8e2 1173 break;
3e1410ad
AB		 1174 case SAA7134_BOARD_KWORLD_ATSC110:
1175 dev->dvb.frontend = nxt200x_attach(&kworldatsc110, &dev->i2c_adap);
a79ddae9
AQ		 1176 if (dev->dvb.frontend) {
1177 dvb_pll_attach(dev->dvb.frontend, 0x61, &dev->i2c_adap, &dvb_pll_tuv1236d);
1178 }
3e1410ad 1179 break;
86ddd96f 1180#endif
1da177e4
LT		 1181 default:
1182 printk("%s: Huh? unknown DVB card?\n",dev->name);
1183 break;
1184 }
1185
1186 if (NULL == dev->dvb.frontend) {
1187 printk("%s: frontend initialization failed\n",dev->name);
1188 return -1;
1189 }
1190
1191 /* register everything else */
d09dbf92 1192 return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev);
1da177e4
LT		 1193}
1194
1195static int dvb_fini(struct saa7134_dev *dev)
1196{
1197 static int on = TDA9887_PRESENT | TDA9887_PORT2_INACTIVE;
1198
1da177e4
LT		 1199 switch (dev->board) {
1200 case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL:
1201 /* otherwise we don't detect the tuner on next insmod */
1202 saa7134_i2c_call_clients(dev,TDA9887_SET_CONFIG,&on);
1203 break;
1204 };
1205 videobuf_dvb_unregister(&dev->dvb);
1206 return 0;
1207}
1208
1209static struct saa7134_mpeg_ops dvb_ops = {
1210 .type = SAA7134_MPEG_DVB,
1211 .init = dvb_init,
1212 .fini = dvb_fini,
1213};
1214
1215static int __init dvb_register(void)
1216{
1217 return saa7134_ts_register(&dvb_ops);
1218}
1219
1220static void __exit dvb_unregister(void)
1221{
1222 saa7134_ts_unregister(&dvb_ops);
1223}
1224
1225module_init(dvb_register);
1226module_exit(dvb_unregister);
1227
1228/* ------------------------------------------------------------------ */
1229/*
1230 * Local variables:
1231 * c-basic-offset: 8
1232 * End:
1233 */
Linux kernel - Deliverables
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