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7ec94453 A |
1 | /* |
2 | * EMIF driver | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments, Inc. | |
5 | * | |
6 | * Aneesh V <aneesh@ti.com> | |
7 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/reboot.h> | |
15 | #include <linux/platform_data/emif_plat.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/slab.h> | |
e6b42eb6 | 21 | #include <linux/of.h> |
aac10aaa | 22 | #include <linux/debugfs.h> |
7ec94453 A |
23 | #include <linux/seq_file.h> |
24 | #include <linux/module.h> | |
25 | #include <linux/list.h> | |
a93de288 | 26 | #include <linux/spinlock.h> |
7ec94453 A |
27 | #include <memory/jedec_ddr.h> |
28 | #include "emif.h" | |
e6b42eb6 | 29 | #include "of_memory.h" |
7ec94453 A |
30 | |
31 | /** | |
32 | * struct emif_data - Per device static data for driver's use | |
33 | * @duplicate: Whether the DDR devices attached to this EMIF | |
34 | * instance are exactly same as that on EMIF1. In | |
35 | * this case we can save some memory and processing | |
36 | * @temperature_level: Maximum temperature of LPDDR2 devices attached | |
37 | * to this EMIF - read from MR4 register. If there | |
38 | * are two devices attached to this EMIF, this | |
39 | * value is the maximum of the two temperature | |
40 | * levels. | |
41 | * @node: node in the device list | |
42 | * @base: base address of memory-mapped IO registers. | |
43 | * @dev: device pointer. | |
a93de288 A |
44 | * @addressing table with addressing information from the spec |
45 | * @regs_cache: An array of 'struct emif_regs' that stores | |
46 | * calculated register values for different | |
47 | * frequencies, to avoid re-calculating them on | |
48 | * each DVFS transition. | |
49 | * @curr_regs: The set of register values used in the last | |
50 | * frequency change (i.e. corresponding to the | |
51 | * frequency in effect at the moment) | |
7ec94453 | 52 | * @plat_data: Pointer to saved platform data. |
aac10aaa | 53 | * @debugfs_root: dentry to the root folder for EMIF in debugfs |
e6b42eb6 | 54 | * @np_ddr: Pointer to ddr device tree node |
7ec94453 A |
55 | */ |
56 | struct emif_data { | |
57 | u8 duplicate; | |
58 | u8 temperature_level; | |
a93de288 | 59 | u8 lpmode; |
7ec94453 | 60 | struct list_head node; |
a93de288 | 61 | unsigned long irq_state; |
7ec94453 A |
62 | void __iomem *base; |
63 | struct device *dev; | |
a93de288 A |
64 | const struct lpddr2_addressing *addressing; |
65 | struct emif_regs *regs_cache[EMIF_MAX_NUM_FREQUENCIES]; | |
66 | struct emif_regs *curr_regs; | |
7ec94453 | 67 | struct emif_platform_data *plat_data; |
aac10aaa | 68 | struct dentry *debugfs_root; |
e6b42eb6 | 69 | struct device_node *np_ddr; |
7ec94453 A |
70 | }; |
71 | ||
72 | static struct emif_data *emif1; | |
a93de288 A |
73 | static spinlock_t emif_lock; |
74 | static unsigned long irq_state; | |
75 | static u32 t_ck; /* DDR clock period in ps */ | |
7ec94453 A |
76 | static LIST_HEAD(device_list); |
77 | ||
e5445ee6 | 78 | #ifdef CONFIG_DEBUG_FS |
aac10aaa A |
79 | static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif, |
80 | struct emif_regs *regs) | |
81 | { | |
82 | u32 type = emif->plat_data->device_info->type; | |
83 | u32 ip_rev = emif->plat_data->ip_rev; | |
84 | ||
85 | seq_printf(s, "EMIF register cache dump for %dMHz\n", | |
86 | regs->freq/1000000); | |
87 | ||
88 | seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw); | |
89 | seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw); | |
90 | seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw); | |
91 | seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw); | |
92 | ||
93 | if (ip_rev == EMIF_4D) { | |
94 | seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n", | |
95 | regs->read_idle_ctrl_shdw_normal); | |
96 | seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n", | |
97 | regs->read_idle_ctrl_shdw_volt_ramp); | |
98 | } else if (ip_rev == EMIF_4D5) { | |
99 | seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n", | |
100 | regs->dll_calib_ctrl_shdw_normal); | |
101 | seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n", | |
102 | regs->dll_calib_ctrl_shdw_volt_ramp); | |
103 | } | |
104 | ||
105 | if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) { | |
106 | seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n", | |
107 | regs->ref_ctrl_shdw_derated); | |
108 | seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n", | |
109 | regs->sdram_tim1_shdw_derated); | |
110 | seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n", | |
111 | regs->sdram_tim3_shdw_derated); | |
112 | } | |
113 | } | |
114 | ||
115 | static int emif_regdump_show(struct seq_file *s, void *unused) | |
116 | { | |
117 | struct emif_data *emif = s->private; | |
118 | struct emif_regs **regs_cache; | |
119 | int i; | |
120 | ||
121 | if (emif->duplicate) | |
122 | regs_cache = emif1->regs_cache; | |
123 | else | |
124 | regs_cache = emif->regs_cache; | |
125 | ||
126 | for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) { | |
127 | do_emif_regdump_show(s, emif, regs_cache[i]); | |
128 | seq_printf(s, "\n"); | |
129 | } | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | static int emif_regdump_open(struct inode *inode, struct file *file) | |
135 | { | |
136 | return single_open(file, emif_regdump_show, inode->i_private); | |
137 | } | |
138 | ||
139 | static const struct file_operations emif_regdump_fops = { | |
140 | .open = emif_regdump_open, | |
141 | .read = seq_read, | |
142 | .release = single_release, | |
143 | }; | |
144 | ||
145 | static int emif_mr4_show(struct seq_file *s, void *unused) | |
146 | { | |
147 | struct emif_data *emif = s->private; | |
148 | ||
149 | seq_printf(s, "MR4=%d\n", emif->temperature_level); | |
150 | return 0; | |
151 | } | |
152 | ||
153 | static int emif_mr4_open(struct inode *inode, struct file *file) | |
154 | { | |
155 | return single_open(file, emif_mr4_show, inode->i_private); | |
156 | } | |
157 | ||
158 | static const struct file_operations emif_mr4_fops = { | |
159 | .open = emif_mr4_open, | |
160 | .read = seq_read, | |
161 | .release = single_release, | |
162 | }; | |
163 | ||
164 | static int __init_or_module emif_debugfs_init(struct emif_data *emif) | |
165 | { | |
166 | struct dentry *dentry; | |
167 | int ret; | |
168 | ||
169 | dentry = debugfs_create_dir(dev_name(emif->dev), NULL); | |
e5445ee6 AL |
170 | if (!dentry) { |
171 | ret = -ENOMEM; | |
aac10aaa A |
172 | goto err0; |
173 | } | |
174 | emif->debugfs_root = dentry; | |
175 | ||
176 | dentry = debugfs_create_file("regcache_dump", S_IRUGO, | |
177 | emif->debugfs_root, emif, &emif_regdump_fops); | |
e5445ee6 AL |
178 | if (!dentry) { |
179 | ret = -ENOMEM; | |
aac10aaa A |
180 | goto err1; |
181 | } | |
182 | ||
183 | dentry = debugfs_create_file("mr4", S_IRUGO, | |
184 | emif->debugfs_root, emif, &emif_mr4_fops); | |
e5445ee6 AL |
185 | if (!dentry) { |
186 | ret = -ENOMEM; | |
aac10aaa A |
187 | goto err1; |
188 | } | |
189 | ||
190 | return 0; | |
191 | err1: | |
192 | debugfs_remove_recursive(emif->debugfs_root); | |
193 | err0: | |
194 | return ret; | |
195 | } | |
196 | ||
197 | static void __exit emif_debugfs_exit(struct emif_data *emif) | |
198 | { | |
199 | debugfs_remove_recursive(emif->debugfs_root); | |
200 | emif->debugfs_root = NULL; | |
201 | } | |
e5445ee6 AL |
202 | #else |
203 | static inline int __init_or_module emif_debugfs_init(struct emif_data *emif) | |
204 | { | |
205 | return 0; | |
206 | } | |
207 | ||
208 | static inline void __exit emif_debugfs_exit(struct emif_data *emif) | |
209 | { | |
210 | } | |
211 | #endif | |
aac10aaa | 212 | |
a93de288 A |
213 | /* |
214 | * Calculate the period of DDR clock from frequency value | |
215 | */ | |
216 | static void set_ddr_clk_period(u32 freq) | |
217 | { | |
218 | /* Divide 10^12 by frequency to get period in ps */ | |
219 | t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq); | |
220 | } | |
221 | ||
98231c4f A |
222 | /* |
223 | * Get bus width used by EMIF. Note that this may be different from the | |
224 | * bus width of the DDR devices used. For instance two 16-bit DDR devices | |
225 | * may be connected to a given CS of EMIF. In this case bus width as far | |
226 | * as EMIF is concerned is 32, where as the DDR bus width is 16 bits. | |
227 | */ | |
228 | static u32 get_emif_bus_width(struct emif_data *emif) | |
229 | { | |
230 | u32 width; | |
231 | void __iomem *base = emif->base; | |
232 | ||
233 | width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK) | |
234 | >> NARROW_MODE_SHIFT; | |
235 | width = width == 0 ? 32 : 16; | |
236 | ||
237 | return width; | |
238 | } | |
239 | ||
a93de288 A |
240 | /* |
241 | * Get the CL from SDRAM_CONFIG register | |
242 | */ | |
243 | static u32 get_cl(struct emif_data *emif) | |
244 | { | |
245 | u32 cl; | |
246 | void __iomem *base = emif->base; | |
247 | ||
248 | cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT; | |
249 | ||
250 | return cl; | |
251 | } | |
252 | ||
253 | static void set_lpmode(struct emif_data *emif, u8 lpmode) | |
254 | { | |
255 | u32 temp; | |
256 | void __iomem *base = emif->base; | |
257 | ||
258 | temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL); | |
259 | temp &= ~LP_MODE_MASK; | |
260 | temp |= (lpmode << LP_MODE_SHIFT); | |
261 | writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL); | |
262 | } | |
263 | ||
264 | static void do_freq_update(void) | |
265 | { | |
266 | struct emif_data *emif; | |
267 | ||
268 | /* | |
269 | * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE | |
270 | * | |
271 | * i728 DESCRIPTION: | |
272 | * The EMIF automatically puts the SDRAM into self-refresh mode | |
273 | * after the EMIF has not performed accesses during | |
274 | * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles | |
275 | * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set | |
276 | * to 0x2. If during a small window the following three events | |
277 | * occur: | |
278 | * - The SR_TIMING counter expires | |
279 | * - And frequency change is requested | |
280 | * - And OCP access is requested | |
281 | * Then it causes instable clock on the DDR interface. | |
282 | * | |
283 | * WORKAROUND | |
284 | * To avoid the occurrence of the three events, the workaround | |
285 | * is to disable the self-refresh when requesting a frequency | |
286 | * change. Before requesting a frequency change the software must | |
287 | * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the | |
288 | * frequency change has been done, the software can reprogram | |
289 | * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2 | |
290 | */ | |
291 | list_for_each_entry(emif, &device_list, node) { | |
292 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) | |
293 | set_lpmode(emif, EMIF_LP_MODE_DISABLE); | |
294 | } | |
295 | ||
296 | /* | |
297 | * TODO: Do FREQ_UPDATE here when an API | |
298 | * is available for this as part of the new | |
299 | * clock framework | |
300 | */ | |
301 | ||
302 | list_for_each_entry(emif, &device_list, node) { | |
303 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) | |
304 | set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH); | |
305 | } | |
306 | } | |
307 | ||
308 | /* Find addressing table entry based on the device's type and density */ | |
309 | static const struct lpddr2_addressing *get_addressing_table( | |
310 | const struct ddr_device_info *device_info) | |
311 | { | |
312 | u32 index, type, density; | |
313 | ||
314 | type = device_info->type; | |
315 | density = device_info->density; | |
316 | ||
317 | switch (type) { | |
318 | case DDR_TYPE_LPDDR2_S4: | |
319 | index = density - 1; | |
320 | break; | |
321 | case DDR_TYPE_LPDDR2_S2: | |
322 | switch (density) { | |
323 | case DDR_DENSITY_1Gb: | |
324 | case DDR_DENSITY_2Gb: | |
325 | index = density + 3; | |
326 | break; | |
327 | default: | |
328 | index = density - 1; | |
329 | } | |
330 | break; | |
331 | default: | |
332 | return NULL; | |
333 | } | |
334 | ||
335 | return &lpddr2_jedec_addressing_table[index]; | |
336 | } | |
337 | ||
338 | /* | |
339 | * Find the the right timing table from the array of timing | |
340 | * tables of the device using DDR clock frequency | |
341 | */ | |
342 | static const struct lpddr2_timings *get_timings_table(struct emif_data *emif, | |
343 | u32 freq) | |
344 | { | |
345 | u32 i, min, max, freq_nearest; | |
346 | const struct lpddr2_timings *timings = NULL; | |
347 | const struct lpddr2_timings *timings_arr = emif->plat_data->timings; | |
348 | struct device *dev = emif->dev; | |
349 | ||
350 | /* Start with a very high frequency - 1GHz */ | |
351 | freq_nearest = 1000000000; | |
352 | ||
353 | /* | |
354 | * Find the timings table such that: | |
355 | * 1. the frequency range covers the required frequency(safe) AND | |
356 | * 2. the max_freq is closest to the required frequency(optimal) | |
357 | */ | |
358 | for (i = 0; i < emif->plat_data->timings_arr_size; i++) { | |
359 | max = timings_arr[i].max_freq; | |
360 | min = timings_arr[i].min_freq; | |
361 | if ((freq >= min) && (freq <= max) && (max < freq_nearest)) { | |
362 | freq_nearest = max; | |
363 | timings = &timings_arr[i]; | |
364 | } | |
365 | } | |
366 | ||
367 | if (!timings) | |
368 | dev_err(dev, "%s: couldn't find timings for - %dHz\n", | |
369 | __func__, freq); | |
370 | ||
371 | dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n", | |
372 | __func__, freq, freq_nearest); | |
373 | ||
374 | return timings; | |
375 | } | |
376 | ||
377 | static u32 get_sdram_ref_ctrl_shdw(u32 freq, | |
378 | const struct lpddr2_addressing *addressing) | |
379 | { | |
380 | u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi; | |
381 | ||
382 | /* Scale down frequency and t_refi to avoid overflow */ | |
383 | freq_khz = freq / 1000; | |
384 | t_refi = addressing->tREFI_ns / 100; | |
385 | ||
386 | /* | |
387 | * refresh rate to be set is 'tREFI(in us) * freq in MHz | |
388 | * division by 10000 to account for change in units | |
389 | */ | |
390 | val = t_refi * freq_khz / 10000; | |
391 | ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT; | |
392 | ||
393 | return ref_ctrl_shdw; | |
394 | } | |
395 | ||
396 | static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings, | |
397 | const struct lpddr2_min_tck *min_tck, | |
398 | const struct lpddr2_addressing *addressing) | |
399 | { | |
400 | u32 tim1 = 0, val = 0; | |
401 | ||
402 | val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; | |
403 | tim1 |= val << T_WTR_SHIFT; | |
404 | ||
405 | if (addressing->num_banks == B8) | |
406 | val = DIV_ROUND_UP(timings->tFAW, t_ck*4); | |
407 | else | |
408 | val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck)); | |
409 | tim1 |= (val - 1) << T_RRD_SHIFT; | |
410 | ||
411 | val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1; | |
412 | tim1 |= val << T_RC_SHIFT; | |
413 | ||
414 | val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck)); | |
415 | tim1 |= (val - 1) << T_RAS_SHIFT; | |
416 | ||
417 | val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; | |
418 | tim1 |= val << T_WR_SHIFT; | |
419 | ||
420 | val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1; | |
421 | tim1 |= val << T_RCD_SHIFT; | |
422 | ||
423 | val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1; | |
424 | tim1 |= val << T_RP_SHIFT; | |
425 | ||
426 | return tim1; | |
427 | } | |
428 | ||
429 | static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings, | |
430 | const struct lpddr2_min_tck *min_tck, | |
431 | const struct lpddr2_addressing *addressing) | |
432 | { | |
433 | u32 tim1 = 0, val = 0; | |
434 | ||
435 | val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; | |
436 | tim1 = val << T_WTR_SHIFT; | |
437 | ||
438 | /* | |
439 | * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps | |
440 | * to tFAW for de-rating | |
441 | */ | |
442 | if (addressing->num_banks == B8) { | |
443 | val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1; | |
444 | } else { | |
445 | val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck); | |
446 | val = max(min_tck->tRRD, val) - 1; | |
447 | } | |
448 | tim1 |= val << T_RRD_SHIFT; | |
449 | ||
450 | val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck); | |
451 | tim1 |= (val - 1) << T_RC_SHIFT; | |
452 | ||
453 | val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck); | |
454 | val = max(min_tck->tRASmin, val) - 1; | |
455 | tim1 |= val << T_RAS_SHIFT; | |
456 | ||
457 | val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; | |
458 | tim1 |= val << T_WR_SHIFT; | |
459 | ||
460 | val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck)); | |
461 | tim1 |= (val - 1) << T_RCD_SHIFT; | |
462 | ||
463 | val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck)); | |
464 | tim1 |= (val - 1) << T_RP_SHIFT; | |
465 | ||
466 | return tim1; | |
467 | } | |
468 | ||
469 | static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings, | |
470 | const struct lpddr2_min_tck *min_tck, | |
471 | const struct lpddr2_addressing *addressing, | |
472 | u32 type) | |
473 | { | |
474 | u32 tim2 = 0, val = 0; | |
475 | ||
476 | val = min_tck->tCKE - 1; | |
477 | tim2 |= val << T_CKE_SHIFT; | |
478 | ||
479 | val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1; | |
480 | tim2 |= val << T_RTP_SHIFT; | |
481 | ||
482 | /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */ | |
483 | val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1; | |
484 | tim2 |= val << T_XSNR_SHIFT; | |
485 | ||
486 | /* XSRD same as XSNR for LPDDR2 */ | |
487 | tim2 |= val << T_XSRD_SHIFT; | |
488 | ||
489 | val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1; | |
490 | tim2 |= val << T_XP_SHIFT; | |
491 | ||
492 | return tim2; | |
493 | } | |
494 | ||
495 | static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings, | |
496 | const struct lpddr2_min_tck *min_tck, | |
497 | const struct lpddr2_addressing *addressing, | |
498 | u32 type, u32 ip_rev, u32 derated) | |
499 | { | |
500 | u32 tim3 = 0, val = 0, t_dqsck; | |
501 | ||
502 | val = timings->tRAS_max_ns / addressing->tREFI_ns - 1; | |
503 | val = val > 0xF ? 0xF : val; | |
504 | tim3 |= val << T_RAS_MAX_SHIFT; | |
505 | ||
506 | val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1; | |
507 | tim3 |= val << T_RFC_SHIFT; | |
508 | ||
509 | t_dqsck = (derated == EMIF_DERATED_TIMINGS) ? | |
510 | timings->tDQSCK_max_derated : timings->tDQSCK_max; | |
511 | if (ip_rev == EMIF_4D5) | |
512 | val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1; | |
513 | else | |
514 | val = DIV_ROUND_UP(t_dqsck, t_ck) - 1; | |
515 | ||
516 | tim3 |= val << T_TDQSCKMAX_SHIFT; | |
517 | ||
518 | val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1; | |
519 | tim3 |= val << ZQ_ZQCS_SHIFT; | |
520 | ||
521 | val = DIV_ROUND_UP(timings->tCKESR, t_ck); | |
522 | val = max(min_tck->tCKESR, val) - 1; | |
523 | tim3 |= val << T_CKESR_SHIFT; | |
524 | ||
525 | if (ip_rev == EMIF_4D5) { | |
526 | tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT; | |
527 | ||
528 | val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1; | |
529 | tim3 |= val << T_PDLL_UL_SHIFT; | |
530 | } | |
531 | ||
532 | return tim3; | |
533 | } | |
534 | ||
98231c4f A |
535 | static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing, |
536 | bool cs1_used, bool cal_resistors_per_cs) | |
537 | { | |
538 | u32 zq = 0, val = 0; | |
539 | ||
540 | val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns; | |
541 | zq |= val << ZQ_REFINTERVAL_SHIFT; | |
542 | ||
543 | val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1; | |
544 | zq |= val << ZQ_ZQCL_MULT_SHIFT; | |
545 | ||
546 | val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1; | |
547 | zq |= val << ZQ_ZQINIT_MULT_SHIFT; | |
548 | ||
549 | zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT; | |
550 | ||
551 | if (cal_resistors_per_cs) | |
552 | zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT; | |
553 | else | |
554 | zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT; | |
555 | ||
556 | zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */ | |
557 | ||
558 | val = cs1_used ? 1 : 0; | |
559 | zq |= val << ZQ_CS1EN_SHIFT; | |
560 | ||
561 | return zq; | |
562 | } | |
563 | ||
564 | static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing, | |
565 | const struct emif_custom_configs *custom_configs, bool cs1_used, | |
566 | u32 sdram_io_width, u32 emif_bus_width) | |
567 | { | |
568 | u32 alert = 0, interval, devcnt; | |
569 | ||
570 | if (custom_configs && (custom_configs->mask & | |
571 | EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)) | |
572 | interval = custom_configs->temp_alert_poll_interval_ms; | |
573 | else | |
574 | interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS; | |
575 | ||
576 | interval *= 1000000; /* Convert to ns */ | |
577 | interval /= addressing->tREFI_ns; /* Convert to refresh cycles */ | |
578 | alert |= (interval << TA_REFINTERVAL_SHIFT); | |
579 | ||
580 | /* | |
581 | * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width | |
582 | * also to this form and subtract to get TA_DEVCNT, which is | |
583 | * in log2(x) form. | |
584 | */ | |
585 | emif_bus_width = __fls(emif_bus_width) - 1; | |
586 | devcnt = emif_bus_width - sdram_io_width; | |
587 | alert |= devcnt << TA_DEVCNT_SHIFT; | |
588 | ||
589 | /* DEVWDT is in 'log2(x) - 3' form */ | |
590 | alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT; | |
591 | ||
592 | alert |= 1 << TA_SFEXITEN_SHIFT; | |
593 | alert |= 1 << TA_CS0EN_SHIFT; | |
594 | alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT; | |
595 | ||
596 | return alert; | |
597 | } | |
598 | ||
a93de288 A |
599 | static u32 get_read_idle_ctrl_shdw(u8 volt_ramp) |
600 | { | |
601 | u32 idle = 0, val = 0; | |
602 | ||
603 | /* | |
604 | * Maximum value in normal conditions and increased frequency | |
605 | * when voltage is ramping | |
606 | */ | |
607 | if (volt_ramp) | |
608 | val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1; | |
609 | else | |
610 | val = 0x1FF; | |
611 | ||
612 | /* | |
613 | * READ_IDLE_CTRL register in EMIF4D has same offset and fields | |
614 | * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts | |
615 | */ | |
616 | idle |= val << DLL_CALIB_INTERVAL_SHIFT; | |
617 | idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT; | |
618 | ||
619 | return idle; | |
620 | } | |
621 | ||
622 | static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp) | |
623 | { | |
624 | u32 calib = 0, val = 0; | |
625 | ||
626 | if (volt_ramp == DDR_VOLTAGE_RAMPING) | |
627 | val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1; | |
628 | else | |
629 | val = 0; /* Disabled when voltage is stable */ | |
630 | ||
631 | calib |= val << DLL_CALIB_INTERVAL_SHIFT; | |
632 | calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT; | |
633 | ||
634 | return calib; | |
635 | } | |
636 | ||
637 | static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings, | |
638 | u32 freq, u8 RL) | |
639 | { | |
640 | u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0; | |
641 | ||
642 | val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1; | |
643 | phy |= val << READ_LATENCY_SHIFT_4D; | |
644 | ||
645 | if (freq <= 100000000) | |
646 | val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY; | |
647 | else if (freq <= 200000000) | |
648 | val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY; | |
649 | else | |
650 | val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY; | |
651 | ||
652 | phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D; | |
653 | ||
654 | return phy; | |
655 | } | |
656 | ||
657 | static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl) | |
658 | { | |
659 | u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay; | |
660 | ||
661 | /* | |
662 | * DLL operates at 266 MHz. If DDR frequency is near 266 MHz, | |
663 | * half-delay is not needed else set half-delay | |
664 | */ | |
665 | if (freq >= 265000000 && freq < 267000000) | |
666 | half_delay = 0; | |
667 | else | |
668 | half_delay = 1; | |
669 | ||
670 | phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5; | |
671 | phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS, | |
672 | t_ck) - 1) << READ_LATENCY_SHIFT_4D5); | |
673 | ||
674 | return phy; | |
675 | } | |
676 | ||
677 | static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void) | |
678 | { | |
679 | u32 fifo_we_slave_ratio; | |
680 | ||
681 | fifo_we_slave_ratio = DIV_ROUND_CLOSEST( | |
682 | EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); | |
683 | ||
684 | return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 | | |
685 | fifo_we_slave_ratio << 22; | |
686 | } | |
687 | ||
688 | static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void) | |
689 | { | |
690 | u32 fifo_we_slave_ratio; | |
691 | ||
692 | fifo_we_slave_ratio = DIV_ROUND_CLOSEST( | |
693 | EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); | |
694 | ||
695 | return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 | | |
696 | fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23; | |
697 | } | |
698 | ||
699 | static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void) | |
700 | { | |
701 | u32 fifo_we_slave_ratio; | |
702 | ||
703 | fifo_we_slave_ratio = DIV_ROUND_CLOSEST( | |
704 | EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); | |
705 | ||
706 | return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 | | |
707 | fifo_we_slave_ratio << 13; | |
708 | } | |
709 | ||
710 | static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev) | |
711 | { | |
712 | u32 pwr_mgmt_ctrl = 0, timeout; | |
713 | u32 lpmode = EMIF_LP_MODE_SELF_REFRESH; | |
714 | u32 timeout_perf = EMIF_LP_MODE_TIMEOUT_PERFORMANCE; | |
715 | u32 timeout_pwr = EMIF_LP_MODE_TIMEOUT_POWER; | |
716 | u32 freq_threshold = EMIF_LP_MODE_FREQ_THRESHOLD; | |
717 | ||
718 | struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs; | |
719 | ||
720 | if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) { | |
721 | lpmode = cust_cfgs->lpmode; | |
722 | timeout_perf = cust_cfgs->lpmode_timeout_performance; | |
723 | timeout_pwr = cust_cfgs->lpmode_timeout_power; | |
724 | freq_threshold = cust_cfgs->lpmode_freq_threshold; | |
725 | } | |
726 | ||
727 | /* Timeout based on DDR frequency */ | |
728 | timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr; | |
729 | ||
730 | /* The value to be set in register is "log2(timeout) - 3" */ | |
731 | if (timeout < 16) { | |
732 | timeout = 0; | |
733 | } else { | |
734 | timeout = __fls(timeout) - 3; | |
735 | if (timeout & (timeout - 1)) | |
736 | timeout++; | |
737 | } | |
738 | ||
739 | switch (lpmode) { | |
740 | case EMIF_LP_MODE_CLOCK_STOP: | |
741 | pwr_mgmt_ctrl = (timeout << CS_TIM_SHIFT) | | |
742 | SR_TIM_MASK | PD_TIM_MASK; | |
743 | break; | |
744 | case EMIF_LP_MODE_SELF_REFRESH: | |
745 | /* Workaround for errata i735 */ | |
746 | if (timeout < 6) | |
747 | timeout = 6; | |
748 | ||
749 | pwr_mgmt_ctrl = (timeout << SR_TIM_SHIFT) | | |
750 | CS_TIM_MASK | PD_TIM_MASK; | |
751 | break; | |
752 | case EMIF_LP_MODE_PWR_DN: | |
753 | pwr_mgmt_ctrl = (timeout << PD_TIM_SHIFT) | | |
754 | CS_TIM_MASK | SR_TIM_MASK; | |
755 | break; | |
756 | case EMIF_LP_MODE_DISABLE: | |
757 | default: | |
758 | pwr_mgmt_ctrl = CS_TIM_MASK | | |
759 | PD_TIM_MASK | SR_TIM_MASK; | |
760 | } | |
761 | ||
762 | /* No CS_TIM in EMIF_4D5 */ | |
763 | if (ip_rev == EMIF_4D5) | |
764 | pwr_mgmt_ctrl &= ~CS_TIM_MASK; | |
765 | ||
766 | pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT; | |
767 | ||
768 | return pwr_mgmt_ctrl; | |
769 | } | |
770 | ||
68b4aee3 A |
771 | /* |
772 | * Get the temperature level of the EMIF instance: | |
773 | * Reads the MR4 register of attached SDRAM parts to find out the temperature | |
774 | * level. If there are two parts attached(one on each CS), then the temperature | |
775 | * level for the EMIF instance is the higher of the two temperatures. | |
776 | */ | |
777 | static void get_temperature_level(struct emif_data *emif) | |
778 | { | |
779 | u32 temp, temperature_level; | |
780 | void __iomem *base; | |
781 | ||
782 | base = emif->base; | |
783 | ||
784 | /* Read mode register 4 */ | |
785 | writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG); | |
786 | temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA); | |
787 | temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >> | |
788 | MR4_SDRAM_REF_RATE_SHIFT; | |
789 | ||
790 | if (emif->plat_data->device_info->cs1_used) { | |
791 | writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG); | |
792 | temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA); | |
793 | temp = (temp & MR4_SDRAM_REF_RATE_MASK) | |
794 | >> MR4_SDRAM_REF_RATE_SHIFT; | |
795 | temperature_level = max(temp, temperature_level); | |
796 | } | |
797 | ||
798 | /* treat everything less than nominal(3) in MR4 as nominal */ | |
799 | if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL)) | |
800 | temperature_level = SDRAM_TEMP_NOMINAL; | |
801 | ||
802 | /* if we get reserved value in MR4 persist with the existing value */ | |
803 | if (likely(temperature_level != SDRAM_TEMP_RESERVED_4)) | |
804 | emif->temperature_level = temperature_level; | |
805 | } | |
806 | ||
a93de288 A |
807 | /* |
808 | * Program EMIF shadow registers that are not dependent on temperature | |
809 | * or voltage | |
810 | */ | |
811 | static void setup_registers(struct emif_data *emif, struct emif_regs *regs) | |
812 | { | |
813 | void __iomem *base = emif->base; | |
814 | ||
815 | writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW); | |
816 | writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW); | |
817 | ||
818 | /* Settings specific for EMIF4D5 */ | |
819 | if (emif->plat_data->ip_rev != EMIF_4D5) | |
820 | return; | |
821 | writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW); | |
822 | writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW); | |
823 | writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW); | |
824 | } | |
825 | ||
826 | /* | |
827 | * When voltage ramps dll calibration and forced read idle should | |
828 | * happen more often | |
829 | */ | |
830 | static void setup_volt_sensitive_regs(struct emif_data *emif, | |
831 | struct emif_regs *regs, u32 volt_state) | |
832 | { | |
833 | u32 calib_ctrl; | |
834 | void __iomem *base = emif->base; | |
835 | ||
836 | /* | |
837 | * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as | |
838 | * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_* | |
839 | * is an alias of the respective read_idle_ctrl_shdw_* (members of | |
840 | * a union). So, the below code takes care of both cases | |
841 | */ | |
842 | if (volt_state == DDR_VOLTAGE_RAMPING) | |
843 | calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp; | |
844 | else | |
845 | calib_ctrl = regs->dll_calib_ctrl_shdw_normal; | |
846 | ||
847 | writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW); | |
848 | } | |
849 | ||
850 | /* | |
851 | * setup_temperature_sensitive_regs() - set the timings for temperature | |
852 | * sensitive registers. This happens once at initialisation time based | |
853 | * on the temperature at boot time and subsequently based on the temperature | |
854 | * alert interrupt. Temperature alert can happen when the temperature | |
855 | * increases or drops. So this function can have the effect of either | |
856 | * derating the timings or going back to nominal values. | |
857 | */ | |
858 | static void setup_temperature_sensitive_regs(struct emif_data *emif, | |
859 | struct emif_regs *regs) | |
860 | { | |
861 | u32 tim1, tim3, ref_ctrl, type; | |
862 | void __iomem *base = emif->base; | |
863 | u32 temperature; | |
864 | ||
865 | type = emif->plat_data->device_info->type; | |
866 | ||
867 | tim1 = regs->sdram_tim1_shdw; | |
868 | tim3 = regs->sdram_tim3_shdw; | |
869 | ref_ctrl = regs->ref_ctrl_shdw; | |
870 | ||
871 | /* No de-rating for non-lpddr2 devices */ | |
872 | if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4) | |
873 | goto out; | |
874 | ||
875 | temperature = emif->temperature_level; | |
876 | if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) { | |
877 | ref_ctrl = regs->ref_ctrl_shdw_derated; | |
878 | } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) { | |
879 | tim1 = regs->sdram_tim1_shdw_derated; | |
880 | tim3 = regs->sdram_tim3_shdw_derated; | |
881 | ref_ctrl = regs->ref_ctrl_shdw_derated; | |
882 | } | |
883 | ||
884 | out: | |
885 | writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW); | |
886 | writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW); | |
887 | writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW); | |
888 | } | |
889 | ||
68b4aee3 A |
890 | static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif) |
891 | { | |
892 | u32 old_temp_level; | |
893 | irqreturn_t ret = IRQ_HANDLED; | |
894 | ||
895 | spin_lock_irqsave(&emif_lock, irq_state); | |
896 | old_temp_level = emif->temperature_level; | |
897 | get_temperature_level(emif); | |
898 | ||
899 | if (unlikely(emif->temperature_level == old_temp_level)) { | |
900 | goto out; | |
901 | } else if (!emif->curr_regs) { | |
902 | dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n"); | |
903 | goto out; | |
904 | } | |
905 | ||
906 | if (emif->temperature_level < old_temp_level || | |
907 | emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) { | |
908 | /* | |
909 | * Temperature coming down - defer handling to thread OR | |
910 | * Temperature far too high - do kernel_power_off() from | |
911 | * thread context | |
912 | */ | |
913 | ret = IRQ_WAKE_THREAD; | |
914 | } else { | |
915 | /* Temperature is going up - handle immediately */ | |
916 | setup_temperature_sensitive_regs(emif, emif->curr_regs); | |
917 | do_freq_update(); | |
918 | } | |
919 | ||
920 | out: | |
921 | spin_unlock_irqrestore(&emif_lock, irq_state); | |
922 | return ret; | |
923 | } | |
924 | ||
925 | static irqreturn_t emif_interrupt_handler(int irq, void *dev_id) | |
926 | { | |
927 | u32 interrupts; | |
928 | struct emif_data *emif = dev_id; | |
929 | void __iomem *base = emif->base; | |
930 | struct device *dev = emif->dev; | |
931 | irqreturn_t ret = IRQ_HANDLED; | |
932 | ||
933 | /* Save the status and clear it */ | |
934 | interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); | |
935 | writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); | |
936 | ||
937 | /* | |
938 | * Handle temperature alert | |
939 | * Temperature alert should be same for all ports | |
940 | * So, it's enough to process it only for one of the ports | |
941 | */ | |
942 | if (interrupts & TA_SYS_MASK) | |
943 | ret = handle_temp_alert(base, emif); | |
944 | ||
945 | if (interrupts & ERR_SYS_MASK) | |
946 | dev_err(dev, "Access error from SYS port - %x\n", interrupts); | |
947 | ||
948 | if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) { | |
949 | /* Save the status and clear it */ | |
950 | interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS); | |
951 | writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS); | |
952 | ||
953 | if (interrupts & ERR_LL_MASK) | |
954 | dev_err(dev, "Access error from LL port - %x\n", | |
955 | interrupts); | |
956 | } | |
957 | ||
958 | return ret; | |
959 | } | |
960 | ||
961 | static irqreturn_t emif_threaded_isr(int irq, void *dev_id) | |
962 | { | |
963 | struct emif_data *emif = dev_id; | |
964 | ||
965 | if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) { | |
966 | dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n"); | |
967 | kernel_power_off(); | |
968 | return IRQ_HANDLED; | |
969 | } | |
970 | ||
971 | spin_lock_irqsave(&emif_lock, irq_state); | |
972 | ||
973 | if (emif->curr_regs) { | |
974 | setup_temperature_sensitive_regs(emif, emif->curr_regs); | |
975 | do_freq_update(); | |
976 | } else { | |
977 | dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n"); | |
978 | } | |
979 | ||
980 | spin_unlock_irqrestore(&emif_lock, irq_state); | |
981 | ||
982 | return IRQ_HANDLED; | |
983 | } | |
984 | ||
985 | static void clear_all_interrupts(struct emif_data *emif) | |
986 | { | |
987 | void __iomem *base = emif->base; | |
988 | ||
989 | writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS), | |
990 | base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); | |
991 | if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) | |
992 | writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS), | |
993 | base + EMIF_LL_OCP_INTERRUPT_STATUS); | |
994 | } | |
995 | ||
996 | static void disable_and_clear_all_interrupts(struct emif_data *emif) | |
997 | { | |
998 | void __iomem *base = emif->base; | |
999 | ||
1000 | /* Disable all interrupts */ | |
1001 | writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET), | |
1002 | base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR); | |
1003 | if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) | |
1004 | writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET), | |
1005 | base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR); | |
1006 | ||
1007 | /* Clear all interrupts */ | |
1008 | clear_all_interrupts(emif); | |
1009 | } | |
1010 | ||
1011 | static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq) | |
1012 | { | |
1013 | u32 interrupts, type; | |
1014 | void __iomem *base = emif->base; | |
1015 | ||
1016 | type = emif->plat_data->device_info->type; | |
1017 | ||
1018 | clear_all_interrupts(emif); | |
1019 | ||
1020 | /* Enable interrupts for SYS interface */ | |
1021 | interrupts = EN_ERR_SYS_MASK; | |
1022 | if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) | |
1023 | interrupts |= EN_TA_SYS_MASK; | |
1024 | writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET); | |
1025 | ||
1026 | /* Enable interrupts for LL interface */ | |
1027 | if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) { | |
1028 | /* TA need not be enabled for LL */ | |
1029 | interrupts = EN_ERR_LL_MASK; | |
1030 | writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET); | |
1031 | } | |
1032 | ||
1033 | /* setup IRQ handlers */ | |
1034 | return devm_request_threaded_irq(emif->dev, irq, | |
1035 | emif_interrupt_handler, | |
1036 | emif_threaded_isr, | |
1037 | 0, dev_name(emif->dev), | |
1038 | emif); | |
1039 | ||
1040 | } | |
1041 | ||
98231c4f A |
1042 | static void __init_or_module emif_onetime_settings(struct emif_data *emif) |
1043 | { | |
1044 | u32 pwr_mgmt_ctrl, zq, temp_alert_cfg; | |
1045 | void __iomem *base = emif->base; | |
1046 | const struct lpddr2_addressing *addressing; | |
1047 | const struct ddr_device_info *device_info; | |
1048 | ||
1049 | device_info = emif->plat_data->device_info; | |
1050 | addressing = get_addressing_table(device_info); | |
1051 | ||
1052 | /* | |
1053 | * Init power management settings | |
1054 | * We don't know the frequency yet. Use a high frequency | |
1055 | * value for a conservative timeout setting | |
1056 | */ | |
1057 | pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif, | |
1058 | emif->plat_data->ip_rev); | |
1059 | emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT; | |
1060 | writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL); | |
1061 | ||
1062 | /* Init ZQ calibration settings */ | |
1063 | zq = get_zq_config_reg(addressing, device_info->cs1_used, | |
1064 | device_info->cal_resistors_per_cs); | |
1065 | writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG); | |
1066 | ||
1067 | /* Check temperature level temperature level*/ | |
1068 | get_temperature_level(emif); | |
1069 | if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) | |
1070 | dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n"); | |
1071 | ||
1072 | /* Init temperature polling */ | |
1073 | temp_alert_cfg = get_temp_alert_config(addressing, | |
1074 | emif->plat_data->custom_configs, device_info->cs1_used, | |
1075 | device_info->io_width, get_emif_bus_width(emif)); | |
1076 | writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG); | |
1077 | ||
1078 | /* | |
1079 | * Program external PHY control registers that are not frequency | |
1080 | * dependent | |
1081 | */ | |
1082 | if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY) | |
1083 | return; | |
1084 | writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW); | |
1085 | writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW); | |
1086 | writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW); | |
1087 | writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW); | |
1088 | writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW); | |
1089 | writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW); | |
1090 | writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW); | |
1091 | writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW); | |
1092 | writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW); | |
1093 | writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW); | |
1094 | writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW); | |
1095 | writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW); | |
1096 | writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW); | |
1097 | writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW); | |
1098 | writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW); | |
1099 | writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW); | |
1100 | writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW); | |
1101 | writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW); | |
1102 | writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW); | |
1103 | writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW); | |
1104 | writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW); | |
1105 | } | |
1106 | ||
7ec94453 A |
1107 | static void get_default_timings(struct emif_data *emif) |
1108 | { | |
1109 | struct emif_platform_data *pd = emif->plat_data; | |
1110 | ||
1111 | pd->timings = lpddr2_jedec_timings; | |
1112 | pd->timings_arr_size = ARRAY_SIZE(lpddr2_jedec_timings); | |
1113 | ||
1114 | dev_warn(emif->dev, "%s: using default timings\n", __func__); | |
1115 | } | |
1116 | ||
1117 | static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type, | |
1118 | u32 ip_rev, struct device *dev) | |
1119 | { | |
1120 | int valid; | |
1121 | ||
1122 | valid = (type == DDR_TYPE_LPDDR2_S4 || | |
1123 | type == DDR_TYPE_LPDDR2_S2) | |
1124 | && (density >= DDR_DENSITY_64Mb | |
1125 | && density <= DDR_DENSITY_8Gb) | |
1126 | && (io_width >= DDR_IO_WIDTH_8 | |
1127 | && io_width <= DDR_IO_WIDTH_32); | |
1128 | ||
1129 | /* Combinations of EMIF and PHY revisions that we support today */ | |
1130 | switch (ip_rev) { | |
1131 | case EMIF_4D: | |
1132 | valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY); | |
1133 | break; | |
1134 | case EMIF_4D5: | |
1135 | valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY); | |
1136 | break; | |
1137 | default: | |
1138 | valid = 0; | |
1139 | } | |
1140 | ||
1141 | if (!valid) | |
1142 | dev_err(dev, "%s: invalid DDR details\n", __func__); | |
1143 | return valid; | |
1144 | } | |
1145 | ||
1146 | static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs, | |
1147 | struct device *dev) | |
1148 | { | |
1149 | int valid = 1; | |
1150 | ||
1151 | if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) && | |
1152 | (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE)) | |
1153 | valid = cust_cfgs->lpmode_freq_threshold && | |
1154 | cust_cfgs->lpmode_timeout_performance && | |
1155 | cust_cfgs->lpmode_timeout_power; | |
1156 | ||
1157 | if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL) | |
1158 | valid = valid && cust_cfgs->temp_alert_poll_interval_ms; | |
1159 | ||
1160 | if (!valid) | |
1161 | dev_warn(dev, "%s: invalid custom configs\n", __func__); | |
1162 | ||
1163 | return valid; | |
1164 | } | |
1165 | ||
e6b42eb6 A |
1166 | #if defined(CONFIG_OF) |
1167 | static void __init_or_module of_get_custom_configs(struct device_node *np_emif, | |
1168 | struct emif_data *emif) | |
1169 | { | |
1170 | struct emif_custom_configs *cust_cfgs = NULL; | |
1171 | int len; | |
1172 | const int *lpmode, *poll_intvl; | |
1173 | ||
1174 | lpmode = of_get_property(np_emif, "low-power-mode", &len); | |
1175 | poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len); | |
1176 | ||
1177 | if (lpmode || poll_intvl) | |
1178 | cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs), | |
1179 | GFP_KERNEL); | |
1180 | ||
1181 | if (!cust_cfgs) | |
1182 | return; | |
1183 | ||
1184 | if (lpmode) { | |
1185 | cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE; | |
1186 | cust_cfgs->lpmode = *lpmode; | |
1187 | of_property_read_u32(np_emif, | |
1188 | "low-power-mode-timeout-performance", | |
1189 | &cust_cfgs->lpmode_timeout_performance); | |
1190 | of_property_read_u32(np_emif, | |
1191 | "low-power-mode-timeout-power", | |
1192 | &cust_cfgs->lpmode_timeout_power); | |
1193 | of_property_read_u32(np_emif, | |
1194 | "low-power-mode-freq-threshold", | |
1195 | &cust_cfgs->lpmode_freq_threshold); | |
1196 | } | |
1197 | ||
1198 | if (poll_intvl) { | |
1199 | cust_cfgs->mask |= | |
1200 | EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL; | |
1201 | cust_cfgs->temp_alert_poll_interval_ms = *poll_intvl; | |
1202 | } | |
1203 | ||
1204 | if (!is_custom_config_valid(cust_cfgs, emif->dev)) { | |
1205 | devm_kfree(emif->dev, cust_cfgs); | |
1206 | return; | |
1207 | } | |
1208 | ||
1209 | emif->plat_data->custom_configs = cust_cfgs; | |
1210 | } | |
1211 | ||
1212 | static void __init_or_module of_get_ddr_info(struct device_node *np_emif, | |
1213 | struct device_node *np_ddr, | |
1214 | struct ddr_device_info *dev_info) | |
1215 | { | |
1216 | u32 density = 0, io_width = 0; | |
1217 | int len; | |
1218 | ||
1219 | if (of_find_property(np_emif, "cs1-used", &len)) | |
1220 | dev_info->cs1_used = true; | |
1221 | ||
1222 | if (of_find_property(np_emif, "cal-resistor-per-cs", &len)) | |
1223 | dev_info->cal_resistors_per_cs = true; | |
1224 | ||
1225 | if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s4")) | |
1226 | dev_info->type = DDR_TYPE_LPDDR2_S4; | |
1227 | else if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s2")) | |
1228 | dev_info->type = DDR_TYPE_LPDDR2_S2; | |
1229 | ||
1230 | of_property_read_u32(np_ddr, "density", &density); | |
1231 | of_property_read_u32(np_ddr, "io-width", &io_width); | |
1232 | ||
1233 | /* Convert from density in Mb to the density encoding in jedc_ddr.h */ | |
1234 | if (density & (density - 1)) | |
1235 | dev_info->density = 0; | |
1236 | else | |
1237 | dev_info->density = __fls(density) - 5; | |
1238 | ||
1239 | /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */ | |
1240 | if (io_width & (io_width - 1)) | |
1241 | dev_info->io_width = 0; | |
1242 | else | |
1243 | dev_info->io_width = __fls(io_width) - 1; | |
1244 | } | |
1245 | ||
1246 | static struct emif_data * __init_or_module of_get_memory_device_details( | |
1247 | struct device_node *np_emif, struct device *dev) | |
1248 | { | |
1249 | struct emif_data *emif = NULL; | |
1250 | struct ddr_device_info *dev_info = NULL; | |
1251 | struct emif_platform_data *pd = NULL; | |
1252 | struct device_node *np_ddr; | |
1253 | int len; | |
1254 | ||
1255 | np_ddr = of_parse_phandle(np_emif, "device-handle", 0); | |
1256 | if (!np_ddr) | |
1257 | goto error; | |
1258 | emif = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL); | |
1259 | pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); | |
1260 | dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL); | |
1261 | ||
1262 | if (!emif || !pd || !dev_info) { | |
1263 | dev_err(dev, "%s: Out of memory!!\n", | |
1264 | __func__); | |
1265 | goto error; | |
1266 | } | |
1267 | ||
1268 | emif->plat_data = pd; | |
1269 | pd->device_info = dev_info; | |
1270 | emif->dev = dev; | |
1271 | emif->np_ddr = np_ddr; | |
1272 | emif->temperature_level = SDRAM_TEMP_NOMINAL; | |
1273 | ||
1274 | if (of_device_is_compatible(np_emif, "ti,emif-4d")) | |
1275 | emif->plat_data->ip_rev = EMIF_4D; | |
1276 | else if (of_device_is_compatible(np_emif, "ti,emif-4d5")) | |
1277 | emif->plat_data->ip_rev = EMIF_4D5; | |
1278 | ||
1279 | of_property_read_u32(np_emif, "phy-type", &pd->phy_type); | |
1280 | ||
1281 | if (of_find_property(np_emif, "hw-caps-ll-interface", &len)) | |
1282 | pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE; | |
1283 | ||
1284 | of_get_ddr_info(np_emif, np_ddr, dev_info); | |
1285 | if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density, | |
1286 | pd->device_info->io_width, pd->phy_type, pd->ip_rev, | |
1287 | emif->dev)) { | |
1288 | dev_err(dev, "%s: invalid device data!!\n", __func__); | |
1289 | goto error; | |
1290 | } | |
1291 | /* | |
1292 | * For EMIF instances other than EMIF1 see if the devices connected | |
1293 | * are exactly same as on EMIF1(which is typically the case). If so, | |
1294 | * mark it as a duplicate of EMIF1. This will save some memory and | |
1295 | * computation. | |
1296 | */ | |
1297 | if (emif1 && emif1->np_ddr == np_ddr) { | |
1298 | emif->duplicate = true; | |
1299 | goto out; | |
1300 | } else if (emif1) { | |
1301 | dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n", | |
1302 | __func__); | |
1303 | } | |
1304 | ||
1305 | of_get_custom_configs(np_emif, emif); | |
1306 | emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev, | |
1307 | emif->plat_data->device_info->type, | |
1308 | &emif->plat_data->timings_arr_size); | |
1309 | ||
1310 | emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev); | |
1311 | goto out; | |
1312 | ||
1313 | error: | |
1314 | return NULL; | |
1315 | out: | |
1316 | return emif; | |
1317 | } | |
1318 | ||
1319 | #else | |
1320 | ||
1321 | static struct emif_data * __init_or_module of_get_memory_device_details( | |
1322 | struct device_node *np_emif, struct device *dev) | |
1323 | { | |
1324 | return NULL; | |
1325 | } | |
1326 | #endif | |
1327 | ||
7ec94453 A |
1328 | static struct emif_data *__init_or_module get_device_details( |
1329 | struct platform_device *pdev) | |
1330 | { | |
1331 | u32 size; | |
1332 | struct emif_data *emif = NULL; | |
1333 | struct ddr_device_info *dev_info; | |
1334 | struct emif_custom_configs *cust_cfgs; | |
1335 | struct emif_platform_data *pd; | |
1336 | struct device *dev; | |
1337 | void *temp; | |
1338 | ||
1339 | pd = pdev->dev.platform_data; | |
1340 | dev = &pdev->dev; | |
1341 | ||
1342 | if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type, | |
1343 | pd->device_info->density, pd->device_info->io_width, | |
1344 | pd->phy_type, pd->ip_rev, dev))) { | |
1345 | dev_err(dev, "%s: invalid device data\n", __func__); | |
1346 | goto error; | |
1347 | } | |
1348 | ||
1349 | emif = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL); | |
1350 | temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); | |
1351 | dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL); | |
1352 | ||
1353 | if (!emif || !pd || !dev_info) { | |
1354 | dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__); | |
1355 | goto error; | |
1356 | } | |
1357 | ||
1358 | memcpy(temp, pd, sizeof(*pd)); | |
1359 | pd = temp; | |
1360 | memcpy(dev_info, pd->device_info, sizeof(*dev_info)); | |
1361 | ||
1362 | pd->device_info = dev_info; | |
1363 | emif->plat_data = pd; | |
1364 | emif->dev = dev; | |
1365 | emif->temperature_level = SDRAM_TEMP_NOMINAL; | |
1366 | ||
1367 | /* | |
1368 | * For EMIF instances other than EMIF1 see if the devices connected | |
1369 | * are exactly same as on EMIF1(which is typically the case). If so, | |
1370 | * mark it as a duplicate of EMIF1 and skip copying timings data. | |
1371 | * This will save some memory and some computation later. | |
1372 | */ | |
1373 | emif->duplicate = emif1 && (memcmp(dev_info, | |
1374 | emif1->plat_data->device_info, | |
1375 | sizeof(struct ddr_device_info)) == 0); | |
1376 | ||
1377 | if (emif->duplicate) { | |
1378 | pd->timings = NULL; | |
1379 | pd->min_tck = NULL; | |
1380 | goto out; | |
1381 | } else if (emif1) { | |
1382 | dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n", | |
1383 | __func__); | |
1384 | } | |
1385 | ||
1386 | /* | |
1387 | * Copy custom configs - ignore allocation error, if any, as | |
1388 | * custom_configs is not very critical | |
1389 | */ | |
1390 | cust_cfgs = pd->custom_configs; | |
1391 | if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) { | |
1392 | temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL); | |
1393 | if (temp) | |
1394 | memcpy(temp, cust_cfgs, sizeof(*cust_cfgs)); | |
1395 | else | |
1396 | dev_warn(dev, "%s:%d: allocation error\n", __func__, | |
1397 | __LINE__); | |
1398 | pd->custom_configs = temp; | |
1399 | } | |
1400 | ||
1401 | /* | |
1402 | * Copy timings and min-tck values from platform data. If it is not | |
1403 | * available or if memory allocation fails, use JEDEC defaults | |
1404 | */ | |
1405 | size = sizeof(struct lpddr2_timings) * pd->timings_arr_size; | |
1406 | if (pd->timings) { | |
1407 | temp = devm_kzalloc(dev, size, GFP_KERNEL); | |
1408 | if (temp) { | |
1409 | memcpy(temp, pd->timings, sizeof(*pd->timings)); | |
1410 | pd->timings = temp; | |
1411 | } else { | |
1412 | dev_warn(dev, "%s:%d: allocation error\n", __func__, | |
1413 | __LINE__); | |
1414 | get_default_timings(emif); | |
1415 | } | |
1416 | } else { | |
1417 | get_default_timings(emif); | |
1418 | } | |
1419 | ||
1420 | if (pd->min_tck) { | |
1421 | temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL); | |
1422 | if (temp) { | |
1423 | memcpy(temp, pd->min_tck, sizeof(*pd->min_tck)); | |
1424 | pd->min_tck = temp; | |
1425 | } else { | |
1426 | dev_warn(dev, "%s:%d: allocation error\n", __func__, | |
1427 | __LINE__); | |
1428 | pd->min_tck = &lpddr2_jedec_min_tck; | |
1429 | } | |
1430 | } else { | |
1431 | pd->min_tck = &lpddr2_jedec_min_tck; | |
1432 | } | |
1433 | ||
1434 | out: | |
1435 | return emif; | |
1436 | ||
1437 | error: | |
1438 | return NULL; | |
1439 | } | |
1440 | ||
1441 | static int __init_or_module emif_probe(struct platform_device *pdev) | |
1442 | { | |
1443 | struct emif_data *emif; | |
1444 | struct resource *res; | |
68b4aee3 | 1445 | int irq; |
7ec94453 | 1446 | |
e6b42eb6 A |
1447 | if (pdev->dev.of_node) |
1448 | emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev); | |
1449 | else | |
1450 | emif = get_device_details(pdev); | |
1451 | ||
7ec94453 A |
1452 | if (!emif) { |
1453 | pr_err("%s: error getting device data\n", __func__); | |
1454 | goto error; | |
1455 | } | |
1456 | ||
7ec94453 | 1457 | list_add(&emif->node, &device_list); |
a93de288 | 1458 | emif->addressing = get_addressing_table(emif->plat_data->device_info); |
7ec94453 A |
1459 | |
1460 | /* Save pointers to each other in emif and device structures */ | |
1461 | emif->dev = &pdev->dev; | |
1462 | platform_set_drvdata(pdev, emif); | |
1463 | ||
1464 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1465 | if (!res) { | |
1466 | dev_err(emif->dev, "%s: error getting memory resource\n", | |
1467 | __func__); | |
1468 | goto error; | |
1469 | } | |
1470 | ||
1471 | emif->base = devm_request_and_ioremap(emif->dev, res); | |
1472 | if (!emif->base) { | |
1473 | dev_err(emif->dev, "%s: devm_request_and_ioremap() failed\n", | |
1474 | __func__); | |
1475 | goto error; | |
1476 | } | |
1477 | ||
68b4aee3 A |
1478 | irq = platform_get_irq(pdev, 0); |
1479 | if (irq < 0) { | |
1480 | dev_err(emif->dev, "%s: error getting IRQ resource - %d\n", | |
1481 | __func__, irq); | |
1482 | goto error; | |
1483 | } | |
1484 | ||
98231c4f | 1485 | emif_onetime_settings(emif); |
aac10aaa | 1486 | emif_debugfs_init(emif); |
68b4aee3 A |
1487 | disable_and_clear_all_interrupts(emif); |
1488 | setup_interrupts(emif, irq); | |
1489 | ||
a93de288 A |
1490 | /* One-time actions taken on probing the first device */ |
1491 | if (!emif1) { | |
1492 | emif1 = emif; | |
1493 | spin_lock_init(&emif_lock); | |
1494 | ||
1495 | /* | |
1496 | * TODO: register notifiers for frequency and voltage | |
1497 | * change here once the respective frameworks are | |
1498 | * available | |
1499 | */ | |
1500 | } | |
1501 | ||
68b4aee3 A |
1502 | dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n", |
1503 | __func__, emif->base, irq); | |
7ec94453 A |
1504 | |
1505 | return 0; | |
1506 | error: | |
1507 | return -ENODEV; | |
1508 | } | |
1509 | ||
aac10aaa A |
1510 | static int __exit emif_remove(struct platform_device *pdev) |
1511 | { | |
1512 | struct emif_data *emif = platform_get_drvdata(pdev); | |
1513 | ||
1514 | emif_debugfs_exit(emif); | |
1515 | ||
1516 | return 0; | |
1517 | } | |
1518 | ||
68b4aee3 A |
1519 | static void emif_shutdown(struct platform_device *pdev) |
1520 | { | |
1521 | struct emif_data *emif = platform_get_drvdata(pdev); | |
1522 | ||
1523 | disable_and_clear_all_interrupts(emif); | |
1524 | } | |
1525 | ||
a93de288 A |
1526 | static int get_emif_reg_values(struct emif_data *emif, u32 freq, |
1527 | struct emif_regs *regs) | |
1528 | { | |
1529 | u32 cs1_used, ip_rev, phy_type; | |
1530 | u32 cl, type; | |
1531 | const struct lpddr2_timings *timings; | |
1532 | const struct lpddr2_min_tck *min_tck; | |
1533 | const struct ddr_device_info *device_info; | |
1534 | const struct lpddr2_addressing *addressing; | |
1535 | struct emif_data *emif_for_calc; | |
1536 | struct device *dev; | |
1537 | const struct emif_custom_configs *custom_configs; | |
1538 | ||
1539 | dev = emif->dev; | |
1540 | /* | |
1541 | * If the devices on this EMIF instance is duplicate of EMIF1, | |
1542 | * use EMIF1 details for the calculation | |
1543 | */ | |
1544 | emif_for_calc = emif->duplicate ? emif1 : emif; | |
1545 | timings = get_timings_table(emif_for_calc, freq); | |
1546 | addressing = emif_for_calc->addressing; | |
1547 | if (!timings || !addressing) { | |
1548 | dev_err(dev, "%s: not enough data available for %dHz", | |
1549 | __func__, freq); | |
1550 | return -1; | |
1551 | } | |
1552 | ||
1553 | device_info = emif_for_calc->plat_data->device_info; | |
1554 | type = device_info->type; | |
1555 | cs1_used = device_info->cs1_used; | |
1556 | ip_rev = emif_for_calc->plat_data->ip_rev; | |
1557 | phy_type = emif_for_calc->plat_data->phy_type; | |
1558 | ||
1559 | min_tck = emif_for_calc->plat_data->min_tck; | |
1560 | custom_configs = emif_for_calc->plat_data->custom_configs; | |
1561 | ||
1562 | set_ddr_clk_period(freq); | |
1563 | ||
1564 | regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing); | |
1565 | regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck, | |
1566 | addressing); | |
1567 | regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck, | |
1568 | addressing, type); | |
1569 | regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck, | |
1570 | addressing, type, ip_rev, EMIF_NORMAL_TIMINGS); | |
1571 | ||
1572 | cl = get_cl(emif); | |
1573 | ||
1574 | if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) { | |
1575 | regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d( | |
1576 | timings, freq, cl); | |
1577 | } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) { | |
1578 | regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl); | |
1579 | regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5(); | |
1580 | regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5(); | |
1581 | regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5(); | |
1582 | } else { | |
1583 | return -1; | |
1584 | } | |
1585 | ||
1586 | /* Only timeout values in pwr_mgmt_ctrl_shdw register */ | |
1587 | regs->pwr_mgmt_ctrl_shdw = | |
1588 | get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) & | |
1589 | (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK); | |
1590 | ||
1591 | if (ip_rev & EMIF_4D) { | |
1592 | regs->read_idle_ctrl_shdw_normal = | |
1593 | get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE); | |
1594 | ||
1595 | regs->read_idle_ctrl_shdw_volt_ramp = | |
1596 | get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING); | |
1597 | } else if (ip_rev & EMIF_4D5) { | |
1598 | regs->dll_calib_ctrl_shdw_normal = | |
1599 | get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE); | |
1600 | ||
1601 | regs->dll_calib_ctrl_shdw_volt_ramp = | |
1602 | get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING); | |
1603 | } | |
1604 | ||
1605 | if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) { | |
1606 | regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4, | |
1607 | addressing); | |
1608 | ||
1609 | regs->sdram_tim1_shdw_derated = | |
1610 | get_sdram_tim_1_shdw_derated(timings, min_tck, | |
1611 | addressing); | |
1612 | ||
1613 | regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings, | |
1614 | min_tck, addressing, type, ip_rev, | |
1615 | EMIF_DERATED_TIMINGS); | |
1616 | } | |
1617 | ||
1618 | regs->freq = freq; | |
1619 | ||
1620 | return 0; | |
1621 | } | |
1622 | ||
1623 | /* | |
1624 | * get_regs() - gets the cached emif_regs structure for a given EMIF instance | |
1625 | * given frequency(freq): | |
1626 | * | |
1627 | * As an optimisation, every EMIF instance other than EMIF1 shares the | |
1628 | * register cache with EMIF1 if the devices connected on this instance | |
1629 | * are same as that on EMIF1(indicated by the duplicate flag) | |
1630 | * | |
1631 | * If we do not have an entry corresponding to the frequency given, we | |
1632 | * allocate a new entry and calculate the values | |
1633 | * | |
1634 | * Upon finding the right reg dump, save it in curr_regs. It can be | |
1635 | * directly used for thermal de-rating and voltage ramping changes. | |
1636 | */ | |
1637 | static struct emif_regs *get_regs(struct emif_data *emif, u32 freq) | |
1638 | { | |
1639 | int i; | |
1640 | struct emif_regs **regs_cache; | |
1641 | struct emif_regs *regs = NULL; | |
1642 | struct device *dev; | |
1643 | ||
1644 | dev = emif->dev; | |
1645 | if (emif->curr_regs && emif->curr_regs->freq == freq) { | |
1646 | dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq); | |
1647 | return emif->curr_regs; | |
1648 | } | |
1649 | ||
1650 | if (emif->duplicate) | |
1651 | regs_cache = emif1->regs_cache; | |
1652 | else | |
1653 | regs_cache = emif->regs_cache; | |
1654 | ||
1655 | for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) { | |
1656 | if (regs_cache[i]->freq == freq) { | |
1657 | regs = regs_cache[i]; | |
1658 | dev_dbg(dev, | |
1659 | "%s: reg dump found in reg cache for %u Hz\n", | |
1660 | __func__, freq); | |
1661 | break; | |
1662 | } | |
1663 | } | |
1664 | ||
1665 | /* | |
1666 | * If we don't have an entry for this frequency in the cache create one | |
1667 | * and calculate the values | |
1668 | */ | |
1669 | if (!regs) { | |
1670 | regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC); | |
1671 | if (!regs) | |
1672 | return NULL; | |
1673 | ||
1674 | if (get_emif_reg_values(emif, freq, regs)) { | |
1675 | devm_kfree(emif->dev, regs); | |
1676 | return NULL; | |
1677 | } | |
1678 | ||
1679 | /* | |
1680 | * Now look for an un-used entry in the cache and save the | |
1681 | * newly created struct. If there are no free entries | |
1682 | * over-write the last entry | |
1683 | */ | |
1684 | for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) | |
1685 | ; | |
1686 | ||
1687 | if (i >= EMIF_MAX_NUM_FREQUENCIES) { | |
1688 | dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n", | |
1689 | __func__); | |
1690 | i = EMIF_MAX_NUM_FREQUENCIES - 1; | |
1691 | devm_kfree(emif->dev, regs_cache[i]); | |
1692 | } | |
1693 | regs_cache[i] = regs; | |
1694 | } | |
1695 | ||
1696 | return regs; | |
1697 | } | |
1698 | ||
1699 | static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state) | |
1700 | { | |
1701 | dev_dbg(emif->dev, "%s: voltage notification : %d", __func__, | |
1702 | volt_state); | |
1703 | ||
1704 | if (!emif->curr_regs) { | |
1705 | dev_err(emif->dev, | |
1706 | "%s: volt-notify before registers are ready: %d\n", | |
1707 | __func__, volt_state); | |
1708 | return; | |
1709 | } | |
1710 | ||
1711 | setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state); | |
1712 | } | |
1713 | ||
1714 | /* | |
1715 | * TODO: voltage notify handling should be hooked up to | |
1716 | * regulator framework as soon as the necessary support | |
1717 | * is available in mainline kernel. This function is un-used | |
1718 | * right now. | |
1719 | */ | |
1720 | static void __attribute__((unused)) volt_notify_handling(u32 volt_state) | |
1721 | { | |
1722 | struct emif_data *emif; | |
1723 | ||
1724 | spin_lock_irqsave(&emif_lock, irq_state); | |
1725 | ||
1726 | list_for_each_entry(emif, &device_list, node) | |
1727 | do_volt_notify_handling(emif, volt_state); | |
1728 | do_freq_update(); | |
1729 | ||
1730 | spin_unlock_irqrestore(&emif_lock, irq_state); | |
1731 | } | |
1732 | ||
1733 | static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq) | |
1734 | { | |
1735 | struct emif_regs *regs; | |
1736 | ||
1737 | regs = get_regs(emif, new_freq); | |
1738 | if (!regs) | |
1739 | return; | |
1740 | ||
1741 | emif->curr_regs = regs; | |
1742 | ||
1743 | /* | |
1744 | * Update the shadow registers: | |
1745 | * Temperature and voltage-ramp sensitive settings are also configured | |
1746 | * in terms of DDR cycles. So, we need to update them too when there | |
1747 | * is a freq change | |
1748 | */ | |
1749 | dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz", | |
1750 | __func__, new_freq); | |
1751 | setup_registers(emif, regs); | |
1752 | setup_temperature_sensitive_regs(emif, regs); | |
1753 | setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE); | |
1754 | ||
1755 | /* | |
1756 | * Part of workaround for errata i728. See do_freq_update() | |
1757 | * for more details | |
1758 | */ | |
1759 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) | |
1760 | set_lpmode(emif, EMIF_LP_MODE_DISABLE); | |
1761 | } | |
1762 | ||
1763 | /* | |
1764 | * TODO: frequency notify handling should be hooked up to | |
1765 | * clock framework as soon as the necessary support is | |
1766 | * available in mainline kernel. This function is un-used | |
1767 | * right now. | |
1768 | */ | |
1769 | static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq) | |
1770 | { | |
1771 | struct emif_data *emif; | |
1772 | ||
1773 | /* | |
1774 | * NOTE: we are taking the spin-lock here and releases it | |
1775 | * only in post-notifier. This doesn't look good and | |
1776 | * Sparse complains about it, but this seems to be | |
1777 | * un-avoidable. We need to lock a sequence of events | |
1778 | * that is split between EMIF and clock framework. | |
1779 | * | |
1780 | * 1. EMIF driver updates EMIF timings in shadow registers in the | |
1781 | * frequency pre-notify callback from clock framework | |
1782 | * 2. clock framework sets up the registers for the new frequency | |
1783 | * 3. clock framework initiates a hw-sequence that updates | |
1784 | * the frequency EMIF timings synchronously. | |
1785 | * | |
1786 | * All these 3 steps should be performed as an atomic operation | |
1787 | * vis-a-vis similar sequence in the EMIF interrupt handler | |
1788 | * for temperature events. Otherwise, there could be race | |
1789 | * conditions that could result in incorrect EMIF timings for | |
1790 | * a given frequency | |
1791 | */ | |
1792 | spin_lock_irqsave(&emif_lock, irq_state); | |
1793 | ||
1794 | list_for_each_entry(emif, &device_list, node) | |
1795 | do_freq_pre_notify_handling(emif, new_freq); | |
1796 | } | |
1797 | ||
1798 | static void do_freq_post_notify_handling(struct emif_data *emif) | |
1799 | { | |
1800 | /* | |
1801 | * Part of workaround for errata i728. See do_freq_update() | |
1802 | * for more details | |
1803 | */ | |
1804 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) | |
1805 | set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH); | |
1806 | } | |
1807 | ||
1808 | /* | |
1809 | * TODO: frequency notify handling should be hooked up to | |
1810 | * clock framework as soon as the necessary support is | |
1811 | * available in mainline kernel. This function is un-used | |
1812 | * right now. | |
1813 | */ | |
1814 | static void __attribute__((unused)) freq_post_notify_handling(void) | |
1815 | { | |
1816 | struct emif_data *emif; | |
1817 | ||
1818 | list_for_each_entry(emif, &device_list, node) | |
1819 | do_freq_post_notify_handling(emif); | |
1820 | ||
1821 | /* | |
1822 | * Lock is done in pre-notify handler. See freq_pre_notify_handling() | |
1823 | * for more details | |
1824 | */ | |
1825 | spin_unlock_irqrestore(&emif_lock, irq_state); | |
1826 | } | |
1827 | ||
e6b42eb6 A |
1828 | #if defined(CONFIG_OF) |
1829 | static const struct of_device_id emif_of_match[] = { | |
1830 | { .compatible = "ti,emif-4d" }, | |
1831 | { .compatible = "ti,emif-4d5" }, | |
1832 | {}, | |
1833 | }; | |
1834 | MODULE_DEVICE_TABLE(of, emif_of_match); | |
1835 | #endif | |
1836 | ||
7ec94453 | 1837 | static struct platform_driver emif_driver = { |
aac10aaa | 1838 | .remove = __exit_p(emif_remove), |
68b4aee3 | 1839 | .shutdown = emif_shutdown, |
7ec94453 A |
1840 | .driver = { |
1841 | .name = "emif", | |
e6b42eb6 | 1842 | .of_match_table = of_match_ptr(emif_of_match), |
7ec94453 A |
1843 | }, |
1844 | }; | |
1845 | ||
1846 | static int __init_or_module emif_register(void) | |
1847 | { | |
1848 | return platform_driver_probe(&emif_driver, emif_probe); | |
1849 | } | |
1850 | ||
1851 | static void __exit emif_unregister(void) | |
1852 | { | |
1853 | platform_driver_unregister(&emif_driver); | |
1854 | } | |
1855 | ||
1856 | module_init(emif_register); | |
1857 | module_exit(emif_unregister); | |
1858 | MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver"); | |
1859 | MODULE_LICENSE("GPL"); | |
1860 | MODULE_ALIAS("platform:emif"); | |
1861 | MODULE_AUTHOR("Texas Instruments Inc"); |