Commit | Line | Data |
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cfb61a41 | 1 | /* |
4fd41151 | 2 | * MFD core driver for the X-Powers' Power Management ICs |
cfb61a41 | 3 | * |
af7e9069 JP |
4 | * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC |
5 | * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature | |
6 | * as well as configurable GPIOs. | |
cfb61a41 | 7 | * |
4fd41151 CYT |
8 | * This file contains the interface independent core functions. |
9 | * | |
e740235d CYT |
10 | * Copyright (C) 2014 Carlo Caione |
11 | * | |
cfb61a41 CC |
12 | * Author: Carlo Caione <carlo@caione.org> |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | ||
19 | #include <linux/err.h> | |
179dc63d | 20 | #include <linux/delay.h> |
cfb61a41 CC |
21 | #include <linux/interrupt.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/regmap.h> | |
cfb61a41 CC |
26 | #include <linux/regulator/consumer.h> |
27 | #include <linux/mfd/axp20x.h> | |
28 | #include <linux/mfd/core.h> | |
29 | #include <linux/of_device.h> | |
af7e9069 | 30 | #include <linux/acpi.h> |
cfb61a41 CC |
31 | |
32 | #define AXP20X_OFF 0x80 | |
33 | ||
c31e858b | 34 | static const char * const axp20x_model_names[] = { |
d8d79f8f | 35 | "AXP152", |
af7e9069 JP |
36 | "AXP202", |
37 | "AXP209", | |
f05be589 | 38 | "AXP221", |
02071f0f | 39 | "AXP223", |
af7e9069 | 40 | "AXP288", |
20147f0d | 41 | "AXP809", |
af7e9069 JP |
42 | }; |
43 | ||
d8d79f8f MS |
44 | static const struct regmap_range axp152_writeable_ranges[] = { |
45 | regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE), | |
46 | regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE), | |
47 | }; | |
48 | ||
49 | static const struct regmap_range axp152_volatile_ranges[] = { | |
50 | regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE), | |
51 | regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE), | |
52 | regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT), | |
53 | }; | |
54 | ||
55 | static const struct regmap_access_table axp152_writeable_table = { | |
56 | .yes_ranges = axp152_writeable_ranges, | |
57 | .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges), | |
58 | }; | |
59 | ||
60 | static const struct regmap_access_table axp152_volatile_table = { | |
61 | .yes_ranges = axp152_volatile_ranges, | |
62 | .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges), | |
63 | }; | |
64 | ||
cfb61a41 CC |
65 | static const struct regmap_range axp20x_writeable_ranges[] = { |
66 | regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE), | |
67 | regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES), | |
553ed4b5 | 68 | regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)), |
cfb61a41 CC |
69 | }; |
70 | ||
71 | static const struct regmap_range axp20x_volatile_ranges[] = { | |
553ed4b5 BP |
72 | regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS), |
73 | regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2), | |
cfb61a41 | 74 | regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE), |
553ed4b5 BP |
75 | regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L), |
76 | regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL), | |
77 | regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L), | |
cfb61a41 CC |
78 | }; |
79 | ||
80 | static const struct regmap_access_table axp20x_writeable_table = { | |
81 | .yes_ranges = axp20x_writeable_ranges, | |
82 | .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges), | |
83 | }; | |
84 | ||
85 | static const struct regmap_access_table axp20x_volatile_table = { | |
86 | .yes_ranges = axp20x_volatile_ranges, | |
87 | .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges), | |
88 | }; | |
89 | ||
20147f0d | 90 | /* AXP22x ranges are shared with the AXP809, as they cover the same range */ |
f05be589 BB |
91 | static const struct regmap_range axp22x_writeable_ranges[] = { |
92 | regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE), | |
93 | regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1), | |
94 | }; | |
95 | ||
96 | static const struct regmap_range axp22x_volatile_ranges[] = { | |
15093250 | 97 | regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE), |
f05be589 | 98 | regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE), |
15093250 HG |
99 | regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE), |
100 | regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES), | |
f05be589 BB |
101 | }; |
102 | ||
103 | static const struct regmap_access_table axp22x_writeable_table = { | |
104 | .yes_ranges = axp22x_writeable_ranges, | |
105 | .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges), | |
106 | }; | |
107 | ||
108 | static const struct regmap_access_table axp22x_volatile_table = { | |
109 | .yes_ranges = axp22x_volatile_ranges, | |
110 | .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges), | |
111 | }; | |
112 | ||
af7e9069 JP |
113 | static const struct regmap_range axp288_writeable_ranges[] = { |
114 | regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE), | |
115 | regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5), | |
116 | }; | |
117 | ||
118 | static const struct regmap_range axp288_volatile_ranges[] = { | |
119 | regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L), | |
120 | }; | |
121 | ||
122 | static const struct regmap_access_table axp288_writeable_table = { | |
123 | .yes_ranges = axp288_writeable_ranges, | |
124 | .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges), | |
125 | }; | |
126 | ||
127 | static const struct regmap_access_table axp288_volatile_table = { | |
128 | .yes_ranges = axp288_volatile_ranges, | |
129 | .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges), | |
130 | }; | |
131 | ||
d8d79f8f MS |
132 | static struct resource axp152_pek_resources[] = { |
133 | DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"), | |
134 | DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"), | |
135 | }; | |
136 | ||
cd7cf27b MH |
137 | static struct resource axp20x_ac_power_supply_resources[] = { |
138 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"), | |
139 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"), | |
140 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"), | |
141 | }; | |
142 | ||
cfb61a41 CC |
143 | static struct resource axp20x_pek_resources[] = { |
144 | { | |
145 | .name = "PEK_DBR", | |
146 | .start = AXP20X_IRQ_PEK_RIS_EDGE, | |
147 | .end = AXP20X_IRQ_PEK_RIS_EDGE, | |
148 | .flags = IORESOURCE_IRQ, | |
149 | }, { | |
150 | .name = "PEK_DBF", | |
151 | .start = AXP20X_IRQ_PEK_FAL_EDGE, | |
152 | .end = AXP20X_IRQ_PEK_FAL_EDGE, | |
153 | .flags = IORESOURCE_IRQ, | |
154 | }, | |
155 | }; | |
156 | ||
8de4efda HG |
157 | static struct resource axp20x_usb_power_supply_resources[] = { |
158 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"), | |
159 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"), | |
160 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"), | |
161 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"), | |
162 | }; | |
163 | ||
ecd98cce HG |
164 | static struct resource axp22x_usb_power_supply_resources[] = { |
165 | DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"), | |
166 | DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"), | |
167 | }; | |
168 | ||
f05be589 BB |
169 | static struct resource axp22x_pek_resources[] = { |
170 | { | |
171 | .name = "PEK_DBR", | |
172 | .start = AXP22X_IRQ_PEK_RIS_EDGE, | |
173 | .end = AXP22X_IRQ_PEK_RIS_EDGE, | |
174 | .flags = IORESOURCE_IRQ, | |
175 | }, { | |
176 | .name = "PEK_DBF", | |
177 | .start = AXP22X_IRQ_PEK_FAL_EDGE, | |
178 | .end = AXP22X_IRQ_PEK_FAL_EDGE, | |
179 | .flags = IORESOURCE_IRQ, | |
180 | }, | |
181 | }; | |
182 | ||
e56e5ad6 BF |
183 | static struct resource axp288_power_button_resources[] = { |
184 | { | |
185 | .name = "PEK_DBR", | |
186 | .start = AXP288_IRQ_POKN, | |
187 | .end = AXP288_IRQ_POKN, | |
188 | .flags = IORESOURCE_IRQ, | |
189 | }, | |
190 | { | |
191 | .name = "PEK_DBF", | |
192 | .start = AXP288_IRQ_POKP, | |
193 | .end = AXP288_IRQ_POKP, | |
194 | .flags = IORESOURCE_IRQ, | |
195 | }, | |
196 | }; | |
197 | ||
d6387874 | 198 | static struct resource axp288_fuel_gauge_resources[] = { |
af7e9069 JP |
199 | { |
200 | .start = AXP288_IRQ_QWBTU, | |
201 | .end = AXP288_IRQ_QWBTU, | |
202 | .flags = IORESOURCE_IRQ, | |
203 | }, | |
204 | { | |
205 | .start = AXP288_IRQ_WBTU, | |
206 | .end = AXP288_IRQ_WBTU, | |
207 | .flags = IORESOURCE_IRQ, | |
208 | }, | |
209 | { | |
210 | .start = AXP288_IRQ_QWBTO, | |
211 | .end = AXP288_IRQ_QWBTO, | |
212 | .flags = IORESOURCE_IRQ, | |
213 | }, | |
214 | { | |
215 | .start = AXP288_IRQ_WBTO, | |
216 | .end = AXP288_IRQ_WBTO, | |
217 | .flags = IORESOURCE_IRQ, | |
218 | }, | |
219 | { | |
220 | .start = AXP288_IRQ_WL2, | |
221 | .end = AXP288_IRQ_WL2, | |
222 | .flags = IORESOURCE_IRQ, | |
223 | }, | |
224 | { | |
225 | .start = AXP288_IRQ_WL1, | |
226 | .end = AXP288_IRQ_WL1, | |
227 | .flags = IORESOURCE_IRQ, | |
228 | }, | |
229 | }; | |
230 | ||
20147f0d CYT |
231 | static struct resource axp809_pek_resources[] = { |
232 | { | |
233 | .name = "PEK_DBR", | |
234 | .start = AXP809_IRQ_PEK_RIS_EDGE, | |
235 | .end = AXP809_IRQ_PEK_RIS_EDGE, | |
236 | .flags = IORESOURCE_IRQ, | |
237 | }, { | |
238 | .name = "PEK_DBF", | |
239 | .start = AXP809_IRQ_PEK_FAL_EDGE, | |
240 | .end = AXP809_IRQ_PEK_FAL_EDGE, | |
241 | .flags = IORESOURCE_IRQ, | |
242 | }, | |
243 | }; | |
244 | ||
d8d79f8f MS |
245 | static const struct regmap_config axp152_regmap_config = { |
246 | .reg_bits = 8, | |
247 | .val_bits = 8, | |
248 | .wr_table = &axp152_writeable_table, | |
249 | .volatile_table = &axp152_volatile_table, | |
250 | .max_register = AXP152_PWM1_DUTY_CYCLE, | |
251 | .cache_type = REGCACHE_RBTREE, | |
252 | }; | |
253 | ||
cfb61a41 CC |
254 | static const struct regmap_config axp20x_regmap_config = { |
255 | .reg_bits = 8, | |
256 | .val_bits = 8, | |
257 | .wr_table = &axp20x_writeable_table, | |
258 | .volatile_table = &axp20x_volatile_table, | |
553ed4b5 | 259 | .max_register = AXP20X_OCV(AXP20X_OCV_MAX), |
cfb61a41 CC |
260 | .cache_type = REGCACHE_RBTREE, |
261 | }; | |
262 | ||
f05be589 BB |
263 | static const struct regmap_config axp22x_regmap_config = { |
264 | .reg_bits = 8, | |
265 | .val_bits = 8, | |
266 | .wr_table = &axp22x_writeable_table, | |
267 | .volatile_table = &axp22x_volatile_table, | |
268 | .max_register = AXP22X_BATLOW_THRES1, | |
269 | .cache_type = REGCACHE_RBTREE, | |
270 | }; | |
271 | ||
af7e9069 JP |
272 | static const struct regmap_config axp288_regmap_config = { |
273 | .reg_bits = 8, | |
274 | .val_bits = 8, | |
275 | .wr_table = &axp288_writeable_table, | |
276 | .volatile_table = &axp288_volatile_table, | |
277 | .max_register = AXP288_FG_TUNE5, | |
278 | .cache_type = REGCACHE_RBTREE, | |
279 | }; | |
280 | ||
281 | #define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \ | |
282 | [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) } | |
cfb61a41 | 283 | |
d8d79f8f MS |
284 | static const struct regmap_irq axp152_regmap_irqs[] = { |
285 | INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6), | |
286 | INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5), | |
287 | INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3), | |
288 | INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2), | |
289 | INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5), | |
290 | INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4), | |
291 | INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3), | |
292 | INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2), | |
293 | INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1), | |
294 | INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0), | |
295 | INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7), | |
296 | INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6), | |
297 | INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5), | |
298 | INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3), | |
299 | INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2), | |
300 | INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1), | |
301 | INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0), | |
302 | }; | |
303 | ||
cfb61a41 | 304 | static const struct regmap_irq axp20x_regmap_irqs[] = { |
af7e9069 JP |
305 | INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7), |
306 | INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6), | |
307 | INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5), | |
308 | INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4), | |
309 | INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3), | |
310 | INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2), | |
311 | INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1), | |
312 | INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7), | |
313 | INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6), | |
314 | INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5), | |
315 | INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4), | |
316 | INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3), | |
317 | INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2), | |
318 | INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1), | |
319 | INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0), | |
320 | INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7), | |
321 | INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6), | |
322 | INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5), | |
323 | INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4), | |
324 | INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3), | |
325 | INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1), | |
326 | INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0), | |
327 | INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7), | |
328 | INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6), | |
329 | INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5), | |
330 | INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4), | |
331 | INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3), | |
332 | INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2), | |
333 | INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1), | |
334 | INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0), | |
335 | INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7), | |
336 | INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6), | |
337 | INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5), | |
338 | INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3), | |
339 | INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2), | |
340 | INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1), | |
341 | INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0), | |
342 | }; | |
343 | ||
f05be589 BB |
344 | static const struct regmap_irq axp22x_regmap_irqs[] = { |
345 | INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7), | |
346 | INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6), | |
347 | INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5), | |
348 | INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4), | |
349 | INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3), | |
350 | INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2), | |
351 | INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1), | |
352 | INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7), | |
353 | INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6), | |
354 | INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5), | |
355 | INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4), | |
356 | INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3), | |
357 | INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2), | |
358 | INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1), | |
359 | INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0), | |
360 | INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7), | |
361 | INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1), | |
362 | INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0), | |
363 | INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1), | |
364 | INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0), | |
365 | INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7), | |
366 | INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6), | |
367 | INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5), | |
368 | INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1), | |
369 | INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0), | |
370 | }; | |
371 | ||
af7e9069 JP |
372 | /* some IRQs are compatible with axp20x models */ |
373 | static const struct regmap_irq axp288_regmap_irqs[] = { | |
ff3bbc5c JP |
374 | INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2), |
375 | INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3), | |
376 | INIT_REGMAP_IRQ(AXP288, OV, 0, 4), | |
af7e9069 | 377 | |
ff3bbc5c JP |
378 | INIT_REGMAP_IRQ(AXP288, DONE, 1, 2), |
379 | INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3), | |
af7e9069 JP |
380 | INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4), |
381 | INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5), | |
ff3bbc5c JP |
382 | INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6), |
383 | INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7), | |
af7e9069 JP |
384 | |
385 | INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0), | |
386 | INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1), | |
387 | INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2), | |
ff3bbc5c | 388 | INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3), |
af7e9069 JP |
389 | INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4), |
390 | INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5), | |
391 | INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6), | |
392 | INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7), | |
393 | ||
394 | INIT_REGMAP_IRQ(AXP288, WL2, 3, 0), | |
395 | INIT_REGMAP_IRQ(AXP288, WL1, 3, 1), | |
396 | INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2), | |
397 | INIT_REGMAP_IRQ(AXP288, OT, 3, 7), | |
398 | ||
399 | INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0), | |
400 | INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1), | |
401 | INIT_REGMAP_IRQ(AXP288, POKO, 4, 2), | |
402 | INIT_REGMAP_IRQ(AXP288, POKL, 4, 3), | |
403 | INIT_REGMAP_IRQ(AXP288, POKS, 4, 4), | |
404 | INIT_REGMAP_IRQ(AXP288, POKN, 4, 5), | |
405 | INIT_REGMAP_IRQ(AXP288, POKP, 4, 6), | |
ff3bbc5c | 406 | INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7), |
af7e9069 JP |
407 | |
408 | INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0), | |
409 | INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1), | |
cfb61a41 CC |
410 | }; |
411 | ||
20147f0d CYT |
412 | static const struct regmap_irq axp809_regmap_irqs[] = { |
413 | INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7), | |
414 | INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6), | |
415 | INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5), | |
416 | INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4), | |
417 | INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3), | |
418 | INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2), | |
419 | INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1), | |
420 | INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7), | |
421 | INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6), | |
422 | INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5), | |
423 | INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4), | |
424 | INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3), | |
425 | INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2), | |
426 | INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7), | |
427 | INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6), | |
428 | INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5), | |
429 | INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4), | |
430 | INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3), | |
431 | INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2), | |
432 | INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1), | |
433 | INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0), | |
434 | INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7), | |
435 | INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1), | |
436 | INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0), | |
437 | INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7), | |
438 | INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6), | |
439 | INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5), | |
440 | INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4), | |
441 | INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3), | |
442 | INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2), | |
443 | INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1), | |
444 | INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0), | |
445 | }; | |
446 | ||
d8d79f8f MS |
447 | static const struct regmap_irq_chip axp152_regmap_irq_chip = { |
448 | .name = "axp152_irq_chip", | |
449 | .status_base = AXP152_IRQ1_STATE, | |
450 | .ack_base = AXP152_IRQ1_STATE, | |
451 | .mask_base = AXP152_IRQ1_EN, | |
452 | .mask_invert = true, | |
453 | .init_ack_masked = true, | |
454 | .irqs = axp152_regmap_irqs, | |
455 | .num_irqs = ARRAY_SIZE(axp152_regmap_irqs), | |
456 | .num_regs = 3, | |
457 | }; | |
458 | ||
cfb61a41 CC |
459 | static const struct regmap_irq_chip axp20x_regmap_irq_chip = { |
460 | .name = "axp20x_irq_chip", | |
461 | .status_base = AXP20X_IRQ1_STATE, | |
462 | .ack_base = AXP20X_IRQ1_STATE, | |
463 | .mask_base = AXP20X_IRQ1_EN, | |
af7e9069 JP |
464 | .mask_invert = true, |
465 | .init_ack_masked = true, | |
cfb61a41 CC |
466 | .irqs = axp20x_regmap_irqs, |
467 | .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs), | |
af7e9069 JP |
468 | .num_regs = 5, |
469 | ||
470 | }; | |
471 | ||
f05be589 BB |
472 | static const struct regmap_irq_chip axp22x_regmap_irq_chip = { |
473 | .name = "axp22x_irq_chip", | |
474 | .status_base = AXP20X_IRQ1_STATE, | |
475 | .ack_base = AXP20X_IRQ1_STATE, | |
476 | .mask_base = AXP20X_IRQ1_EN, | |
477 | .mask_invert = true, | |
478 | .init_ack_masked = true, | |
479 | .irqs = axp22x_regmap_irqs, | |
480 | .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs), | |
481 | .num_regs = 5, | |
482 | }; | |
483 | ||
af7e9069 JP |
484 | static const struct regmap_irq_chip axp288_regmap_irq_chip = { |
485 | .name = "axp288_irq_chip", | |
486 | .status_base = AXP20X_IRQ1_STATE, | |
487 | .ack_base = AXP20X_IRQ1_STATE, | |
488 | .mask_base = AXP20X_IRQ1_EN, | |
cfb61a41 CC |
489 | .mask_invert = true, |
490 | .init_ack_masked = true, | |
af7e9069 JP |
491 | .irqs = axp288_regmap_irqs, |
492 | .num_irqs = ARRAY_SIZE(axp288_regmap_irqs), | |
493 | .num_regs = 6, | |
494 | ||
cfb61a41 CC |
495 | }; |
496 | ||
20147f0d CYT |
497 | static const struct regmap_irq_chip axp809_regmap_irq_chip = { |
498 | .name = "axp809", | |
499 | .status_base = AXP20X_IRQ1_STATE, | |
500 | .ack_base = AXP20X_IRQ1_STATE, | |
501 | .mask_base = AXP20X_IRQ1_EN, | |
502 | .mask_invert = true, | |
503 | .init_ack_masked = true, | |
504 | .irqs = axp809_regmap_irqs, | |
505 | .num_irqs = ARRAY_SIZE(axp809_regmap_irqs), | |
506 | .num_regs = 5, | |
507 | }; | |
508 | ||
cfb61a41 CC |
509 | static struct mfd_cell axp20x_cells[] = { |
510 | { | |
8de4efda HG |
511 | .name = "axp20x-pek", |
512 | .num_resources = ARRAY_SIZE(axp20x_pek_resources), | |
513 | .resources = axp20x_pek_resources, | |
cfb61a41 | 514 | }, { |
8de4efda | 515 | .name = "axp20x-regulator", |
cd7cf27b MH |
516 | }, { |
517 | .name = "axp20x-ac-power-supply", | |
518 | .of_compatible = "x-powers,axp202-ac-power-supply", | |
519 | .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources), | |
520 | .resources = axp20x_ac_power_supply_resources, | |
8de4efda HG |
521 | }, { |
522 | .name = "axp20x-usb-power-supply", | |
523 | .of_compatible = "x-powers,axp202-usb-power-supply", | |
524 | .num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources), | |
525 | .resources = axp20x_usb_power_supply_resources, | |
cfb61a41 CC |
526 | }, |
527 | }; | |
528 | ||
f05be589 BB |
529 | static struct mfd_cell axp22x_cells[] = { |
530 | { | |
531 | .name = "axp20x-pek", | |
532 | .num_resources = ARRAY_SIZE(axp22x_pek_resources), | |
533 | .resources = axp22x_pek_resources, | |
6d4fa89d CYT |
534 | }, { |
535 | .name = "axp20x-regulator", | |
ecd98cce HG |
536 | }, { |
537 | .name = "axp20x-usb-power-supply", | |
538 | .of_compatible = "x-powers,axp221-usb-power-supply", | |
539 | .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources), | |
540 | .resources = axp22x_usb_power_supply_resources, | |
f05be589 BB |
541 | }, |
542 | }; | |
543 | ||
d8d79f8f MS |
544 | static struct mfd_cell axp152_cells[] = { |
545 | { | |
546 | .name = "axp20x-pek", | |
547 | .num_resources = ARRAY_SIZE(axp152_pek_resources), | |
548 | .resources = axp152_pek_resources, | |
549 | }, | |
550 | }; | |
551 | ||
af7e9069 JP |
552 | static struct resource axp288_adc_resources[] = { |
553 | { | |
554 | .name = "GPADC", | |
555 | .start = AXP288_IRQ_GPADC, | |
556 | .end = AXP288_IRQ_GPADC, | |
557 | .flags = IORESOURCE_IRQ, | |
558 | }, | |
559 | }; | |
560 | ||
bdb01f78 RP |
561 | static struct resource axp288_extcon_resources[] = { |
562 | { | |
563 | .start = AXP288_IRQ_VBUS_FALL, | |
564 | .end = AXP288_IRQ_VBUS_FALL, | |
565 | .flags = IORESOURCE_IRQ, | |
566 | }, | |
567 | { | |
568 | .start = AXP288_IRQ_VBUS_RISE, | |
569 | .end = AXP288_IRQ_VBUS_RISE, | |
570 | .flags = IORESOURCE_IRQ, | |
571 | }, | |
572 | { | |
573 | .start = AXP288_IRQ_MV_CHNG, | |
574 | .end = AXP288_IRQ_MV_CHNG, | |
575 | .flags = IORESOURCE_IRQ, | |
576 | }, | |
577 | { | |
578 | .start = AXP288_IRQ_BC_USB_CHNG, | |
579 | .end = AXP288_IRQ_BC_USB_CHNG, | |
580 | .flags = IORESOURCE_IRQ, | |
581 | }, | |
582 | }; | |
583 | ||
af7e9069 JP |
584 | static struct resource axp288_charger_resources[] = { |
585 | { | |
586 | .start = AXP288_IRQ_OV, | |
587 | .end = AXP288_IRQ_OV, | |
588 | .flags = IORESOURCE_IRQ, | |
589 | }, | |
590 | { | |
591 | .start = AXP288_IRQ_DONE, | |
592 | .end = AXP288_IRQ_DONE, | |
593 | .flags = IORESOURCE_IRQ, | |
594 | }, | |
595 | { | |
596 | .start = AXP288_IRQ_CHARGING, | |
597 | .end = AXP288_IRQ_CHARGING, | |
598 | .flags = IORESOURCE_IRQ, | |
599 | }, | |
600 | { | |
601 | .start = AXP288_IRQ_SAFE_QUIT, | |
602 | .end = AXP288_IRQ_SAFE_QUIT, | |
603 | .flags = IORESOURCE_IRQ, | |
604 | }, | |
605 | { | |
606 | .start = AXP288_IRQ_SAFE_ENTER, | |
607 | .end = AXP288_IRQ_SAFE_ENTER, | |
608 | .flags = IORESOURCE_IRQ, | |
609 | }, | |
610 | { | |
611 | .start = AXP288_IRQ_QCBTU, | |
612 | .end = AXP288_IRQ_QCBTU, | |
613 | .flags = IORESOURCE_IRQ, | |
614 | }, | |
615 | { | |
616 | .start = AXP288_IRQ_CBTU, | |
617 | .end = AXP288_IRQ_CBTU, | |
618 | .flags = IORESOURCE_IRQ, | |
619 | }, | |
620 | { | |
621 | .start = AXP288_IRQ_QCBTO, | |
622 | .end = AXP288_IRQ_QCBTO, | |
623 | .flags = IORESOURCE_IRQ, | |
624 | }, | |
625 | { | |
626 | .start = AXP288_IRQ_CBTO, | |
627 | .end = AXP288_IRQ_CBTO, | |
628 | .flags = IORESOURCE_IRQ, | |
629 | }, | |
630 | }; | |
631 | ||
632 | static struct mfd_cell axp288_cells[] = { | |
633 | { | |
634 | .name = "axp288_adc", | |
635 | .num_resources = ARRAY_SIZE(axp288_adc_resources), | |
636 | .resources = axp288_adc_resources, | |
637 | }, | |
bdb01f78 RP |
638 | { |
639 | .name = "axp288_extcon", | |
640 | .num_resources = ARRAY_SIZE(axp288_extcon_resources), | |
641 | .resources = axp288_extcon_resources, | |
642 | }, | |
af7e9069 JP |
643 | { |
644 | .name = "axp288_charger", | |
645 | .num_resources = ARRAY_SIZE(axp288_charger_resources), | |
646 | .resources = axp288_charger_resources, | |
647 | }, | |
648 | { | |
d6387874 TB |
649 | .name = "axp288_fuel_gauge", |
650 | .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources), | |
651 | .resources = axp288_fuel_gauge_resources, | |
af7e9069 | 652 | }, |
e56e5ad6 BF |
653 | { |
654 | .name = "axp20x-pek", | |
655 | .num_resources = ARRAY_SIZE(axp288_power_button_resources), | |
656 | .resources = axp288_power_button_resources, | |
657 | }, | |
d8139f63 AL |
658 | { |
659 | .name = "axp288_pmic_acpi", | |
660 | }, | |
af7e9069 JP |
661 | }; |
662 | ||
20147f0d CYT |
663 | static struct mfd_cell axp809_cells[] = { |
664 | { | |
665 | .name = "axp20x-pek", | |
666 | .num_resources = ARRAY_SIZE(axp809_pek_resources), | |
667 | .resources = axp809_pek_resources, | |
668 | }, { | |
669 | .name = "axp20x-regulator", | |
670 | }, | |
671 | }; | |
672 | ||
cfb61a41 CC |
673 | static struct axp20x_dev *axp20x_pm_power_off; |
674 | static void axp20x_power_off(void) | |
675 | { | |
af7e9069 JP |
676 | if (axp20x_pm_power_off->variant == AXP288_ID) |
677 | return; | |
678 | ||
cfb61a41 CC |
679 | regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL, |
680 | AXP20X_OFF); | |
179dc63d HG |
681 | |
682 | /* Give capacitors etc. time to drain to avoid kernel panic msg. */ | |
683 | msleep(500); | |
cfb61a41 CC |
684 | } |
685 | ||
4fd41151 | 686 | int axp20x_match_device(struct axp20x_dev *axp20x) |
af7e9069 | 687 | { |
e47a3cf7 | 688 | struct device *dev = axp20x->dev; |
af7e9069 JP |
689 | const struct acpi_device_id *acpi_id; |
690 | const struct of_device_id *of_id; | |
691 | ||
692 | if (dev->of_node) { | |
af7acc3d | 693 | of_id = of_match_device(dev->driver->of_match_table, dev); |
af7e9069 JP |
694 | if (!of_id) { |
695 | dev_err(dev, "Unable to match OF ID\n"); | |
696 | return -ENODEV; | |
697 | } | |
2260a453 | 698 | axp20x->variant = (long)of_id->data; |
af7e9069 JP |
699 | } else { |
700 | acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev); | |
701 | if (!acpi_id || !acpi_id->driver_data) { | |
702 | dev_err(dev, "Unable to match ACPI ID and data\n"); | |
703 | return -ENODEV; | |
704 | } | |
2260a453 | 705 | axp20x->variant = (long)acpi_id->driver_data; |
af7e9069 JP |
706 | } |
707 | ||
708 | switch (axp20x->variant) { | |
d8d79f8f MS |
709 | case AXP152_ID: |
710 | axp20x->nr_cells = ARRAY_SIZE(axp152_cells); | |
711 | axp20x->cells = axp152_cells; | |
712 | axp20x->regmap_cfg = &axp152_regmap_config; | |
713 | axp20x->regmap_irq_chip = &axp152_regmap_irq_chip; | |
714 | break; | |
af7e9069 JP |
715 | case AXP202_ID: |
716 | case AXP209_ID: | |
717 | axp20x->nr_cells = ARRAY_SIZE(axp20x_cells); | |
718 | axp20x->cells = axp20x_cells; | |
719 | axp20x->regmap_cfg = &axp20x_regmap_config; | |
720 | axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip; | |
721 | break; | |
f05be589 | 722 | case AXP221_ID: |
02071f0f | 723 | case AXP223_ID: |
f05be589 BB |
724 | axp20x->nr_cells = ARRAY_SIZE(axp22x_cells); |
725 | axp20x->cells = axp22x_cells; | |
726 | axp20x->regmap_cfg = &axp22x_regmap_config; | |
727 | axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip; | |
728 | break; | |
af7e9069 JP |
729 | case AXP288_ID: |
730 | axp20x->cells = axp288_cells; | |
731 | axp20x->nr_cells = ARRAY_SIZE(axp288_cells); | |
732 | axp20x->regmap_cfg = &axp288_regmap_config; | |
733 | axp20x->regmap_irq_chip = &axp288_regmap_irq_chip; | |
734 | break; | |
20147f0d CYT |
735 | case AXP809_ID: |
736 | axp20x->nr_cells = ARRAY_SIZE(axp809_cells); | |
737 | axp20x->cells = axp809_cells; | |
738 | axp20x->regmap_cfg = &axp22x_regmap_config; | |
739 | axp20x->regmap_irq_chip = &axp809_regmap_irq_chip; | |
740 | break; | |
af7e9069 JP |
741 | default: |
742 | dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant); | |
743 | return -EINVAL; | |
744 | } | |
745 | dev_info(dev, "AXP20x variant %s found\n", | |
2260a453 | 746 | axp20x_model_names[axp20x->variant]); |
af7e9069 JP |
747 | |
748 | return 0; | |
749 | } | |
4fd41151 | 750 | EXPORT_SYMBOL(axp20x_match_device); |
af7e9069 | 751 | |
4fd41151 | 752 | int axp20x_device_probe(struct axp20x_dev *axp20x) |
cfb61a41 | 753 | { |
cfb61a41 CC |
754 | int ret; |
755 | ||
4fd41151 | 756 | ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq, |
cfb61a41 | 757 | IRQF_ONESHOT | IRQF_SHARED, -1, |
af7e9069 | 758 | axp20x->regmap_irq_chip, |
cfb61a41 CC |
759 | &axp20x->regmap_irqc); |
760 | if (ret) { | |
4fd41151 | 761 | dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret); |
cfb61a41 CC |
762 | return ret; |
763 | } | |
764 | ||
af7e9069 | 765 | ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells, |
2260a453 | 766 | axp20x->nr_cells, NULL, 0, NULL); |
cfb61a41 CC |
767 | |
768 | if (ret) { | |
4fd41151 CYT |
769 | dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret); |
770 | regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc); | |
cfb61a41 CC |
771 | return ret; |
772 | } | |
773 | ||
774 | if (!pm_power_off) { | |
775 | axp20x_pm_power_off = axp20x; | |
776 | pm_power_off = axp20x_power_off; | |
777 | } | |
778 | ||
4fd41151 | 779 | dev_info(axp20x->dev, "AXP20X driver loaded\n"); |
cfb61a41 CC |
780 | |
781 | return 0; | |
782 | } | |
4fd41151 | 783 | EXPORT_SYMBOL(axp20x_device_probe); |
cfb61a41 | 784 | |
4fd41151 | 785 | int axp20x_device_remove(struct axp20x_dev *axp20x) |
cfb61a41 | 786 | { |
cfb61a41 CC |
787 | if (axp20x == axp20x_pm_power_off) { |
788 | axp20x_pm_power_off = NULL; | |
789 | pm_power_off = NULL; | |
790 | } | |
791 | ||
792 | mfd_remove_devices(axp20x->dev); | |
4fd41151 | 793 | regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc); |
cfb61a41 CC |
794 | |
795 | return 0; | |
796 | } | |
4fd41151 | 797 | EXPORT_SYMBOL(axp20x_device_remove); |
cfb61a41 CC |
798 | |
799 | MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X"); | |
800 | MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); | |
801 | MODULE_LICENSE("GPL"); |