[deliverable/linux.git] / drivers / mfd / htc-egpio.c

/*
 * Support for the GPIO/IRQ expander chips present on several HTC phones.
 * These are implemented in CPLD chips present on the board.
 *
 * Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
 * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
 *
 * This file may be distributed under the terms of the GNU GPL license.
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/mfd/htc-egpio.h>

struct egpio_chip {
	int              reg_start;
	int              cached_values;
	unsigned long    is_out;
	struct device    *dev;
	struct gpio_chip chip;
};

struct egpio_info {
	spinlock_t        lock;

	/* iomem info */
	void __iomem      *base_addr;
	int               bus_shift;	/* byte shift */
	int               reg_shift;	/* bit shift */
	int               reg_mask;

	/* irq info */
	int               ack_register;
	int               ack_write;
	u16               irqs_enabled;
	uint              irq_start;
	int               nirqs;
	uint              chained_irq;

	/* egpio info */
	struct egpio_chip *chip;
	int               nchips;
};

static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
{
	writew(value, ei->base_addr + (reg << ei->bus_shift));
}

static inline u16 egpio_readw(struct egpio_info *ei, int reg)
{
	return readw(ei->base_addr + (reg << ei->bus_shift));
}

/*
 * IRQs
 */

static inline void ack_irqs(struct egpio_info *ei)
{
	egpio_writew(ei->ack_write, ei, ei->ack_register);
	pr_debug("EGPIO ack - write %x to base+%x\n",
			ei->ack_write, ei->ack_register << ei->bus_shift);
}

static void egpio_ack(struct irq_data *data)
{
}

/* There does not appear to be a way to proactively mask interrupts
 * on the egpio chip itself.  So, we simply ignore interrupts that
 * aren't desired. */
static void egpio_mask(struct irq_data *data)
{
	struct egpio_info *ei = irq_data_get_irq_chip_data(data);
	ei->irqs_enabled &= ~(1 << (data->irq - ei->irq_start));
	pr_debug("EGPIO mask %d %04x\n", data->irq, ei->irqs_enabled);
}

static void egpio_unmask(struct irq_data *data)
{
	struct egpio_info *ei = irq_data_get_irq_chip_data(data);
	ei->irqs_enabled |= 1 << (data->irq - ei->irq_start);
	pr_debug("EGPIO unmask %d %04x\n", data->irq, ei->irqs_enabled);
}

static struct irq_chip egpio_muxed_chip = {
	.name		= "htc-egpio",
	.irq_ack	= egpio_ack,
	.irq_mask	= egpio_mask,
	.irq_unmask	= egpio_unmask,
};

static void egpio_handler(unsigned int irq, struct irq_desc *desc)
{
	struct egpio_info *ei = get_irq_data(irq);
	int irqpin;

	/* Read current pins. */
	unsigned long readval = egpio_readw(ei, ei->ack_register);
	pr_debug("IRQ reg: %x\n", (unsigned int)readval);
	/* Ack/unmask interrupts. */
	ack_irqs(ei);
	/* Process all set pins. */
	readval &= ei->irqs_enabled;
	for_each_set_bit(irqpin, &readval, ei->nirqs) {
		/* Run irq handler */
		pr_debug("got IRQ %d\n", irqpin);
		irq = ei->irq_start + irqpin;
		desc = irq_to_desc(irq);
		desc->handle_irq(irq, desc);
	}
}

int htc_egpio_get_wakeup_irq(struct device *dev)
{
	struct egpio_info *ei = dev_get_drvdata(dev);

	/* Read current pins. */
	u16 readval = egpio_readw(ei, ei->ack_register);
	/* Ack/unmask interrupts. */
	ack_irqs(ei);
	/* Return first set pin. */
	readval &= ei->irqs_enabled;
	return ei->irq_start + ffs(readval) - 1;
}
EXPORT_SYMBOL(htc_egpio_get_wakeup_irq);

static inline int egpio_pos(struct egpio_info *ei, int bit)
{
	return bit >> ei->reg_shift;
}

static inline int egpio_bit(struct egpio_info *ei, int bit)
{
	return 1 << (bit & ((1 << ei->reg_shift)-1));
}

/*
 * Input pins
 */

static int egpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct egpio_chip *egpio;
	struct egpio_info *ei;
	unsigned           bit;
	int                reg;
	int                value;

	pr_debug("egpio_get_value(%d)\n", chip->base + offset);

	egpio = container_of(chip, struct egpio_chip, chip);
	ei    = dev_get_drvdata(egpio->dev);
	bit   = egpio_bit(ei, offset);
	reg   = egpio->reg_start + egpio_pos(ei, offset);

	value = egpio_readw(ei, reg);
	pr_debug("readw(%p + %x) = %x\n",
			ei->base_addr, reg << ei->bus_shift, value);
	return value & bit;
}

static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct egpio_chip *egpio;

	egpio = container_of(chip, struct egpio_chip, chip);
	return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
}


/*
 * Output pins
 */

static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	unsigned long     flag;
	struct egpio_chip *egpio;
	struct egpio_info *ei;
	unsigned          bit;
	int               pos;
	int               reg;
	int               shift;

	pr_debug("egpio_set(%s, %d(%d), %d)\n",
			chip->label, offset, offset+chip->base, value);

	egpio = container_of(chip, struct egpio_chip, chip);
	ei    = dev_get_drvdata(egpio->dev);
	bit   = egpio_bit(ei, offset);
	pos   = egpio_pos(ei, offset);
	reg   = egpio->reg_start + pos;
	shift = pos << ei->reg_shift;

	pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
			reg, (egpio->cached_values >> shift) & ei->reg_mask);

	spin_lock_irqsave(&ei->lock, flag);
	if (value)
		egpio->cached_values |= (1 << offset);
	else
		egpio->cached_values &= ~(1 << offset);
	egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
	spin_unlock_irqrestore(&ei->lock, flag);
}

static int egpio_direction_output(struct gpio_chip *chip,
					unsigned offset, int value)
{
	struct egpio_chip *egpio;

	egpio = container_of(chip, struct egpio_chip, chip);
	if (test_bit(offset, &egpio->is_out)) {
		egpio_set(chip, offset, value);
		return 0;
	} else {
		return -EINVAL;
	}
}

static void egpio_write_cache(struct egpio_info *ei)
{
	int               i;
	struct egpio_chip *egpio;
	int               shift;

	for (i = 0; i < ei->nchips; i++) {
		egpio = &(ei->chip[i]);
		if (!egpio->is_out)
			continue;

		for (shift = 0; shift < egpio->chip.ngpio;
				shift += (1<<ei->reg_shift)) {

			int reg = egpio->reg_start + egpio_pos(ei, shift);

			if (!((egpio->is_out >> shift) & ei->reg_mask))
				continue;

			pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
				(egpio->cached_values >> shift) & ei->reg_mask,
				egpio_readw(ei, reg));

			egpio_writew((egpio->cached_values >> shift)
					& ei->reg_mask, ei, reg);
		}
	}
}


/*
 * Setup
 */

static int __init egpio_probe(struct platform_device *pdev)
{
	struct htc_egpio_platform_data *pdata = pdev->dev.platform_data;
	struct resource   *res;
	struct egpio_info *ei;
	struct gpio_chip  *chip;
	unsigned int      irq, irq_end;
	int               i;
	int               ret;

	/* Initialize ei data structure. */
	ei = kzalloc(sizeof(*ei), GFP_KERNEL);
	if (!ei)
		return -ENOMEM;

	spin_lock_init(&ei->lock);

	/* Find chained irq */
	ret = -EINVAL;
	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (res)
		ei->chained_irq = res->start;

	/* Map egpio chip into virtual address space. */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		goto fail;
	ei->base_addr = ioremap_nocache(res->start, resource_size(res));
	if (!ei->base_addr)
		goto fail;
	pr_debug("EGPIO phys=%08x virt=%p\n", (u32)res->start, ei->base_addr);

	if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
		goto fail;
	ei->bus_shift = fls(pdata->bus_width - 1) - 3;
	pr_debug("bus_shift = %d\n", ei->bus_shift);

	if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
		goto fail;
	ei->reg_shift = fls(pdata->reg_width - 1);
	pr_debug("reg_shift = %d\n", ei->reg_shift);

	ei->reg_mask = (1 << pdata->reg_width) - 1;

	platform_set_drvdata(pdev, ei);

	ei->nchips = pdata->num_chips;
	ei->chip = kzalloc(sizeof(struct egpio_chip) * ei->nchips, GFP_KERNEL);
	if (!ei->chip) {
		ret = -ENOMEM;
		goto fail;
	}
	for (i = 0; i < ei->nchips; i++) {
		ei->chip[i].reg_start = pdata->chip[i].reg_start;
		ei->chip[i].cached_values = pdata->chip[i].initial_values;
		ei->chip[i].is_out = pdata->chip[i].direction;
		ei->chip[i].dev = &(pdev->dev);
		chip = &(ei->chip[i].chip);
		chip->label           = "htc-egpio";
		chip->dev             = &pdev->dev;
		chip->owner           = THIS_MODULE;
		chip->get             = egpio_get;
		chip->set             = egpio_set;
		chip->direction_input = egpio_direction_input;
		chip->direction_output = egpio_direction_output;
		chip->base            = pdata->chip[i].gpio_base;
		chip->ngpio           = pdata->chip[i].num_gpios;

		gpiochip_add(chip);
	}

	/* Set initial pin values */
	egpio_write_cache(ei);

	ei->irq_start = pdata->irq_base;
	ei->nirqs = pdata->num_irqs;
	ei->ack_register = pdata->ack_register;

	if (ei->chained_irq) {
		/* Setup irq handlers */
		ei->ack_write = 0xFFFF;
		if (pdata->invert_acks)
			ei->ack_write = 0;
		irq_end = ei->irq_start + ei->nirqs;
		for (irq = ei->irq_start; irq < irq_end; irq++) {
			set_irq_chip(irq, &egpio_muxed_chip);
			set_irq_chip_data(irq, ei);
			set_irq_handler(irq, handle_simple_irq);
			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
		}
		set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
		set_irq_data(ei->chained_irq, ei);
		set_irq_chained_handler(ei->chained_irq, egpio_handler);
		ack_irqs(ei);

		device_init_wakeup(&pdev->dev, 1);
	}

	return 0;

fail:
	printk(KERN_ERR "EGPIO failed to setup\n");
	kfree(ei);
	return ret;
}

static int __exit egpio_remove(struct platform_device *pdev)
{
	struct egpio_info *ei = platform_get_drvdata(pdev);
	unsigned int      irq, irq_end;

	if (ei->chained_irq) {
		irq_end = ei->irq_start + ei->nirqs;
		for (irq = ei->irq_start; irq < irq_end; irq++) {
			set_irq_chip(irq, NULL);
			set_irq_handler(irq, NULL);
			set_irq_flags(irq, 0);
		}
		set_irq_chained_handler(ei->chained_irq, NULL);
		device_init_wakeup(&pdev->dev, 0);
	}
	iounmap(ei->base_addr);
	kfree(ei->chip);
	kfree(ei);

	return 0;
}

#ifdef CONFIG_PM
static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct egpio_info *ei = platform_get_drvdata(pdev);

	if (ei->chained_irq && device_may_wakeup(&pdev->dev))
		enable_irq_wake(ei->chained_irq);
	return 0;
}

static int egpio_resume(struct platform_device *pdev)
{
	struct egpio_info *ei = platform_get_drvdata(pdev);

	if (ei->chained_irq && device_may_wakeup(&pdev->dev))
		disable_irq_wake(ei->chained_irq);

	/* Update registers from the cache, in case
	   the CPLD was powered off during suspend */
	egpio_write_cache(ei);
	return 0;
}
#else
#define egpio_suspend NULL
#define egpio_resume NULL
#endif


static struct platform_driver egpio_driver = {
	.driver = {
		.name = "htc-egpio",
	},
	.remove       = __exit_p(egpio_remove),
	.suspend      = egpio_suspend,
	.resume       = egpio_resume,
};

static int __init egpio_init(void)
{
	return platform_driver_probe(&egpio_driver, egpio_probe);
}

static void __exit egpio_exit(void)
{
	platform_driver_unregister(&egpio_driver);
}

/* start early for dependencies */
subsys_initcall(egpio_init);
module_exit(egpio_exit)

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Kevin O'Connor <kevin@koconnor.net>");
Commit	Line	Data
a1635b8f PZ	1	/*
	2	* Support for the GPIO/IRQ expander chips present on several HTC phones.
	3	* These are implemented in CPLD chips present on the board.
	4	*
	5	* Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
	6	* Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
	7	*
	8	* This file may be distributed under the terms of the GNU GPL license.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/errno.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/irq.h>
	15	#include <linux/io.h>
	16	#include <linux/spinlock.h>
	17	#include <linux/platform_device.h>
5a0e3ad6	18	#include <linux/slab.h>
a1635b8f PZ	19	#include <linux/module.h>
	20	#include <linux/mfd/htc-egpio.h>
	21
	22	struct egpio_chip {
	23	int reg_start;
	24	int cached_values;
	25	unsigned long is_out;
	26	struct device *dev;
	27	struct gpio_chip chip;
	28	};
	29
	30	struct egpio_info {
	31	spinlock_t lock;
	32
	33	/* iomem info */
	34	void __iomem *base_addr;
	35	int bus_shift; /* byte shift */
	36	int reg_shift; /* bit shift */
	37	int reg_mask;
	38
	39	/* irq info */
	40	int ack_register;
	41	int ack_write;
	42	u16 irqs_enabled;
	43	uint irq_start;
	44	int nirqs;
	45	uint chained_irq;
	46
	47	/* egpio info */
	48	struct egpio_chip *chip;
	49	int nchips;
	50	};
	51
	52	static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
	53	{
	54	writew(value, ei->base_addr + (reg << ei->bus_shift));
	55	}
	56
	57	static inline u16 egpio_readw(struct egpio_info *ei, int reg)
	58	{
	59	return readw(ei->base_addr + (reg << ei->bus_shift));
	60	}
	61
	62	/*
	63	* IRQs
	64	*/
	65
	66	static inline void ack_irqs(struct egpio_info *ei)
	67	{
	68	egpio_writew(ei->ack_write, ei, ei->ack_register);
	69	pr_debug("EGPIO ack - write %x to base+%x\n",
	70	ei->ack_write, ei->ack_register << ei->bus_shift);
	71	}
	72
949b9dec	73	static void egpio_ack(struct irq_data *data)
a1635b8f PZ	74	{
	75	}
	76
	77	/* There does not appear to be a way to proactively mask interrupts
	78	* on the egpio chip itself. So, we simply ignore interrupts that
	79	* aren't desired. */
949b9dec	80	static void egpio_mask(struct irq_data *data)
a1635b8f	81	{
949b9dec MB	82	struct egpio_info *ei = irq_data_get_irq_chip_data(data);
	83	ei->irqs_enabled &= ~(1 << (data->irq - ei->irq_start));
	84	pr_debug("EGPIO mask %d %04x\n", data->irq, ei->irqs_enabled);
a1635b8f	85	}
949b9dec MB	86
949b9dec MB	87	static void egpio_unmask(struct irq_data *data)
a1635b8f	88	{
949b9dec MB	89	struct egpio_info *ei = irq_data_get_irq_chip_data(data);
	90	ei->irqs_enabled \|= 1 << (data->irq - ei->irq_start);
	91	pr_debug("EGPIO unmask %d %04x\n", data->irq, ei->irqs_enabled);
a1635b8f PZ	92	}
	93
	94	static struct irq_chip egpio_muxed_chip = {
949b9dec MB	95	.name = "htc-egpio",
	96	.irq_ack = egpio_ack,
	97	.irq_mask = egpio_mask,
	98	.irq_unmask = egpio_unmask,
a1635b8f PZ	99	};
	100
	101	static void egpio_handler(unsigned int irq, struct irq_desc *desc)
	102	{
	103	struct egpio_info *ei = get_irq_data(irq);
	104	int irqpin;
	105
	106	/* Read current pins. */
	107	unsigned long readval = egpio_readw(ei, ei->ack_register);
	108	pr_debug("IRQ reg: %x\n", (unsigned int)readval);
	109	/* Ack/unmask interrupts. */
	110	ack_irqs(ei);
	111	/* Process all set pins. */
	112	readval &= ei->irqs_enabled;
984b3f57	113	for_each_set_bit(irqpin, &readval, ei->nirqs) {
a1635b8f PZ	114	/* Run irq handler */
	115	pr_debug("got IRQ %d\n", irqpin);
	116	irq = ei->irq_start + irqpin;
08678b08	117	desc = irq_to_desc(irq);
a1635b8f PZ	118	desc->handle_irq(irq, desc);
	119	}
	120	}
	121
	122	int htc_egpio_get_wakeup_irq(struct device *dev)
	123	{
	124	struct egpio_info *ei = dev_get_drvdata(dev);
	125
	126	/* Read current pins. */
	127	u16 readval = egpio_readw(ei, ei->ack_register);
	128	/* Ack/unmask interrupts. */
	129	ack_irqs(ei);
	130	/* Return first set pin. */
	131	readval &= ei->irqs_enabled;
	132	return ei->irq_start + ffs(readval) - 1;
	133	}
	134	EXPORT_SYMBOL(htc_egpio_get_wakeup_irq);
	135
	136	static inline int egpio_pos(struct egpio_info *ei, int bit)
	137	{
	138	return bit >> ei->reg_shift;
	139	}
	140
	141	static inline int egpio_bit(struct egpio_info *ei, int bit)
	142	{
	143	return 1 << (bit & ((1 << ei->reg_shift)-1));
	144	}
	145
	146	/*
	147	* Input pins
	148	*/
	149
	150	static int egpio_get(struct gpio_chip *chip, unsigned offset)
	151	{
	152	struct egpio_chip *egpio;
	153	struct egpio_info *ei;
	154	unsigned bit;
	155	int reg;
	156	int value;
	157
	158	pr_debug("egpio_get_value(%d)\n", chip->base + offset);
	159
	160	egpio = container_of(chip, struct egpio_chip, chip);
	161	ei = dev_get_drvdata(egpio->dev);
	162	bit = egpio_bit(ei, offset);
	163	reg = egpio->reg_start + egpio_pos(ei, offset);
	164
	165	value = egpio_readw(ei, reg);
	166	pr_debug("readw(%p + %x) = %x\n",
	167	ei->base_addr, reg << ei->bus_shift, value);
	168	return value & bit;
	169	}
	170
	171	static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
	172	{
	173	struct egpio_chip *egpio;
	174
	175	egpio = container_of(chip, struct egpio_chip, chip);
	176	return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
	177	}
	178
	179
	180	/*
	181	* Output pins
182	*/
183
184	static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
185	{
186	unsigned long flag;
187	struct egpio_chip *egpio;
188	struct egpio_info *ei;
189	unsigned bit;
190	int pos;
191	int reg;
192	int shift;
193
194	pr_debug("egpio_set(%s, %d(%d), %d)\n",
195	chip->label, offset, offset+chip->base, value);
196
197	egpio = container_of(chip, struct egpio_chip, chip);
198	ei = dev_get_drvdata(egpio->dev);
199	bit = egpio_bit(ei, offset);
200	pos = egpio_pos(ei, offset);
201	reg = egpio->reg_start + pos;
202	shift = pos << ei->reg_shift;
203
204	pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
205	reg, (egpio->cached_values >> shift) & ei->reg_mask);
206
207	spin_lock_irqsave(&ei->lock, flag);
208	if (value)
209	egpio->cached_values \|= (1 << offset);
210	else
211	egpio->cached_values &= ~(1 << offset);
212	egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
213	spin_unlock_irqrestore(&ei->lock, flag);
214	}
215
216	static int egpio_direction_output(struct gpio_chip *chip,
217	unsigned offset, int value)
218	{
219	struct egpio_chip *egpio;
220
221	egpio = container_of(chip, struct egpio_chip, chip);
222	if (test_bit(offset, &egpio->is_out)) {
223	egpio_set(chip, offset, value);
224	return 0;
225	} else {
226	return -EINVAL;
227	}
228	}
229
230	static void egpio_write_cache(struct egpio_info *ei)
231	{
232	int i;
233	struct egpio_chip *egpio;
234	int shift;
235
236	for (i = 0; i < ei->nchips; i++) {
237	egpio = &(ei->chip[i]);
238	if (!egpio->is_out)
239	continue;
240
241	for (shift = 0; shift < egpio->chip.ngpio;
242	shift += (1<<ei->reg_shift)) {
243
244	int reg = egpio->reg_start + egpio_pos(ei, shift);
245
246	if (!((egpio->is_out >> shift) & ei->reg_mask))
247	continue;
248
249	pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
250	(egpio->cached_values >> shift) & ei->reg_mask,
251	egpio_readw(ei, reg));
252
253	egpio_writew((egpio->cached_values >> shift)
254	& ei->reg_mask, ei, reg);
255	}
256	}
257	}
258
259
260	/*
261	* Setup
262	*/
263
264	static int __init egpio_probe(struct platform_device *pdev)
265	{
266	struct htc_egpio_platform_data *pdata = pdev->dev.platform_data;
267	struct resource *res;
268	struct egpio_info *ei;
269	struct gpio_chip *chip;
270	unsigned int irq, irq_end;
271	int i;
272	int ret;
273
274	/* Initialize ei data structure. */
275	ei = kzalloc(sizeof(*ei), GFP_KERNEL);
276	if (!ei)
277	return -ENOMEM;
278
279	spin_lock_init(&ei->lock);
280
281	/* Find chained irq */
282	ret = -EINVAL;
283	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
284	if (res)
285	ei->chained_irq = res->start;
286
287	/* Map egpio chip into virtual address space. */
288	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
289	if (!res)
290	goto fail;
9427c34b	291	ei->base_addr = ioremap_nocache(res->start, resource_size(res));
a1635b8f PZ	292	if (!ei->base_addr)
a1635b8f PZ	293	goto fail;
504f97f8	294	pr_debug("EGPIO phys=%08x virt=%p\n", (u32)res->start, ei->base_addr);
a1635b8f PZ	295
	296	if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
	297	goto fail;
	298	ei->bus_shift = fls(pdata->bus_width - 1) - 3;
	299	pr_debug("bus_shift = %d\n", ei->bus_shift);
	300
	301	if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
	302	goto fail;
	303	ei->reg_shift = fls(pdata->reg_width - 1);
	304	pr_debug("reg_shift = %d\n", ei->reg_shift);
	305
	306	ei->reg_mask = (1 << pdata->reg_width) - 1;
	307
	308	platform_set_drvdata(pdev, ei);
	309
	310	ei->nchips = pdata->num_chips;
	311	ei->chip = kzalloc(sizeof(struct egpio_chip) * ei->nchips, GFP_KERNEL);
720fd66d	312	if (!ei->chip) {
a1635b8f PZ	313	ret = -ENOMEM;
	314	goto fail;
	315	}
	316	for (i = 0; i < ei->nchips; i++) {
	317	ei->chip[i].reg_start = pdata->chip[i].reg_start;
	318	ei->chip[i].cached_values = pdata->chip[i].initial_values;
	319	ei->chip[i].is_out = pdata->chip[i].direction;
	320	ei->chip[i].dev = &(pdev->dev);
	321	chip = &(ei->chip[i].chip);
	322	chip->label = "htc-egpio";
d8f388d8 DB	323	chip->dev = &pdev->dev;
d8f388d8 DB	324	chip->owner = THIS_MODULE;
a1635b8f PZ	325	chip->get = egpio_get;
	326	chip->set = egpio_set;
	327	chip->direction_input = egpio_direction_input;
	328	chip->direction_output = egpio_direction_output;
	329	chip->base = pdata->chip[i].gpio_base;
	330	chip->ngpio = pdata->chip[i].num_gpios;
	331
	332	gpiochip_add(chip);
	333	}
	334
	335	/* Set initial pin values */
	336	egpio_write_cache(ei);
	337
	338	ei->irq_start = pdata->irq_base;
	339	ei->nirqs = pdata->num_irqs;
	340	ei->ack_register = pdata->ack_register;
	341
	342	if (ei->chained_irq) {
	343	/* Setup irq handlers */
	344	ei->ack_write = 0xFFFF;
	345	if (pdata->invert_acks)
	346	ei->ack_write = 0;
	347	irq_end = ei->irq_start + ei->nirqs;
	348	for (irq = ei->irq_start; irq < irq_end; irq++) {
	349	set_irq_chip(irq, &egpio_muxed_chip);
	350	set_irq_chip_data(irq, ei);
	351	set_irq_handler(irq, handle_simple_irq);
	352	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	353	}
	354	set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
	355	set_irq_data(ei->chained_irq, ei);
	356	set_irq_chained_handler(ei->chained_irq, egpio_handler);
	357	ack_irqs(ei);
	358
	359	device_init_wakeup(&pdev->dev, 1);
	360	}
	361
	362	return 0;
	363
	364	fail:
	365	printk(KERN_ERR "EGPIO failed to setup\n");
	366	kfree(ei);
	367	return ret;
	368	}
	369
	370	static int __exit egpio_remove(struct platform_device *pdev)
	371	{
	372	struct egpio_info *ei = platform_get_drvdata(pdev);
	373	unsigned int irq, irq_end;
	374
	375	if (ei->chained_irq) {
	376	irq_end = ei->irq_start + ei->nirqs;
	377	for (irq = ei->irq_start; irq < irq_end; irq++) {
	378	set_irq_chip(irq, NULL);
	379	set_irq_handler(irq, NULL);
	380	set_irq_flags(irq, 0);
	381	}
	382	set_irq_chained_handler(ei->chained_irq, NULL);
	383	device_init_wakeup(&pdev->dev, 0);
	384	}
	385	iounmap(ei->base_addr);
	386	kfree(ei->chip);
	387	kfree(ei);
	388
389	return 0;
390	}
391
392	#ifdef CONFIG_PM
393	static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
394	{
395	struct egpio_info *ei = platform_get_drvdata(pdev);
396
397	if (ei->chained_irq && device_may_wakeup(&pdev->dev))
398	enable_irq_wake(ei->chained_irq);
399	return 0;
400	}
401
402	static int egpio_resume(struct platform_device *pdev)
403	{
404	struct egpio_info *ei = platform_get_drvdata(pdev);
405
406	if (ei->chained_irq && device_may_wakeup(&pdev->dev))
407	disable_irq_wake(ei->chained_irq);
408
409	/* Update registers from the cache, in case
410	the CPLD was powered off during suspend */
411	egpio_write_cache(ei);
412	return 0;
413	}
414	#else
415	#define egpio_suspend NULL
416	#define egpio_resume NULL
417	#endif
418
419
420	static struct platform_driver egpio_driver = {
421	.driver = {
422	.name = "htc-egpio",
423	},
424	.remove = __exit_p(egpio_remove),
425	.suspend = egpio_suspend,
426	.resume = egpio_resume,
427	};
428
429	static int __init egpio_init(void)
430	{
431	return platform_driver_probe(&egpio_driver, egpio_probe);
432	}
433
434	static void __exit egpio_exit(void)
435	{
436	platform_driver_unregister(&egpio_driver);
437	}
438
439	/* start early for dependencies */
440	subsys_initcall(egpio_init);
441	module_exit(egpio_exit)
442
443	MODULE_LICENSE("GPL");
444	MODULE_AUTHOR("Kevin O'Connor <kevin@koconnor.net>");